JP2015162999A - Power conversion apparatus and control method of power conversion apparatus - Google Patents
Power conversion apparatus and control method of power conversion apparatus Download PDFInfo
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本発明は，電力変換装置および電力変換装置の制御方法に係り、特に、単位変換器を用いた電力変換に好適な電力変換装置および電力変換装置の制御方法に関する。
The present invention relates to a power converter and a method for controlling the power converter, and more particularly to a power converter suitable for power conversion using a unit converter and a method for controlling the power converter.
単位変換器を用いたいわゆるモジュラー・マルチレベル変換器（MMC）と呼ばれる電力変換装置は，IGBT(Insulated Gate Bipolar Transistor)などのオン・オフ制御可能なスイッチング素子を使用するものであり，該スイッチング素子の耐圧以上の電圧を出力でき，直流送電システム（HVDC）や無効電力補償装置（STATCOM），モータドライブインバータなどへの応用が期待されている。 A so-called modular multi-level converter (MMC) using a unit converter uses a switching element such as an IGBT (Insulated Gate Bipolar Transistor) that can be turned on and off, and the switching element. It is expected to be applied to DC power transmission systems (HVDC), reactive power compensators (STATCOM), motor drive inverters, etc.
この電力変換装置は，直列(カスケード)接続された１つまたは複数の単位変換器で構成されたアームを例えばブリッジ状に接続して構成されている。各単位変換器は，例えばいわゆる双方向チョッパ回路であり，スイッチング素子と直流コンデンサを備えている。各単位変換器は，少なくとも２端子を介して外部と接続しており，該２端子間の電圧を，該単位変換器の有する直流コンデンサの電圧か，または零に制御できる。 This power conversion device is configured by connecting, for example, an arm formed of one or a plurality of unit converters connected in series (cascade) in a bridge shape. Each unit converter is a so-called bidirectional chopper circuit, for example, and includes a switching element and a DC capacitor. Each unit converter is connected to the outside through at least two terminals, and the voltage between the two terminals can be controlled to the voltage of the DC capacitor of the unit converter or zero.
直列(カスケード)接続された１つまたは複数の単位変換器はアームとして構成され、このアームの電圧を制御することで電力変換を行うのであるが、その中の１の単位変換器に異常が発生するとアーム全体に波及するので、冗長動作を確保するためには、欠陥のある単位変換器が端子間において永続的に短絡する機能を有することが望ましい。そのために、単位変換器の故障時に各アームの導通を確保するように、該単位変換器の出力端子間にサイリスタを設置して，該単位変換器が故障した時にサイリスタを点呼して導通を確保する技術が知られている。このような各単位変換器が故障した時に該単位変換器の出力を短絡する技術は、例えば、特表２００９−５０６７３６号公報に記載されている。
One or more unit converters connected in series (cascade) are configured as an arm, and power conversion is performed by controlling the voltage of this arm, but an abnormality occurs in one of the unit converters Then, since it spreads to the whole arm, in order to ensure redundant operation, it is desirable that the defective unit converter has a function of permanently short-circuiting between terminals. For this purpose, a thyristor is installed between the output terminals of the unit converter so as to ensure the continuity of each arm when the unit converter fails, and the thyristor is called to ensure the continuity when the unit converter fails. The technology to do is known. A technique for short-circuiting the output of each unit converter when each unit converter fails is described in, for example, JP-T-2009-506736.
ここで，電源故障等により制御回路が機能しなくなったときは、スイッチング素子は導通/遮断状態に固定される。このときに、端子の電流の流れ方によっては、並列接続のダイオードを介してコンデンサに充電電圧が印加される。このような電流が流れ続けると，直流コンデンサの電圧は上昇し続ける。 Here, when the control circuit does not function due to a power failure or the like, the switching element is fixed to the conductive / shut off state. At this time, a charging voltage is applied to the capacitor via a diode connected in parallel depending on how the current flows through the terminal. If such a current continues to flow, the voltage of the DC capacitor will continue to rise.
特許文献１で開示される技術では，この故障時のコンデンサの充電について意識されておらず、単位変換器におけるコンデンサ電圧の上昇について対応できない。特に、電源故障等により制御回路が機能しなくなったときが問題であった。また、運転継続のためのサイリスタが必要であり，装置が大型化する。 The technology disclosed in Patent Document 1 is not conscious of charging of the capacitor at the time of the failure, and cannot cope with the increase of the capacitor voltage in the unit converter. In particular, there was a problem when the control circuit stopped functioning due to a power failure or the like. In addition, a thyristor is required to continue operation, which increases the size of the device.
本発明の目的は、装置が大型化せずに、単位変換器のデンデンサ上昇を抑制することが可能な電力変換装置および電力変換装置を提供することにある。
An object of the present invention is to provide a power conversion device and a power conversion device that can suppress an increase in the density of a unit converter without increasing the size of the device.
上記目的を達成するために、本発明では、１つまたは直列に接続された複数の単位変換器で構成された電力変換装置であって，前記単位変換器の少なくとも１は、端子と、コンデンサと、前記端子と前記前記コンデンサを導通及び遮断する直列接続された第１及び第２のスイッチング素子と、前記第１及び第２のスイッチング素子の各々に並列に接続された第１及び第２のダイオードを有し、前記第１及び第２のスイッチング素子は所定以上の過電流が流れると短絡するものであって、前記コンデンサと前記第１のスイッチング素子のゲートを接続可能にすると共に前記コンデンサと前記第２のスイッチング素子のゲートを接続可能とする導通回路を有し、前記コンデンサが過電圧状態となった場合に前記第１及び第２のスイッチング素子に所定以上の過電流が流れるように前記導通回路を導通状態にするように構成した。
To achieve the above object, according to the present invention, there is provided a power conversion device including one or a plurality of unit converters connected in series, wherein at least one of the unit converters includes a terminal, a capacitor, , First and second switching elements connected in series for connecting and disconnecting the terminal and the capacitor, and first and second diodes connected in parallel to each of the first and second switching elements The first and second switching elements are short-circuited when an overcurrent exceeding a predetermined level flows, and the capacitor and the gate of the first switching element are connectable and the capacitor and the A conduction circuit capable of connecting the gate of the second switching element; and when the capacitor is in an overvoltage state, the first and second switching elements And forming the conductive circuit as a constant or more overcurrent to the conductive state.
本発明によれば，小型・簡素化することができる。また，コンデンサの過電圧破壊や絶縁破壊を阻止することができる。
According to the present invention, it can be reduced in size and simplified. In addition, overvoltage breakdown and dielectric breakdown of the capacitor can be prevented.
以下，本発明の実施形態を図面とともに説明する。なお，実施例を説明する図では，同一の機能を有する物には同一の符号を付けた。以下の実施例ではスイッチング素子にIGBTを例にとって説明するが，IGBTをIGBT以外のMOSゲートデバイスに置換えても同様の効果を得ることができる。また，以下の実施例は本発明の一形態を示すものであり，本発明は要旨を逸脱しない限り，他の形態を含むものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings for explaining the embodiments, the same reference numerals are given to those having the same function. In the following embodiments, an IGBT will be described as an example of the switching element, but the same effect can be obtained even if the IGBT is replaced with a MOS gate device other than the IGBT. Further, the following examples show one form of the present invention, and the present invention includes other forms unless departing from the gist.
図１を参照して，本実施例の全体構成を説明する。 With reference to FIG. 1, the overall configuration of the present embodiment will be described.
電力変換装置８０１は，変圧器１０５，レグ８０２ｕ，ｖ，ｗを備えている。 The power conversion device 801 includes a transformer 105 and legs 802u, v, and w.
Ｕ相について説明すると，レグ８０２ｕは，アーム８０３ｕｐ（単位変換器１を直列に接続。他のアームも同様。），２つのリアクトルＬＢ８０４，アーム８０３ｕｎの直列回路であり，２つのリアクトル８０４の接続点をＵ’点を変圧器１０５を介して交流電力系統１０１に接続する。 The U phase will be described. The leg 802u is a series circuit of an arm 803up (unit converter 1 is connected in series. The other arms are also the same), two reactors LB804, and an arm 803un, and a connection point between the two reactors 804 Is connected to the AC power system 101 via the transformer 105.
同様に，レグ８０２ｖは，アーム８０３ｖｐ，２つのリアクトルＬＢ８０４，アーム８０３ｖｎの直列回路であり，２つのリアクトル８０４の接続点をＶ’点 を変圧器１０５を介して交流電力系統１０１に接続する。 Similarly, the leg 802v is a series circuit of the arm 803vp, the two reactors LB804, and the arm 803vn, and connects the connection point of the two reactors 804 to the AC power system 101 via the transformer 105.
また，レグ８０２ｗは，アーム８０３ｗｐ，２つのリアクトルＬＢ８０４，アーム８０３ｗｎの直列回路であり，２つのリアクトルＬＢ８０３の接続点をＷ’点 を変圧器１０５を介して交流電力系統１０１に接続する。 The leg 802w is a series circuit of the arm 803wp, the two reactors LB804, and the arm 803wn, and connects the connection point of the two reactors LB803 to the AC power system 101 via the transformer 105.
また，レグ８０２ｕ，ｖ，ｗを，Ｐ点とＮ点で並列接続する。 Further, the legs 802u, v, and w are connected in parallel at the P point and the N point.
直流端子Ｐ点とＮ点の間には，直流装置８０６が接続されている。直流装置８０６は，例えば直流負荷，直流電源，他の交直変換装置等である。例えば，直流送電線を介して他の交直変換装置を接続すれば，電力変換装置８０１と直流装置８０６はＨＶＤＣシステムを構成する。 A DC device 806 is connected between the DC terminals P and N. The DC device 806 is, for example, a DC load, a DC power source, another AC / DC converter, or the like. For example, if another AC / DC converter is connected via a DC power transmission line, the power converter 801 and the DC device 806 constitute an HVDC system.
中央制御手段８１０は、各単位変換器１からコンデンサ電圧VCuk、VCvk、VCwk（入力信号112）を通信で入手して、これに基づいて演算を行い、各単位変換器１に対して電圧指令guk、gvk、gwk(出力信号111)を通信で供給する。 The central control means 810 obtains capacitor voltages VCuk, VCvk, VCwk (input signal 112) from each unit converter 1 through communication, performs an operation based on this, and sends a voltage command guk to each unit converter 1. , Gvk, gwk (output signal 111) are supplied by communication.
このように各単位変換器１の出力を制御することでレグ８０２ｕ，ｖ，ｗの出力電圧を制御し、その結果、交流系統１０１の電力に直流に電力変換して（あるいはその逆に）直流端子Ｐ点、Ｎ点を介して直流送電（受電）を行う。 In this way, by controlling the output of each unit converter 1, the output voltage of the legs 802u, v, w is controlled, and as a result, the power of the AC system 101 is converted to DC (or vice versa). Direct current power transmission (power reception) is performed via terminals P and N.
図２に単位変換器１の構成図を示す（U相を例として説明する。他の相も同様であるので説明は省略する）。単位変換器制御回路１５は、いわゆるPWM(Pulse-Width Modulation)制御を行う。すなわち、単位変換器制御回路１５は、電源１７から電力の供給を受けて、中央制御手段８１０から受けた電圧指令guk（V相；gvk、W相；gwk）を搬送波（単位変換器制御回路１５内部で生成）と比較してパルスを生成してゲートドライバ１６に供給する。PWM制御している場合，単位変換器１毎の搬送波の位相を適切にシフトすることによって出力電圧波形をマルチレベル波形にできる。これによって，２レベル変換器に比較して高調波成分を低減できる。 FIG. 2 shows a configuration diagram of the unit converter 1 (the U phase will be described as an example. The other phases are the same and will not be described). The unit converter control circuit 15 performs so-called PWM (Pulse-Width Modulation) control. That is, the unit converter control circuit 15 receives power supply from the power supply 17 and receives the voltage command guk (V phase; gvk, W phase; gwk) received from the central control means 810 as a carrier wave (unit converter control circuit 15 Compared with (generated internally), a pulse is generated and supplied to the gate driver 16. When PWM control is performed, the output voltage waveform can be converted into a multilevel waveform by appropriately shifting the phase of the carrier wave for each unit converter 1. As a result, harmonic components can be reduced as compared with the two-level converter.
単位変換器１は，スイッチング素子である上アームのプレスパック素子１１ａ−２、下アームのプレスパック素子１１ｂ−２，上アームの還流ダイード１１ａ−１、下アームの還流ダイオード１１ｂ−１，直流コンデンサ１２を有する，いわゆる双方向チョッパ構成の主回路であり，単位変換器制御回路１５，ゲートドライバ１６，電源１７により構成されている。単位変換器１の出力端子は２つあるが，高電位側の出力端子を２００Ｐ，低電位側の出力端子を２００Ｎとする。 The unit converter 1 includes an upper arm press pack element 11a-2, a lower arm press pack element 11b-2, an upper arm reflux diode 11a-1, a lower arm reflux diode 11b-1, and a DC capacitor. 12 is a main circuit having a so-called bidirectional chopper configuration, and includes a unit converter control circuit 15, a gate driver 16, and a power supply 17. The unit converter 1 has two output terminals. The output terminal on the high potential side is 200P and the output terminal on the low potential side is 200N.
上アームのプレスパック素子１１ａ−２がオン状態であり、下アームのプレスパック素子１１ｂ−２がオフ状態である場合、単位変換器１のアーム電流に関わらず、出力電圧は、概ねコンデンサ電圧ＶＣｖｋと等しくなる。 When the upper arm press pack element 11a-2 is in the on state and the lower arm press pack element 11b-2 is in the off state, the output voltage is approximately the capacitor voltage VCvk regardless of the arm current of the unit converter 1. Is equal to
ただし、アーム電流が正の場合(端子200Ｎから端子200P方向を正とする)は、コンデンサ１２に蓄積されたエネルギーが放電される。また、アーム電流が負の場合は、コンデンサ１２にエネルギーが蓄積(充電)される。 However, when the arm current is positive (the direction from the terminal 200N to the terminal 200P is positive), the energy accumulated in the capacitor 12 is discharged. When the arm current is negative, energy is stored (charged) in the capacitor 12.
上アームのプレスパック素子１１ａ−２がオフ状態であり、下アームのプレスパック素子１１ｂ−２がオン状態である場合、アーム電流関わらず、出力電圧ＶＣｖｋは、概ね零と等しくなる。この場合、コンデンサ１２のエネルギーは変化しない。 When the upper arm press pack element 11a-2 is in an off state and the lower arm press pack element 11b-2 is in an on state, the output voltage VCvk is substantially equal to zero regardless of the arm current. In this case, the energy of the capacitor 12 does not change.
上アームのプレスパック素子１１ａ−２、および下アームのプレスパック素子１１ｂ−２が両方ともオフ状態である場合、アーム電流が正の時は、出力電圧は、概ね零と等しくなる。また、アーム電流が負の時は、出力電圧は概ねコンデンサ電圧VCＶkと等しくなる。この時、コンデンサ１２にエネルギーが蓄積(充電)される。 When both the upper arm press pack element 11a-2 and the lower arm press pack element 11b-2 are in the OFF state, the output voltage is approximately equal to zero when the arm current is positive. When the arm current is negative, the output voltage is approximately equal to the capacitor voltage VCVk. At this time, energy is stored (charged) in the capacitor 12.
プレスパック１１ａ−２のコレクタと，プレスパック１１ａ−２，１１ｂ−２のゲート２１ａ，２１ｂの間には，過電圧検出回路５０を接続する。過電圧検出回路５０は，過電圧検出素子５１ａと抵抗器５２ａからなる直列体がプレスパック１１ａ−２のゲート２１ａに接続し，且つ過電圧検出素子５１ｂと抵抗器５２ｂからなる直列体がプレスパック１１ｂ−２のゲート２１ｂに接続した構成となる。また，プレスパック１１ａ−２のゲート２１ａとエミッタ（ゲート帰線２２ａ）の間には，ゲート電圧クランプ回路６０ａが接続され，プレスパック１１ｂ−２のゲート２１ｂとエミッタ（ゲート帰線２２ｂ）の間には，ゲート電圧クランプ回路６０ｂが接続される。 An overvoltage detection circuit 50 is connected between the collector of the press pack 11a-2 and the gates 21a and 21b of the press packs 11a-2 and 11b-2. In the overvoltage detection circuit 50, a series body including the overvoltage detection element 51a and the resistor 52a is connected to the gate 21a of the press pack 11a-2, and a series body including the overvoltage detection element 51b and the resistor 52b is connected to the press pack 11b-2. This is connected to the gate 21b. A gate voltage clamp circuit 60a is connected between the gate 21a and the emitter (gate return line 22a) of the press pack 11a-2, and between the gate 21b and the emitter (gate return line 22b) of the press pack 11b-2. Is connected to the gate voltage clamp circuit 60b.
図３はプレスパック素子（１１ａ−２、１１ｂ−２）の構成を示す。２極のプレスパック素子の電極導体７７７に，プレスパック素子の半導体６６６が挟まれた構成になっており，プレスパック素子の電極導体７７７どうしが何らかの機構で互いに引き寄せ合う方向の応力が印加されていることを特徴とする。プレスパック素子の電極導体７７７を外部機構で押してもよいし，プレスパック素子の電極導体７７７の内側から引き合う形の応力を加えてもよい。プレスパック素子の電極導体７７７どうしが互いに引き寄せ合っていて，且つ故障時に発生する熱や短絡後に電流が導通することによって発生する熱を吸収する熱容量もしくは冷却系があれば，プレスパック素子の半導体６６６が故障した場合，プレスパック素子の半導体６６６は短絡となり，大電流を通流できる。すなわち、プレスパック素子の半導体６６６に所定以上の過電流（短絡閾電流値）が流れると、プレスパック素子の半導体６６６はその後は、どうようなゲート信号が入力するかを問わず、ＯＮ（短絡）状態を維持する。 FIG. 3 shows the configuration of the press pack elements (11a-2, 11b-2). The electrode conductor 777 of the two-pole press pack element is sandwiched between the semiconductors 666 of the press pack element, and stress in a direction in which the electrode conductors 777 of the press pack element are attracted to each other by some mechanism is applied. It is characterized by being. The electrode conductor 777 of the press pack element may be pushed by an external mechanism, or stress that attracts from the inside of the electrode conductor 777 of the press pack element may be applied. If there is a heat capacity or cooling system that absorbs heat generated when the electrode conductors 777 of the press pack element are attracted to each other and heat is generated at the time of failure or current is conducted after a short circuit, the semiconductor 666 of the press pack element is provided. If a failure occurs, the semiconductor 666 of the press pack element is short-circuited, and a large current can flow. That is, when an overcurrent (short-circuit threshold current value) of a predetermined level or more flows through the semiconductor 666 of the press pack element, the semiconductor 666 of the press pack element is turned ON (short circuit) regardless of what gate signal is input thereafter. ) Maintain state.
プレスパック素子１１ａ−２及び１１ｂ−２は，十分な冷却能力を持つか，十分な冷却能力を持つ冷却系から熱を引くことができることを前提として説明する。 The press pack elements 11a-2 and 11b-2 will be described on the assumption that they have sufficient cooling capacity or can draw heat from a cooling system having sufficient cooling capacity.
次に，メカニズムと効果を説明する。ゲートドライバ１６は，単位変換器制御回路１５から伝達された信号に基づき，プレスパック素子１１ａ−２及び１１ｂ−２を交互にオンオフ制御する。この制御により，出力端子２００Ｐに出力される電圧は，プレスパック素子１１ａ−２がオン，プレスパック素子１１ｂ−２がオフの時に直流コンデンサ１２の電圧を出力し，プレスパック素子１１ａ−２がオフ，プレスパック素子１１ｂ−２がオンの時に零を出力する。このように，通常の運転動作時は上アームと下アームのプレスパック素子が同時にオンはしない。 Next, the mechanism and effect will be explained. Based on the signal transmitted from the unit converter control circuit 15, the gate driver 16 alternately controls the press pack elements 11 a-2 and 11 b-2 on and off. With this control, the voltage output to the output terminal 200P is the voltage of the DC capacitor 12 when the press pack element 11a-2 is on and the press pack element 11b-2 is off, and the press pack element 11a-2 is off. , Outputs zero when the press pack element 11b-2 is on. Thus, during normal operation, the press pack elements of the upper arm and the lower arm are not turned on simultaneously.
ここで，電源１７の故障により単位変換器制御回路１５の電源が喪失した場合を想定する。また，ゲートドライバ１６は単位変換器制御回路１５からの信号が伝達されない場合にオフを出力する，いわゆるノーマリーオフで構成された回路であると想定する。電源の喪失により，ゲートドライバ１６からプレスパック素子１１ａ−２及びプレスパック素子１１ｂ−２に伝達される信号は，どちらもオフとなる。出力端子２００Ｐから出力端子２００Ｎに向かって電流が流れている時は，プレスパック素子１１ａ−２のダイオード１１ａ−１を通り，直流コンデンサ１２を通るため，直流コンデンサ１２の電圧が上昇する。
また，出力端子２００Ｎから出力端子２００Ｐに向かって電流が流れている時は，プレスパック素子１１ｂ−２のダイオード１１ｂ−１を通るため，直流コンデンサ１２の電圧は変化しない。このように，電源が喪失した状態で交流電流が流れると，直流コンデンサ１２の電圧を放電する経路がなくなるため，直流コンデンサ１２の電圧は上昇し続ける。
Here, it is assumed that the power source of the unit converter control circuit 15 is lost due to the failure of the power source 17. Further, it is assumed that the gate driver 16 is a circuit constituted by so-called normally-off which outputs OFF when a signal from the unit converter control circuit 15 is not transmitted. Due to the loss of power, both signals transmitted from the gate driver 16 to the press pack element 11a-2 and the press pack element 11b-2 are turned off. When current flows from the output terminal 200P toward the output terminal 200N, the voltage of the DC capacitor 12 rises because it passes through the diode 11a-1 of the press pack element 11a-2 and the DC capacitor 12.
Further, when a current flows from the output terminal 200N toward the output terminal 200P, the voltage of the DC capacitor 12 does not change because it passes through the diode 11b-1 of the press pack element 11b-2. Thus, when an alternating current flows in a state where the power source is lost, there is no path for discharging the voltage of the DC capacitor 12, so the voltage of the DC capacitor 12 continues to rise.
過電圧検出素子５１ｂは，直流コンデンサ１２の電圧が印加されるため，出力端子２００Ｐから出力端子２００Ｎに向かって電流が流れ，直流コンデンサ１２の電圧が上昇を続けると，いずれ閾値電圧に到達し短絡する。過電圧検出素子５１ｂが短絡すると，抵抗器５２ｂとゲート電圧クランプ回路６０ｂで分圧された電圧がゲート２１ｂに印加され，プレスパック素子１１ｂ−２がオンとなる。この時，出力端子２００Ｐから出力端子２００Ｎに向かって流れる電流はプレスパック素子１１ｂ−２に流れるため，直流コンデンサ１２の電圧はプレスパック素子１１ａ−２に印加される。過電圧検出素子５１ａは，プレスパック素子１１ａ−２の電圧が印加されるため短絡状態となり，抵抗器５２ａとゲート電圧クランプ回路６０ａで分圧された電圧がゲート２１ａに印加され，プレスパック素子１１ａ−２がオンとなる。プレスパック素子１１ａ−２と１１ｂ−２は両方がオンとなり，直流コンデンサ１２が短絡状態となるため，短絡電流が流れる。短絡電流によりプレスパック素子１１ａ−２とプレスパック素子１１ｂ−２は故障し，短絡状態となることで，出力端子２００Ｐと出力端子２００Ｎは電流の通電が可能となり，変換器の運転が継続される。 Since the voltage of the DC capacitor 12 is applied to the overvoltage detection element 51b, when a current flows from the output terminal 200P toward the output terminal 200N and the voltage of the DC capacitor 12 continues to rise, it eventually reaches the threshold voltage and short-circuits. . When the overvoltage detection element 51b is short-circuited, the voltage divided by the resistor 52b and the gate voltage clamp circuit 60b is applied to the gate 21b, and the press pack element 11b-2 is turned on. At this time, since the current flowing from the output terminal 200P toward the output terminal 200N flows to the press pack element 11b-2, the voltage of the DC capacitor 12 is applied to the press pack element 11a-2. The overvoltage detection element 51a is short-circuited because the voltage of the press pack element 11a-2 is applied, and the voltage divided by the resistor 52a and the gate voltage clamp circuit 60a is applied to the gate 21a, and the press pack element 11a- 2 is turned on. Since both the press pack elements 11a-2 and 11b-2 are turned on and the DC capacitor 12 is short-circuited, a short-circuit current flows. The short circuit current causes the press pack element 11a-2 and the press pack element 11b-2 to break down, resulting in a short circuit state, so that the output terminal 200P and the output terminal 200N can be energized, and the operation of the converter is continued. .
図４に第２の実施例を示す。過電圧検出素子５１は，直流コンデンサ１２の電圧が印加され，直流コンデンサ１２の電圧が閾値電圧に到達すると短絡する。過電圧検出回路５０に印加される直流コンデンサ１２の電圧は，おおよそ抵抗器５３と抵抗器５４により分圧される。実施例１と同様に，抵抗器５２ｂとゲート電圧クランプ回路６０ｂで分圧された電圧がゲート２１ｂに印加されることで，プレスパック素子１１ｂ−２がオンになると同時に，プレスパック素子１１ａ−２がオンとなる。即ち，プレスパック素子１１ａ−２と１１ｂ−２は両方がオンとなり，直流コンデンサ１２が短絡状態となり，プレスパック素子が短絡故障することで変換器の運転が継続される。また，プレスパック素子１１ｂ−２がオンするまでの間，逆流防止のためのダイオード５５が設けられている。 FIG. 4 shows a second embodiment. The overvoltage detection element 51 is short-circuited when the voltage of the DC capacitor 12 is applied and the voltage of the DC capacitor 12 reaches the threshold voltage. The voltage of the DC capacitor 12 applied to the overvoltage detection circuit 50 is approximately divided by the resistor 53 and the resistor 54. As in the first embodiment, the voltage divided by the resistor 52b and the gate voltage clamp circuit 60b is applied to the gate 21b, so that the press pack element 11b-2 is turned on and at the same time the press pack element 11a-2 is turned on. Is turned on. That is, both the press pack elements 11a-2 and 11b-2 are turned on, the DC capacitor 12 is short-circuited, and the operation of the converter is continued when the press pack element is short-circuited. Further, a diode 55 for preventing backflow is provided until the press pack element 11b-2 is turned on.
図５に，第２の実施例の変形例の１つを示す。本実施例は，過電圧検出後のプレスパック素子短絡を高速化するものである。 FIG. 5 shows one modified example of the second embodiment. This embodiment speeds up the short circuit of the press pack element after the overvoltage is detected.
本実施例は，直流コンデンサ１２に通常動作時の電圧が印加されている状態で，スピードアップコンデンサ１０３をあらかじめ充電している。直流コンデンサ１２が過電圧となり，過電圧検出素子５１ｃが短絡すると，スピードアップコンデンサ１０３の電圧が第二の過電圧検出素子５１ｄに印加されると共に，第二の過電圧検出素子５１ｄが短絡するように抵抗器５３，抵抗器５４，抵抗器１００，抵抗器１０１を構成する。スピードアップコンデンサ１０３の電荷は，ダイオード１０２を介して放電されるため，第２の実施例よりも高速にプレスパック素子のゲートをオンにすることができる。 In the present embodiment, the speed-up capacitor 103 is charged in advance in a state where the voltage during normal operation is applied to the DC capacitor 12. When the DC capacitor 12 becomes overvoltage and the overvoltage detection element 51c is short-circuited, the voltage of the speed-up capacitor 103 is applied to the second overvoltage detection element 51d, and the resistor 53 so that the second overvoltage detection element 51d is short-circuited. , Resistor 54, resistor 100, and resistor 101. Since the charge of the speed-up capacitor 103 is discharged through the diode 102, the gate of the press pack element can be turned on faster than in the second embodiment.
以上のように，過電圧によるMMC単位変換器の絶縁破壊や直流コンデンサの故障を回避し，電力変換装置の確実な運転継続を可能とする。
As described above, it is possible to avoid the breakdown of the MMC unit converter and the failure of the DC capacitor due to overvoltage, and to continue the operation of the power converter reliably.
１ 単位変換器
１１ａ−２ プレスパック素子
１１ｂ−２ プレスパック素子
１２ 直流コンデンサ
１５ 単位変換器制御回路
１６ ゲートドライバ
１７ 電源
２００Ｐ 出力端子
２００Ｎ 出力端子
２１ａ ゲート
２１ｂ ゲート
２２ａ ゲート帰線
２２ｂ ゲート帰線
５０ 過電圧検出回路
５１ 過電圧検出素子
５１ａ 過電圧検出素子
５１ｂ 過電圧検出素子
５１ｃ 過電圧検出素子
５１ｄ 過電圧検出素子
５２ａ 抵抗器
５２ｂ 抵抗器
５３ 抵抗器
５４ 抵抗器
５５ ダイオード
６０ａ ゲート電圧クランプ回路
６０ｂ ゲート電圧クランプ回路
１００ 抵抗器
１０１ 抵抗器
１０２ ダイオード
１０３ スピードアップコンデンサ
６６６ 半導体
７７７ 電極導体
1 Unit converter 11a-2 Press pack element 11b-2 Press pack element 12 DC capacitor 15 Unit converter control circuit 16 Gate driver 17 Power supply 200P Output terminal 200N Output terminal 21a Gate 21b Gate 22a Gate return line 22b Gate return line 50 Overvoltage Detection circuit 51 Overvoltage detection element 51a Overvoltage detection element 51b Overvoltage detection element 51c Overvoltage detection element 51d Overvoltage detection element 52a Resistor 52b Resistor 53 Resistor 54 Resistor 55 Diode 60a Gate voltage clamp circuit 60b Gate voltage clamp circuit 100 Resistor 101 Resistor 102 Diode 103 Speed-up capacitor 666 Semiconductor 777 Electrode conductor
Claims (10)
A power conversion device including one or a plurality of unit converters connected in series, wherein at least one of the unit converters conducts and cuts off a terminal, a capacitor, and the terminal and the capacitor. First and second switching elements connected in series, and first and second diodes connected in parallel to each of the first and second switching elements, the first and second switching elements The element is short-circuited when an overcurrent exceeding a predetermined value flows, and the capacitor and the gate of the first switching element can be connected and the capacitor and the gate of the second switching element can be connected. A conduction circuit, and when the capacitor is in an overvoltage state, the conduction is performed so that an overcurrent exceeding a predetermined value flows in the first and second switching elements. Power converter, characterized by a road in a conductive state.
2. The overvoltage detection circuit according to claim 1, wherein a collector of the first switching element, a gate of the first switching element, and a gate of the second switching element are connected via the overvoltage detection circuit. A power conversion apparatus comprising: a gate voltage clamp circuit connecting a gate and an emitter of the first switching element and the second switching element.
3. The overvoltage detection circuit according to claim 2, wherein the overvoltage detection circuit includes one or a plurality of voltage detection elements connected to the gate of the first switching element and the gate of the second switching element, and a resistor. The power conversion device, wherein the detection element and the resistor are connected in series.
3. The overvoltage detection circuit according to claim 2, wherein the overvoltage detection circuit has one or a plurality of voltage detection elements, and the low voltage side of the voltage detection element has at least two resistors and a voltage clamp element connected in parallel, One resistor is connected to the gate of the press pack element of the lower arm and the other resistor is connected to the anode of a diode having a cathode connected to the gate of the press pack element of the upper arm; The power conversion device, wherein the voltage clamp element is connected to an emitter of the second switching element.
4. The overvoltage detection circuit according to claim 2, wherein the overvoltage detection circuit is a Zener diode, a breakover diode, or a breakover thyristor, and the cathode of the voltage detection element is connected to the high potential side and the anode is connected to the low potential side. The power converter characterized by this.
5. The power conversion device according to claim 4, wherein the gate voltage clamp element is constituted by a resistor.
5. The power converter according to claim 4, wherein the gate voltage clamp element is a Zener diode, and an anode of the Zener diode is connected to an emitter of the press pack element of the lower arm.
3. The power converter according to claim 2, wherein the gate voltage clamp circuit is constituted by a resistor or a varistor element.
3. The gate voltage clamp circuit according to claim 2, wherein two Zener diodes are connected in series, one of the Zener diodes has an anode connected to the gate wiring, and the other Zener diode has an anode connected to the gate wiring. A power converter connected to a gate return line, wherein the cathodes of the Zener diodes are connected to each other.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105207504A (en) * | 2015-10-09 | 2015-12-30 | 中国南方电网有限责任公司超高压输电公司检修试验中心 | Half-bridge and full-bridge mixed type MMC topology with voltage enhancement characteristic |
| CN105245117A (en) * | 2015-11-09 | 2016-01-13 | 南京南瑞继保电气有限公司 | Modular multilevel converter and converter module |
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| JP2017195682A (en) * | 2016-04-19 | 2017-10-26 | 東芝三菱電機産業システム株式会社 | Power converter |
| JP2017216808A (en) * | 2016-05-31 | 2017-12-07 | 東芝三菱電機産業システム株式会社 | Power conversion device |
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| JP2018107888A (en) * | 2016-12-26 | 2018-07-05 | 東芝三菱電機産業システム株式会社 | Controller and method for semiconductor device and power converter |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008043003A (en) * | 2006-08-03 | 2008-02-21 | Fuji Electric Systems Co Ltd | Gate drive unit of voltage-driven type semiconductor element |
| JP2010135656A (en) * | 2008-12-08 | 2010-06-17 | Rohm Co Ltd | Electrostatic breakdown protection circuit and semiconductor integrated circuit device with same |
| JP2012515522A (en) * | 2009-01-16 | 2012-07-05 | エービービー テクノロジー アーゲー | Fault protection of voltage source converters with redundant switching cells by mechanical switches closed by sparks |
| JP2013110515A (en) * | 2011-11-18 | 2013-06-06 | Denso Corp | Circuit for driving power semiconductor element |
| JP2015115975A (en) * | 2013-12-09 | 2015-06-22 | 東芝三菱電機産業システム株式会社 | Power converter |
-
2014
- 2014-02-28 JP JP2014037694A patent/JP6334201B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008043003A (en) * | 2006-08-03 | 2008-02-21 | Fuji Electric Systems Co Ltd | Gate drive unit of voltage-driven type semiconductor element |
| JP2010135656A (en) * | 2008-12-08 | 2010-06-17 | Rohm Co Ltd | Electrostatic breakdown protection circuit and semiconductor integrated circuit device with same |
| JP2012515522A (en) * | 2009-01-16 | 2012-07-05 | エービービー テクノロジー アーゲー | Fault protection of voltage source converters with redundant switching cells by mechanical switches closed by sparks |
| JP2013110515A (en) * | 2011-11-18 | 2013-06-06 | Denso Corp | Circuit for driving power semiconductor element |
| JP2015115975A (en) * | 2013-12-09 | 2015-06-22 | 東芝三菱電機産業システム株式会社 | Power converter |
Cited By (14)
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|---|---|---|---|---|
| CN105207504A (en) * | 2015-10-09 | 2015-12-30 | 中国南方电网有限责任公司超高压输电公司检修试验中心 | Half-bridge and full-bridge mixed type MMC topology with voltage enhancement characteristic |
| CN105245117A (en) * | 2015-11-09 | 2016-01-13 | 南京南瑞继保电气有限公司 | Modular multilevel converter and converter module |
| CN105591562A (en) * | 2016-03-02 | 2016-05-18 | 广州供电局有限公司 | Modularization multi-level current transformer |
| CN105591562B (en) * | 2016-03-02 | 2018-07-20 | 广州供电局有限公司 | modular multi-level converter |
| JP2017195682A (en) * | 2016-04-19 | 2017-10-26 | 東芝三菱電機産業システム株式会社 | Power converter |
| JP2017216808A (en) * | 2016-05-31 | 2017-12-07 | 東芝三菱電機産業システム株式会社 | Power conversion device |
| JP2018107888A (en) * | 2016-12-26 | 2018-07-05 | 東芝三菱電機産業システム株式会社 | Controller and method for semiconductor device and power converter |
| CN106786724A (en) * | 2017-01-23 | 2017-05-31 | 浙江大学 | A kind of control strategy of many times MMC HVDC feed-ins pole light current net |
| CN106786724B (en) * | 2017-01-23 | 2019-05-28 | 浙江大学 | A kind of control strategy of more times MMC-HVDC feed-ins pole weak grid |
| CN107196539A (en) * | 2017-06-23 | 2017-09-22 | 西安交通大学 | A kind of MMC zero DC voltage fault traversing control methods under bridge arm parameter unbalance state |
| CN107508267A (en) * | 2017-09-20 | 2017-12-22 | 国家电网公司 | A kind of modularization multi-level converter of voltage source converter submodule unit and its composition |
| US10840903B2 (en) | 2018-09-14 | 2020-11-17 | Kabushiki Kaisha Toshiba | Semiconductor module |
| CN116961440A (en) * | 2023-05-25 | 2023-10-27 | 国网湖北省电力有限公司经济技术研究院 | Method, device and equipment for suppressing short-circuit current of direct-current port of power electronic transformer |
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