JP2015162003A - Processor management apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a configuration capable of analyzing an event that occurs to a processor without providing a dedicated hardware in the processor.SOLUTION: If a PM mechanism 40 incorporated in a processor 100 detects the occurrence of a specific even during execution of a program by the processor 100, a PM interruption handler 400 is activated in response to an interruption from the PM mechanism 40 and receives processor state information indicating a state of the processor 100 during the occurrence of the specific event. An address locating unit 600 locates a memory address that causes the occurrence of the specific event using a program 800 and the processor state information.

Description

  The present invention relates to a technique for analyzing events occurring in a processor.

In a processor mounted on a conventional embedded system, a performance monitor mechanism (PM mechanism) is incorporated as a mechanism for analyzing the operating state of hardware.
The PM mechanism can measure the number of instructions executed and the number of events such as the number of cache misses, and analyzes the operation of the program.
In an embedded system, since cyclic processing is repeated, an event that occurs once often occurs again in another cycle. Therefore, the number of events is collected over multiple cycles, and the program is analyzed based on this information. It was.
In particular, since a cache miss has a large effect on processing time, detailed information such as a cache missed address is required.
However, with a simple PM mechanism, it is difficult to collect detailed information such as a cache missed address, and in order to perform a detailed analysis of the program, a history recording unit is provided as dedicated hardware in the processor to make a cache miss. A method for obtaining address information has been proposed (Patent Document 1).

JP 2010-218367 A

In order to obtain detailed information of an address where a cache miss has occurred in a conventional processor, there has been a problem that a history recording unit must be provided in the processor as dedicated hardware.
The main object of the present invention is to solve the above-described problems, and it is a main object of the present invention to obtain a configuration that can analyze an event occurring in a processor without providing dedicated hardware in the processor. .

The processor management device according to the present invention is:
When the performance monitor mechanism incorporated in the processor detects that a specific event has occurred during the execution of the program by the processor, it is activated by an interrupt from the performance monitor mechanism, and when the specific event occurs An interrupt handler for receiving processor state information indicating the state of the processor;
An address specifying unit that specifies a memory address that caused the specific event using the program and the processor state information.

  According to the present invention, the processor status information is received by an interrupt from the performance monitor mechanism, and the processor address information and the received program are used to identify the memory address that generated the specific event. Events that occur in the processor can be analyzed without providing hardware.

2 is a diagram illustrating a configuration example of a processor and a processor management device according to Embodiment 1. FIG. FIG. 3 is a flowchart showing an operation example of a PM mechanism control unit according to the first embodiment. FIG. 4 is a flowchart showing an operation example of a PM interrupt handler according to the first embodiment. FIG. 6 is a diagram illustrating an operation example of a cache miss history recording unit according to the first embodiment. FIG. 6 is a diagram illustrating an operation example of an address specifying unit according to the first embodiment.

Embodiment 1 FIG.
Hereinafter, the present embodiment will be described with reference to the drawings.
In the present embodiment, a cache miss is taken as an example of an event that has occurred in the processor.

  FIG. 1 shows a configuration example of the processor 100 and the processor management device 700.

  In the processor 100, reference numeral 10 denotes a processor core unit that fetches and decodes instructions, executes instructions, and stores execution results.

11 is an instruction fetch request from the processor core unit 10.
Reference numeral 12 denotes information such as an instruction address referred to when the instruction fetch request 11 from the processor core unit 10 is valid.
Reference numeral 13 denotes an instruction code supplied to the processor core unit 10.
Reference numeral 14 denotes an operand access request from the processor core unit 10.
Reference numeral 15 denotes operand address and other information that is referred to when the operand access request 14 from the processor core unit 10 is valid.
Reference numeral 16 denotes operand data for writing from the processor core unit 10 or operand data for a read request from the processor core unit 10.

Reference numeral 20 denotes an instruction cache that receives an instruction fetch request 11 and an instruction address other information 12 from the processor core unit 10, refers to an internal cache memory, and supplies the fetched instruction code 13 to the processor core unit 10.
When the instruction cache 20 is not included in the instruction cache 20 as a result of searching the instruction cache 20 using the instruction fetch request 11 from the processor core unit 10 and the instruction address and other information 12, This is an instruction fetch request for requesting fetch.
Reference numeral 22 denotes information such as an instruction address referred to when the instruction fetch request 21 is valid.
Reference numeral 23 denotes an instruction code supplied to the instruction cache.
When a read request is made to the data cache 30, the internal cache memory is referred to and the extracted operand data 16 is supplied to the processor core unit 10.

Reference numeral 30 denotes a data cache unit that accepts operand access request 14 (read or write) from the processor core unit 10, operand address and other information 15, and operand data 16 in a write request, and writes it to the internal cache memory.
34, if the result of searching the inside of the data cache 30 with the operand access request 14 from the processor core unit 10 and the operand address and other information 15 is not included in the data cache 30, operand access is made to the upper cache memory. Operand access request to request.
Reference numeral 35 denotes operand address and other information referred to when the operand access request 34 is valid.
Reference numeral 36 denotes an operand that moves between the data cache 30 and the upper cache or the memory controller 200.

Reference numeral 40 denotes a PM mechanism that monitors the occurrence of a set event and notifies the processor core unit 10 when the occurrence of the set number of times is detected.
In the PM mechanism 40, reference numeral 41 denotes a number measuring unit that measures the number of occurrences of an event selected by a selector 44 that selects an event to be monitored.
42 is an interrupt interval for setting a predetermined number of occurrences for generating a notification to the processor core unit 10.
Reference numeral 43 denotes a comparator that compares the value of the number counting unit 41 and the interrupt interval 42 and notifies the processor core unit 10 when they match.
A selector 44 selects either the instruction fetch request 21 or the operand access request 34.
Reference numeral 45 denotes a PM interrupt signal notified to the processor core unit 10 when the comparator 43 matches the value of the number counting unit 41 and the interrupt interval 42.

  Reference numeral 200 denotes a higher-level cache or a memory controller that is referred to when a cache miss occurs due to an instruction fetch in the instruction cache 20 or when a cache miss occurs when an operand is fetched and stored in the data cache 30.

  Reference numeral 700 denotes a processor management device that identifies a memory address that causes a specific event when a specific event (for example, a cache miss) occurs.

  In the processor management apparatus 700, 300 is a PM mechanism control unit that sets a specific event to be measured by the PM mechanism 40 in the selector 44 and sets a predetermined value in the interrupt interval 42.

Reference numeral 400 denotes a PM interrupt handler in which an interrupt notified by the PM mechanism 40 is recognized by the processor core unit 10 and a program is executed when a specific event occurs.
The PM interrupt handler 400 receives processor state information indicating the state of the processor when a specific event occurs from the processor core unit 10.
401 is a PM interrupt handler activation signal generated by the interrupt notified by the PM mechanism 40.

  Reference numeral 500 denotes a cache miss history recording unit in which the PM interrupt handler 400 stores processor state information.

  Reference numeral 600 denotes an address specifying unit that specifies the memory address that caused the cache miss using the processor state information stored in the cache miss history recording unit 500 and the program 800.

The PM mechanism control unit 300, the PM interrupt handler 400, and the address specifying unit 600 are realized by programs, for example.
A program for realizing the PM mechanism control unit 300, the PM interrupt handler 400, and the address specifying unit 600 is executed by the processor 100 or another processor in the embedded system, and the processing described below is performed.
The cache miss history recording unit 500 is realized by a register in the processor 100 or a RAM (Random Access Memory).

  Next, the operation will be described.

First, the PM mechanism control unit 300 sets an event to be measured by the PM mechanism 40 and determines a selection condition of the selector 44.
In addition, the PM mechanism control unit 300 sets the interrupt interval to the interrupt interval 42.
By setting the selector 44 and the interrupt interval 42, measurement of the number of events that need to be measured during program execution is started.

  A processing flow of the PM mechanism control unit 300 will be described with reference to FIG.

In S201, the PM mechanism control unit 300 determines an event to be measured and sets the selector 44.
In S202, the interrupt interval 42 is not set, and the number of occurrences of events in the cycle is measured.
In S203, the execution time of the PM interrupt handler 400 is measured.
In S204, an interrupt generation interval is determined from the number of occurrences of measurement events per period and the execution time of the PM interrupt handler 400, and the interrupt interval 42 is set.

The interrupt interval 42 is determined by any of the following methods (1) to (3).
(1) Number of executions of the PM interrupt handler that can be executed within the time margin of the periodic processing set in the embedded system For example, when the cycle is 1 ms, the margin is 5%, and the execution time of one PM interrupt handler is 5 u seconds 1 ms × 5% / 5 u seconds = 10 times.
This can be measured without changing the cycle time or the processing content.
However, if the number of events that occur in one cycle is large, it is necessary to collect data for a plurality of cycles and supplement the data.
The minimum number of cycles to be collected is the number of events that occur in one cycle / the number of PM interrupt handler executions.
(2) The interrupt count ratio according to the ratio to the number of events that occur within the period of the periodic processing set in the embedded system is changed according to the number of occurrences per cycle.
For example, when 2000 events occur in one cycle, the ratio is 1%, and 2000 × 1% = 20 times.
Further, when an event occurs 20 times in one cycle, the ratio is 10%, and 20 times × 10% = 2 times.
If the data collection overhead is equal to or greater than the time margin of the periodic processing, the periodic time and the processing content are corrected.
Since the ratio to the number of occurrences is determined, the minimum number of cycles to be collected is determined.
(3) Combination of (1) and (2) The optimum number is determined from the ratio to the number of occurrences and the execution time of the interrupt handler.

  Next, the processing flow of the PM interrupt handler 400 will be described with reference to FIG.

In step S301, the PM interrupt handler 400 saves a PC (program counter) for returning from an interrupt.
In S302, the PC and register contents are recorded in the cache miss history recording unit 500.
In S303, the PC saved (S301) for returning from the interrupt is set.
In S304, the process returns from the interrupt.

In S302, data to be recorded as processor state information differs depending on the measurement event.
In the instruction cache miss measurement, only the PC is recorded, and in the data cache miss measurement, the PC and register contents are recorded.
This is because an instruction cache miss results in an address where the PC has missed the cache, but a data cache miss requires analysis of the instruction code indicated by the PC and generation of an operand address.
Some processors hold a cache missed address and can be read from the program. In this case, the read address is recorded.

  A write operation to the cache miss history recording unit 500 during program execution will be described with reference to FIG.

The program to be measured is the program shown in FIG.
The program shown in FIG. 4 is stored at a memory address obtained by adding “0x0000” to the memory address stored in the register R2 when “LDR R13, R2, 0x0000” of “0x1010” is taken as an example. The content is that data is loaded into the register R2.
In FIG. 4, the measurement event is a data cache miss, and the interrupt generation interval is 2.

The load instruction at address 0x1010 (instruction to copy the memory contents to the register) hits the data cache.
In the load instruction at address 0x1020, a data cache miss occurs, and as a result, a PM interrupt signal 45 is output.
The PM interrupt handler 400 activated by the PM interrupt stores the PC and register contents (contents of all registers R0 to R15) in the cache miss history recording unit 500 as processor state information.
The load instruction at address 0x1030 causes a data cache miss, but the interrupt interval is 2, and an interrupt is generated at the load instruction at address 0x1020. Therefore, in the data cache miss due to the load instruction at address 0x1030, the PM interrupt signal 45 is Not output.
A data cache miss occurs in the load instruction at address 0x1040, and as a result, a PM interrupt signal 45 is output.
The PM interrupt handler 400 activated by the PM interrupt stores the PC and register contents (contents of all registers R0 to R15) in the cache miss history recording unit 500 as processor state information.

  With reference to FIG. 5, a description will be given of the reproduction of an address where a data cache miss has occurred from the information recorded in the cache miss history recording unit 500 and the executed program.

The address specifying unit 600 specifies an instruction from the PC value recorded in the cache miss history recording unit 500 and the executed program 800.
In the example of FIG. 5, since PC = 0x1020, the address specifying unit 600 determines the instruction having a data cache miss as
LDR R15, R1, 0x1000
Is specified.
At this time, since the memory address referring to the data cache is generated from R1 + 0x1000, the address specifying unit 600 determines that 0x00011000 obtained by adding the contents of R1 (0x00010000) and 0x1000 is the address where the data cache miss occurred. Identify.

Next, since the record recorded in the cache miss history recording unit 500 is PC = 0x1040, the address specifying unit 600 determines the instruction that caused the data cache miss as follows:
LDR R14, R15, 0x2000
Is specified.
At this time, since the address referring to the data cache is generated from R15 + 0x2000, the address specifying unit 600 specifies that 0x00004000 obtained by adding the contents of R15 (0x00002000) and 0x2000 is the address that caused the data cache miss. To do.
A method for generating an address for referring to a memory is defined for each processor architecture, and according to the definition, an address in which a data cache miss is generated is generated.

  As described above, an event to be measured such as a cache miss and an interrupt interval are set at the time of program execution, and a register and a PC used for address generation are recorded when a PM interrupt occurs. And the address where the cache miss occurred can be generated from the recorded information.

  10 processor core, 11 instruction fetch request, 12 instruction address and other information, 13 instruction code, 14 operand access request, 15 operand address and other information, 16 operand data, 20 instruction cache, 21 instruction fetch request, 22 instruction address and others Information, 23 instruction code, 30 data cache, 34 operand access request, 35 operand address and other information, 36 operand data, 40 PM mechanism, 41 count unit, 42 interrupt interval, 43 comparator, 44 selector, 100 processor, 200 upper cache or memory controller, 300 PM mechanism control unit, 400 PM interrupt handler, 500 cache miss history recording unit, 600 address specifying unit, 700 processor management device, 800 Program.

Claims (6)

When the performance monitor mechanism incorporated in the processor detects that a specific event has occurred during the execution of the program by the processor, it is activated by an interrupt from the performance monitor mechanism, and when the specific event occurs An interrupt handler for receiving processor state information indicating the state of the processor;
A processor management apparatus, comprising: an address specifying unit that specifies a memory address that causes the specific event using the program and the processor state information. The interrupt handler is
When the performance monitor mechanism detects that an instruction cache miss has occurred during execution of a program by the processor, the processor status information receives a value of a program counter at the time of occurrence of the instruction cache miss,
The address specifying unit includes:
The processor management apparatus according to claim 1, wherein a memory address at which the instruction cache miss has occurred is specified using the program and the value of the program counter. The interrupt handler is
When the performance monitor mechanism detects that a data cache miss has occurred during execution of a program by the processor, the processor status information includes a value of a program counter when the data cache miss occurs, Receives the memory address stored in the register used for execution,
The address specifying unit
2. The processor management apparatus according to claim 1, wherein the memory address causing the data cache miss is specified using the program, the value of the program counter, and the memory address stored in the register. . The processor management device further includes:
The processor management apparatus according to claim 1, further comprising a performance monitor mechanism control unit configured to set an interrupt generation frequency in the performance monitor mechanism. The performance monitor mechanism controller is
5. The processor management according to claim 4, wherein a frequency of an interrupt calculated based on a margin time of periodic processing performed by the processor and an execution time of the interrupt handler is set in the performance monitor mechanism. apparatus. The performance monitor mechanism controller is
5. The processor management apparatus according to claim 4, wherein an interrupt frequency calculated based on an occurrence frequency of the specific event in the periodic processing performed by the processor is set in the performance monitor mechanism.

Images