JP2015159252A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the high frequency characteristics of a semiconductor device using the electron tunneling effect.SOLUTION: A semiconductor device comprises: a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; an insulating film formed on side surfaces of the second and third semiconductor layers; a gate electrode formed so as to be in contact with the insulating film; a source electrode formed on the first semiconductor layer; and a drain electrode formed on the fourth semiconductor layer. The first and fourth semiconductor layers are formed of a first-conductivity-type semiconductor material. The third semiconductor layer is formed of a second-conductivity-type semiconductor material.

Description

  The present invention relates to a semiconductor device.

  In the semiconductor device, there is a field effect transistor typified by CMOS or the like using Si as a semiconductor material. In such a CMOS using Si, the characteristics can be improved by shortening the gate length, but there is a limit in terms of semiconductor material and structure, and an increase in subthreshold current, Problems such as an increase in voltage difference during switching occur.

For this reason, a semiconductor device using an electron tunnel effect is disclosed as a semiconductor device having a structure in which these problems do not occur (for example, Non-Patent Document 1). In this semiconductor device, as shown in FIG. 1, a p ⁺ region 921 is formed on the surface of a semiconductor substrate 910 by doping a p-type impurity element at a high concentration on the side where the source electrode 942 is formed. The n ⁺ region 923 is formed by doping the n-type impurity element at a high concentration on the side where the drain electrode 943 is formed. An i region 922 that is not doped with an impurity element is formed between the p ⁺ region 921 and the n ⁺ region 923, and a gate insulating film 930 is formed on the i region 922. A gate electrode 941 is formed on the gate insulating film 930. Note that a source electrode 942 is formed on the p ⁺ region 921, and a drain electrode 943 is formed on the n ⁺ region 923.

FIG. 2 is an energy band diagram of the semiconductor device having the structure shown in FIG. As shown in FIG. 2, the energy level in the i region 922 can be controlled by controlling the potential applied to the gate electrode 941, and electrons transmitted from the p ⁺ region 921 to the i region 922 by the tunnel effect. Can be controlled. In this way, the tunnel current that flows due to electrons transmitted through the tunnel effect rises more steeply than the normal diffusion current, and when it is off, the current flow can be cut off, thus preventing an increase in subthreshold current and the like. it can.

JP 2011-100706 A JP 2011-238909 A

Appl. Phys. Lett. 67, 494 (1995)

  However, in the semiconductor device having the structure shown in FIG. 1, since a high-concentration pn junction is formed between the source and the drain, the capacitance Cds between the source electrode 942 and the drain electrode 943 is increased, and can cope with high frequency. Have difficulty.

  Therefore, there is a demand for a semiconductor device that has good high-frequency characteristics in a semiconductor device that uses the tunneling effect of electrons.

  According to one aspect of this embodiment, a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, and the second semiconductor layer A third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; and a side surface of the second semiconductor layer and the third semiconductor layer. An insulating film, a gate electrode formed in contact with the insulating film, a source electrode formed on the first semiconductor layer, a drain electrode formed on the fourth semiconductor layer, The first semiconductor layer and the fourth semiconductor layer are made of a first conductive type semiconductor material, and the third semiconductor layer is made of a second conductive type semiconductor material. It is formed.

  According to the disclosed semiconductor device, high-frequency characteristics can be improved in the semiconductor device using the electron tunnel effect.

Structure diagram of transistor using tunnel effect (1) Energy band diagram of the transistor having the structure shown in FIG. Transistor structure using tunnel effect (2) Energy band diagram of the transistor having the structure shown in FIG. Structure diagram of the semiconductor device in the first embodiment Energy band diagram of semiconductor device in first embodiment Structure diagram of the semiconductor device in which the n ⁺ layer is not formed in the first embodiment Energy band diagram of semiconductor device in which n ⁺ layer is not formed in the first embodiment Manufacturing Process Diagram of Semiconductor Device in First Embodiment (1) Manufacturing process diagram of semiconductor device in first embodiment (2) Manufacturing process diagram of semiconductor device in first embodiment (3) Manufacturing process diagram of semiconductor device in first embodiment (4) Manufacturing process diagram of semiconductor device in first embodiment (5) Structural diagram of another semiconductor device according to the first embodiment Structure diagram of semiconductor device according to second embodiment Energy band diagram of semiconductor device according to second embodiment Structure diagram of semiconductor device according to third embodiment Energy band diagram of semiconductor device according to third embodiment Structure diagram of semiconductor device according to fourth embodiment Energy band diagram of semiconductor device according to fourth embodiment Manufacturing Process Diagram of Semiconductor Device in Fourth Embodiment (1) Manufacturing process diagram of semiconductor device in fourth embodiment (2) Manufacturing process diagram of semiconductor device in fourth embodiment (3) Manufacturing process diagram of semiconductor device in fourth embodiment (4) Manufacturing process diagram of semiconductor device according to fourth embodiment (5) Structure diagram of semiconductor device according to fifth embodiment Energy band diagram of semiconductor device according to fifth embodiment

  The form for implementing is demonstrated below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
Incidentally, when a semiconductor device having the structure shown in FIG. 1 is manufactured, a manufacturing process is extremely complicated by a plurality of compound semiconductor materials having different compositions. Therefore, it is difficult to manufacture a semiconductor device having a desired structure. Therefore, as a semiconductor device having a structure that can be easily manufactured in a semiconductor device using the electron tunnel effect, as shown in FIG. 3, a vertical semiconductor device in which semiconductor layers are stacked in the film thickness direction is used. Can be mentioned.

In the semiconductor device shown in FIG. 3, an i-type layer 962 is formed of i-InGaAs on one surface of a p ⁺ -type substrate 961 formed of p ⁺ -GaAsSb. The n ⁺ -type layer 963 is formed of n ⁺ -GaAsSb. The i-type layer 962 and the n ⁺ -type layer 963 are formed in a mesa shape on a part of one surface of the p ⁺ -type substrate 961. Further, an insulating film 970 serving as a gate insulating film is formed on the exposed surface of the p ⁺ type substrate 961 and the side surfaces on both sides of the i type layer 962 and the n ⁺ type layer 963 formed in a mesa shape. Yes. The gate electrode 981 is formed through insulating films 970 formed on both side surfaces of the i-type layer 962. That is, the insulating film 970 is formed on the side surface of the i-type layer 962 formed in a mesa shape, and the gate electrode 981 is formed on the side surface of the insulating film 970 which is the side surface of the mesa in contact with the insulating film 970. ing. The source electrode 982 is formed on the other surface of the p ⁺ type substrate 961, and the drain electrode 983 is formed on the n ⁺ type layer 963.

The semiconductor device shown in FIG. 3, on one side of the ^{p +} -type substrate 961, is formed by sequentially laminating an ^{n +} -type layer 963 by the i-type layer ^962, n + -GaAsSb by i-InGaAs Yes. Therefore, even when the semiconductor device is formed of a plurality of semiconductor materials having different compositions and composition ratios, it can be easily manufactured by forming a film while changing the composition or the like during film formation. However, in the semiconductor device shown in FIG. 3 as well, the capacitance Cds between the source electrode 982 and the drain electrode 983 is large as in the semiconductor device having the structure shown in FIG. .

4 is an energy band diagram of the semiconductor device having the structure shown in FIG. As shown in FIG. 4, by controlling the potential applied to the gate electrode 981, the energy level in the i-type layer 962 can be controlled, and the tunneling effect can be applied from the p ⁺ -type substrate 961 to the i-type layer 962. The transmitted electrons can be controlled.

(Semiconductor device)
Next, the semiconductor device in the first embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 5, a buffer layer 11 is formed of i-InAlAs on a substrate 10, and a buffer layer 11 is formed of p ⁺ -GaAsSb on the buffer layer 11. One semiconductor layer 21 is formed. A part of the first semiconductor layer 21 serving as a p ⁺ type layer includes a second semiconductor layer 22 formed of i-InGaAs, a third semiconductor layer 23 formed of n ⁺ -InGaAs, p ^A fourth semiconductor layer 24 made of ⁺ -GaAsSb is sequentially stacked. Therefore, in the semiconductor device shown in FIG. 5, the second semiconductor layer 22 and the third semiconductor layer 23 are formed of a material having a narrower band gap than the first semiconductor layer 21 and the fourth semiconductor layer 24. Yes. In the present embodiment, the substrate 10 is made of semi-insulating InP.

third fourth semiconductor layer 24 of the semiconductor layer 23, p ⁺ -type layer serving as the second semiconductor layer 22, n ⁺ -type layer serving as the i-type layer, a first semiconductor layer comprising a p ⁺ -type layer It is formed in a mesa shape in a part on 21. The insulating film 30 serving as a gate insulating film is formed on the surface of the first semiconductor layer 21, the second semiconductor layer 22 formed in a mesa shape, the third semiconductor layer 23, and the side surfaces of the fourth semiconductor layer 24. Is formed.

The gate electrode 41 is formed via an insulating film 30 formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 23. That is, the insulating film 30 is formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 23 formed in a mesa shape, and the insulating film 30 is formed on the side surface of the insulating film 30 serving as the side surface of the mesa. A gate electrode 41 is formed in contact with 30. The source electrode 42, p ⁺ -type layer in which is formed on the first semiconductor layer 21, the drain electrode 43 is formed on the fourth semiconductor layer 24 is a p ⁺ -type layer Yes. In the present embodiment, the first semiconductor layer 21 is the first semiconductor region, the second semiconductor layer 22 is the second semiconductor region, the third semiconductor layer 23 is the third semiconductor region, The semiconductor layer 24 may be referred to as a fourth semiconductor region.

In the present embodiment, the p-type impurity element doped in the first semiconductor layer 21 and the fourth semiconductor layer 24 is Zn (zinc), Be (beryllium), or the like, which is 1 × 10 ¹⁸ cm. It is doped to a concentration of ⁻³ or higher. The n-type impurity element doped in the third semiconductor layer 23 is Si (silicon), Se (selenium), or the like, and is doped so as to have a concentration of 1 × 10 ¹⁷ cm ⁻³ or more. Yes. The second semiconductor layer 22 is not doped with an impurity element. For example, the concentration of the impurity element in the second semiconductor layer 22 is 1 × 10 ¹⁶ cm ⁻³ or less. In the semiconductor device in the present embodiment, for example, the first semiconductor layer 21 and the fourth semiconductor layer 24 are doped with Zn at a concentration of 2 × 10 ¹⁹ cm ⁻³ , and the third semiconductor layer 23 is doped with Se at a concentration of 1 × 10 ¹⁹ cm ⁻³ .

FIG. 6 is an energy band diagram of the semiconductor device in the present embodiment shown in FIG. 6A is an energy band diagram in an equilibrium state where no voltage is applied to the gate electrode 41, and FIG. 6B is an energy band diagram in a state where a voltage is applied to the gate electrode 41. FIG. FIG. As shown in FIG. 6, by controlling the voltage applied to the gate electrode 41, the energy levels in the second semiconductor layer 22 that becomes the i-type layer and the third semiconductor layer 23 that becomes the n ⁺ -type layer are changed. Can be controlled. That is, as shown in FIG. 6A, in the state where no voltage is applied to the gate electrode 41, the second semiconductor layer 22 that becomes an i-type layer and the third semiconductor layer that becomes an n ⁺ -type layer. 23 serves as a barrier, and no current flows between the first semiconductor layer 21 and the fourth semiconductor layer 24. On the other hand, as shown in FIG. 6B, by applying a voltage to the gate electrode 41, the second semiconductor layer 22 that becomes the i-type layer and the third semiconductor layer 23 that becomes the n ⁺ -type layer. The energy level at decreases. Thus, electrons are transmitted from the first semiconductor layer 21 to the second semiconductor layer 22 by the tunnel effect, and electrons are transmitted from the third semiconductor layer 23 to the fourth semiconductor layer 24 by the tunnel effect. Accordingly, a current flows between the first semiconductor layer 21 and the fourth semiconductor layer 24.

Next, the effect of forming the third semiconductor layer 23 to be an n ⁺ type layer will be described. FIG. 7 shows a structure of a semiconductor device in which the third semiconductor layer 23 to be an n ⁺ -type layer is not formed, and FIG. 8 is an energy band diagram in the semiconductor device having the structure shown in FIG. The semiconductor device having the structure shown in FIG. 7 has the same structure as that of the semiconductor device having the structure shown in FIG. 5 except that the third semiconductor layer 23 to be an n ⁺ type layer is not formed. . 8A is an energy band diagram in an equilibrium state where no voltage is applied to the gate electrode 41, and FIG. 8B is an energy band diagram in a state where a voltage is applied to the gate electrode 41. FIG. FIG.

As shown in FIG. 8, the semiconductor device shown in FIG. 7 is a second semiconductor that becomes an i-type layer by controlling the voltage applied to the gate electrode, similarly to the semiconductor device shown in FIG. The energy level in layer 22 can be controlled. That is, as shown in FIG. 8A, in the state where no voltage is applied to the gate electrode 41, the second semiconductor layer 22 which is an i-type layer serves as a barrier, and the first semiconductor layer 21 and the first semiconductor layer 21 No current flows between the four semiconductor layers 24. Further, as shown in FIG. 8B, by applying a voltage to the gate electrode 41, the energy level in the second semiconductor layer 22 that is an i-type layer is lowered, and the second semiconductor layer 21 is changed from the first semiconductor layer 21 to the second semiconductor layer 21. In the semiconductor layer 22, electrons are transmitted by the tunnel effect. However, if the energy level of the second semiconductor layer 22 is not sufficiently low, it is difficult for electrons to pass through the tunnel effect between the second semiconductor layer 22 and the fourth semiconductor layer 24, and it does not turn on, or Even if it is turned on, the on-resistance increases. Therefore, by forming the third semiconductor layer 23 to be an n ⁺ -type layer, the on / off control of the semiconductor device can be easily performed, and the on-resistance can be lowered.

In the semiconductor device in this embodiment, since the first semiconductor layer 21 and the fourth semiconductor layer 24 are both p ⁺ -type layers, the capacitance between the source electrode 42 and the drain electrode 43 can be reduced. High frequency characteristics can be improved. Further, since it can be turned on with a low gate voltage, low voltage driving is possible. As described above, the current flowing due to the tunneling effect of electrons undergoes a rapid current change compared to the normal diffusion current, so that the current interruption performance is particularly high when transitioning from the on state to the off state. . Therefore, since the semiconductor device in this embodiment can be controlled on and off with a low voltage, the high-frequency characteristics can be further improved and the power consumption of the semiconductor device can be reduced.

In the semiconductor device in this embodiment, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, and the fourth semiconductor layer 24 are formed of the same semiconductor material, for example, Si or InGaAs. May be. Also in this case, the first semiconductor layer 21 and the fourth semiconductor layer 24 are p ⁺ type layers, the second semiconductor layer 22 is an i type layer, and the third semiconductor layer 23 is an n ⁺ type layer. To form. However, in order to easily control the on / off of the semiconductor device and to reduce the on-resistance, as shown in FIG. 5, a material having a narrower band gap than the first semiconductor layer 21 and the fourth semiconductor layer 24 is used. A structure in which the second semiconductor layer 22 and the third semiconductor layer 23 are formed is preferable.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 9A, the buffer layer 11, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, and the fourth semiconductor layer 24 are formed on the substrate 10. A semiconductor layer such as is formed by epitaxial growth. In the present embodiment, the buffer layer 11, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, and the fourth semiconductor layer 24 are formed by MOVPE (Metal-Organic Vapor Phase Epitaxy). Form. The substrate 10 is a substrate made of semi-insulating InP, and the buffer layer 11 is made of i-InAlAs having a thickness of about 300 nm. The first semiconductor layer 21 is formed of p ⁺ -GaAs _0.51 Sb _0.49 having a film thickness of about 200 nm, and Zn as a p-type impurity element has a concentration of 2 × 10 ¹⁹ cm ⁻³ . Doped so that The second semiconductor layer 22 is formed of i-In _0.53 Ga _0.47 As having a thickness of about 100 nm. The third semiconductor layer 23 is formed of n ⁺ -In _0.53 Ga _0.47 As having a thickness of about 2 nm, and Si is 1 × 10 ¹⁹ cm ⁻³ as an impurity element that becomes n-type. It is doped to a concentration. The fourth semiconductor layer 24 is formed of p ⁺ -GaAs _0.51 Sb _0.49 having a film thickness of about 200 nm, and Zn as a p-type impurity element has a concentration of 2 × 10 ¹⁹ cm ⁻³ . Doped so that

  Next, as shown in FIG. 9B, the drain electrode 43 is formed on a part of the fourth semiconductor layer 24. Specifically, a W (tungsten) film having a thickness of about 200 nm is formed on the fourth semiconductor layer 24 by sputtering, a photoresist is applied on the formed W film, and exposure is performed. Perform exposure and development by the apparatus. Thereby, a resist pattern (not shown) is formed in a region where the drain electrode 43 is formed. Thereafter, the W film in the region where the resist pattern is not formed is removed by dry etching such as RIE (Reactive Ion Etching), thereby forming the drain electrode 43 from the remaining W film. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Next, as shown in FIG. 10A, the fourth semiconductor layer 24, the third semiconductor layer 24 in the region where the drain electrode 43 is not formed by wet etching using the drain electrode 43 formed of W as a mask. The semiconductor layer 23 and the second semiconductor layer 22 are removed. Thereby, the surface of the first semiconductor layer 21 is exposed. At this time, the first semiconductor layer 21 may be slightly removed. In this wet etching, for example, a mixed solution of phosphoric acid and hydrogen peroxide water may be used as an etchant. Such an etching solution does not etch W which becomes the drain electrode 43, and the fourth semiconductor layer 24, the third semiconductor layer 23, and the second semiconductor layer in the region where the drain electrode 43 is not formed. 22 can be removed. In addition, since the semiconductor layer is isotropically etched in the wet etching, the width of the remaining fourth semiconductor layer 24, third semiconductor layer 23, and second semiconductor layer 22 is the width of the drain electrode 43. Narrower than that. Accordingly, the fourth semiconductor layer 24, the third semiconductor layer 23, and the second semiconductor layer 22 are formed in a mesa shape on the first semiconductor layer 21, and one of the mesas thus formed is formed. A drain electrode 43 is formed on the upper fourth semiconductor layer 24.

Next, as shown in FIG. 10B, the surface of the first semiconductor layer 21, the side surfaces of the second semiconductor layer 22, the third semiconductor layer 23, and the fourth semiconductor layer 24 formed in a mesa shape. The insulating film 30 is formed on the surface and side surfaces of the drain electrode 43. The insulating film 30 is formed of Al ₂ O ₃ or SiN formed by ALD (Atomic Layer Deposition). In ALD, vapor deposition particles wrap around to form a film. Therefore, the surface of the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, and the fourth semiconductor layer formed in a mesa shape. The insulating film 30 can be formed on the 24 side surfaces, the surface and side surfaces of the drain electrode 43 and the like. In the present embodiment, the insulating film 30 is formed of an Al ₂ O ₃ film having a thickness of about 5 nm.

  Next, as shown in FIG. 11A, after forming a resist mask 61 on the insulating film 30, the resist is exposed until the surface of the insulating film 30 on the region where the drain electrode 43 is formed is exposed. Etching back is performed by etching the mask 61. Specifically, after applying a photoresist on the insulating film 30, the resist mask 61 is formed on the entire surface by exposure with an exposure apparatus or the like. Thereafter, etching is performed by removing the resist mask 61 by etching using oxygen plasma until the surface of the insulating film 30 in the region where the drain electrode 43 is formed is exposed.

  Next, as shown in FIG. 11B, the insulating film 30 exposed from the resist mask 61 is removed by dry etching such as RIE, and the surface of the drain electrode 43 is exposed.

  Next, as shown in FIG. 12A, the resist mask 61 is removed with an organic solvent or the like.

  Next, as shown in FIG. 12B, a gate electrode 41 in contact with the insulating film 30 formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 23 is formed. Specifically, a photoresist is applied to the surface of the insulating film 30, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the surface of the drain electrode 43 and the gate electrode 41 are formed. A resist pattern is formed. Thereafter, a metal laminated film made of Ti (10 nm) / Pt (30 nm) / Au (100 nm) is formed by vacuum deposition. In vacuum vapor deposition performed at this time, vapor deposition particles are incident from an oblique direction and the substrate 10 is rotated. Thereby, the gate electrode 41 in contact with the insulating film 30 formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 23 formed in a mesa shape is formed. Since the drain electrode 43 is wider than the fourth semiconductor layer 24, the third semiconductor layer 23, and the second semiconductor layer 22, the vapor deposition particles do not reach the back side of the drain electrode 43. The gate electrode 41 is formed separately from the drain electrode 43. The metal stacked film formed when forming the gate electrode 41 is also formed on the drain electrode 43, but the metal stacked film formed on the drain electrode 43 is a part of the drain electrode 43. Part.

  Next, as shown in FIG. 13A, the opening 30a is formed by removing the insulating film 30 in the region where the source electrode 42 is to be formed. Specifically, a photoresist is applied on the insulating film 30, the gate electrode 41, and the drain electrode 43, and an opening is provided in a region where the source electrode 42 is formed by performing exposure and development with an exposure apparatus. A resist pattern (not shown) is formed. Thereafter, the insulating film 30 in the region where the resist pattern is not formed is removed by dry etching such as RIE, and the surface of the first semiconductor layer 21 is exposed to form the opening 30a. The resist pattern is thereafter removed with an organic solvent or the like.

  Next, as shown in FIG. 13B, the source electrode 42 is formed in the opening 30a of the insulating film 30 where the first semiconductor layer 21 is exposed. Specifically, a photoresist is applied on the insulating film 30, the gate electrode 41, and the drain electrode 43, and an opening is provided in a region where the source electrode 42 is formed by performing exposure and development with an exposure apparatus. A resist pattern (not shown) is formed. Thereafter, a metal multilayer film made of Pt (30 nm) / Au (300 nm) is formed by vacuum deposition, and immersed in an organic solvent or the like, so that the metal multilayer film formed on the resist pattern is combined with the resist pattern. Remove. Thereby, the source electrode 42 is formed by the remaining metal multilayer film.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

(Other structures of semiconductor devices)
In the above description, the vertical semiconductor device formed by stacking the semiconductor layers on the substrate 10 has been described. However, the semiconductor device in the present embodiment is formed on the surface of the substrate as shown in FIG. Different types of semiconductor regions may be formed.

Specifically, on the surface of the substrate 10, the first semiconductor region 121 is formed by p ⁺ -GaAsSb, the second semiconductor region 122 is formed by i-InGaAs, the third semiconductor region 123 is formed by n ⁺ -InGaAs, and p ⁺ -GaAsSb. Thus, the fourth semiconductor region 124 may be formed. The first semiconductor region 121 to be the p ⁺ type region formed in this way is formed in contact with the second semiconductor region 122 to be the i type region. The second semiconductor region 122 is formed in contact with the third semiconductor region 123 to be an n ⁺ type region. The third semiconductor region 123 is formed in contact with the fourth semiconductor region 124 to be a p ⁺ type region.

An insulating film 30 serving as a gate insulating film is formed over the second semiconductor region 122 serving as the i-type region and the third semiconductor region 123 serving as the n ⁺ -type region. A gate electrode 41 is formed. Also, on the first semiconductor region 121 serving as the p ⁺ -type region, the source electrode 42 is formed on the fourth semiconductor region 124 serving as the p ⁺ -type region, the drain electrode 43 is formed Has been. The semiconductor device having such a structure can obtain the same effects as the semiconductor device having the structure shown in FIG.

  In the semiconductor device having the structure shown in FIG. 14, the first semiconductor region 121 corresponds to the first semiconductor layer 21 in the semiconductor device having the structure shown in FIG. 5, and the second semiconductor region 122 is This corresponds to the second semiconductor layer 22. In addition, the third semiconductor region 123 corresponds to the third semiconductor layer 23, and the fourth semiconductor region 124 corresponds to the fourth semiconductor layer 24.

[Second Embodiment]
Next, a semiconductor device according to the second embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 15, a buffer layer 11 is formed of i-InAlAs on a substrate 10, and p ⁺ -GaAs _0. The first semiconductor layer 21 is formed of ₅₁ Sb _0.49 . A part of the first semiconductor layer 21 serving as a p ⁺ type layer is formed on the second semiconductor layer 22 by i-In _0.53 Ga _0.47 As, i-In _0.8 Ga _0.2 As Thus, the fourth semiconductor layer 24 is formed by sequentially stacking the third semiconductor layer 223 and p ⁺ -GaAs _0.51 Sb _0.49 .

  The substrate 10 is made of semi-insulating InP. InGaAs can reduce the band gap by increasing the In composition ratio and decreasing the Ga composition. Therefore, in the semiconductor device according to the present embodiment, the third semiconductor layer 223 is formed to have a narrower band gap than the second semiconductor layer 22.

The fourth semiconductor layer 24 serving as the third semiconductor layer 223, p ⁺ -type layer serving as a second semiconductor layer 22, i-type layer serving as the i-type layer, the first semiconductor layer 21 of the p ⁺ -type layer It is formed in a mesa shape in a part on the top. The insulating film 30 serving as a gate insulating film is formed on the surface of the first semiconductor layer 21, the second semiconductor layer 22 formed in a mesa shape, the third semiconductor layer 223, and the side surfaces of the fourth semiconductor layer 24. Is formed.

The gate electrode 41 is formed via an insulating film 30 formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 223. That is, the insulating film 30 is formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 223 that are formed in a mesa shape, and the insulating film 30 that is the side surface of the mesa is insulated on the side surface. A gate electrode 41 is formed in contact with the film 30. The source electrode 42, p ⁺ -type layer in which is formed on the first semiconductor layer 21, the drain electrode 43 is formed on the fourth semiconductor layer 24 is a p ⁺ -type layer Yes. In this embodiment, the first semiconductor layer 21 is the first semiconductor region, the second semiconductor layer 22 is the second semiconductor region, the third semiconductor layer 223 is the third semiconductor region, The semiconductor layer 24 may be referred to as a fourth semiconductor region.

  FIG. 16 is an energy band diagram of the semiconductor device in the present embodiment shown in FIG. 16A is an energy band diagram in an equilibrium state where no voltage is applied to the gate electrode 41, and FIG. 16B is an energy band diagram in a state where a voltage is applied to the gate electrode 41. FIG. FIG. As shown in FIG. 16, by controlling the voltage applied to the gate electrode 41, the energy level in the second semiconductor layer 22 serving as the i-type layer and the third semiconductor layer 223 serving as the i-type layer is controlled. can do. That is, as shown in FIG. 16A, in the state where no voltage is applied to the gate electrode 41, the second semiconductor layer 22 that becomes the i-type layer and the third semiconductor layer 223 that becomes the i-type layer. Becomes a barrier, and no current flows between the first semiconductor layer 21 and the fourth semiconductor layer 24. On the other hand, as shown in FIG. 16B, by applying a voltage to the gate electrode 41, in the second semiconductor layer 22 that becomes the i-type layer and the third semiconductor layer 223 that becomes the i-type layer. Energy level can be lowered. Thus, electrons are transmitted from the first semiconductor layer 21 to the second semiconductor layer 22 by the tunnel effect, and electrons are transmitted from the third semiconductor layer 223 to the fourth semiconductor layer 24 by the tunnel effect. Accordingly, a current flows between the first semiconductor layer 21 and the fourth semiconductor layer 24.

In the present embodiment, the third semiconductor layer 223 is formed of i-In _0.8 Ga _0.2 As, and the second semiconductor layer 22 is formed of i-In _0.53 Ga _0.47 As. Since the third semiconductor layer 223 is formed, the band gap is narrower than that of the second semiconductor layer 22. Therefore, electrons can be easily transmitted through the third semiconductor layer 223 to the fourth semiconductor layer 24 by a tunnel effect. Therefore, in this embodiment, by forming the third semiconductor layer 223 whose band gap is narrower than that of the second semiconductor layer 22, the on / off control of the semiconductor device can be easily performed and the on-resistance can be lowered. it can.

  Note that the manufacturing method of the semiconductor device in this embodiment is the same as the manufacturing method of the first semiconductor device, except that the material forming the third semiconductor layer 223 is different. Further, although the case where the third semiconductor layer 223 is formed using an i-type layer has been described in this embodiment, the third semiconductor layer 223 is formed using an n-type layer doped with an n-type impurity element. It may be formed. About contents other than the above, it is the same as that of 1st Embodiment.

[Third Embodiment]
Next, a semiconductor device according to a third embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 17, a buffer layer 11 is formed of i-InAlAs on a substrate 10, and p ⁺ -GaAs _0. The first semiconductor layer 21 is formed of ₅₁ Sb _0.49 . A part of the first semiconductor layer 21 serving as a p ⁺ type layer includes a second semiconductor layer 22 made of i-In _0.53 Ga _0.47 As, a third semiconductor layer 323 made of i-InGaAs, A fourth semiconductor layer 24 is sequentially stacked by p ⁺ -GaAs _0.51 Sb _0.49 . The substrate 10 is made of semi-insulating InP.

In the present embodiment, as shown in FIG. 18, the composition of InGaAs in the third semiconductor layer 323 is inclined. Specifically, the third semiconductor layer 323 gradually _increases from In _0.53 Ga _0.47 As to the interface with the fourth semiconductor layer 24 from the interface with the second semiconductor layer 22. The composition ratio of Ga is decreased while the composition ratio is increased, so that In _0.8 Ga _0.2 As is obtained. Since InGaAs increases the In composition ratio and decreases the Ga composition to narrow the band gap, the third semiconductor layer 323 is connected to the fourth semiconductor layer 24 from the interface with the second semiconductor layer 22. The band gap gradually narrows toward the interface. Note that the composition ratio of In and Ga in the third semiconductor layer 323 may be changed stepwise instead of continuously.

The fourth semiconductor layer 24 serving as the third semiconductor layer 323, p ⁺ -type layer serving as a second semiconductor layer 22, i-type layer serving as the i-type layer, the first semiconductor layer 21 of the p ⁺ -type layer It is formed in a mesa shape in a part on the top. The insulating film 30 serving as a gate insulating film is formed on the surface of the first semiconductor layer 21, the second semiconductor layer 22 formed in a mesa shape, the third semiconductor layer 323, and the side surfaces of the fourth semiconductor layer 24. Is formed.

The gate electrode 41 is formed via the insulating film 30 formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 323. That is, the insulating film 30 is formed on the side surfaces of the second semiconductor layer 22 and the third semiconductor layer 323 formed in a mesa shape, and the insulating film 30 is formed on the side surface of the insulating film 30 serving as the side surface of the mesa. A gate electrode 41 is formed in contact with 30. The source electrode 42, p ⁺ -type layer in which is formed on the first semiconductor layer 21, the drain electrode 43 is formed on the fourth semiconductor layer 24 is a p ⁺ -type layer Yes. In this embodiment mode, the first semiconductor layer 21 is the first semiconductor region, the second semiconductor layer 22 is the second semiconductor region, the third semiconductor layer 323 is the third semiconductor region, The semiconductor layer 24 may be referred to as a fourth semiconductor region.

  FIG. 18 is an energy band diagram of the semiconductor device according to the present embodiment shown in FIG. 18A is an energy band diagram in an equilibrium state where no voltage is applied to the gate electrode 41, and FIG. 18B is an energy band diagram in a state where a voltage is applied to the gate electrode 41. FIG. FIG. As shown in FIG. 18, by controlling the voltage applied to the gate electrode 41, the energy level in the second semiconductor layer 22 serving as the i-type layer and the third semiconductor layer 323 serving as the i-type layer is controlled. can do. That is, as shown in FIG. 18A, in the state where no voltage is applied to the gate electrode 41, the second semiconductor layer 22 that becomes the i-type layer and the third semiconductor layer 323 that becomes the i-type layer. Becomes a barrier, and no current flows between the first semiconductor layer 21 and the fourth semiconductor layer 24. On the other hand, as shown in FIG. 18B, by applying a voltage to the gate electrode 41, in the second semiconductor layer 22 that becomes the i-type layer and the third semiconductor layer 323 that becomes the i-type layer. Energy level can be lowered. Thus, electrons are transmitted from the first semiconductor layer 21 to the second semiconductor layer 22 by the tunnel effect, and electrons are easily transmitted from the third semiconductor layer 323 to the fourth semiconductor layer 24 by the tunnel effect. To do. Accordingly, a current flows between the first semiconductor layer 21 and the fourth semiconductor layer 24.

In the present embodiment, the third semiconductor layer 323 is formed from i-In _0.53 Ga _0.47 As from the interface with the second semiconductor layer 22 toward the interface with the fourth semiconductor layer 24. The In composition ratio is gradually increased so as to be i-In _0.8 Ga _0.2 As. Therefore, the band gap of the third semiconductor layer 323 is narrower at the interface with the fourth semiconductor layer 24 than at the interface with the second semiconductor layer 22, and the third semiconductor layer 323 has a second band gap from the third semiconductor layer 323. In the fourth semiconductor layer 24, electrons can be transmitted by the tunnel effect. Therefore, in this embodiment mode, the on / off control of the semiconductor device is facilitated, and the on-resistance can be reduced.

  Note that the manufacturing method of the semiconductor device according to the present embodiment is the same as that of the first semiconductor device except that when the third semiconductor layer 323 is formed, the In composition ratio is gradually increased. It is the same as the method. Further, when the third semiconductor layer 323 is formed, the film formation is performed while the supply amount of the source gas containing In is gradually increased and the supply amount of the source gas containing Ga is gradually decreased. In the description of this embodiment mode, the case where the third semiconductor layer 323 is formed using an i-type layer has been described; however, the third semiconductor layer 323 is formed using an n-type layer doped with an n-type impurity element. It may be formed. In addition, the third semiconductor layer 323 is doped with an impurity element which becomes n-type in the third semiconductor layer 323 instead of the composition gradient, and the fourth semiconductor layer 24 is connected to the second semiconductor layer 22 from the interface with the second semiconductor layer 22. The concentration of the n-type impurity element may gradually increase toward the interface. About contents other than the above, it is the same as that of 1st Embodiment.

[Fourth Embodiment]
(Semiconductor device)
Next, a semiconductor device according to a fourth embodiment will be described. In the semiconductor device in the present embodiment, as shown in FIG. 19, a buffer layer 11 is formed on a substrate 10 by i-InAlAs, and the buffer layer 11 is formed by p ⁺ -GaAsSb. One semiconductor layer 421 is formed. A part of the first semiconductor layer 421 to be a p ⁺ type layer is formed by sequentially stacking a second semiconductor layer 422 by i-InGaAs and a third semiconductor layer 423 by p ⁺ -GaAsSb. Yes. The substrate 10 is made of semi-insulating InP.

In the present embodiment, as shown in FIG. 20, the composition of InGaAs in the second semiconductor layer 422 is inclined. Specifically, the second semiconductor layer 422 gradually _increases from In _0.53 Ga _0.47 As to the interface with the third semiconductor layer 423 from the interface with the first semiconductor layer 421. The composition ratio of Ga is decreased while the composition ratio is increased, so that In _0.8 Ga _0.2 As is obtained. InGaAs increases the In composition ratio and decreases the Ga composition to narrow the band gap. Therefore, the second semiconductor layer 422 is connected to the third semiconductor layer 423 from the interface with the first semiconductor layer 421. The band gap gradually narrows toward the interface. Note that the composition ratio of In and Ga in the second semiconductor layer 422 may change stepwise instead of continuously.

the third semiconductor layer 423 serving as the second semiconductor layer 422, p ⁺ -type layer serving as the i-type layer is formed in a mesa shape in some on the first semiconductor layer 421 formed of the p ⁺ -type layer Yes. An insulating film 30 serving as a gate insulating film is formed on the surface of the first semiconductor layer 421, the second semiconductor layer 422 formed in a mesa shape, and the side surfaces of the third semiconductor layer 423.

The gate electrode 41 is formed via the insulating film 30 formed on the side surface of the second semiconductor layer 422. That is, the insulating film 30 is formed on the side surface of the second semiconductor layer 422 formed in a mesa shape, and the gate electrode 41 is in contact with the insulating film 30 on the side surface of the insulating film 30 which is the side surface of the mesa. Is formed. The source electrode 42 is a p ⁺ -type layer is formed on the first semiconductor layer 421, the drain electrode 43 is formed on the third semiconductor layer 423 is a p ⁺ -type layer Yes. Note that in this embodiment, the first semiconductor layer 421 is referred to as a first semiconductor region, the second semiconductor layer 422 is referred to as a second semiconductor region, and the third semiconductor layer 423 is referred to as a third semiconductor region. There is a case.

In this embodiment mode, the p-type impurity element doped in the first semiconductor layer 421 and the third semiconductor layer 423 is Zn (zinc), Be (beryllium), or the like, which is 1 × 10 ¹⁸ cm. It is doped to a concentration of ⁻³ or higher. The second semiconductor layer 422 is not doped with an impurity element. For example, the concentration of the impurity element in the second semiconductor layer 422 is 1 × 10 ¹⁶ cm ⁻³ or less. In the semiconductor device in this embodiment, for example, the first semiconductor layer 421 and the third semiconductor layer 423 are doped with Zn so as to have a concentration of 2 × 10 ¹⁹ cm ⁻³ .

In the semiconductor device in this embodiment, since the first semiconductor layer 421 and the third semiconductor layer 423 are both p ⁺ -type layers, the capacitance between the source electrode 42 and the drain electrode 43 can be reduced. High frequency characteristics can be improved. Further, since it can be turned on with a low gate voltage, low voltage driving is possible. As described above, the current that flows due to the tunnel effect undergoes a rapid current change as compared with a normal diffusion current, and thus has a particularly high current interruption performance when transitioning from an on state to an off state. Therefore, since the semiconductor device in this embodiment can be controlled on and off with a low voltage, the high-frequency characteristics can be further improved and the power consumption can be reduced.

  FIG. 20 is an energy band diagram of the semiconductor device in the present embodiment shown in FIG. 20A is an energy band diagram in an equilibrium state in which no voltage is applied to the gate electrode 41, and FIG. 20B is an energy band diagram in a state where a voltage is applied to the gate electrode 41. FIG. FIG. As shown in FIG. 20, by controlling the voltage applied to the gate electrode 41, the energy level in the second semiconductor layer 422 serving as the i-type layer can be controlled. That is, as shown in FIG. 20A, in a state where no voltage is applied to the gate electrode 41, the second semiconductor layer 422 that is an i-type layer serves as a barrier, and the first semiconductor layer 421 and the first semiconductor layer 421 No current flows between the semiconductor layer 423 and the third semiconductor layer 423. On the other hand, as shown in FIG. 20B, by applying a voltage to the gate electrode 41, the energy level in the second semiconductor layer 422 serving as the i-type layer can be lowered. Accordingly, electrons are transmitted from the first semiconductor layer 421 to the second semiconductor layer 422 by a tunnel effect, and electrons are transmitted from the second semiconductor layer 422 to the third semiconductor layer 423 by a tunnel effect. Accordingly, current flows between the first semiconductor layer 421 and the third semiconductor layer 423.

In this embodiment, the second semiconductor layer 422 is formed from i-In _0.53 Ga _0.47 As from the interface with the first semiconductor layer 421 toward the interface with the third semiconductor layer 423. The In composition ratio is gradually increased so as to be i-In _0.8 Ga _0.2 As. Accordingly, the band gap of the second semiconductor layer 422 is narrower at the interface with the third semiconductor layer 423 than at the interface with the first semiconductor layer 421. Electrons can be easily transmitted to and from the semiconductor layer 423 by a tunnel effect. Therefore, in this embodiment mode, the on / off control of the semiconductor device is facilitated, and the on-resistance can be reduced.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 21A, semiconductor layers such as the buffer layer 11, the first semiconductor layer 421, the second semiconductor layer 422, and the third semiconductor layer 423 are epitaxially grown on the substrate 10. Form. In this embodiment, the buffer layer 11, the first semiconductor layer 421, the second semiconductor layer 422, and the third semiconductor layer 423 are formed by MOVPE. The substrate 10 is a substrate made of semi-insulating InP, and the buffer layer 11 is made of i-InAlAs having a thickness of about 300 nm. The first semiconductor layer 421 is formed of p ⁺ -GaAs _0.51 Sb _0.49 having a film thickness of about 200 nm, and Zn as a p-type impurity element has a concentration of 2 × 10 ¹⁹ cm ⁻³ . Doped so that The second semiconductor layer 422 is made of i-InGaAs having a thickness of about 100 nm, and the composition of InGaAs is gradient in composition. Specifically, the second semiconductor layer 422 gradually _increases from In _0.53 Ga _0.47 As to the interface with the third semiconductor layer 423 from the interface with the first semiconductor layer 421. The composition ratio of Ga is decreased while the composition ratio is increased, so that In _0.8 Ga _0.2 As is obtained. The third semiconductor layer 423 is formed of p ⁺ -GaAs _0.51 Sb _0.49 having a film thickness of about 200 nm, and Zn has a concentration of 2 × 10 ¹⁹ cm ⁻³ as a p-type impurity element. Doped so that

  Next, as illustrated in FIG. 21B, the drain electrode 43 is formed on part of the third semiconductor layer 423. Specifically, a W film having a thickness of about 200 nm is formed on the third semiconductor layer 423 by sputtering, a photoresist is applied on the formed W film, and exposure by an exposure apparatus is performed. Develop. Thereby, a resist pattern (not shown) is formed in a region where the drain electrode 43 is formed. Thereafter, the W film in the region where the resist pattern is not formed is removed by dry etching such as RIE, whereby the drain electrode 43 is formed from the remaining W film. Thereafter, the resist pattern is removed with an organic solvent or the like.

  Next, as shown in FIG. 22A, the third semiconductor layer 423 and the second semiconductor layer 423 in the region where the drain electrode 43 is not formed by wet etching using the drain electrode 43 formed of W as a mask. The semiconductor layer 422 is removed. Thereby, the surface of the first semiconductor layer 421 is exposed. At this time, the first semiconductor layer 421 may be slightly removed. In this wet etching, for example, a mixed solution of phosphoric acid and hydrogen peroxide water may be used as an etchant. Such an etching solution does not etch W that becomes the drain electrode 43, and can remove the third semiconductor layer 423 and the second semiconductor layer 422 in the region where the drain electrode 43 is not formed. . In the wet etching, the semiconductor layer is isotropically etched, so that the remaining third semiconductor layer 423 and the second semiconductor layer 422 are formed to be narrower than the drain electrode 43. Accordingly, the third semiconductor layer 423 and the second semiconductor layer 422 are formed in a mesa shape on the first semiconductor layer 421, and the third semiconductor on the top of the mesa thus formed is formed. A drain electrode 43 is formed on the layer 423.

Next, as shown in FIG. 22B, the surface of the first semiconductor layer 421, the second semiconductor layer 422 formed in a mesa shape, the side surfaces of the third semiconductor layer 423, the surface of the drain electrode 43, and An insulating film 30 is formed on the side surface. The insulating film 30 is made of Al ₂ O ₃ or SiN formed by ALD. In ALD, vapor deposition particles wrap around to form a film. Therefore, the surface of the first semiconductor layer 421, the second semiconductor layer 422 formed in a mesa shape, the side surfaces of the third semiconductor layer 423, and the drain electrode 43 An insulating film 30 can be formed on the surface, side surfaces, and the like. In the present embodiment, the insulating film 30 is formed of an Al ₂ O ₃ film having a thickness of about 5 nm.

  Next, as shown in FIG. 23A, after a resist mask 461 is formed on the insulating film 30, the resist is resisted until the surface of the insulating film 30 on the region where the drain electrode 43 is formed is exposed. Etching back is performed by etching the mask 461. Specifically, after applying a photoresist on the insulating film 30, the resist mask 461 is formed on the entire surface by exposing with a light exposure apparatus or the like. Thereafter, etching is performed by removing the resist mask 461 by etching using oxygen plasma until the surface of the insulating film 30 in the region where the drain electrode 43 is formed is exposed.

  Next, as shown in FIG. 23B, the insulating film 30 exposed from the resist mask 461 is removed by dry etching such as RIE, and the surface of the drain electrode 43 is exposed.

  Next, as shown in FIG. 24A, the resist mask 461 is removed with an organic solvent or the like.

  Next, as shown in FIG. 24B, the gate electrode 41 in contact with the insulating film 30 formed on the side surface of the second semiconductor layer 422 is formed. Specifically, a photoresist is applied to the surface of the insulating film 30, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where the surface of the drain electrode 43 and the gate electrode 41 are formed. A resist pattern is formed. Thereafter, a metal laminated film made of Ti (10 nm) / Pt (30 nm) / Au (100 nm) is formed by vacuum deposition. In vacuum vapor deposition performed at this time, vapor deposition particles are incident from an oblique direction and the substrate 10 is rotated. Thereby, the gate electrode 41 in contact with the insulating film 30 formed on the side surface of the second semiconductor layer 422 formed in a mesa shape is formed. Since the drain electrode 43 is wider than the third semiconductor layer 423 and the second semiconductor layer 422, the vapor deposition particles do not reach the back side of the drain electrode 43. 43 is formed separately. The metal stacked film formed when forming the gate electrode 41 is also formed on the drain electrode 43, but the metal stacked film formed on the drain electrode 43 is a part of the drain electrode 43. Part.

  Next, as shown in FIG. 25A, the insulating film 30 in the region where the source electrode 42 is formed is removed to form an opening 30a. Specifically, a photoresist is applied on the insulating film 30, the gate electrode 41, and the drain electrode 43, and an opening is provided in a region where the source electrode 42 is formed by performing exposure and development with an exposure apparatus. A resist pattern (not shown) is formed. Thereafter, the insulating film 30 in the region where the resist pattern is not formed is removed by dry etching such as RIE, and the surface of the first semiconductor layer 421 is exposed to form the opening 30a. The resist pattern is thereafter removed with an organic solvent or the like.

  Next, as shown in FIG. 25B, the source electrode 42 is formed in the opening 30a of the insulating film 30 where the first semiconductor layer 421 is exposed. Specifically, a photoresist is applied on the insulating film 30, the gate electrode 41, and the drain electrode 43, and an opening is provided in a region where the source electrode 42 is formed by performing exposure and development with an exposure apparatus. A resist pattern (not shown) is formed. Thereafter, a metal multilayer film made of Pt (30 nm) / Au (300 nm) is formed by vacuum deposition, and immersed in an organic solvent or the like, so that the metal multilayer film formed on the resist pattern is combined with the resist pattern. Remove. Thereby, the source electrode 42 is formed by the remaining metal multilayer film.

  Through the above steps, the semiconductor device in this embodiment can be manufactured.

[Fifth Embodiment]
Next, a semiconductor device according to a fifth embodiment will be described. In the semiconductor device according to the present embodiment, as shown in FIG. 26, the buffer layer 11 is formed of i-InAlAs on the substrate 10, and p ⁺ − is formed on a part of the buffer layer 11. A first semiconductor layer 421 is formed of GaAsSb. on the first semiconductor layer 421 formed of the p ⁺ -type layer, and the third semiconductor layer 423 are sequentially stacked, which is formed by the second semiconductor layer ^522, p + -GaAsSb formed by n-InGaAs Is formed. The substrate 10 is made of semi-insulating InP.

In this embodiment mode, the second semiconductor layer 522 includes the third semiconductor layer 423 from the interface with the first semiconductor layer 421 having an n-type impurity element doped with InGaAs, for example, Si. It is formed to gradually increase toward the interface. Specifically, the second semiconductor layer 522 has an Si concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 from the interface with the first semiconductor layer 421 toward the interface with the third semiconductor layer 423. It is formed so that it may become ^x10 < ¹⁹ > cm <^-3> . As a result, as shown in FIG. 27A described later, in the second semiconductor layer 522, the energy level is increased from the interface with the first semiconductor layer 421 toward the interface with the third semiconductor layer 423. Go down. Note that the Si concentration may be changed stepwise instead of continuously.

the third semiconductor layer 423 serving as the second semiconductor layer 522, p ⁺ -type layer serving as n-type layer is formed in a mesa shape in some on the first semiconductor layer 421 formed of the p ⁺ -type layer Yes. An insulating film 30 serving as a gate insulating film is formed on the surface of the first semiconductor layer 421, the second semiconductor layer 522 formed in a mesa shape, and the side surfaces of the third semiconductor layer 423.

The gate electrode 41 is formed via the insulating film 30 formed on the side surface of the second semiconductor layer 522. That is, the insulating film 30 is formed on the side surface of the second semiconductor layer 522 formed in a mesa shape, and the gate electrode 41 is in contact with the insulating film 30 on the side surface of the insulating film 30 serving as the side surface of the mesa. Is formed. The source electrode 42 is a p ⁺ -type layer is formed on the first semiconductor layer 421, the drain electrode 43 is formed on the third semiconductor layer 423 is a p ⁺ -type layer Yes. Note that in this embodiment, the first semiconductor layer 421 is referred to as a first semiconductor region, the second semiconductor layer 522 is referred to as a second semiconductor region, and the third semiconductor layer 423 is referred to as a third semiconductor region. There is a case.

  FIG. 27 is an energy band diagram of the semiconductor device in the present embodiment shown in FIG. 27A is an energy band diagram in an equilibrium state where no voltage is applied to the gate electrode 41, and FIG. 27B is an energy band diagram in a state where a voltage is applied to the gate electrode 41. FIG. FIG. As shown in FIG. 27, by controlling the voltage applied to the gate electrode 41, the energy level in the second semiconductor layer 522 serving as the n-type layer can be controlled. That is, as shown in FIG. 27A, in the state where no voltage is applied to the gate electrode 41, the second semiconductor layer 522 which is an n-type layer serves as a barrier, and the first semiconductor layer 421 and the first semiconductor layer 421 No current flows between the semiconductor layer 423 and the third semiconductor layer 423. On the other hand, as shown in FIG. 27B, by applying a voltage to the gate electrode 41, the energy level in the second semiconductor layer 522 serving as an n-type layer can be lowered. Accordingly, electrons are transmitted from the first semiconductor layer 421 to the second semiconductor layer 522 by a tunnel effect, and electrons are transmitted from the second semiconductor layer 522 to the third semiconductor layer 423 by a tunnel effect. Accordingly, current flows between the first semiconductor layer 421 and the third semiconductor layer 423.

  In this embodiment mode, the energy level of the second semiconductor layer 522 decreases from the interface with the first semiconductor layer 421 toward the interface with the third semiconductor layer 423. Therefore, in the second semiconductor layer 522 to the third semiconductor layer 423, electrons can be easily transmitted by a tunnel effect. Therefore, in this embodiment mode, the on / off control of the semiconductor device is facilitated, and the on-resistance can be reduced. The contents other than the above are the same as in the fourth embodiment.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A fourth semiconductor layer formed on the third semiconductor layer;
Insulating films formed on side surfaces of the second semiconductor layer and the third semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the fourth semiconductor layer;
Have
The first semiconductor layer and the fourth semiconductor layer are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor layer is formed of a semiconductor material of a second conductivity type.
(Appendix 2)
The semiconductor device according to appendix 1, wherein the third semiconductor layer has an impurity concentration that increases from the second semiconductor layer toward the fourth semiconductor layer.
(Appendix 3)
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A fourth semiconductor layer formed on the third semiconductor layer;
Insulating films formed on side surfaces of the second semiconductor layer and the third semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the fourth semiconductor layer;
Have
The first semiconductor layer and the fourth semiconductor layer are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor layer is formed of a material having a narrower band gap than the second semiconductor layer.
(Appendix 4)
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A fourth semiconductor layer formed on the third semiconductor layer;
Insulating films formed on side surfaces of the second semiconductor layer and the third semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the fourth semiconductor layer;
Have
The first semiconductor layer and the fourth semiconductor layer are formed of a semiconductor material of a first conductivity type,
The third semiconductor layer has a band gap that narrows from the second semiconductor layer toward the fourth semiconductor layer.
(Appendix 5)
The semiconductor device according to appendix 3 or 4, wherein the third semiconductor layer is formed of a semiconductor material of a second conductivity type.
(Appendix 6)
6. The semiconductor device according to appendix 1, 2, or 5, wherein the second conductivity type is n-type.
(Appendix 7)
The semiconductor device according to any one of appendices 1 to 6, wherein the first conductivity type is a p-type.
(Appendix 8)
The impurity concentration in the first semiconductor layer and the fourth semiconductor layer is 1 × 10 ¹⁸ cm ⁻³ or more,
8. The semiconductor device according to any one of appendices 1 to 7, wherein an impurity concentration in the second semiconductor layer is 1 × 10 ¹⁶ cm ⁻³ or less.
(Appendix 9)
The semiconductor device according to appendix 6, wherein an impurity concentration in the third semiconductor layer is 1 × 10 ¹⁷ cm ⁻³ or more.
(Appendix 10)
The first semiconductor layer and the fourth semiconductor layer are formed of the same semiconductor material,
Any one of appendices 1 to 9, wherein the second semiconductor layer and the third semiconductor layer are made of a semiconductor material different from that of the first semiconductor layer and the fourth semiconductor layer. A semiconductor device according to 1.
(Appendix 11)
The first semiconductor layer and the fourth semiconductor layer are made of a material containing GaAsSb,
11. The semiconductor device according to any one of appendices 1 to 10, wherein the second semiconductor layer and the third semiconductor layer are made of a material containing InGaAs.
(Appendix 12)
The semiconductor device according to any one of appendices 1 to 11, wherein the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are formed in a mesa shape.
(Appendix 13)
A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
An insulating film formed on a side surface of the second semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the third semiconductor layer;
Have
The first semiconductor layer and the third semiconductor layer are formed of a p-type semiconductor material,
The semiconductor device is characterized in that the impurity concentration in the second semiconductor layer is 1 × 10 ¹⁶ cm ⁻³ or less.
(Appendix 14)
14. The semiconductor device according to appendix 13, wherein the second semiconductor layer has a band gap that narrows from the first semiconductor layer toward the third semiconductor layer.
(Appendix 15)
The first semiconductor layer and the third semiconductor layer are formed of the same semiconductor material,
15. The semiconductor device according to appendix 13 or 14, wherein the second semiconductor layer is made of a semiconductor material different from that of the first semiconductor layer and the third semiconductor layer.
(Appendix 16)
The first semiconductor layer and the third semiconductor layer are made of a material containing GaAsSb,
16. The semiconductor device according to any one of appendices 13 to 15, wherein the second semiconductor layer is made of a material containing InGaAs.
(Appendix 17)
17. The semiconductor device according to any one of appendices 13 to 16, wherein the second semiconductor layer and the third semiconductor layer are formed in a mesa shape.
(Appendix 18)
A first semiconductor region formed on the substrate;
A second semiconductor region formed in contact with the first semiconductor region;
A third semiconductor region formed in contact with the second semiconductor region;
A fourth semiconductor region formed in contact with the third semiconductor region;
An insulating film formed on the second semiconductor region and the third semiconductor region;
A gate electrode formed on the insulating film;
A source electrode formed on the first semiconductor region;
A drain electrode formed on the fourth semiconductor region;
Have
The first semiconductor region and the fourth semiconductor region are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor region is formed of a semiconductor material of a second conductivity type.
(Appendix 19)
A first semiconductor region formed on the substrate;
A second semiconductor region formed in contact with the first semiconductor region;
A third semiconductor region formed in contact with the second semiconductor region;
A fourth semiconductor region formed in contact with the third semiconductor region;
An insulating film formed on the second semiconductor region and the third semiconductor region;
A gate electrode formed on the insulating film;
A source electrode formed on the first semiconductor region;
A drain electrode formed on the fourth semiconductor region;
Have
The first semiconductor region and the fourth semiconductor region are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor region is formed of a material having a narrower band gap than the second semiconductor region.
(Appendix 20)
A first semiconductor region formed on the substrate;
A second semiconductor region formed in contact with the first semiconductor region;
A third semiconductor region formed in contact with the second semiconductor region;
An insulating film formed on the second semiconductor region;
A gate electrode formed on the insulating film;
A source electrode formed on the first semiconductor region;
A drain electrode formed on the third semiconductor region;
Have
The first semiconductor region and the third semiconductor region are formed of a p-type semiconductor material,
The semiconductor device is characterized in that the impurity concentration in the second semiconductor region is 1 × 10 ¹⁶ cm ⁻³ or less.

10 Substrate 11 Buffer layer 21 First semiconductor layer (p ⁺ -type layer)
22 Second semiconductor layer (i-type layer)
23. Third semiconductor layer (n ⁺ type layer)
24 4th semiconductor layer (p ⁺ type layer)
30 Insulating film 41 Gate electrode 42 Source electrode 43 Drain electrode

Claims (11)

A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A fourth semiconductor layer formed on the third semiconductor layer;
Insulating films formed on side surfaces of the second semiconductor layer and the third semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the fourth semiconductor layer;
Have
The first semiconductor layer and the fourth semiconductor layer are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor layer is formed of a semiconductor material of a second conductivity type. A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A fourth semiconductor layer formed on the third semiconductor layer;
Insulating films formed on side surfaces of the second semiconductor layer and the third semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the fourth semiconductor layer;
Have
The first semiconductor layer and the fourth semiconductor layer are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor layer is formed of a material having a narrower band gap than the second semiconductor layer. A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
A fourth semiconductor layer formed on the third semiconductor layer;
Insulating films formed on side surfaces of the second semiconductor layer and the third semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the fourth semiconductor layer;
Have
The first semiconductor layer and the fourth semiconductor layer are formed of a semiconductor material of a first conductivity type,
The third semiconductor layer has a band gap that narrows from the second semiconductor layer toward the fourth semiconductor layer.   The semiconductor device according to claim 1, wherein the first conductivity type is a p-type. The impurity concentration in the first semiconductor layer and the fourth semiconductor layer is 1 × 10 ¹⁸ cm ⁻³ or more,
5. The semiconductor device according to claim 1, wherein an impurity concentration in the second semiconductor layer is 1 × 10 ¹⁶ cm ⁻³ or less. The first semiconductor layer and the fourth semiconductor layer are made of a material containing GaAsSb,
6. The semiconductor device according to claim 1, wherein the second semiconductor layer and the third semiconductor layer are made of a material containing InGaAs. A first semiconductor layer formed on the substrate;
A second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
An insulating film formed on a side surface of the second semiconductor layer;
A gate electrode formed in contact with the insulating film;
A source electrode formed on the first semiconductor layer;
A drain electrode formed on the third semiconductor layer;
Have
The first semiconductor layer and the third semiconductor layer are formed of a p-type semiconductor material,
The semiconductor device is characterized in that the impurity concentration in the second semiconductor layer is 1 × 10 ¹⁶ cm ⁻³ or less.   The semiconductor device according to claim 7, wherein the second semiconductor layer has a band gap that narrows from the first semiconductor layer toward the third semiconductor layer. A first semiconductor region formed on the substrate;
A second semiconductor region formed in contact with the first semiconductor region;
A third semiconductor region formed in contact with the second semiconductor region;
A fourth semiconductor region formed in contact with the third semiconductor region;
An insulating film formed on the second semiconductor region and the third semiconductor region;
A gate electrode formed on the insulating film;
A source electrode formed on the first semiconductor region;
A drain electrode formed on the fourth semiconductor region;
Have
The first semiconductor region and the fourth semiconductor region are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor region is formed of a semiconductor material of a second conductivity type. A first semiconductor region formed on the substrate;
A second semiconductor region formed in contact with the first semiconductor region;
A third semiconductor region formed in contact with the second semiconductor region;
A fourth semiconductor region formed in contact with the third semiconductor region;
An insulating film formed on the second semiconductor region and the third semiconductor region;
A gate electrode formed on the insulating film;
A source electrode formed on the first semiconductor region;
A drain electrode formed on the fourth semiconductor region;
Have
The first semiconductor region and the fourth semiconductor region are formed of a semiconductor material of a first conductivity type,
The semiconductor device, wherein the third semiconductor region is formed of a material having a narrower band gap than the second semiconductor region. A first semiconductor region formed on the substrate;
A second semiconductor region formed in contact with the first semiconductor region;
A third semiconductor region formed in contact with the second semiconductor region;
An insulating film formed on the second semiconductor region;
A gate electrode formed on the insulating film;
A source electrode formed on the first semiconductor region;
A drain electrode formed on the third semiconductor region;
Have
The first semiconductor region and the third semiconductor region are formed of a p-type semiconductor material,
The semiconductor device is characterized in that the impurity concentration in the second semiconductor region is 1 × 10 ¹⁶ cm ⁻³ or less.

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