JP2015142417A - Booster circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a booster circuit that boosts a low power supply voltage with high magnification.SOLUTION: A boosting circuit has first charging means 30 for charging the output of first boosting means 201 and second charging means 70 for charging the output of second boosting means 202. The boosting circuit has a first block 1 in which the first boosting means 201 for boosting power supply means 10, first control means 40 for controlling the first boosting means 201, oscillation detecting means 50 and switch means 60 for connecting the power supply means 10 and the first charging means 30 are constructed by switching elements operated with low voltages, and a second block 2 in which the second boosting means 202 for boosting the output of the first boosting means 201, second control means 80 for controlling the second boosting means 202, and voltage detecting means 90 for detecting the voltage of the second charging means 70 are constructed by switching elements having high breakdown voltages.

Description

  The present invention relates to a booster circuit and a control method thereof.

  Conventionally, a charge pump type booster circuit that generates a high voltage by charging a power supply voltage to a plurality of capacitors and switching the connection is known. This booster circuit is used in an electronic device having a function of boosting a voltage to a higher voltage from a power source means such as a solar cell represented by a rechargeable electronic timepiece and charging the power storage means. Here, FIG. 8 shows an 8-times booster circuit for outputting the conventional booster circuit by multiplying the power supply voltage by eight.

  Here, the description of FIG.

  Reference numeral 140 denotes a power supply means, which is a power generation means for converting external energy into electrical energy. Although the power supply means 140 is not particularly limited, a power generation means having a low output voltage, such as a single cell solar cell (solar cell) or a thermoelectric generator, is assumed.

  Reference numeral 110 denotes a booster, which includes a first booster block 111, a second booster block 112, and a third booster block 113. Each block is composed of a switching element and a capacitor, and each switching element performs a boosting operation according to output signals S111a to S111c, S112a to S112c, and S113a to S113d from a control circuit 130 described later, and outputs a boosted voltage VL.

  Reference numeral 120 denotes power storage means such as a secondary battery, which is supplied with a boosted voltage VL and charged.

  Reference numeral 130 denotes a control means which operates by being supplied with the boosted voltage VL, and performs various controls such as outputting control signals such as S111a to S111c, S112a to S112c, and S113a to S113d.

  In the conventional booster circuit shown in FIG. 8 described above, a MOSFET is used as a switching element for switching the circuit connection. Signals S111a to S111c, S112a to S112c, and S113a to S113d input to each MOSFET are generated by the control means 130 at the boosted voltage VL.

  For example, when the power supply voltage is low, the boosted voltage VL is low when the booster circuit is started up, so that a MOSFET driven with a low voltage is required. On the other hand, when the boosting ratio is increased, the boosted voltage VL is also increased, and the voltage for driving the MOSFET is also increased, so that a high breakdown voltage MOSFET is required.

JP 2002-262546 A (FIG. 8)

  By the way, in the MOSIC manufacturing process, a MOSFET that is driven at a voltage of less than 0.5V with a 3V breakdown voltage (hereinafter, “low voltage MOSFET”) and a MOSFET that is driven at a voltage of 3V or higher and is driven at 0.5V or higher (hereinafter, “high voltage MOSFET”) ) Can be manufactured.

  The former can reduce power consumption by suppressing leakage, but has low breakdown voltage characteristics. The latter has a high breakdown voltage but increases power consumption due to leakage.

  At that time, if an 8-fold booster circuit with a power supply voltage of 0.5V is to be configured with a conventional booster circuit, it is driven at 0.5V at the time of start-up. Need to be. On the other hand, since the voltage boosted by 8 times reaches 4.0 V, the low voltage MOSFET exceeds the withstand voltage. Therefore, the MOSFET to be used must be the high withstand voltage MOSFET. Therefore, a high withstand voltage and low voltage driving MOSFET is required to construct the above-described booster circuit.

  However, in the MOSIC manufacturing process, the high withstand voltage and low voltage driving MOSFET cannot be manufactured. Therefore, the conventional circuit configuration cannot make a boosting circuit that boosts 0.5V by 8 times. In other words, due to the manufacturing process, the conventional circuit configuration has a problem that a booster circuit having a low power supply voltage and a large boost ratio cannot be formed.

  An object of the present invention is to provide a booster circuit having a low power supply voltage and a large boosting factor, regardless of manufacturing process restrictions, in order to solve the above-described problems of the prior art.

In order to solve the above problem, the present invention provides:
Power supply means (10) for converting external energy into electrical energy;
First boosting means (201) for boosting the power generation output of the power supply means (10);
First power storage means (30) for charging the boost output of the first boost means (201);
First control means (40) for controlling the boosting operation of the first boosting means (201) using the first power storage means (30) as a power source;
Second boosting means (202) for boosting the boosted output of the first boosting means (201);
Second power storage means (70) for charging the boost output of the second boost means (202);
Second control means (80) for controlling the boosting operation of the second boosting means (202) using the second power storage means (70) as a power source;
Voltage detection means (90) for detecting the voltage of the second power storage means (70),
The first block (1) includes the first booster (201) and the first controller (40).
The second block (2) includes the second booster (202), the second controller (80), and the voltage detector (90).
The first block (1) is configured to be operable at a first voltage value or less,
The second block (2) is configured to be operable at a second voltage value higher than the first voltage value.

The present invention
An initial stage in which the power supply means (10) and the first power storage means (30) are connected and the first power storage means (30) is charged when boosting from the stop state is started;
When the first power storage means (30) is charged, the first control means (40) starts operating to control the boosting operation of the first boosting means (201), and A first cycle in which the boost output of the boosting means (201) is charged to the first power storage means (30) and charged to the second power storage means (70);
When the second power storage means (70) is charged to a predetermined voltage or higher, the second control means (80) starts operating to control the boosting operation of the second boosting means (202). And a second cycle in which the boosted output of the second boosting means (202) is charged in the second power storage means (70).

According to the present invention, in the first cycle, charging of the boost output of the first booster (201) to the second power storage unit (70) is stopped when the second booster (202) is stopped. ).

A detection means (50) for detecting an operating state of the first control means (40);
A switch means (60) connected between the power supply means (10) and the first power storage means (30) and controlled to be opened and closed by the detection means (50);
The switch means (60)
When the detection means (50) detects the stop of the first control means (40), the detection means (50) is in a closed state to connect the power supply means (10) and the first power storage means (30),
When the detection means (50) detects the operation of the first control means (40), the detection means (50) is opened, and the power supply means (10) and the first power storage means (30) are disconnected. To do.

Furthermore, the present invention is characterized in that the detection means (50) and the switch means (60) are included in the first block (1).

Furthermore, the present invention is characterized in that the first block (1) and the second block (2) are composed of semiconductors of different chips.

  The booster circuit of the present invention realizes a booster circuit with a low power supply voltage and a large boosting factor in the above manufacturing process. In other words, as described above, a booster circuit with a low power supply voltage and a large boosting factor is realized regardless of manufacturing process restrictions.

It is a circuit diagram which shows the structure of the booster circuit in the Example of this invention. It is a circuit diagram which shows the structure of the pressure | voltage rise means in the Example of this invention. It is a transition diagram which shows the transition of the connection state of the booster circuit in the Example of this invention. It is a timing chart of the booster circuit in the Example of this invention. It is a structure of the pressure | voltage rise switch in the Example of this invention. It is a block diagram of a boosting system when the boosting circuit in the embodiment of the present invention is made into a semiconductor by one chip. It is a block diagram of a boosting system when the booster circuit in the embodiment of the present invention is made into a semiconductor with two chips. It is a circuit diagram which shows the structure of the conventional booster circuit.

  Hereinafter, embodiments of a booster circuit according to the present invention will be described in detail with reference to the accompanying drawings.

  First, the configuration of the booster circuit of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing an example of the configuration of a booster circuit according to an embodiment of the present invention.

The power supply means 10 is a power generation means having a low output voltage, such as a single cell solar cell (solar cell). The positive electrode is grounded, and the negative electrode is connected to a booster 20 and a switch 60 described later. The boosting means 20 is composed of a first boosting means 201 and a second boosting means 202, and boosts the output of the power supply means 10 whose output voltage is lower than those of the first power storage means 30 and the second power storage means 70 described later, In the booster circuit for charging the first power storage means 30 and the second power storage means 70, the power supply means 10 is on the input side, and the first power storage means 30 and the second power storage means 70 are on the output side. The detailed configuration of the booster 20 will be described later.

  As shown in FIG. 1, the first control means 40 and the oscillation detection means 50 using the first power storage means 30 as a power source, the switch means 60 disposed between the power supply means 10 and the first power storage means 30, the first The first boosting means 201 for storing electricity in the power storage means 30 is collectively referred to as a first block 1. The first block 1 is composed of a low voltage MOSFET.

  The second control unit 80, the voltage detection unit 90, and the second boosting unit 202 for storing power in the second power storage unit 70 are collectively referred to as a second block. . The second block is composed of a high voltage MOSFET.

  The power storage means may be a secondary battery such as a capacitor or a lithium ion battery.

  The first power storage unit 30 is provided for the purpose of charging the boosted voltage output output from the output node 20a of the first boosting unit 201 and operating the first control unit 40 and the oscillation detecting unit 50 described later. is there. The positive electrode of the first power storage unit 30 is grounded, and the negative electrode is connected to the output node 20 a of the first boosting unit 201, the first control unit 40, the oscillation detection unit 50, and the switch unit 60.

  The first control means 40 includes an oscillation circuit (not shown) and a frequency dividing circuit (not shown), a waveform generation circuit (not shown) that generates various clock waveforms by dividing the oscillation signal S1 of the oscillation circuit, and It is composed of other logic circuits (not shown), regulator circuits (not shown) for operating these circuits, and the like.

  The first control means 40 includes first to third boost signals S21a to S21c, fourth to sixth boost signals S22a to S22c, and seventh to tenth boost signals S23a to S21c. S23d and the oscillation signal S1 of the oscillation circuit are output. These boost signals are connected to first booster 201 described later. Further, a voltage detection signal S2 output from the voltage detection means 90 described later is input.

  The oscillation detection means 50 is a circuit block including a circuit that detects the oscillation signal S1 of the oscillation circuit, and outputs an oscillation detection output signal S3.

  The oscillation detection means 50 is a means for detecting, based on the oscillation signal S1 of the oscillation circuit, that the first power storage means 30 is charged to a state where the first control means 40 is operable and starts the boosting operation. In other words, it is an operation detection unit of the first control unit 40. Therefore, other methods may be used as long as the operation of the first control means 40 can be detected. Even when oscillation is detected, it may be detected by the presence or absence of an output from the frequency divider.

  The switch means 60 is a switch for connecting the power supply means 10 and the first power storage means 30. When the boosting means 20 stops operating, the voltage charged in the first power storage means 30 is the power supply means. When the voltage is lower than 10, the first power storage means 30 and the power supply means 10 are connected, and when boosting is started, the oscillation detection means 50 detects the oscillation of the oscillation circuit and the oscillation detection signal S3 is at the high level. It is composed of a circuit that is in an open state.

The second power storage means 70 is provided for the purpose of charging the boosted voltage output output from the output node 20c of the second boosting means 202 and operating the second control means 80 and the voltage detecting means 90 described later. . The positive electrode of the second power storage means 70 is grounded, and the negative electrode is connected to the output node 20 c of the second boosting means 202, the second control means 80, and the voltage detection means 90.

  The second power storage means 70 may be a power source for operating the timepiece function by means for realizing the timepiece function of the rechargeable timepiece.

  The second control unit 80 generates a first to fourteenth boost signals S24a to S24d which are boost signal groups from the oscillation signal S1 of the first control unit 40 and other logic circuits (not shown). (Not shown) and a regulator circuit (not shown) for operating these circuits. The second control means 80 receives the voltage detection signal S2 output from the voltage detection means 90 described later, and outputs the 11th to 14th boost signals S24a to S24d.

The voltage detection unit 90 is a circuit block including a circuit that detects a boosted voltage charged in the second power storage unit 70, and outputs a voltage detection signal S2.
The voltage detection unit 90 is a unit that detects that the second power storage unit has been charged to a state where the second control unit 80 can operate.

  Next, the configuration of the booster 20 will be described with reference to FIG.

  The boosting unit 20 includes a first boosting unit 201 and a second boosting unit 202.

  The first booster 201 includes a first booster block 21, a second booster block 22, and a third booster block 23. Each booster block 21-23 controls the capacitor and the charge / discharge of the capacitor. This is a circuit block composed of a low-voltage MOSFET.

  The first booster block 21 includes a first booster switch 21a, a second booster switch 21b, a third booster switch 21c, and a first capacitor 21e.

  Similarly, the second booster block 22 includes a fourth booster switch 22a, a fifth booster switch 22b, a sixth booster switch 22c, and a second capacitor 22e.

  The third booster block 23 includes a seventh booster switch 23a, an eighth booster switch 23b, a ninth booster switch 23c, a tenth booster switch 23d, and a third capacitor 23e.

  The first boost switch 21a, the fourth boost switch 22a, and the seventh boost switch 23a are P-channel MOSFETs, and the other boost switches are all N-channel MOSFETs. All bulk terminals are connected to source terminals.

  The drain terminal of the first boost switch 21a is connected to the positive terminal of the first capacitor 21e and the drain terminal of the second boost switch 21b, and the source terminal is grounded.

  The drain terminal of the fourth boost switch 22a is connected to the positive terminal of the second capacitor 22e and the drain terminal of the fifth boost switch 22b, and the source terminal is grounded.

  The drain terminal of the seventh boost switch 23a is connected to the positive terminal of the third capacitor 23e and the drain terminal of the eighth boost switch 23b, and the source terminal is grounded.

The source terminal of the second booster switch 21b is connected to the node 11 connected to the negative electrode of the power supply means 10 and the drain terminal of the third booster switch 21c.

  The source terminal of the fifth boost switch 22b is connected to the negative electrode of the first capacitor 21e, the source terminal of the third boost switch 21c, and the drain terminal of the sixth boost switch 22c.

  The source terminal of the eighth boost switch 23b is connected to the negative electrode of the second capacitor 22e, the source terminal of the sixth boost switch 22c, and the drain terminal of the ninth boost switch 23c.

  The node 20 a is a node connecting the source terminal of the tenth boost switch 23 d and the negative electrode of the first power storage means 30, and outputs a boosted voltage that is four times the voltage of the power supply means 10 to charge the first power storage means 30. .

  The node 20b is a node connecting the source terminal of the ninth booster switch 23c, the negative terminal of the third capacitor 23e, and the drain terminal of the tenth booster switch 23d, and outputs a quadruple boosted voltage in the same manner as the node 20b. Input to the second booster 202.

  The second booster 202 is constituted by a fourth booster block 24. The booster block 24 is a circuit block composed of a capacitor and the above-mentioned high voltage MOSFET that controls charging / discharging of the capacitor.

  The fourth booster block 24 includes an eleventh booster switch 24a, a twelfth booster switch 24b, a thirteenth booster switch 24c, a fourteenth booster switch 24d, and a fourth capacitor 24e. Reference numeral 24a denotes a P-channel MOSFET, and twelfth to fourteenth boost switches 24b to 24d are N-channel MOSFETs. All the bulk terminals of the MOSFETs described above are connected to the source terminals.

  The drain terminal of the eleventh boost switch 24a is connected to the positive terminal of the fourth capacitor 24e and the drain terminal of the twelfth boost switch 24b, and the source terminal is grounded.

  The source terminal of the twelfth boost switch 24b is connected to the node 20b and the drain terminal of the thirteenth boost switch 24c.

  The source terminal of the thirteenth boost switch 24c is connected to the negative terminal of the fourth capacitor 24e and the drain terminal of the fourteenth boost switch 24d.

  The node 20c is a node that connects the source terminal of the fourteenth boost switch 24d and the negative electrode of the second power storage means 70, and outputs a boosted voltage that is eight times the voltage of the power supply means 10 to charge the second power storage means 70. To do.

  The booster circuit according to the embodiment of the present invention is configured as described above.

  Next, the overall operation of the booster circuit according to the embodiment of the present invention will be described with reference to FIGS.

  FIG. 3 is a transition diagram showing the transition of the connection state of the booster circuit according to the embodiment of the present invention. In order to clearly show the connection state, each booster switch and the switch means 60 are simply described.

  First, the power supply means 10 is installed in an environment capable of generating an output voltage of about 0.5V. Then, as described above, in this state, the switch unit 60 is in the connected state, and the generated power of the power source unit 10 can be charged to the first power storage unit 30 via the switch unit 60, Charging is performed (see FIG. 3A).

  If the terminal voltage of the 1st electrical storage means 30 is charged to about 0.5V, the 1st control means 40 will start operation | movement. When the first control means 40 starts operation, the oscillation signal S1 is output from the oscillation circuit of the first control means 40, and the boost clocks S21a to S24d, which are signals for operating the boost means, are output in a predetermined waveform. Then, the boosting operation is started.

  Further, when the oscillation signal S1 is output, the oscillation detection means 50 changes the output of the oscillation detection output signal S3 from the low level to the high level. Then, the switch means 60 is turned off, and the power supply means 10 and the first power storage means 30 are shut off.

  Next, when the boosting operation starts, the first cycle in FIG. 4 is reached. In the first cycle, the boosting operation is performed by repeating the period T1 and the period T2.

  First, in the period T1, the first boost switch 21a, the third boost switch 21c, the fourth boost switch S22a, the sixth boost switch 22c, the seventh boost switch 23a, and the ninth boost switch S23c are turned on. Therefore, the first capacitor 21e, the second capacitor 22e, and the third capacitor 23e are connected in parallel to both ends of the power supply means 10, and charge the first capacitor 21e, the second capacitor 22e, and the third capacitor 23e. (See FIG. 3B).

  Next, in the period T2, the first boost switch 21a, the third boost switch 21c, the fourth boost switch 22a, the sixth boost switch 22c, the seventh boost switch 23a, and the ninth boost switch 23c are turned off. On the contrary, since the second boost switch 21b, the fifth boost switch 22b, the eighth boost switch 23b, and the tenth boost switch 23d are turned on, the first capacitor 21e, the second capacitor 22e, The first power storage means 30 is connected to both ends of the power supply means 10 connected in series to the third capacitor 23e, and the first power storage means 30 is charged.

At this time, the first power storage means 30 is charged with boosted power four times the power generated by the power supply means 10. When the power generation voltage of the power supply means 10 is 0.5V, the boosted voltage is 2V, and the voltage applied to the MOSFET used in the boost switches 21a to 23d is 2V at the maximum.
Further, since the voltage applied to the MOSFET is 0.5 V immediately after the boosting operation is started, the low voltage MOSFET is selected in order to operate the MOSFET normally.

  Further, during the first cycle, the eleventh boost switch 24a, the twelfth boost switch 24b, the thirteenth boost switch 24c, and the fourteenth boost switch 24 are always off, but are used in each boost switch. In the MOSFET, the bulk terminal and the source terminal are connected (see FIG. 5A), and a diode-connected state is created between the source terminal and the drain terminal via the bulk terminal. ) Can be considered equivalent to the circuit configuration.

  Therefore, when the voltage at the node 20b increases during the first cycle, the conductive state is substantially established between the source terminal and the drain terminal of the thirteenth boost switch 24c. Similarly, the fourteenth step-up switch 24d is also turned on, and the second power storage unit 70 is also charged (see FIG. 3C).

When the terminal voltage of the second power storage means 70 is charged to about 0.6 V, the second control means 80 and the voltage detection means 90 start to operate. Assuming that the voltage at which the second control means 80 detects the operable state is 1.4V, the voltage detection means 90 is at a high level when the terminal voltage of the second power storage means 70 exceeds 1.4V. Changes from low to low.

  Then, the second cycle in FIG. 3 is switched, and the first control means 40 and the second control means 80 each output a predetermined waveform of the second cycle.

  Note that the voltage at which the second control means 80 detects the operable state is set to 1.4 V, assuming that the second control means 80 is driven by a 1.1 V output regulator, so that a margin is provided. It is set. An appropriate value can be set in consideration of actual use conditions.

  During the second cycle, the boosting operation is performed by repeating the period T3, the period T4, the period T5, and the period T6.

  First, in the period T3, the second boost switch 21b, the fifth boost switch 22b, the eighth boost switch 23b, the tenth boost switch 23d, the eleventh boost switch 24a, the twelfth boost switch 24b, The thirteenth boost switch 24c and the fourteenth boost switch 24d are off, and the first boost switch 21a, the third boost switch 21c, the fourth boost switch 22a, the sixth boost switch 22c, and the seventh boost switch Since the boost switch 23a and the ninth boost switch 23c are turned on, the first capacitor 21e, the second capacitor 22e, and the third capacitor 23e are connected in parallel to both ends of the power supply means 10, and the first capacitor 21e. And the second capacitor 22e and the third capacitor 23e are charged (see FIG. 3D).

  Next, in a period T4, the first boost switch 21a, the third boost switch 21c, the fourth boost switch 22a, the sixth boost switch 22c, the seventh boost switch 23a, the ninth boost switch 23c, and the twelfth The second boost switch 24b and the fourteenth boost switch 24d are turned off, and the second boost switch 21b, the fifth boost switch 22b, the eighth boost switch 23b, the tenth boost switch 23d, and the eleventh boost switch 24a. And the thirteenth step-up switch 24c are turned on, so that the first power storage unit 30 and the fourth capacitor are connected to both ends of the first capacitor 21e, the second capacitor 22e, and the third capacitor 23e connected to the power source unit 10 in series. Are connected in parallel to charge the first power storage means 30 and the fourth capacitor 24e (see FIG. 3E). At this time, the first power storage means 30 and the fourth capacitor 24e are charged with boosted power four times the power generated by the power supply means 10.

  Next, in the period T5, the second boost switch 21b, the fifth boost switch 22b, the eighth boost switch 23b, the tenth boost switch 23d, the eleventh boost switch 24a, the twelfth boost switch 24b, and the thirteenth boost switch 21b. The first boost switch 24c and the fourteenth boost switch 24d are turned off, and the first boost switch 21a, the third boost switch 21c, the fourth boost switch S22a, the sixth boost switch 22c, and the seventh boost switch 23a. And the ninth step-up switch S23c are turned on, so that the first capacitor 21e, the second capacitor 22e, and the third capacitor 23e are connected in parallel to both ends of the power supply means 10, and the first capacitor 21e and the The second capacitor 22e and the third capacitor 23e are charged (see FIG. 3F).

  Next, in the period T6, the first boost switch 21a, the third boost switch 21c, the fourth boost switch S22a, the sixth boost switch 22c, the seventh boost switch 23a, and the ninth boost switch S23c are turned off. Since the second boost switch 21b, the fifth boost switch 22b, the eighth boost switch 23b, the twelfth boost switch 24b, and the fourteenth boost switch 24d are turned on, the first capacitor 21e and the second The second power storage means 70 is connected to both ends of the power supply means 10 connected in series to the capacitor 22e, the third capacitor 23e, and the fourth capacitor 24e to charge the second power storage means 70 (FIG. 3 ( g)).

At this time, the second power storage means 70 is charged with boosted power that is eight times the power generated by the power supply means 10. When the power generation voltage of the power supply means 10 is 0.5V, the boosted voltage is 4V, and the voltage applied to the MOSFET used in the boost switches 24a to 24d is 4V at the maximum.
Further, since the boost switches 24a to 24d operate only when the terminal voltage of the second power storage means 70 is 1.4 V or higher, the switch to be selected is a high breakdown voltage MOSFET.

  As described above, the booster circuit according to the embodiment of the present invention operates.

  In the embodiment of the present invention, the boosting factor is about 8. However, it is possible to easily increase the boosting factor to other integer multiples by changing the number of boosting capacitors and the boosting signal.

  Further, in the embodiment of the present invention, the two power storage units are configured. However, there may be a case where there are a number of power storage units depending on the boosting magnification and the voltage for driving the boost switch.

  Further, although the control means is connected to the power storage means in parallel, it is also conceivable to distribute these boosted outputs to the power storage means and the control means by using them as separate power systems.

  Furthermore, even if the power supply means selects a thermoelectric generator or the like, the same operation as in the embodiment of the present invention can be obtained.

The effects of the present invention are as follows.
(1) Coexistence of low power consumption and high withstand voltage by dividing blocks When charging power storage means such as lithium ion batteries that require a charge voltage of 3 V or more,
The first block 1 required for boosting to a low voltage of 3 V or less is configured by a process that can operate at a low voltage, and the second block 2 that is boosted to 3 V or higher is configured by a high breakdown voltage process.

This makes it possible to achieve both low power consumption and high breakdown voltage.
(2) Reduction of power consumption by partial operation In gradually increasing the voltage from the stop state of the booster circuit, until the power storage unit is charged to a voltage that requires the boosting operation by the second boosting unit 202, Since the second boosting means 202 is stopped, there is no circuit that operates wastefully, and a boosting operation with low power consumption is possible.
(3) Charging Using Parasitic Diode The charging of the second power storage unit 70 when the second boosting unit 202 is stopped is performed via the parasitic diode in the second boosting unit 202. Therefore, an additional circuit such as a bypass switch is not required, and the size can be reduced.

  Here, FIG. 6 shows a system configuration diagram when the circuit configuration shown in FIG.

  FIG. 6 is a system configuration diagram in a case where components other than the power source unit 10, the first power storage unit 30, and the second power storage unit 70 are configured by one chip. The same components as those in FIG. 1 are denoted by the same reference numerals, and the first block 1 and the second block 2 are simply described.

  As shown in FIG. 6, a first block 1 composed of a low voltage MOSFET operating at 3V and a second block 2 composed of a high voltage MOSFET are mixed.

  The configuration of FIG. 6 has an advantage that the mounting area can be reduced and the number of mounting steps can be reduced because the booster circuit is configured by one chip. On the other hand, since both processes are mixed, the semiconductor manufacturing cost may increase.

FIG. 7 is a system configuration diagram when the first block 1 and the second block 2 are configured by separate chips. As the number of chips increases, the mounting area increases and mounting man-hours increase. On the other hand, the chip 100 constituting the first block 1 can be composed of only a low-voltage MOSFET, and the chip 200 constituting the second block can be composed only of a high-voltage MOSFET, so that it can be manufactured relatively easily and the semiconductor manufacturing cost is reduced. It is possible.

  The configuration shown in FIG. 6 or the configuration shown in FIG. 7 may be adopted as appropriate in consideration of the mounting area, cost, etc. of the product to be applied.

DESCRIPTION OF SYMBOLS 1 1st block 2 2nd block 10 Power supply means 20 Boosting means 30 1st electrical storage means 40 1st control means 50 Oscillation detection means 60 Switch means 70 2nd electrical storage means 80 2nd control means 90 Voltage detection Means 201 First boosting means 202 Second boosting means

Claims (6)

Power supply means (10) for converting external energy into electrical energy;
First boosting means (201) for boosting the power generation output of the power supply means (10);
First power storage means (30) for charging the boost output of the first boost means (201);
First control means (40) for controlling the boosting operation of the first boosting means (201) using the first power storage means (30) as a power source;
Second boosting means (202) for boosting the boosted output of the first boosting means (201);
Second power storage means (70) for charging the boost output of the second boost means (202);
Second control means (80) for controlling the boosting operation of the second boosting means (202) using the second power storage means (70) as a power source;
Voltage detection means (90) for detecting the voltage of the second power storage means (70),
The first block (1) includes the first booster (201) and the first controller (40).
The second block (2) includes the second booster (202), the second controller (80), and the voltage detector (90).
The first block (1) is configured to be operable at a first voltage value or less,
The booster circuit according to claim 2, wherein the second block (2) is configured to be operable at a second voltage value higher than the first voltage value. An initial stage in which the power supply means (10) and the first power storage means (30) are connected and the first power storage means (30) is charged when boosting from the stop state is started;
When the first power storage means (30) is charged, the first control means (40) starts operating to control the boosting operation of the first boosting means (201), and A first cycle in which the boost output of the boosting means (201) is charged to the first power storage means (30) and charged to the second power storage means (70);
When the second power storage means (70) is charged to a predetermined voltage or higher, the second control means (80) starts operating to control the boosting operation of the second boosting means (202). 2. The booster circuit according to claim 1, further comprising: a second cycle in which the boost output of the second booster means (202) is charged in the second power storage means (70). In the first cycle, charging of the boosted output of the first booster (201) to the second power storage unit (70) is performed via the stopped second booster (202). The booster circuit according to claim 2, wherein: Detection means (50) for detecting an operating state of the first control means (40);
A switch means (60) connected between the power supply means (10) and the first power storage means (30) and controlled to be opened and closed by the detection means (50);
The switch means (60)
When the detection means (50) detects the stop of the first control means (40), the detection means (50) is in a closed state to connect the power supply means (10) and the first power storage means (30),
When the detection means (50) detects the operation of the first control means (40), the detection means (50) is opened, and the power supply means (10) and the first power storage means (30) are disconnected. The booster circuit according to claim 2 or 3. 5. The booster circuit according to claim 4, wherein the detection means (50) and the switch means (60) are included in the first block (1). The booster circuit according to any one of claims 1 to 5, wherein the first block (1) and the second block (2) are formed of semiconductors of different chips.

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