JP2015141541A - Image recognition apparatus, image recognition method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image recognition apparatus capable of preventing occurrence of interference or reduction of storage capacity by removing a correlation between patterns of images while partially holding sparse of image patterns to be stored in an associated storage model, an image recognition method and a program.SOLUTION: An image recognition method includes a logical operation step in which, on the basis of a source pattern of a plurality of designated images, a mask pattern is generated that is a binary pattern being random in an allocation probability for suppressing inversion of high appearance frequency in the source pattern among random patterns. By calculating exclusive OR or negative exclusive OR of the source pattern and the mask pattern, a masked pattern is generated which suppressing the bit inversion in a value of the high appearance frequency. The masked pattern corresponding to the mask pattern is learnt as a connection pattern by an associated storage model using a neural network.

Description

  The present invention relates to an image recognition apparatus, an image recognition method, and a program.

  Conventionally, self-associative memory models, sequence associative memory models, and the like have been developed as associative memory models in neural networks.

  For example, in Patent Document 1, a self-propagating neural network is used in the storage layer to form a subnetwork in which nodes corresponding to the pattern of the input vector are connected, and learning is performed as a subclass of the input vector. An association is established between the key class of the key vector that is the key of the association held in the storage layer and the association class that is recalled from the key vector, and the input key vector is changed to the key class or association class. It is disclosed that the weight of a corresponding node is output as a recall result.

  In Non-Patent Document 1, a color image is converted into binary data, a bit is inverted, a reversible code is generated, and stored in a neural network, so that it is inverted with a bit expression when decoded. It is disclosed to adjust the representation to be the same integer value.

JP 2011-86132 A

“Oku, Makito, Aihara, Kazuyuki,“ Associative dynamics of color images in a large-scale I l e and p e n e i n e i n e t e n e i n e i n e i n e i t e n e i t e n e i t e n e i ” 508-521 (2011).

  However, in the conventional associative memory model, when the original image pattern is messed up by the mask pattern and stored in the associative memory model, the sparseness of the associative memory model is inherent in the associative memory model. There is a problem that the effect of increasing the storage capacity due to cannot be obtained.

  The present invention has been made in view of the above problems, and removes the correlation between image patterns while retaining a part of the sparsity of the image patterns stored in the associative memory model, thereby reducing the occurrence of interference and reducing the storage capacity. An object of the present invention is to provide an image recognition apparatus, an image recognition method, and a program that can be prevented.

  In order to achieve such an object, an image recognition device of the present invention is an image recognition device including at least a storage unit and a control unit, and the control unit is based on a plurality of designated original patterns of images. A mask generating means for generating a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of a bit that has a high appearance frequency in the original pattern, and the original pattern and the mask pattern are exclusive A logical operation means for generating a masked pattern in which bit inversion of a value having a high appearance frequency is suppressed by obtaining a logical sum or a negative exclusive logical sum, and a concatenated pattern of the masked pattern associated with the mask pattern And learning means for learning with an associative memory model using a neural network.

  The image recognition apparatus according to the present invention is characterized in that, in the image recognition apparatus described above, the mask generation unit sets the allocation probability to be smaller as the firing rate of the original pattern is closer to 0 or 1. .

Moreover, the image recognition apparatus of the present invention is characterized in that, in the above-described image recognition apparatus, the mask generation means obtains the allocation probability based on the following equation.

  In the image recognition apparatus according to the present invention, in the image recognition apparatus described above, the mask generation unit has a smaller correlation between the plurality of original patterns as the firing rate of the original pattern is closer to 0 or 1. As described above, the allocation probability is set to be small.

  In the image recognition apparatus of the present invention, in the image recognition apparatus described above, the logic operation unit sets the mask pattern common to any number of bits in the original pattern among the plurality of images. And creating the mask pattern.

  The image recognition apparatus according to the present invention is the image recognition apparatus described above, wherein the logical operation means divides the original pattern of length N by the plurality of images into L-1 blocks from the beginning. The mask pattern having a different value for each block is set, and the connected pattern having a length of LN / (L-1) is generated.

In the image recognition apparatus according to the present invention, in the image recognition apparatus described above, the mask generation means sets the mask pattern having a different value for each block from the allocation probability p to the following equation: Based on this, the distribution probability g for inverting the bit string in the block is obtained.

  The image recognition apparatus according to the present invention is the image recognition apparatus described above, wherein the logical operation means uses the one-dimensional binary data of the image as the original pattern and is based on the original pattern having the same or short length. Using the random binary data of the allocation probability as the mask pattern, and generating the masked pattern by obtaining an exclusive OR or a negative exclusive OR of corresponding values of both data. .

  In the image recognition apparatus according to the present invention, in the image recognition apparatus described above, the learning unit stores the mask pattern in the storage unit, and the logical operation unit is a matching pattern that is a designated clue image. On the other hand, a masked collation pattern is generated by obtaining the exclusive OR or the negative exclusive OR using one of the plurality of mask patterns stored in the storage unit, and the control unit Repeats the state update until the masked matching pattern is introduced into the associative memory model and converges, and if the result of the energy function in the converged state is less than the threshold value, a mask with another mask pattern is used. Recollection means for searching for an original pattern by trying a normalized collation pattern is further provided.

  The present invention also relates to an image recognition method. The image recognition method of the present invention is an image recognition method executed in a computer having at least a storage unit and a control unit, and is designated by the control unit. A mask generation step for generating a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of a bit having a high appearance frequency in the original pattern based on the original pattern of a plurality of images; Corresponding to the mask pattern, a logical operation step for generating a masked pattern in which bit inversion of the value having a high appearance frequency is suppressed by calculating an exclusive OR or a negative exclusive OR of the pattern and the mask pattern Associative memory model using a neural network with the masked pattern attached as a connected pattern Characterized in that it comprises a learning step of learning Te.

  The present invention also relates to a program. The program of the present invention is a program for causing a computer including at least a storage unit and a control unit to execute the program. A mask generation step of generating a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of a bit having a high appearance frequency in the original pattern among the binary values based on the pattern, and the original pattern and the mask pattern A logical operation step of generating a masked pattern in which bit inversion of a value having a high appearance frequency is suppressed by obtaining an exclusive OR or a negative exclusive OR, and the masked mask associated with the mask pattern Learning with an associative memory model using neural networks, with patterns as connected patterns A learning step of, characterized in that for the execution.

  The present invention also relates to a recording medium, wherein the program described above is recorded.

  According to the present invention, based on the original patterns of a plurality of designated images, a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of bits that frequently occur in the original pattern among the binary values. Generating a masked pattern in which bit inversion of a value having a high appearance frequency is suppressed by obtaining an exclusive OR or a negative exclusive OR of the original pattern and the mask pattern, and generating a mask pattern associated with the mask pattern. A mask pattern is used as a connection pattern, and learning is performed using an associative memory model using a neural network. As a result, the original image is messed up by the mask pattern, and the correlation between the image patterns is reduced, so that the occurrence of interference can be prevented and the reduction in storage capacity can be suppressed. In addition to performing the above randomization, when creating a mask pattern based on the original pattern, a random mask pattern is created so as to retain a part of the sparsity of the original pattern. The effect of increasing the storage capacity due to sparsity can be obtained. Also, since the weight does not take an extreme value, it is convenient for hardware implementation.

  Also, according to the present invention, when creating a mask pattern based on the original pattern, the allocation probability is set to be smaller as the firing rate of the original pattern is closer to 0 or 1, so that the greater the sparsity, the less the randomness. Thus, there is an effect that the sparsity can be appropriately maintained while obtaining the effect of decreasing the correlation between patterns due to randomization.

Further, according to the present invention, when creating a mask pattern based on the original pattern, the allocation probability is obtained based on the following formula, so that an appropriate allocation probability can be obtained by simple calculation based on the firing rate of the original pattern. There is an effect that it can be calculated.

  Further, according to the present invention, when the mask pattern is created based on the original pattern, the allocation probability becomes smaller as the firing rate of the original pattern is closer to 0 or 1, and as the correlation between the plurality of original patterns is smaller. Since the correlation between patterns is large and sparsity is small, priority is given to increase in storage capacity due to randomization, while when the correlation between patterns is small and sparsity is large, the sparsity By giving priority to the increase in the storage capacity due to the maintenance, it is possible to increase the storage capacity.

  Further, according to the present invention, a mask pattern is created by setting a common mask pattern for each arbitrary number of bits in the original pattern of a plurality of images. It is possible to suppress the extension of the storage capacity and to suppress the decrease in the storage capacity.

  Further, according to the present invention, an original pattern of length N by a plurality of images is divided into L-1 blocks from the beginning, and mask patterns having different values for each block are set, and LN / (L -1) is generated. As a result, the present invention has the effect that the mask pattern can be set in units of blocks, the extension of the connection pattern can be suppressed, and the reduction in storage capacity can be suppressed.

Further, according to the present invention, in order to set a mask pattern having a different value for each block, a distribution probability g for inverting the bit string in the block is obtained from the allocation probability p based on the following expression, There is an effect that it is possible to appropriately obtain a block that inverts from the allocation probability.

  In addition, according to the present invention, the corresponding values of both data are obtained by using one-dimensional binary data of an image as an original pattern and random binary data of an allocation probability based on the same or short original pattern as a mask pattern. Since the masked pattern is generated by obtaining the exclusive OR or the negative exclusive OR, there is an effect that the correlation between the original images can be reduced by a simple calculation.

  Further, according to the present invention, an exclusive OR or a negative exclusive OR is obtained for one of the specified mask patterns stored in the storage unit with respect to a matching pattern that is a cue image. To generate a masked collation pattern, repeat the state update until the masked collation pattern is introduced into the associative memory model and converge, and another result is obtained until the energy function value of the convergence state is equal to or less than the threshold value. The masked collation pattern by the mask pattern is tried to search for the original pattern. Thereby, even if it is a case where a mask pattern is not known, this invention has an effect that the corresponding correct pattern candidate can be searched from a collation pattern.

FIG. 1 is a diagram schematically showing the memorizing stage of the associative memory model. FIG. 2 is a diagram schematically showing the recall stage of the associative memory model. FIG. 3 is a diagram schematically showing a case where patterns having a small correlation with each other are stored. FIG. 4 is a diagram schematically showing a case where patterns having a large correlation with each other are stored. FIG. 5 is a diagram illustrating a relationship among the original pattern, the mask pattern, the mask pattern, and the connection pattern. FIG. 6 is a diagram illustrating an example of the XNOR operation and the XOR operation. FIG. 7 is a diagram illustrating an example of a connection pattern. Figure 8 is a diagram showing an example of connection pattern of the specified mask pattern r _k different for each block. FIG. 9 is a diagram schematically showing a sparse pattern and a non-sparse pattern. FIG. 10 is a diagram schematically showing a process of generating a mask pattern by randomizing while maintaining a part of sparsity according to the present embodiment. FIG. 11 is a diagram illustrating an example of the XOR operation when the bit “1” is a minority group. FIG. 12 is a diagram illustrating an example of an XNOR operation when the bit “0” is a minority. FIG. 13 is a diagram illustrating an example of block processing when the bit “1” is a minority group. FIG. 14 is a diagram illustrating an example of block processing when the bit “0” is a minority. FIG. 15 is a block diagram illustrating an example of the image recognition apparatus 100 to which the present exemplary embodiment is applied. FIG. 16 is a graph showing the optimal allocation probability p with respect to the firing rate f and correlation b of the original pattern. FIG. 17 is a diagram showing the storage capacity when the optimal allocation probability p is set for the firing rate f and correlation b of the original pattern. FIG. 18 is a flowchart illustrating an example of basic processing of the image recognition apparatus 100 in the present embodiment. FIG. 19 is a flowchart illustrating an example of learning processing of the image recognition apparatus 100 according to the present embodiment. FIG. 20 is a flowchart illustrating an example of the recall process of the image recognition apparatus 100 according to the present embodiment. FIG. 21 is a flowchart illustrating an example of the recall process using the series associative memory model of the image recognition apparatus 100 according to the present embodiment.

  Embodiments of an image recognition apparatus, an image recognition method, and a program according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. For example, the present invention may be applied to various associative memory models as well as the associative memory model shown in the present embodiment. In the following embodiments, a self-associative memory model may be described as an example of an associative memory model. However, the present invention is not limited to this and may be applied to a sequence associative memory model. In the associative memory model, the dynamics of the neural network may be either stochastic or deterministic. In the present embodiment, there is a case where the neural network is tightly coupled (for example, a network in which all nerve cell units are coupled to each other). However, the present invention is not limited to this, and the coupling is not limited to this. A sparse neural network may be used.

[Outline of Embodiment of the Present Invention]
Hereinafter, an outline of an embodiment of the present invention will be described with reference to FIGS. 1 to 14, and then the configuration, processing, and the like of the present embodiment will be described in detail. Here, FIG. 1 is a diagram schematically showing the memorizing stage of the associative memory model.

  An associative memory model is a kind of neural network model. The Hopfield network, which is a type of associative memory model, is a model of a neural network proposed by Hopfield in 1982. As an example, as shown in FIG. 1, a neural network in which nerve cell (neuron) units are coupled is constructed and interacts between nerve cell units. The strength of connection between nerve cell units is expressed as a weight (connection coefficient), and the strength increases or decreases by learning.

  FIG. 1 schematically shows an inscription stage for storing a binary image of four patterns in a neural network. In the memorization stage of the self-associative memory model, a plurality of memory patterns are stored, and in the recall stage, one pattern is recalled. Whether or not each neuron unit in the network is fired is determined by the sum of inputs from other neuron units to be connected. The memory pattern in the auto-associative memory model is a way of arranging the activity states of neuronal cell units (typically, two types of firing state and resting state). In the Hopfield model, the memory pattern is stored in the neural network by determining the weight of the synapse connection according to a specific learning rule (such as the Hebb rule) at the inscription stage. Further, at the recall stage, the energy function representing the network state monotonously decreases according to the state update rule, and the update process is repeatedly executed until a minimum value state is reached. FIG. 2 is a diagram schematically showing the recall stage of the associative memory model.

  As shown in FIG. 2, in the recall stage of the self-associative memory model, the original pattern stored in the neural network is searched from the collation pattern serving as a clue to obtain the recalled pattern. More specifically, when retrieving a memory pattern, first, an initial pattern as a clue is given to the neural network, and then a desired memory pattern is updated by updating the state of the neural network a plurality of times according to a specific rule. Get. Note that the clue pattern does not have to be the original pattern itself, but may be a part of the pattern desired to be obtained. That is, in the self-associative memory model, a stored pattern that is most similar to the cue pattern given as an input is obtained.

  The number of patterns that can be stored increases as the number of neurons (number of neuronal cell units) N in the network increases, but the number of patterns that can be stored is limited by the correlation between patterns. The number of patterns in which the self-associative memory model can be remembered is called memory capacity. It is known that when a standard learning rule or state update rule is used as the upper limit of the theoretical storage capacity, it is about 0.14 N with respect to the size N of the neural network and the storage pattern. However, in reality, it is greatly influenced by the correlation of the storage patterns. Here, FIG. 3 is a diagram schematically showing a case where patterns having a small correlation are stored, and FIG. 4 is a diagram schematically showing a case where patterns having a high correlation are stored.

  As shown in FIG. 3, when the storage pattern is a random pattern and the correlation is small, a storage capacity of 0.14N close to the theoretical limit can be obtained. Furthermore, it is generally known that the storage capacity is further increased when the storage pattern is uncorrelated and sparse (when the appearance frequency of each bit value is greatly biased to one of the binary values). However, as shown in FIG. 4, whether the storage pattern is sparse or not, when similar patterns are stored, the correlation between the storage patterns is large, so that the storage capacity generally increases. It will drop significantly.

  Conventionally, (1) a method of improving a learning rule by using a pseudo inverse matrix or sequentially adjusting weights, and (2) adding a bit to the end or a bit against the problem of a decrease in storage capacity. A method of changing a pattern itself by changing a part of the pattern has been proposed. However, since all of the conventional methods have a large calculation load, it is difficult to apply when the size N of the neural network and the storage pattern is large.

  Therefore, the inventors of the present application have made extensive studies and have developed the following new method. As an example, the new method (1) prepares a mask pattern for a storage pattern (original pattern), (2) generates a masked pattern by XNOR operation or XOR operation of the storage pattern and the mask pattern, and (3) The basic element is to store a connected pattern obtained by connecting a mask pattern and a mask pattern in a neural network. In this way, by using the mask pattern for randomization, the pattern to be stored can be pseudo-orthogonalized, and the reduction in storage capacity due to correlation can be suppressed. Here, FIG. 5 is a diagram illustrating the relationship among the original pattern, the mask pattern, the mask pattern, and the connection pattern.

  An XOR operation or XNOR operation is performed for the purpose of randomizing the binary signal sequence. As shown in FIG. 5, as a principle, an original signal sequence (original pattern) and a (pseudo) random number sequence (random mask) for masking it are prepared, and XOR operation or XNOR operation of both is performed. Thus, a messy signal sequence (masked pattern) is obtained. As a result, the storage pattern becomes confused and the correlation becomes small, interference between patterns can be reduced, and a reduction in storage capacity can be prevented.

  More specifically, the embodiment of the present invention generates a mask pattern of (1) a random binary pattern (random mask).

  In this embodiment, (2) a masked pattern is generated by obtaining an exclusive OR (XOR) or a negative exclusive OR (XNOR) of the original pattern of a plurality of designated images and the mask pattern. To do. The mask pattern and the first connection pattern may be stored in the storage unit. As an example, the present embodiment uses an exclusive OR of values corresponding to both data using one-dimensional binary data of an image as an original pattern and random binary data of the same or short length as a mask pattern. XOR) or negative exclusive OR (XNOR) is obtained to generate a masked pattern. Here, FIG. 6 is a diagram illustrating an example of the XNOR operation and the XOR operation.

When binary data of {0, 1} is used as the original pattern (Input1) and the mask pattern (Input2), the XNOR operation shown in FIG. 6A is performed to obtain the masked pattern value (Output). The binary data may be any two values. For example, when binary data of {1, −1} is used as the original pattern (Original) and the mask pattern (Mask), FIG. The XNOR operation shown in b) may be performed to obtain the masked pattern value (Masked). The XNOR calculation in this case corresponds to the product of the original pattern r _i and the mask pattern ξ _i multiplied by r _i × ξ _i .

In one XOR operation, when binary data whose original pattern (Input1) and mask pattern (Input2) are {0, 1} is used, the XOR operation shown in FIG. 6C is performed, and the value of the masked pattern (Output) ) Also in this case, the binary data may be any two values. As an example, when binary data having an original pattern (Original) and a mask pattern (Mask) of {1, -1} is used, The value of the masked pattern (Masked) may be obtained by performing the XOR operation shown in FIG. The XOR operation in this case corresponds to a value obtained by multiplying the original pattern r _i and the mask pattern ξ _i and exchanging the signs, −r _i × ξ _i .

  Subsequently, in the memorizing stage, the present embodiment (3) learns by using an associative memory model using a neural network with a mask pattern associated with the mask pattern as a connected pattern. The order of bits in the connection pattern may be any order. Moreover, the connection pattern completely holds the information of the original pattern. This is because the original pattern can be restored by performing the same logical operation (XNOR / XOR) on the mask pattern / masked pattern pair again. Here, FIG. 7 is a diagram illustrating an example of a connection pattern.

As shown in FIG. 7 as an example, the present embodiment, and the object to be mask pattern r _k xi] _k performing the XOR / XNOR operation using the mask pattern r _k different for each one of the original pattern xi] _k, may be allowed to memorization as connection pattern of the mask pattern r _k alternately arranged (k is the block number). In this case, if the length of the original pattern is N, a connected pattern having a length of 2N is generated. Therefore, the number of necessary neurons (number of nerve cell units) doubles.

Therefore, a plurality of original patterns may be divided in units of blocks, and different mask patterns (such as random masks) may be set for each block unit to reduce the length of the connection pattern. That is, the length of the connected pattern may be made shorter than 2N by preparing a smaller number of bits of the mask pattern than the original pattern and using the same element (mask) following a plurality of XNOR operations. Here, FIG. 8 is a diagram showing an example of connection pattern of the specified mask pattern r _k different for each block. As shown in FIG. 8, in this embodiment, the original pattern of a plurality of images is divided into L-1 block units (blocks of length L including a mask pattern) from the top, and a value is obtained for each block. May be set to generate a connected pattern having a length of LN / (L-1). In the case of FIG. 7, the number of necessary neurons (number of neuronal cell units) is doubled, but by setting the block length to L as shown in FIG. 8, the number can be suppressed to L / (L-1) times.

  In the recall stage following the memorization stage, the original pattern stored in the neural network is usually searched from the input pattern as a clue to obtain the recalled pattern. The mask pattern corresponding to the matching pattern is unknown. Therefore, in the present embodiment, an exclusive OR (XOR) or a negative exclusive OR is used for a matching pattern that is a clue image by using one of a plurality of mask patterns stored in the storage unit by trial. By obtaining (XNOR), a masked matching pattern may be generated, and the original pattern may be derived using this masked matching pattern. In other words, when a masked matching pattern is introduced into the associative memory model and state update is repeated until convergence, a pattern of recall results may be obtained when the energy function value in the convergence state is less than or equal to the threshold value. . If the value of the energy function does not fall below the threshold value, a masked collation pattern using another mask pattern is tried.

  The above shows an aspect in which the original pattern is not sparse, and therefore the mask pattern is generated without considering the sparsity and the original pattern is randomized. Here, in the present embodiment, when the original pattern is sparse, the mask pattern is adjusted according to the value of the original pattern, thereby controlling the sparseness of the original pattern to be partially retained. Here, FIG. 9 is a diagram schematically showing a sparse pattern and a non-sparse pattern.

  As shown in the left diagram of FIG. 9, a pattern in which the appearance frequency of each bit is greatly biased to one of binary values is called a sparse pattern. On the other hand, as shown in the right diagram of FIG. 9, patterns in which the appearance frequency of each bit is almost equal are called non-sparse patterns.

  In the case of a sparse pattern, it is generally known that the storage capacity of an associative memory model increases. However, when the mask pattern is generated without considering the sparsity of the original pattern as described above and the original pattern is messed up, the correlation can be lowered, but the sparsity is not maintained, so that the original sparse As a result, the increase in the storage capacity due to the characteristics is lost.

  Therefore, the inventors of the present application have completed the present invention through intensive studies to maintain the sparsity of the original pattern and reduce the correlation between the original patterns. As an example, the new method proposed in the present application provides (1) a random mask pattern with an allocation probability that suppresses inversion of a bit having a high appearance frequency among binary values in a storage pattern (original pattern), and (2) storage Generate a masked pattern that suppresses bit inversion of frequently occurring values by XNOR operation or XOR operation of the pattern and mask pattern, and (3) store the connected pattern in which the mask pattern and the masked pattern are connected in the neural network Is a basic element. Here, FIG. 10 is a diagram schematically showing a process of generating a mask pattern by randomizing while maintaining a part of sparsity according to the present embodiment. As shown in FIG. 10, in the present embodiment, if the original pattern is sparse, processing is performed so that a sparse masked pattern can be obtained. In this way, by adjusting the mask pattern according to the original pattern, the minority bits are pseudo-orthogonalized by randomization, while suppressing the inversion of the majority bits, thereby maintaining sparseness. By maintaining the storage unit, it is possible to further increase the storage capacity.

  An example of a mask pattern adjustment method based on a more specific original pattern will be described. FIG. 11 is a diagram illustrating an example of the XOR operation when the bit “1” is the minority group, and FIG. 12 is a diagram illustrating an example of the XNOR operation when the bit “0” is the minority group. .

  As an example, as shown in FIG. 11 and FIG. 12, for the original bits of the minority (original bit), the allocation probability is randomized as an equal probability (1/2) in order to reduce the correlation due to randomization. Mask bits may be generated. On the other hand, as shown in FIGS. 11 and 12, mask bits are generated with an allocation probability such that the inversion ratio of the majority bits is small for the majority of the original bits in order to maintain sparsity. In the example of the figure, if the original bit is the majority, the original bit is reversed (inverted) with the allocation probability p, and is kept the same as the original bit with the probability (1-p).

  As shown in FIG. 11, when “1” is a minority, this embodiment inverts the majority bit “0” with an allocation probability p by performing an XOR operation of the original bit and the mask bit. .

  On the other hand, as shown in FIG. 12, when “0” is a minority, the present embodiment inverts the majority bit “1” with an allocation probability p by performing an XNOR operation of the original bit and the mask bit. .

  As described above, the present embodiment obtains masked bits (masked bits) in which inversion of majority bits having a high appearance frequency is suppressed. The processing after the masked pattern is obtained is the same as described above, and in the present embodiment, the generated connected pattern is learned by the associative memory model.

  In addition, when masking is performed in units of blocks in consideration of sparsity, the present embodiment may perform processing as follows. In consideration of sparsity, an example of a method for obtaining a concatenated pattern by setting a different mask pattern (random mask or the like) for each block will be described with reference to FIGS. 13 and 14. FIG. Here, FIG. 13 is a diagram illustrating an example of block processing when the bit “1” is a minority group, and FIG. 14 is a diagram illustrating an example of block processing when the bit “0” is a minority group. .

As described above, the number of bits of the mask pattern is prepared to be smaller than that of the original pattern, and the same element (mask) is continuously used for a plurality of logical operations in units of blocks, so that the length of the connected pattern is 2N. It can be made shorter. When considering sparsity, as shown in FIG. 13 as an example, by setting the distribution probability g of reversing block by block, to produce a connection pattern of the specified mask pattern r _k different for each block.

That is, as shown in FIG. 13, in the present embodiment, the original pattern of a plurality of images is divided into L-1 block units (blocks having a length of L with a mask pattern) from the beginning. At that time, a distribution probability g for determining whether or not to invert the block unit may be calculated from the allocation probability p by the following equation.

  The above is the outline of the present embodiment. In the above description, the self-associative memory model has been described as an example. However, when the sequence associative memory model is used, the present embodiment can be similarly applied. The sequence associative memory model is a variant of the self-associative memory model, which stores a sequence of memory patterns and repeatedly updates the state of the neural network to recall the stored patterns in order. . When the sequence associative memory model is used, the theoretical upper limit of the memory capacity is different from that of the self-associative memory model, but the memory capacity is still lowered due to the correlation between patterns.

  As described above, the pseudo-orthogonalization method has the advantage that (1) only necessary logical operations (XNOR / XOR) are simple calculations, so that the calculation load is small and the implementation is simple. Further, (2) each pattern can be processed independently, and there is no need to consider the relationship between the patterns. Therefore, there is an advantage that the calculation is simple and the additional storage of the pattern can be easily performed. Furthermore, (3) standard learning rules (such as Hebb learning rules that take shifts into account) can be applied as they are, and the resulting synaptic connection weights do not take extreme values. There is an advantage that it is convenient for implementation. Further, (4) since the patterns stored in the neural network are sufficiently separated from each other and their distances are substantially equal, there is an advantage that any stored pattern can be recalled stably.

  In addition, it is possible to increase the storage capacity due to the sparsity by generating a masked pattern that suppresses bit inversion of a majority bit having a high appearance frequency so that a part of the sparsity of the original pattern can be maintained. The advantage of being able to do it is also obtained.

[Configuration of image recognition device]
Next, the configuration of the image recognition apparatus will be described with reference to FIG. FIG. 15 is a block diagram showing an example of the image recognition apparatus 100 to which the present embodiment is applied, and conceptually shows only the portion related to the present embodiment in the configuration.

  As shown in FIG. 15, the image recognition apparatus 100 according to the present embodiment schematically includes at least a control unit 102 and a storage unit 106, and further includes an input / output control interface unit 108 and communication control in the present embodiment. An interface unit 104 is provided. Here, the control unit 102 is a CPU or the like that comprehensively controls the entire image recognition apparatus 100. The communication control interface unit 104 is an interface connected to a communication device (not shown) such as a router connected to a communication line or the like, and the input / output control interface unit 108 is connected to the input unit 112 or the output unit 114. The interface to be connected. The storage unit 106 is a device that stores various databases and tables. Each unit of the image recognition apparatus 100 is connected to be communicable via an arbitrary communication path. Further, the image recognition apparatus 100 is communicably connected to the network 300 via a communication device such as a router and a wired or wireless communication line such as a dedicated line.

  Various databases and tables (mask storage unit 106a, neuron file 106b, etc.) stored in the storage unit 106 are storage means such as a fixed disk device. For example, the storage unit 106 stores various programs, tables, files, databases, web pages, and the like used for various processes.

Of these components of the storage unit 106, the mask storage unit 106a is a mask storage unit that stores a mask pattern, a first connection pattern, and the like. For example, the mask storage unit 106a may store the mask pattern generated by the mask generation unit 102a. More specifically, the mask storage unit 106a may store a random number sequence r ^μ (μ = 1, 2,..., P) generated as a mask pattern by the mask generation unit 102a.

The neuron file 106b is a neural network storage unit that stores data relating to a neural network such as parameters between nerve cell units and parameters (coefficient values, etc.) for each nerve cell unit in association with an index for identifying the nerve cell unit. It is. As an example, the neural network information stored in the neuron file 106b is the nerve at the weight J _ij between the neuron unit i and the neuron unit j at time t (t = 1, 2, 3,...). These are values such as the state x (t) of the network, the reconstruction pattern y (t), the energy function E (t), and the internal potential h (t) of the nerve cell unit. The neuron file 106b may store initial parameters when numerical values are not given in advance when these parameters t = 0. The above-mentioned value may be updated every time state update (t → t + 1) is performed by the learning unit 102c and the recall unit 102d described later.

  The input / output control interface unit 108 controls the input unit 112 and the output unit 114. Here, as the output unit 114, in addition to a monitor (including a home television), a speaker can be used (hereinafter, the output unit 114 may be described as a monitor). As the input unit 112, a keyboard, a mouse, a microphone, and the like can be used.

  In FIG. 15, the control unit 102 has an internal memory for storing a control program such as an OS (Operating System), a program defining various processing procedures, and necessary data. And the control part 102 performs the information processing for performing various processes by these programs. The control unit 102 includes a mask generation unit 102a, a logical operation unit 102b, a learning unit 102c, and a recall unit 102d in terms of functional concept.

  Among these, the mask generation unit 102a is a mask generation unit that generates a mask pattern. In the present embodiment, the mask generation unit 102a generates a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of bits that frequently appear in the original pattern, based on the original pattern. To do. As an example, the mask generation unit 102a may generate a random number sequence using a random number table or the like, and use this to generate a random mask based on the original pattern. In addition, the mask generation unit 102a randomly binarizes each bit set of the original pattern or each bit set grouped in a predetermined number with different probabilities depending on the bit or the total value of the bit sets. The bits of the mask pattern may be generated.

  For example, the mask generation unit 102a may set the allocation probability to invert the majority bit as the firing rate of the original pattern is close to 0 or 1. Furthermore, the mask generation unit 102a may set the allocation probability for inverting majority bits as the firing rate of the original pattern is close to 0 or 1, and as the correlation between the original patterns is smaller. Here, the mask generation unit 102a may set the allocation probability with reference to a correspondence table, a graph, or the like stored in advance in the storage unit 106 based on the firing rate or correlation of the original pattern. It may be calculated and set by calculation.

  First, an example in which a correspondence table, a graph, and the like are stored in advance in the storage unit 106 will be described as a method for determining the allocation probability p. FIG. 16 is a graph showing the optimal allocation probability p with respect to the firing rate f and correlation b of the original pattern. FIG. 17 is a diagram showing the storage capacity when the optimum allocation probability p is set for the firing rate f and correlation b of the original pattern.

  In the first method, the firing rate and correlation value of the original pattern are calculated in advance, and the optimal allocation probability p value is stored for each firing rate and correlation value stored in the storage unit 106 in advance. This is a method of specifying the value of the allocation probability p with reference to the table. The optimum value of p for each firing rate and correlation value is calculated in advance for the artificially generated original pattern.

An artificial pattern having a specific firing rate f and a correlation b value can be generated by a known method (for example, a known paper [1]: M. Oku, T. Makino, and K. Aihara, “ Pseudo-orthogonalization of memory patterns for associative memory ", IEEE Trans. Neural Net. Learn. Syst., Vol. 24, pp. 1877-1887). As an example, in the known paper [1], for a specified average value a = 2f−1 and correlation b, first, a reference pattern {η ⁰ ₁ , η ⁰ ₂ ,. . . , Η ⁰ _N } is generated according to the following equation.

Subsequently, using the generated reference pattern, the artificial patterns {η ^μ ₁ , η ^μ ₂ ,. . . , Η ^μ _N } (μ = 1, 2,..., P) is generated according to the following equation.

  Thus, an artificial pattern having the designated average value a and correlation b is obtained. Using this artificial pattern, it is repeatedly converted into a connected pattern using allocation probabilities p of various values, stored in an associative memory model, and measuring its storage capacity.

  FIG. 16 shows an example in which the values of p at which the average value of the storage capacity becomes the highest are summarized in a table for each average value and correlation value. In FIG. 16, the optimum value of p obtained for the artificially generated pattern is expressed in gray scale. The horizontal axis represents the firing rate f = (1 + a) = 2 of the artificial pattern, and the vertical axis represents the correlation b. In this example, the length of the artificial pattern was 1000, and 10 trial averages were performed for each point. Further, the firing rate f and the correlation b were measured in increments of 0.025, and the allocation probability p was measured in increments of 0.05, changing the conditions.

  As shown in FIG. 16, it was found that the smaller the firing rate f and the smaller the correlation b, the smaller the value of the optimum allocation probability p. Here, FIG. 17 shows the critical load factor (the storage capacity divided by the length N ′ of the connection pattern) of the associative memory model when the optimum allocation probability p specified by FIG. 16 is used. Is. If the pattern is not sparse, the critical load factor cannot exceed 0.14. However, as shown in FIG. 17, by setting an appropriate allocation probability p using the method of the present embodiment, the critical load factor is set. It was confirmed that can exceed 0.14. In particular, it was found that the increase in sparsity occurred remarkably in the portion where the ignition rate f and the correlation b were small.

  In the above example, since the high-order correlation or the like is not given to the artificially generated original pattern, the p-value that is truly optimal for the original pattern due to factors such as high-order correlation that is not considered is There is a possibility of deviating from the p value of the table calculated in advance. Even in this case, the storage capacity is increased compared to processing without considering sparseness at all, but in order to obtain a true optimum value, original patterns having different degrees of higher-order correlation are artificially created. A table indicating the optimum p value generated by taking into account the influence of higher-order correlation may be created and stored in the storage unit 106.

The above is an example in which an appropriate allocation probability p is calculated in advance and a correspondence table or the like is stored in the storage unit 106. Next, a method for obtaining an appropriate allocation probability p by calculation each time will be described. Another method of determining the allocation probability p is to calculate the firing rate f of the original pattern and determine p so that the firing rate f of the connected pattern after conversion is the same. For example, according to the case where “1” is a minority and “0” is a minority, the allocation probability p may be calculated by the following equation.

  This method has a smaller storage capacity than the first method, but has the advantage of being easy to implement because no table is used.

Here, in order to set a mask pattern having a different value for each block, the mask generation unit 102a may obtain a distribution probability g for inverting the bit string in the block from the allocation probability p based on the following expression. .

  Returning again to FIG. 15, the logical operation unit 102 b performs a logical operation (XNOR / XOR) between the mask pattern (random mask or the like) generated by the mask generation unit 102 a and the original pattern, thereby increasing the appearance frequency. This is a logical operation means for generating a masked pattern in which bit inversion is suppressed. For example, the logical operation unit 102b performs an XNOR operation or an XOR operation as described above with reference to FIGS.

  Here, the logical operation unit 102b creates a mask pattern by setting a common mask pattern (random mask, etc.) in units of blocks by making a block for each arbitrary number of bits in the original pattern of a plurality of images. May be. More specifically, the logical operation unit 102b divides an original pattern of length N by a plurality of images into L-1 blocks from the beginning (where N is divisible by L-1). ), A mask pattern having a different value for each block may be set to generate a concatenated pattern having a length of LN / (L−1). In the recall stage, the logical operation unit 102b may extract one mask pattern from the mask storage unit 106a and perform a logical operation (XNOR / XOR) with the verification pattern to generate a masked verification pattern. If the recall unit 102d fails to recall the masked collation pattern using the extracted mask pattern, another mask pattern is extracted and a new masked collation pattern is generated.

  The learning unit 102c is learning means for learning a connection pattern using an associative memory model using a neural network. On the other hand, the recall unit 102d is a recall unit that searches for an original pattern from a matching pattern that is a clue in an associative memory model using a neural network. In the present embodiment, the learning unit 102c may store the used mask pattern in the mask storage unit 106a for the recalling stage of the self-associative memory model by the recalling unit 102d. In the recall stage, the recall unit 102d can obtain a masked collation pattern by selecting one mask pattern stored in the mask storage unit 106a by trial and error and performing a logical operation with the collation mask. In the case of a sequence associative memory model, the learning unit 102c may store only the first connection pattern in the mask storage unit 106a. At the recall stage, the recall unit 102d sets the connection pattern stored in the mask storage unit 106a to the initial state of the neural network, and decodes and outputs it every time the state is updated. Good.

Here, explanation will be given using mathematical formulas. The original pattern to be stored is {ξ ^μ ₁ , ξ ^μ ₂ ,. . . , Ξ ^μ _N }. μ is a pattern number and takes an integer value from 1 to P. ξ ^μ _i represents the i-th value of the μ-th original pattern, and takes a value of 1 or −1 in the present embodiment. On the other hand, the mask pattern is {r ^μ ₁ , r ^μ ₂ ^,. . . , R ^μ _N }. In this embodiment, r ^μ _i indicates the i-th value of the μ-th mask pattern, and takes a value of 1 or −1 at random. The result of the XNOR operation between a value ξ ^μ _i having a stored pattern and the value r ^μ _i of the corresponding mask pattern is ξ ^μ _i r ^μ _i (in the case of XOR operation, −ξ ^μ _i r ^μ _i ).

When the block length L = 2, the mask pattern {r ^μ ₁ , r ^μ ₂ ^,. . . , R ^μ _N } and the masked pattern {ξ ^μ ₁ r ^μ ₁ , ξ ^μ ₂ r ^μ ₂ ,. . . , Xi] ^mu _N one by one from r ^mu _N} that connecting fetches alternately _{^{{r μ 1, ξ μ 1}} r μ 1, r μ 2, ξ μ 2 r μ 2,. . . , R ^μ _N , ξ ^μ _N r ^μ _N } is a connection pattern of length 2N to be stored in the neural network under the control of the learning unit 102c. Here, the symbols are replaced, and the connected patterns {η ^μ ₁ , η ^μ ₂ ,. . . , Η ^μ _{N ′} }. However, N ′ = 2N.

When the block length L = 2 or more, the k-th block of the μ-th original pattern is represented by {ξ ^μ _{k, 1} , ξ ^μ _{k, 2} ,. . . , Ξ ^μ _{k, L−1} }. The value of the mask pattern corresponding to this is set to r ^μ _k , and a logical operation (XNOR / XOR) and a concatenation operation are performed, so that a block of length L {r ^μ _k , r ^μ _k ξ ^μ _{k, 1} , r ^μ _k ξ ^μ _{k, 2} ,. . . , R ^μ _k ξ ^μ _{k, L−1} }. It is good also considering what arranged this in block order as a connection pattern. In this case, N ′ = LN / (L−1). Note that the arrangement order of the above connection patterns is an example, and the arrangement order of the mask pattern and the mask pattern in the connection pattern is arbitrary.

For example, a standard Hebb learning rule (including correction for shift) may be used for learning the connection pattern by the learning unit 102c. In the case of the auto-associative memory model, the strength of the synapse connection from the j-th neuron unit to the i-th neuron unit is represented as J _ij, and in the case of i ≠ j, the learning unit 102c calculates a value according to the following equation: Determine. If i = j, J _ii = 0.

On the other hand, in the case of a sequence associative memory model, the learning unit 102c determines a value according to the following equation. However, it is assumed that η ^{μ + 1} _i = η ¹ _i .

In the above two formulas, a is an average of η ^μ _i and more specifically is represented by the following formula.

The state of the neural network at time t is expressed as {x ₁ (t), x ₂ (t),. . . , X _{N ′} (t)}. x _i (t) represents the active state of the i-th neuron unit and takes a value of 1 (firing state) or −1 (resting state). There are four ways to update the state of a neural network, depending on the combination of synchronous update and asynchronous update, deterministic update and probabilistic update. For sparse patterns, synchronous update and deterministic update are possible. Any of the probabilistic updates may be combined. In the method of combining the simplest synchronous update and deterministic update, the learning unit 102c and the recall unit 102d perform state updating according to the following formulas in both the case of the self-associative memory model and the sequence associative memory model. Also good. Here, sgn (h) is a function that returns 1 when h ≧ 0 and −1 when h <0.

  Here, G (t) is called an adaptive threshold and plays a role of adjusting so that only a fixed number of neurons in the neural network always fire. G (t) can be obtained by a known calculation method (for example, a known paper [2]: M. Okada, “Notions of associative memory and sparse coding”, Neural Networks, vol. 9, pp. 1429-1458. , 1996). In this publicly known document [2], characteristics such as how to determine a learning rule and an update rule, and storage capacity when a sparse pattern is used as a storage pattern in an associative memory model are disclosed.

A specific G (t) calculation method will be described. First, the learning unit 102c obtains an average of the connection patterns by the following equation.

Subsequently, the learning unit 102c calculates the adaptive threshold G (t) by the following formula using the value of a described above.

  As an example, the learning unit 102c and the recall unit 102d repeat the state update until the state of the neural network converges. In the case of the sequence linkage storage model, the state of the neural network does not converge, so the state update is repeated a predetermined number of times.

  As an example, the recall unit 102d searches for a corresponding original pattern by setting an initial pattern in a neural network and repeating state updating until the value of the energy function converges. For example, the recalling unit 102d may set a connection pattern obtained by connecting the masked matching pattern and the mask pattern as the initial pattern.

Note that the recall unit 102d uses another mask pattern (for example, μ → μ + 1), assuming that the recall failed due to being trapped by a false attractor when the energy function value below the threshold value cannot be obtained in the convergence state. The original pattern is searched by trying with the masked matching pattern. That is, if the correct mask pattern is not used for conversion, the recalling unit 102d searches for the correct mask pattern by utilizing the property that the state of the neural network is trapped by the false attractor with a high probability. On the other hand, if conversion is performed using the correct mask pattern, the value of the energy function of the neural network in the converged state is sufficiently low. In this case, the recalling unit 102d regards the recall as successful, and decodes the state to obtain the original pattern. Get the output of Here, the recalling unit 102d may decode the state of the neural network using the following equation. Note that the reconstruction pattern is expressed as {y ₁ (t), y ₂ (t),. . . , Y _N (t)}.

y _k (t) = x _2k−1 (t) x _2k (t)

  In the case of the sequence associative memory model, the learning unit 102c may store only the first connection pattern in the mask storage unit 106a separately from the neural network. Then, the recalling unit 102d sets the first connection pattern stored in the mask storage unit 106a to the initial state of the neural network, and performs decoding and outputting each time the state of the neural network is updated, thereby generating the original A series of patterns can be extracted.

  The above is an example of the configuration of the image recognition apparatus 100 in the present embodiment. Note that the image recognition apparatus 100 may be connected to the external system 200 via the network 300. In this case, the communication control interface unit 104 performs communication control between the image recognition device 100 and the network 300 (or a communication device such as a router). That is, the communication control interface unit 104 has a function of communicating data with other terminals via a communication line. The network 300 has a function of connecting the image recognition apparatus 100 and the external system 200 to each other, for example, the Internet.

  The external system 200 is mutually connected to the image recognition apparatus 100 via the network 300, an external database regarding various parameters, a program for causing the connected computer (information processing apparatus) to execute an image recognition method, and the like. It has a function to provide.

  Here, the external system 200 may be configured as a WEB server, an ASP server, or the like. Further, the hardware configuration of the external system 200 may be configured by an information processing apparatus such as a commercially available workstation or a personal computer and its attached devices. Each function of the external system 200 is realized by a CPU, a disk device, a memory device, an input device, an output device, a communication control device, and the like in the hardware configuration of the external system 200 and a program for controlling them.

  This is the end of the description of the configuration of the present embodiment.

[Processing of Image Recognition Device 100]
Next, an example of processing of the image recognition apparatus 100 according to the present embodiment configured as described above will be described in detail with reference to FIG. FIG. 18 is a flowchart illustrating an example of basic processing of the image recognition apparatus 100 in the present embodiment.

  As shown in FIG. 18, first, the mask generation unit 102a generates a random mask that is a random binary pattern based on the original pattern (step SA-1). As an example, the mask generation unit 102a may generate a random number sequence using a random number table or the like, and use this to generate a random mask based on the original pattern.

  Then, the logic operation unit 102b generates a masked pattern by performing a logic operation (XNOR operation or XOR operation) between the mask pattern (random mask) generated by the mask generation unit 102a and the original pattern (step SA- 2). Here, the logical operation unit 102b may create a masked pattern by making a block for each arbitrary number of bits in the original pattern of a plurality of images and setting a common random mask in units of blocks.

  And the learning part 102c is made to learn a connection pattern by the associative memory model using a neural network (step SA-3). Note that the learning unit 102c may store a mask pattern in the mask storage unit 106a for the recall stage of the self-associative memory model, and only the first connected pattern for the recall stage of the sequence associative memory model. You may store in the mask preservation | save part 106a.

  Then, the recalling unit 102d searches for the corresponding original pattern by setting the connection pattern in the initial state neural network based on the clue pattern and repeating the state update until the energy function value converges (step) SA-4). In the case of the self-associative memory model, the recollection unit 102d extracts one mask pattern from the mask storage unit 106a by the processing of the logical operation unit 102b, performs logical operation (XNOR / XOR) with the matching pattern, Generate a collation pattern and set it as the initial connection pattern. The recalling unit 102d retrieves another mask pattern and generates a new masked collation pattern when the recall fails with the masked collation pattern using the extracted mask pattern. The recalling unit 102d updates the state until the energy function value converges, and when the energy function value is equal to or less than a predetermined threshold in the converged state, the recall is successful and the pattern is decoded from the state. The pattern is output to the output unit 114 or the like. On the other hand, in the case of the sequence associative memory model, the recall unit 102d extracts the first connection pattern from the mask storage unit 106a, sets it as the initial state of the neural network, and performs decoding every time the state of the neural network is updated. By outputting, the original pattern series can be extracted.

  The above is an example of the basic processing of the image recognition apparatus 100 in the present embodiment.

[Learning process]
Next, an example of a learning process that further embodies the basic process of the image recognition apparatus 100 will be described below with reference to FIG. Here, FIG. 19 is a flowchart illustrating an example of learning processing of the image recognition apparatus 100 according to the present embodiment.

  As illustrated in FIG. 19, the learning unit 102c causes the user to input the pattern length N, the number of patterns P, and the block length L via the input unit 112 (step SB-1). Note that the learning unit 102c may obtain the values of N, P, L, and p from the image group input via the input unit 112 by calculation.

Then, the learning unit 102c, all coupling coefficients _{J ij} stored in neurons file 106b is initialized to 0 (step SB-2).

  Then, the learning unit 102c substitutes 1 for the pattern number k (step SB-3).

Then, for the minority bit, the mask generation unit 102a sets the appearance probability Prob (r _i ^μ = ± 1) of 1 and −1 to ½, and uses the mask random number sequence r ^μ (μ = 1, 2, .., P), and for the majority bit, the appearance probability (that is, the allocation probability) of the value (1 or -1) designating bit inversion is set to be smaller than 1/2, A random number sequence is generated (step SB-4). As an example, the mask generation unit 102a may set the allocation probability to be smaller as the firing rate of the original pattern is closer to 0 or 1, and may further set the allocation probability to be lower as the correlation between the original patterns is smaller. . Note that the mask generation unit 102a sets an appropriate allocation probability p with reference to a correspondence table or a graph (FIG. 16, etc.) calculated in advance and stored in the storage unit 106 in correspondence with the firing rate, correlation, and the like. Alternatively, the allocation probability p may be obtained and set by calculation based on the firing rate or correlation of the designated original pattern. As an example, the mask generation unit 102a may obtain the allocation probability p from the firing rate f based on the following equation.

  Then, the logical operation unit 102b randomizes the kth input pattern with a mask by XOR or XNOR logical operation (step SB-5).

  And the learning part 102c performs the learning process which memorize | stores the randomized pattern in a neural network according to a Hebb learning rule etc. (step SB-6).

  When the pattern number k has not reached the number of patterns P (No at Step SB-7), the learning unit 102c increments k (k → k + 1) (Step SB-8), and the above-described Step SB-4 Repeat the process of SB-7.

  On the other hand, when the pattern number k reaches the number of patterns P (step SB-7, Yes), the matrix J of coupling coefficients is output to the neuron file 106b (step SB-9), and the learning process is finished.

[Recall processing (self-associative memory model)]
Next, an example of a recall process that more specifically embodies the basic process of the image recognition apparatus 100 will be described below with reference to FIG. Here, FIG. 20 is a flowchart illustrating an example of a recall process using the self-associative memory model of the image recognition apparatus 100 according to the present embodiment.

  As shown in FIG. 20, first, the recall unit 102d controls the user to input a collation pattern, which is image data serving as a clue, via the input unit 112 or the like (step SC-1).

  Then, the recall unit 102d substitutes 1 for the mask number k (step SC-2).

  Then, the recalling unit 102d acquires the kth mask from the mask storage unit 106a (step SC-3).

  Then, the logical operation unit 102b randomizes the input collation pattern with the kth mask by the logical operation used in Step SB-5 (Step SC-4).

  Then, the recalling unit 102d sets the randomized pattern to the initial state of the neural network (step SC-5).

  Then, the recall unit 102d updates the state of the neural network (step SC-6).

  Then, the recalling unit 102d determines whether or not the state of the neural network has converged (step SC-7). For example, the recalling unit 102d may determine that the state has converged when the state variable x (t) becomes the same value even when it is updated, or when the value of the same pattern is repeated at several state update cycles. Good.

  When the state of the neural network has not converged (step SC-7, No), the recalling unit 102d returns the process to step SC-6 and further updates the state (time t → t + 1).

  On the other hand, when it is determined that the state of the neural network has converged (step SC-7, Yes), the recalling unit 102d determines whether the recall is successful based on the value of the energy function E (t) ( Step SC-8). For example, the recall unit 102d may determine that recall is successful when the value of the energy function E (t) is equal to or less than a predetermined threshold. When the recall is successful (step SC-8, Yes), the recall unit 102d decodes the state x (t) of the neural network and outputs the reconstructed pattern to the output unit 114 (step SC-9).

  On the other hand, if the recall is not successful (step SC-8, No), the recall unit 102d determines whether the pattern number k has reached the number of patterns P (step SC-10), and k is not equal to P. In the case (SC-10, No), k is incremented (k → k + 1) (step SC-11), and the above-described steps SC-3 to SC-8 are repeated. If the recall is not successful (step SC-8, No), and the pattern number k has reached the number of patterns P (step SC-10, Yes), the recall unit 102d outputs a recall failure error (step SC). -12) Finishing the recall process.

[Recollection processing (series associative memory model)]
Next, an example of a recall process that more specifically embodies the basic process of the image recognition apparatus 100 will be described below with reference to FIG. Here, FIG. 21 is a flowchart illustrating an example of the recall process using the sequence associative memory model of the image recognition apparatus 100 according to the present embodiment.

  As shown in FIG. 21, the recalling unit 102d controls the user to input the value of the maximum number of steps T for updating the state via the input unit 112 or the like (step SD-1).

  Then, the recall unit 102d acquires the k = 1st mask from the mask storage unit 106a (step SD-2).

  Then, the recall unit 102d initializes the neural network and sets it to an initial state (step SD-3).

  Then, the recalling unit 102d substitutes 0 for the time t (step SD-4).

  Then, the recall unit 102d updates the state of the neural network (step SD-5).

  Then, the recalling unit 102d decodes the state of the neural network and calculates a reconstruction pattern as an output (step SD-6).

  Then, the recalling unit 102d determines whether or not the time t, which is the updated number of steps, has reached a predetermined maximum number of steps T (step SD-7).

  When the predetermined number of steps T has not been reached (step SD-7, No), the recalling unit 102d increments t (t → t + 1) (step SD-8), and steps SD-5 to SD described above. Repeat the process of -7.

  On the other hand, when the predetermined number of steps T is reached (step SD-7, Yes), the recalling unit 102d decodes the state of the neural network at that time, acquires a reconstruction pattern, and outputs it to the output unit 114. Finish the recall process.

  As described above, the connection pattern corresponding to the first image in the image sequence is defined as the initial value of the neural network, the state update rules are applied sequentially, and the reconstructed pattern is calculated from the state of the neural network at each update step and output. By doing so, images very close to the original image series are output in order.

  This is the end of the description of the present embodiment.

[Other embodiments]
Although the embodiments of the present invention have been described so far, the present invention is not limited to the above-described embodiments, but can be applied to various different embodiments within the scope of the technical idea described in the claims. It may be implemented.

  Moreover, although the case where the image recognition apparatus 100 performs processing in a stand-alone form has been described as an example, the image recognition apparatus 100 performs processing in response to a request from the client terminal, and returns the processing result to the client terminal. You may make it do.

  In addition, among the processes described in the embodiment, all or part of the processes described as being automatically performed can be performed manually, or the processes described as being performed manually can be performed. All or a part can be automatically performed by a known method.

  In addition, unless otherwise specified, the processing procedures, control procedures, specific names, information including registration data for each processing, parameters such as search conditions, screen examples, and database configurations shown in the above documents and drawings Can be changed arbitrarily.

  Further, regarding the image recognition apparatus 100, each illustrated component is functionally conceptual, and does not necessarily need to be physically configured as illustrated.

  For example, the processing functions provided in each device of the image recognition device 100, in particular, the processing functions performed by the control unit 102, all or any part thereof are interpreted and executed by a CPU (Central Processing Unit) and the CPU. It may be realized by a program to be executed, or may be realized as hardware by wired logic. The program is recorded on a recording medium to be described later, and is mechanically read by the image recognition apparatus 100 as necessary. That is, in the storage unit 106 such as a ROM or an HD, a computer program for performing various processes by giving instructions to the CPU in cooperation with an OS (Operating System) is recorded. This computer program is executed by being loaded into the RAM, and constitutes a control unit in cooperation with the CPU.

  The computer program may be stored in an application program server connected to the image recognition apparatus 100 via an arbitrary network 300, and may be downloaded in whole or in part as necessary. It is.

  In addition, the program according to the present invention may be stored in a computer-readable recording medium, and may be configured as a program product. Here, the “recording medium” means a memory card, USB memory, SD card, flexible disk, magneto-optical disk, ROM, EPROM, EEPROM, CD-ROM, MO, DVD, and Blu-ray (registered trademark). It includes any “portable physical medium” such as Disc.

  The “program” is a data processing method described in an arbitrary language or description method, and may be in any format such as source code or binary code. The “program” is not necessarily limited to a single configuration, but is distributed in the form of a plurality of modules and libraries, or in cooperation with a separate program represented by an OS (Operating System). Including those that achieve the function. Note that a well-known configuration and procedure can be used for a specific configuration for reading a recording medium, a reading procedure, an installation procedure after reading, and the like in each device described in the embodiment.

  Various databases (mask storage unit 106a, neuron file 106b, etc.) stored in the storage unit 106 are storage means such as a memory device such as RAM and ROM, a fixed disk device such as a hard disk, a flexible disk, and an optical disk. Yes, it stores various programs, tables, databases, web page files, etc. used for various processes and website provision.

  The image recognition apparatus 100 may be configured as an information processing apparatus such as a known personal computer or workstation, or may be configured by connecting any peripheral device to the information processing apparatus. The image recognition apparatus 100 may be realized by installing software (including programs, data, and the like) that causes the information processing apparatus to realize the method of the present invention.

  Furthermore, the specific form of distribution / integration of the devices is not limited to that shown in the figure, and all or a part of them may be functional or physical in arbitrary units according to various additions or according to functional loads. Can be distributed and integrated. That is, the above-described embodiments may be arbitrarily combined and may be selectively implemented.

  As described above in detail, according to the present invention, an image recognition apparatus and an image recognition that can eliminate the correlation between image patterns to be stored in the associative memory model and prevent occurrence of interference and a decrease in storage capacity. A method and a program can be provided, and it is extremely useful in various fields such as image recognition and image processing.

DESCRIPTION OF SYMBOLS 100 Image recognition apparatus 102 Control part 102a Mask production | generation part 102b Logic operation part 102c Learning part 102d Recollection part 104 Communication control interface part 106 Storage part 106a Mask preservation | save part 106b Neuron file 108 Input / output control interface part 112 Input part 114 Output part 200 External System 300 network

Claims (11)

An image recognition device having at least a storage unit and a control unit,
The control unit
Mask generating means for generating a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of a bit having a high appearance frequency in the original pattern among the binary based on the specified original pattern of a plurality of images; ,
A logical operation means for generating a masked pattern in which bit inversion of the value having a high appearance frequency is suppressed by obtaining an exclusive OR or a negative exclusive OR of the original pattern and the mask pattern;
Learning means for learning with an associative memory model using a neural network, with the masked pattern associated with the mask pattern as a connected pattern;
An image recognition apparatus comprising: The image recognition apparatus according to claim 1,
The mask generation means includes
Setting the allocation probability to be smaller as the firing rate of the original pattern is closer to 0 or 1;
An image recognition apparatus. The image recognition apparatus according to claim 2,
The mask generation means includes
Obtaining the allocation probability based on the following equation:
An image recognition apparatus.
The image recognition apparatus according to claim 2 or 3,
The mask generation means includes
Setting the allocation probability to be smaller as the firing rate of the original pattern is closer to 0 or 1, and as the correlation between the plurality of original patterns is smaller,
An image recognition apparatus. The image recognition device according to any one of claims 1 to 4,
The logical operation means is
Setting the mask pattern common to any number of bits in the original pattern among the plurality of images to create the masked pattern,
An image recognition apparatus. The image recognition apparatus according to claim 5.
The logical operation means is
The original pattern of length N by the plurality of images is divided into L-1 blocks from the beginning, the mask pattern having a different value for each block is set, and the length of LN / (L-1) Generating the above connection pattern;
An image recognition apparatus. The image recognition device according to claim 6.
The mask generation means includes
In order to set the mask pattern having a different value for each block, a distribution probability g for inverting the bit string in the block is determined from the allocation probability p based on the following equation:
An image recognition apparatus.
The image recognition apparatus according to any one of claims 1 to 7,
The logical operation means is
Using the one-dimensional binary data of the image as the original pattern and the random binary data of the allocation probability based on the original pattern of the same or short length as the mask pattern, the corresponding values of both data are mutually exclusive Generating the masked pattern by obtaining a logical OR or a negative exclusive OR,
An image recognition apparatus. The image recognition apparatus according to any one of claims 1 to 8,
The learning means is
Storing the mask pattern in the storage unit;
The logical operation means is
A mask is obtained by obtaining the exclusive OR or the negative exclusive OR using one of a plurality of the mask patterns stored in the storage unit with respect to the specified collation pattern which is a clue image. Generate a collation pattern,
The control unit
If the masked matching pattern is introduced into the associative memory model and state update is repeated until convergence, and if the result of the energy function in the converged state is less than the threshold value, masked matching with another mask pattern Recalling means to search the original pattern by trying the pattern,
An image recognition apparatus further comprising: An image recognition method executed in a computer including at least a storage unit and a control unit,
In the control unit,
A mask generation step for generating a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of a bit having a high appearance frequency in the original pattern among the binary values based on the specified original pattern of the plurality of images; ,
A logical operation step of generating a masked pattern in which bit inversion of the value having a high appearance frequency is suppressed by obtaining an exclusive OR or a negative exclusive OR of the original pattern and the mask pattern;
A learning step of learning with an associative memory model using a neural network, with the masked pattern associated with the mask pattern as a connected pattern,
An image recognition method comprising: A program for causing a computer including at least a storage unit and a control unit to be executed,
In the control unit,
A mask generation step for generating a mask pattern that is a random binary pattern with an allocation probability that suppresses inversion of a bit having a high appearance frequency in the original pattern among the binary values based on the specified original pattern of the plurality of images; ,
A logical operation step of generating a masked pattern in which bit inversion of the value having a high appearance frequency is suppressed by obtaining an exclusive OR or a negative exclusive OR of the original pattern and the mask pattern;
A learning step of learning with an associative memory model using a neural network, with the masked pattern associated with the mask pattern as a connected pattern,
A program for running