JP2015135877A - Semiconductor substrate, and method of manufacturing semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate that has a small threshold current and that can suppress a light loss, and to provide a method of manufacturing the semiconductor substrate.SOLUTION: There is provided a method of manufacturing a semiconductor substrate, including following steps of: forming a QCL (Quantum Cascade Laser) layer 11 on a substrate 30 formed of an n-type semiconductor; bonding the QCL layer 11 with a mounting substrate 36; removing the substrate 30 after the step of bonding with the mounting substrate 36; forming a substrate 10 formed of an n-type semiconductor having an impurity concentration lower than that of the substrate 30, or an insulator, on a lower surface of the QCL layer 11 after the step of removing the substrate 30; and removing the mounting substrate 36 after the step of forming the substrate 10. Also there is provided the semiconductor substrate.

Description

  The present invention relates to a semiconductor substrate and a method for manufacturing the semiconductor substrate.

  In an optical semiconductor device using a compound semiconductor, semiconductor layers such as an active layer and a cladding layer are grown on a substrate (Non-Patent Document 1). The active layer generates light when a current flows. In order to reduce the threshold current at which laser light oscillation occurs, it is preferable that the active layer has a low dislocation.

Applied Physics Letters Volume 85, Number 24, p5842, 13 December 2004 (Applied Physics Letters Volume 85, Number 24, p5842, 13 December 2004)

  In order to make the active layer low dislocation, the active layer may be grown on a low dislocation substrate. However, low dislocation substrates have a high carrier concentration. Since the light generated in the active layer is absorbed by the carriers, the loss increases (the amount of light absorption depends on the carrier concentration. Intraband transition of electrons or holes occurs due to infrared absorption). In order to suppress absorption, a buffer layer may be provided between the active layer and the substrate, but even if the buffer layer is provided, it is difficult to sufficiently suppress loss. An object of the present invention is to provide a semiconductor substrate having a small threshold current and a low loss, and a method for manufacturing the semiconductor substrate.

  The present invention includes a step of forming a semiconductor layer on a first substrate made of an n-type semiconductor, a step of bonding a mounting substrate to the upper surface of the semiconductor layer, and a step of bonding the mounting substrate. After the step of removing the substrate and the step of removing the first substrate, an n-type semiconductor having an impurity concentration lower than that of the first substrate on the surface of the semiconductor layer on which the first substrate is provided, or an insulator And a step of removing the mounting substrate after the step of forming the second substrate.

In the above structure, the impurity concentration of the first substrate may be 2 × 10 ¹⁸ cm ⁻³ or more.

  In the above configuration, the second substrate functions as a first cladding layer, and the semiconductor layer may include an active layer and a second cladding layer from the side closer to the second substrate.

  In the above configuration, the semiconductor device includes a step of forming a first insulating film on an upper surface of the semiconductor layer, the mounting substrate includes a second insulating film, and the step of bonding the semiconductor layer to the mounting substrate includes the first insulating film. The semiconductor layer may be bonded to the mounting substrate by bonding the film and the second insulating film.

  In the above configuration, the method includes a step of forming an etching stop layer on an upper surface of the first substrate, the semiconductor layer is formed on an upper surface of the etching stop layer, and the step of removing the first substrate includes the step of removing the first substrate. The etching stop layer can be configured to stop the etching.

  In the above configuration, the first substrate and the second substrate may be formed of indium phosphide.

  The present invention includes a substrate and a semiconductor layer formed on the substrate, and the substrate is formed of an n-type semiconductor or an insulator having a dislocation density five times or more that of the semiconductor layer. A semiconductor substrate.

  In the above configuration, the substrate may function as a first cladding layer, and the semiconductor layer may include an active layer and a second cladding layer from a side closer to the substrate.

  ADVANTAGE OF THE INVENTION According to this invention, the threshold current is small and the semiconductor substrate which can suppress the loss of light, and the manufacturing method of a semiconductor substrate can be provided.

FIG. 1 is a cross-sectional view illustrating a semiconductor substrate according to the first embodiment. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor substrate. FIG. 3A to FIG. 3C are cross-sectional views illustrating a method for manufacturing a semiconductor substrate. FIG. 4A is a cross-sectional view illustrating a method for manufacturing a semiconductor substrate. FIG. 4B and FIG. 4C are perspective views illustrating a method for manufacturing a semiconductor substrate. FIG. 5A to FIG. 5C are perspective views illustrating a method for manufacturing a semiconductor substrate. FIG. 6 is a schematic view illustrating the relationship between the dislocation density and the threshold current density. FIG. 7A is a cross-sectional view illustrating a semiconductor substrate according to a comparative example. FIG. 7B is a diagram showing a simulation result of light loss.

  Examples will be described.

  FIG. 1 is a cross-sectional view illustrating a semiconductor substrate according to the first embodiment. The semiconductor substrate is viewed from the light propagation direction. As shown in FIG. 1, the semiconductor substrate 100 includes a substrate 10 (second substrate), a buffer layer 12, an active layer 14, cladding layers 16 and 18, a contact layer 20, a protective film 22, and electrodes 24 and 26. The electrode 24 is provided on the lower surface of the substrate 10. A buffer layer 12, an active layer 14, cladding layers 16 and 18, and a contact layer 20 are sequentially provided on the substrate 10. The buffer layer 12 to the contact layer 20 are referred to as a QCL (Quantum Cascade Laser) layer 11. An opening 13 is formed in the QCL layer 11. A portion of the QCL layer 11 sandwiched between the openings 13 forms a mesa stripe 15. The protective film 22 covers the surface of the QCL layer 11. The electrode 26 is provided on the upper surface of the protective film 22 and the upper surface of the contact layer 20. A wiring layer 28 is provided so as to fill the opening 13.

  When a voltage is applied to the electrodes 24 and 26, the active layer 14 emits laser light. The substrate 10 functions as a clad layer that reflects laser light. The laser light propagates in the direction of the paper surface of FIG.

The substrate 10 is made of, for example, indium phosphide (Sn—InP) containing tin (Sn) as an impurity. The thickness is, for example, 350 μm, the carrier concentration is, for example, 2.0 × 10 ¹⁷ cm ⁻³ or less, and the dislocation density is, for example, 5000 / cm ² or more. An impurity is an impurity that supplies free carriers. When all of the doped impurities are activated, the carrier concentration becomes equal to the impurity concentration. The carrier concentration is determined by the amount of impurities introduced.

The dislocation density of the QCL layer 11 is 1000 / cm ² or less. The impurity contained in the QCL layer 11 is silicon (Si). The buffer layer 12 is made of, for example, InP having a thickness of 0.5 μm and a carrier concentration of 8.0 × 10 ¹⁶ cm ⁻³ . The active layer 14 is a GaInAs / AlInAs multiple quantum well layer formed of, for example, gallium indium arsenide and aluminum indium arsenide. For example, 27 cores are included in the active layer 14. The thicknesses of the GaInAs layer and the AlInAs layer included in the active layer 14 are, for example, 56.5 nm. The clad layer 16 is made of, for example, InP having a thickness of 2 μm and a carrier concentration of 2.0 × 10 ¹⁷ cm ⁻³ . The cladding layer 18 is made of, for example, InP having a thickness of 1 μm and a carrier concentration of 8.0 × 10 ¹⁸ cm ⁻³ . The contact layer 20 is formed of, for example, indium gallium arsenide (InGaAs) having a thickness of 0.1 μm and a carrier concentration of 1.0 × 10 ¹⁹ cm ⁻³ .

  The protective film 22 is formed of an insulator such as silicon oxynitride (SiON). The electrode 24 is formed of, for example, a film (Au / Ge / Ni / Ti / Au) in which gold, germanium, nickel, titanium and gold are stacked from the side closer to the substrate 10. The electrode 26 is formed of, for example, a film (Ti / Pt / Au) in which titanium, platinum, and gold are stacked from the side closer to the substrate 10.

  FIG. 2A to FIG. 4A are cross-sectional views illustrating a method for manufacturing a semiconductor substrate. FIG. 4B to FIG. 5C are perspective views illustrating a method for manufacturing a semiconductor substrate.

ＩｎＰは、トリメチルインジウムおよびホスフィンを原料とする。Ｓｉ（シリコン）の原料としてジシランを用いることができる。 A substrate 30 (first substrate) shown in FIG. The substrate 30 is made of Sn—InP having a thickness of 350 μm. The carrier concentration of the substrate 30 is, for example, 1.0 × 10 ¹⁸ cm ⁻³ or more, and the dislocation density is, for example, 1000 / cm ² or less. On the upper surface of the substrate 30, an etching stop layer 32 made of, for example, AlInAs having a thickness of 50 nm is formed. The QCL layer 11 is epitaxially grown on the upper surface of the etching stop layer 32 by metal organic vapor phase epitaxy (MOVPE). The QCL layer 11 is formed of a semiconductor that lattice matches with the substrate 30. The buffer layer 12 is in contact with the etching stop layer 32. Table 1 shows the growth conditions of the QCL layer 11.

InP uses trimethylindium and phosphine as raw materials. Disilane can be used as a raw material for Si (silicon).

実装基板３６は例えば厚さ３５０μｍのシリコン（Ｓｉ）により形成されている。絶縁膜３４および３８はそれぞれ厚さ５００ｎｍの酸化シリコン（ＳｉＯ_２）により形成されている。 As shown in FIG. 2B, an insulating film 34 (first insulating film) is formed on the upper surface of the QCL layer 11 (upper surface of the contact layer 20). As shown in FIG. 2C, a mounting substrate 36 is prepared. An insulating film 38 (second insulating film) is formed on the lower surface of the mounting substrate 36. The insulating films 34 and 38 are formed using a plasma CVD (Chemical Vapor Deposition) apparatus. Table 2 is a table showing the growth conditions of the insulating films 34 and 38.

The mounting substrate 36 is made of, for example, silicon (Si) having a thickness of 350 μm. The insulating films 34 and 38 are each formed of silicon oxide (SiO ₂ ) having a thickness of 500 nm.

プラズマ処理の後、ＲＴＡ装置などの熱処理装置を用いて３００℃、１時間の条件下でアニールを行う。絶縁膜３４および３８はＳｉＯ_２以外の絶縁体により形成してもよい。絶縁膜３４および３８を同じ材料により形成することで、接合が容易になる。 As shown in FIG. 2D, the insulating film 34 and the insulating film 38 are bonded. It is difficult to directly bond the QCL layer 11 to the Si mounting substrate 36. By bonding the insulating films 34 and 38 of SiO ₂ , the QCL layer 11 is bonded to the mounting substrate 36 via the insulating films 34 and 38. Table 3 is a table showing the conditions of the plasma treatment in bonding. The pressure in Table 3 is atmospheric pressure. It is not necessary to apply pressure to the insulating films 34 and 38.

After the plasma treatment, annealing is performed at 300 ° C. for 1 hour using a heat treatment apparatus such as an RTA apparatus. The insulating films 34 and 38 may be formed of an insulator other than SiO ₂ . Bonding is facilitated by forming the insulating films 34 and 38 of the same material.

  As shown in FIG. 3A, the substrate 30 is removed by an etching process using an etchant such as hydrochloric acid. The etching process time is, for example, 5 minutes. Since the etching stop layer 32 has an etching selectivity different from that of the substrate 30, the etching stops at the etching stop layer 32. As shown in FIG. 3B, the etching stop layer 32 is removed by an etching process using an etchant or the like in which sulfuric acid, hydrogen peroxide solution, and water are mixed at 5: 1: 10. The etching process time is, for example, 30 seconds. The lower surface of the QCL layer 11 is exposed by the etching process.

図４（ａ）に示すように、フッ酸を用いたエッチング処理により、実装基板３６、絶縁膜３４および３８を除去する。これによりＱＣＬ層１１の上面が露出する。 As shown in FIG. 3C, the substrate 10 (second substrate) is bonded to the lower surface of the QCL layer 11 (the surface on which the substrate 30 was provided). Table 4 is a table showing plasma processing conditions for bonding the substrates 10. After the plasma treatment, annealing is performed at 300 ° C. for 1 hour using a heat treatment apparatus such as an RTA apparatus.

As shown in FIG. 4A, the mounting substrate 36 and the insulating films 34 and 38 are removed by an etching process using hydrofluoric acid. As a result, the upper surface of the QCL layer 11 is exposed.

  As shown in FIG. 4B, an insulating film 40 made of, for example, silicon nitride (SiN) is formed on the upper surface of the contact layer 20. A part of the upper surface of the contact layer 20 is exposed from the insulating film 40. As shown in FIG. 4C, the exposed contact layer 20 is etched to form an opening 13 in the QCL layer 11.

  As shown in FIG. 5A, the insulating film 40 is removed, and the protective film 22 is formed. As shown in FIG. 5B, the protective film 22 covering the contact layer 20 of the mesa stripe 15 is removed to expose the contact layer 20. As shown in FIG. 5C, electrodes 24 and 26 are formed. Further, the wiring layer 28 shown in FIG. 1 is provided. The semiconductor substrate 100 is formed through the above steps.

  FIG. 6 is a schematic view illustrating the relationship between the dislocation density and the threshold current density. The horizontal axis represents the dislocation density of the substrate 30, and the vertical axis represents the threshold current density. As shown in FIG. 6, the threshold current density decreases as the dislocation density decreases. Since the dislocation density of the substrate 30 is reduced, the dislocation density of the QCL layer 11 grown on the substrate 30 is also reduced, so that the threshold current density is reduced.

According to Example 1, since the QCL layer 11 is grown on the low dislocation substrate 30, the dislocation density of the QCL layer 11 is also reduced to 1000 pieces / cm ² or less. Accordingly, the threshold current becomes small. After the growth of the QCL layer 11, the substrate 30 is removed, and a substrate 10 having a low carrier concentration is provided. Since light absorption by the free carriers of the substrate 10 is difficult to occur, light loss is reduced. A semiconductor substrate with a small threshold current and low loss can be obtained. The QCL layer 11 is preferably lattice matched with the substrate 30. This is because the QCL layer 11 becomes low dislocation due to lattice matching.

In general, in InP, the higher the carrier concentration, the lower the dislocation, and the lower the carrier concentration, the higher the dislocation. In order to make the substrate 30 low dislocation, the carrier concentration of the substrate 30 is preferably 1.0 × 10 ¹⁸ cm ⁻³ or more, or 2.0 × 10 ¹⁸ cm ⁻³ or more. As shown in FIG. 6, the dislocation density of the substrate 30 is preferably 1000 pieces / cm ⁻³ or less in order to set the threshold current to 1.5 kA / cm ² or less.

In order to suppress light absorption, the carrier concentration of the substrate 10 is preferably 2.0 × 10 ¹⁷ cm ⁻³ or less, or 1.0 × 10 ¹⁷ cm ⁻³ or less. In order to reduce the carrier concentration of the substrate 10, the dislocation density of the substrate 10 is preferably 5 times or more the dislocation density of the QCL layer 11. The dislocation density of the substrate 10 may be 7 times or more or 10 times or more that of the QCL layer 11.

  The QCL layer 11 may be grown by MBE (Molecular Beam Epitaxy) method. Although the QCL layer 11 is made of a semiconductor containing In, it may be formed by other Hanto et al. The substrate 10 may be an insulator such as ceramic, sapphire, or glass epoxy resin. Since the carrier concentration of the insulator is low, light absorption in the substrate 10 is difficult to occur.

  The substrate 10 also functions as a cladding layer. The refractive index of the substrate 10 and the cladding layers 16 and 18 is lower than the refractive index of the active layer 14. Light is confined in the active layer 14 due to such a difference in refractive index.

FIG. 7A is a cross-sectional view illustrating a semiconductor substrate 100R according to a comparative example. As shown in FIG. 7A, the QCL layer 11 is provided on the substrate 42. The QCL layer 11 includes an active layer 14, cladding layers 18 and 44, and a contact layer 20. The clad layer 44 is provided between the substrate 42 and the active layer 14. The substrate 42 is made of n-InP containing sulfur (S) as an impurity. The carrier concentration of the substrate 42 is, for example, 2.0 × 10 ¹⁸ cm ⁻³ . The cladding layer 44 is made of, for example, Si—InP having a thickness of 3 μm or more and a carrier concentration of 2.0 × 10 ¹⁷ cm ⁻³ .

FIG. 7B is a diagram showing a simulation result of light loss. The horizontal axis represents the thickness of the cladding layer, and the vertical axis represents the total waveguide loss. The broken line represents an example in which the carrier concentration of the substrate is 1.5 × 10 ¹⁷ cm ⁻³ , and the solid line represents an example in which the carrier concentration of the substrate is 2.0 × 10 ¹⁸ cm ⁻³ (corresponding to a comparative example). As indicated by the broken line, the total waveguide loss is smaller than 10 cm ⁻¹ in the example where the carrier concentration of the substrate is 1.5 × 10 ¹⁷ cm ⁻³ . In the example where the carrier concentration is 2.0 × 10 ¹⁸ cm ⁻³ , the total waveguide loss becomes large. This is because light is absorbed by the carrier of the substrate 42. The thicker the cladding layer, the smaller the total waveguide loss. However, even if a cladding layer of 3 μm or more is provided, the total waveguide loss is about 10 cm ⁻¹ and the carrier concentration is larger than the example of 1.5 × 10 ¹⁷ cm ⁻³ . By setting the cladding layer to 5 μm, the total waveguide loss becomes approximately the same as the carrier concentration of 1.5 × 10 ¹⁷ cm ⁻³ .

  That is, in the comparative example, the thickness of the clad layer 44 is preferably at least 3 μm. However, providing such a thick cladding layer increases the material cost. Further, the occupying time of the growth apparatus in the step of providing the cladding layer becomes long. The cost of the semiconductor substrate increases due to the increase in material cost and man-hour. According to the first embodiment, since it is not necessary to provide a thick cladding layer, the material cost and the man-hour can be reduced as compared with the comparative example, and the cost of the semiconductor substrate can be reduced.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10, 30 Substrate 11 QCL layer 12 Buffer layer 14 Active layer 16, 18 Clad layer 20 Contact layer 22, 24 Electrode 32 Etching stop layer 36, 38 Insulating film

Claims (8)

forming a semiconductor layer on a first substrate made of an n-type semiconductor;
Bonding a mounting substrate to the upper surface of the semiconductor layer;
Removing the first substrate after the step of bonding the mounting substrate;
After the step of removing the first substrate, an n-type semiconductor having an impurity concentration lower than that of the first substrate or a second substrate made of an insulator is formed on the surface of the semiconductor layer where the first substrate is provided. And a process of
And a step of removing the mounting substrate after the step of forming the second substrate. The method of manufacturing a semiconductor substrate according to claim 1, wherein the impurity concentration of the first substrate is 2 × 10 ¹⁸ cm ⁻³ or more. The second substrate functions as a first cladding layer;
The method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor layer includes an active layer and a second cladding layer from a side closer to the second substrate. Forming a first insulating film on the upper surface of the semiconductor layer;
The mounting substrate includes a second insulating film,
The step of bonding the semiconductor layer to the mounting substrate is a step of bonding the semiconductor layer to the mounting substrate by bonding the first insulating film and the second insulating film. The manufacturing method of the semiconductor substrate as described in any one of 1-3. Forming an etching stop layer on the upper surface of the first substrate;
The semiconductor layer is formed on an upper surface of the etching stop layer;
The step of removing the first substrate is a step of removing the first substrate by etching,
The method for manufacturing a semiconductor substrate according to claim 1, wherein the etching stop layer stops the etching.   6. The method of manufacturing a semiconductor substrate according to claim 1, wherein the first substrate and the second substrate are made of indium phosphide. A substrate,
A semiconductor layer formed on the substrate,
The semiconductor substrate is formed of an n-type semiconductor or an insulator having a dislocation density five times or more that of the semiconductor layer. The substrate functions as a first cladding layer;
The semiconductor substrate according to claim 7, wherein the semiconductor layer includes an active layer and a second cladding layer from a side closer to the substrate.

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