JP2015135852A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device whose heat radiation property can be improved.SOLUTION: The semiconductor device according to one embodiment comprises a housing, a substrate housed in the housing, and a semiconductor chip mounted on the substrate. The housing has a portion contacted with the substrate at a position separated from the semiconductor chip.

Description

  Embodiments described herein relate generally to a semiconductor device.

  There is provided an electronic apparatus having a housing and a substrate on which a heat generating component is mounted.

JP 2011-155089 A

  Semiconductor devices are required to improve heat dissipation.

  An object of the present invention is to provide a semiconductor measure capable of improving heat dissipation.

  According to the embodiment, the semiconductor device includes a housing, a substrate housed in the housing, and a semiconductor chip mounted on the substrate. The housing includes a portion in contact with the substrate at a position away from the semiconductor chip.

1 is a block diagram illustrating a configuration of a host device according to a first embodiment. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. The top view which illustrated the 2nd surface of the substrate concerning a 1st embodiment. Sectional drawing which illustrated the semiconductor device which concerns on 2nd Embodiment. The top view which illustrated the 1st surface of the substrate concerning a 3rd embodiment. The top view which illustrated the 2nd surface of the substrate concerning a 3rd embodiment. Sectional drawing which decomposed | disassembled and illustrated the semiconductor device which concerns on 3rd Embodiment. The top view which illustrated the inner surface of the base which concerns on 3rd Embodiment. The top view which illustrated the inner surface of the cover concerning a 3rd embodiment. Sectional drawing which illustrated the mounting structure of the semiconductor device which concerns on 3rd Embodiment. The top view which illustrated the 2nd surface of the substrate concerning a 4th embodiment. Sectional drawing which decomposed | disassembled and illustrated the semiconductor device which concerns on 5th Embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
In the present specification, examples of a plurality of expressions are given to some elements. Note that these examples of expressions are merely examples, and do not deny that the above elements are expressed in other expressions. In addition, elements to which a plurality of expressions are not attached may be expressed in different expressions.

  The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like may be different from the actual ones. Moreover, the part from which the relationship and ratio of a mutual dimension differ between drawings may be contained.

(First embodiment)
1 to 3 show a semiconductor device 1 (unit, module, semiconductor package) according to the first embodiment. The semiconductor device 1 is, for example, a semiconductor storage device (memory system), and an example thereof is an SSD (Solid State Drive). The semiconductor device 1 is not limited to these.

  FIG. 1 shows a host device 2 on which a semiconductor device 1 is mounted. The host device 2 includes a host controller 3 that comprehensively controls the entire host device 2 including the semiconductor device 1, and a power supply unit 4 (power supply circuit) that supplies power to the host device 2 and the semiconductor device 1.

  The semiconductor device 1 is electrically connected to the host controller 3 via the interface 5. The host controller 3 executes data access control with respect to the semiconductor device 1, for example, sends a write request, a read request, and an erase request to the semiconductor device 1, thereby writing and reading data to the semiconductor device 1, and Perform erasure.

  Examples of the interface 5 include, but are not limited to, SATA (Serial Advanced Technology Attachment), PCIe (Peripheral Component Interconnect Express), SAS (Serial Attached SCSI), and USB (Universal Serial Bus). The semiconductor device 1 is electrically connected to the power supply unit 4 of the host device 2 through the power supply line 6.

  FIG. 2 shows a cross-sectional view of the semiconductor device 1. The semiconductor device 1 includes a housing 11, a substrate 12, a plurality of semiconductor memory chips 13, a controller chip 14, and a connector 15. The housing 11 is made of metal. The housing 11 includes a base 21 (base plate, first member) and a cover 22 (top cover, second member). The base 21 and the cover 22 are formed, for example, by bending a metal plate material by pressing or the like. The housing 11 is formed by combining the base 21 and the cover 22.

  The board 12 (circuit board or printed board) is accommodated in the housing 11. The substrate 12 is a multilayer board and has a wiring pattern including a signal line, a power supply layer, and a ground layer 24 (see FIG. 3). The substrate 12 has a first surface 12a and a second surface 12b located on the opposite side of the first surface 12a.

  In the present embodiment, the plurality of semiconductor memory chips 13 and the controller chip 14 are mounted on the first surface 12 a of the substrate 12. The plurality of semiconductor memory chips 13 may be separately mounted on the first surface 12a and the second surface 12b of the substrate 12. The substrate 12 has a first end portion 26a provided with a connector 15 to be described later, and a second end portion 26b located on the opposite side of the first end portion 26a.

  The semiconductor memory chip 13 is an example of “semiconductor chip” and “semiconductor component”. The semiconductor memory chip 13 is an example of a nonvolatile memory, for example, and is a NAND flash memory, for example. The “semiconductor memory chip”, “semiconductor chip” or “semiconductor component” is not limited to a NAND flash memory, and may be, for example, a DRAM (Dynamic Random Access Memory) or an EEPROM (electrically erasable and programmable ROM). The semiconductor memory chip 13 is an example of a heat generating component that generates heat during use (operation).

  The controller chip 14 (controller, storage controller) is another example of “semiconductor chip” and “semiconductor component”. The controller chip 14 is electrically connected to the host controller 3 via the connector 15 and the interface 5, and transmits and receives signals to and from the host device 2.

  Specifically, the controller chip 14 comprehensively controls the operation of the semiconductor device 1 in response to an instruction from the host controller 3. The controller chip 14 performs access control for the plurality of semiconductor memory chips 13. That is, the controller chip 14 controls data writing, holding, reading, and erasing with respect to the semiconductor memory chip 13.

  The controller chip 14 is another example of a heat generating component that generates heat during use (during operation). The controller chip 14 is one of the components that generate the largest amount of heat in the semiconductor device 1. For example, the controller chip 14 generates a larger amount of heat than the semiconductor memory chip 13. For example, the substrate 12 of the semiconductor device 1 such as an SSD has a controller chip 14 and a plurality of semiconductor memory chips 13 arranged closely, and is likely to be hotter than substrates of other electronic devices.

  As shown in FIG. 2, a heat conductive sheet 28 (heat dissipating sheet, heat transfer member) is sandwiched between the semiconductor memory chip 13 and the controller chip 14 and the inner surface of the housing 11. The semiconductor memory chip 13 and the controller chip 14 are thermally connected to the housing 11 via a heat conductive sheet 28. Part of the heat from the semiconductor memory chip 13 and the controller chip 14 is dissipated to the housing 11 through the heat conductive sheet 28.

  The semiconductor memory chip 13 and the controller chip 14 are, for example, BGA (Ball Grid Array) type IC chips, and are connected to the substrate 12 via a plurality of solder balls, respectively. For this reason, heat generated from the semiconductor memory chip 13 and the controller chip 14 is easily transmitted to the ground layer 24 of the substrate 12 via the solder balls.

  As shown in FIG. 2, the connector 15 is provided at the first end portion 26 a of the substrate 12. The connector 15 is exposed to the outside of the housing 11 and connected to the connector of the host device 2. The connector 15 corresponds to the standard of the interface 5 and conforms to a standard such as SATA, PCIe, SAS, or USB. The connector 15 has a plurality of metal terminals 15a that are electrically connected to the connector of the host device 2 (see FIG. 3).

  The controller chip 14 is located between the connector 15 and the plurality of semiconductor memory chips 13. The controller chip 14 is located closer to the first end portion 26 a of the substrate 12. In other words, the controller chip 14 is located between the central portion 26c of the substrate 12 and the first end portion 26a. The substrate 12 includes a DRAM, an oscillator, an EEPROM, a temperature sensor, and a power supply unit in addition to the plurality of semiconductor memory chips 13 and the controller chip 14.

  As illustrated in FIG. 2, the housing 11 includes a first wall 31, a second wall 32, and a third wall 33. The first wall 31 and the second wall 32 extend substantially parallel to the substrate 12. The first wall 31 faces the first surface 12 a of the substrate 12. The second wall 32 is located on the opposite side of the first wall 31 and faces the second surface 12 b of the substrate 12. The third wall 33 extends in a direction substantially orthogonal to the first wall 31 and the second wall 32. The third wall 33 is a peripheral wall (side wall), and connects the peripheral edge of the first wall 31 and the peripheral edge of the second wall 32.

  Moreover, the housing | casing 11 has the 1st end part 11a and the 2nd end part 11b. The first end portion 11a is provided with an opening 34 that exposes the connector 15 of the substrate 12 to the outside. The second end portion 11b is located on the side opposite to the first end portion 11a.

  As shown in FIG. 2, the second wall 32 of the housing 11 has a plurality of contact portions 41 and 42 (connection portions, thermal connection portions, support portions, contact portions) that protrude toward the substrate 12 and come into contact with the substrate 12. , Projecting part, convex part, part). The contact portions 41 and 42 are in contact with the substrate 12 at positions where the plurality of semiconductor memory chips 13 and the controller chip 14 are removed and the periphery of the substrate 12 is removed. In the present embodiment, the contact portions 41 and 42 are in contact with the second surface 12 b of the substrate 12 and are thermally connected to the substrate 12. In other words, the housing 11 (contact portions 41, 42) is in direct contact with the substrate 12.

  The contact portions 41, 42 have a contact surface S (tip surface, contact surface, plane) substantially parallel to the second surface 12 b (or the first surface 12 a) of the substrate 12 and are in surface contact with the substrate 12. . That is, the contact portions 41 and 42 are in contact with the substrate 12 over a predetermined area. The contact area between any one of the contact portions 41 and 42 and the substrate 12 is larger than the bottom area of any one of the semiconductor memory chips 13, for example. The contact area between any one of the contact portions 41 and 42 and the substrate 12 is larger than, for example, the bottom area of the controller chip 14.

  The size of the contact portions 41 and 42 is not limited to the above. For example, the total contact area between the plurality of contact portions 41 and 42 and the substrate 12 is the bottom area of any one of the semiconductor memory chips 13 or the controller chip 14. It may be larger than the bottom area.

  As shown in FIG. 3, a ground layer 24 is provided on the second surface 12 b of the substrate 12. The ground layer 24 has an exposed region 24a (connection region) exposed on the surface of the substrate 12 at least in part. The exposed region 24a is a region where the resist of the substrate 12 is not provided. Solder 51 (for example, solder paste) is applied to the exposed region 24a.

  The contact portions 41 and 42 of the housing 11 have substantially the same outer shape as the exposed region 24 a of the ground layer 24. In the present embodiment, the two contact portions 41 and 42 extend in the width direction of the substrate 12 substantially parallel to each other. The contact portions 41 and 42 extend over substantially the entire width of the substrate 12.

  As shown in FIG. 2, the contact portions 41 and 42 of the housing 11 are in contact with the ground layer 24 of the substrate 12. Note that “the contact portion of the housing is in contact with the ground layer of the substrate” includes a case where a bonding member such as solder is sandwiched between the contact portion of the housing and the ground layer of the substrate. In the present embodiment, solder 51 is provided between the contact portions 41 and 42 of the housing 11 and the ground layer 24 of the substrate 12. The contact portions 41 and 42 of the housing 11 are joined to the ground layer 24 of the substrate 12 with solder 51. Thereby, the substrate 12 is fixed to the housing 11.

  As shown in FIG. 2, at least a part of the first contact portion 41 is in contact with the substrate 12 at a position on the back side of the controller chip 14. That is, the first contact portion 41 is in contact with the substrate 12 at a position between the central portion 26c of the substrate 12 and the first end portion 26a. On the other hand, at least a part of the second contact portion 42 is in contact with the substrate 12 at a position on the back side of the semiconductor memory chip 13. The second contact portion 42 is in contact with the substrate 12 at a position between the central portion 26c of the substrate 12 and the second end portion 26b.

Next, the operation of the semiconductor device 1 will be described.
When the semiconductor device 1 operates, the controller chip 14 and the semiconductor memory chip 13 generate heat. Part of the heat from the controller chip 14 and the semiconductor memory chip 13 is transmitted to the substrate 12 through solder balls included in the respective chips.

  Part of the heat transferred to the substrate 12 is radiated to the host device 2 from the metal terminal 15 a of the connector 15 through the connector of the host device 2. On the other hand, another part of the heat transmitted to the substrate 12 is transmitted from the contact portions 41 and 42 of the housing 11 to the housing 11 and is dissipated to the outside of the housing 11.

According to the semiconductor device 1 having such a configuration, it is possible to improve heat dissipation.
For example, in a semiconductor device such as an SSD, a substrate on which a controller chip and a semiconductor memory chip are mounted is often in a state of being thermally floated in a housing. That is, the heat dissipation path for releasing heat from the controller chip and the semiconductor memory chip is limited to two routes: a connector provided on the board and connected to the host device, and a screw fixing the board to the housing. There are many.

  Here, the controller chip and the semiconductor memory chip may deteriorate in performance when the operating temperature rises. Therefore, in order to maintain the performance of the semiconductor device, it is necessary to efficiently dissipate the generated heat and suppress the temperature rise of the controller chip and the semiconductor memory chip.

  As another configuration for suppressing the temperature rise of the controller chip and the semiconductor memory chip, for example, a heat conductive sheet (heat radiating sheet) is sandwiched between the controller chip and the semiconductor memory chip and the inner surface of the housing. It is conceivable to dissipate heat from the controller chip and the semiconductor memory chip to the housing.

  However, most of the heat conductive sheets are made of an organic material or the like, and delamination or thermosetting may occur due to aging deterioration, which may reduce heat dissipation. In addition, the heat conductive sheet is often inferior in heat transfer efficiency compared to a metal casing.

  Further, as another configuration for suppressing the temperature rise of the heat generating component, a protruding portion that protrudes toward the heat generating component is provided in the housing, and the tip of the protruding portion is brought into direct contact with the heat generating component to heat the heat generating component. It is possible to escape to the case.

  However, when the protruding portion of the casing is in direct contact with the heat generating component, when an external impact is applied to the casing, the impact may be directly input to the heat generating component. For this reason, with such a configuration, the impact resistance of the semiconductor device may be reduced.

  Therefore, the semiconductor device 1 according to this embodiment includes a housing 11, a substrate 12 accommodated in the housing 11, and a plurality of semiconductor memory chips 13 and a controller chip 14 mounted on the substrate 12. The housing 11 has contact portions 41 and 42 that are in contact with the substrate 12 at positions away from the plurality of semiconductor memory chips 13 and the controller chip 14.

  According to such a configuration, since the housing 11 and the substrate 12 are directly thermally connected, heat from the semiconductor memory chip 13 and the controller chip 14 is transmitted from the contact portions 41 and 42 of the housing 11 to the housing 11. The body 11 is efficiently escaped and diffused to the outside of the housing 11. Thereby, the heat dissipation of the semiconductor device 1 can be improved. As a result, performance degradation of the semiconductor device 1 due to temperature rise can be suppressed. In addition, according to such a structure, the malfunction resulting from the delamination and thermosetting by aged deterioration of a heat conductive sheet does not arise.

  In addition, since the contact portions 41 and 42 of the housing 11 are in contact with the substrate 12 at a position away from the semiconductor memory chip 13 and the controller chip 14, even when an external impact is applied to the housing 11, the impact is applied to the semiconductor. It is difficult to transmit directly to the memory chip 13 and the controller chip 14. For this reason, good impact resistance of the semiconductor device 1 can be ensured.

  Further, the contact portions 41 and 42 of the housing 11 are brought into direct contact with the substrate 12, so that the heat connection area serving as a heat dissipation path is not limited by the size (bottom area) of the semiconductor memory chip 13 and the controller chip 14. Can be increased. For example, in this embodiment, the contact area between one of the contact portions 41 and 42 of the housing 11 and the substrate 12 is larger than the bottom area of the semiconductor memory chip 13 or the bottom area of the controller chip 14. According to such a configuration, heat can be more efficiently transferred from the substrate 12 to the housing 11, and the heat dissipation of the semiconductor device 1 can be further improved.

  In the present embodiment, the housing 11 is made of metal. According to such a configuration, heat can be efficiently released from the substrate 12 to the housing 11 as compared with, for example, a case where a heat conductive sheet of an organic material is interposed. Furthermore, the heat transferred from the contact portions 41 and 42 to the housing 11 is efficiently transmitted to substantially the entire housing 11 and is dissipated using the substantially entire housing 11. For this reason, the heat dissipation of the semiconductor device 1 can be further improved.

  In general, heat from a semiconductor memory chip and a controller chip is easily transferred to the ground layer of the substrate. Therefore, in the present embodiment, the substrate 12 has a ground layer 24 at least partially exposed on the surface of the substrate 12. The contact portions 41 and 42 are in contact with the ground layer 24 of the substrate 12. According to such a configuration, the heat transmitted to the ground layer 24 of the substrate 12 can be efficiently released to the housing 11. Thereby, the heat dissipation of the semiconductor device 1 can be further improved.

  In the present embodiment, the contact portions 41 and 42 are joined to the ground layer 24 of the substrate 12 with solder 51. According to such a configuration, the contact portions 41 and 42 and the ground layer 24 of the substrate 12 are further in close contact with each other without any gap, so that heat is more easily transferred from the substrate 12 to the housing 11. For this reason, the heat dissipation of the semiconductor device 1 can be further improved.

  Furthermore, when the contact portions 41 and 42 of the housing 11 are joined to the ground layer 24 of the substrate 12 with the solder 51, fixing members (for example, screws) for fixing the substrate 12 to the housing 11 may be omitted or reduced. it can. Thereby, the number of parts of the semiconductor device 1 can be reduced, and the cost of the semiconductor device 1 can be reduced. In addition, if the fixing screws can be omitted or reduced, it is possible to reduce the number of redo man-hours due to defective screws and the appearance defects due to screw thread destruction. Thereby, the semiconductor device 1 can be provided more inexpensively.

  In the present embodiment, the substrate 12 has a first surface 12a on which the semiconductor memory chip 13 and the controller chip 14 are mounted, and a second surface 12b located on the opposite side of the first surface 12a. The contact portions 41 and 42 of the housing 11 are in contact with the second surface 12 b of the substrate 12. According to such a configuration, since the controller chip 14 is not present, the housing 11 and the substrate 12 can be brought into contact with each other using the second surface 12b of the substrate 12 having a relatively large area. For this reason, it is easy to increase the contact area of the housing | casing 11 and the board | substrate 12, and it becomes easy to improve the heat dissipation of the semiconductor device 1 further.

  In the present embodiment, the substrate 12 has a first end portion 26a provided with the connector 15 and a second end portion 26b located on the opposite side of the first end portion 26a. The connector 15 has a metal terminal 15 a connected to the host device 2, and constitutes one of the heat dissipation paths for releasing the heat of the substrate 12 to the outside of the semiconductor device 1. For this reason, heat in a region near the first end portion 26 a of the substrate 12 is easily radiated through the connector 15. On the other hand, the heat in the region between the central portion 26 c and the second end portion 26 b of the substrate 12 that is relatively far from the connector 15 is not easily radiated through the connector 15.

  Therefore, in the present embodiment, the second contact portion 42 contacts the substrate 12 at a position between the central portion 26c of the substrate 12 and the second end portion 26b. According to such a configuration, the heat in the region between the central portion 26 c and the second end portion 26 b of the substrate 12 that is relatively far from the connector 15 is efficiently released to the housing 11 through the second contact portion 42. Can do. Thereby, a configuration in which heat is easily released from substantially the entire area of the substrate 12 is realized. For this reason, the heat dissipation of the semiconductor device 1 can be further improved.

  The semiconductor device 1 according to the second to fifth embodiments will be described below. In addition, the structure which has the same or similar function as the structure of 1st Embodiment attaches | subjects the same code | symbol, and abbreviate | omits the description. The configuration other than that described below is the same as that of the first embodiment.

(Second Embodiment)
FIG. 4 shows a semiconductor device 1 according to the second embodiment. In the present embodiment, the first wall 31 of the housing 11 has a plurality of contact portions 41 and 42. The contact portions 41 and 42 are in contact with the first surface 12 a of the substrate 12 at positions away from the plurality of semiconductor memory chips 13 and the controller chip 14.

  More specifically, the first contact portion 41 is in contact with the first surface 12 a of the substrate 12 at a position between the semiconductor memory chip 13 and the controller chip 14. On the other hand, the second contact portion 42 is in contact with the first surface 12 a of the substrate 12 at a position between the plurality of semiconductor memory chips 13.

  According to such a configuration, the heat dissipation of the semiconductor device 1 can be improved as in the first embodiment. Further, in the present embodiment, the contact portions 41 and 42 are in contact with the first surface 12 a of the substrate 12. According to such a configuration, even when the plurality of semiconductor memory chips 13 are separately mounted on the first surface 12a and the second surface 12b of the substrate 12, it is possible to ensure contact between the substrate 12 and the housing 11. it can.

  The housing 11 includes contact portions 41 and 42 according to the first embodiment (contact portions in contact with the second surface 12b of the substrate 12) and contact portions 41 and 42 according to the second embodiment (first of the substrate 12). And a contact portion in contact with the surface 12a).

(Third embodiment)
Next, a semiconductor device 1 according to the third embodiment will be described with reference to FIGS. FIG. 5 shows the first surface 12a of the substrate 12 according to this embodiment. A plurality of semiconductor memory chips 13 and a controller chip 14 are mounted on the first surface 12a.

  The semiconductor device 1 according to the present embodiment further includes an electric double layer capacitor 61 (so-called super capacitor or ultra capacitor) on the first surface 12 a of the substrate 12. The electric double layer capacitor 61 is one of heat-sensitive components.

  The electric double layer capacitor 61 is separated from the controller chip 14 which is a heat generating component, and is located closer to the second end portion 26 b of the substrate 12 than the controller chip 14 and the plurality of semiconductor memory chips 13. The electric double layer capacitor 61 is located closest to the second end portion 26 b of the substrate 12 among the plurality of components mounted on the first surface 12 a of the substrate 12. In the present embodiment, the electric double layer capacitor 61 is located at the second end portion 26 b of the substrate 12. The electric double layer capacitor 61 is not limited to being located at the second end portion 26b, and may be located between the central portion 26c of the substrate 12 and the second end portion 26b.

  FIG. 6 shows the second surface 12 b of the substrate 12. The second surface 12b is provided with a wiring pattern 63 including signal lines and a ground layer 24. A part of the ground layer 24 is exposed on the surface of the substrate 12 as an exposed region 24a. For convenience of explanation, the exposed region 24a in the figure is hatched. The ground layer 24 is provided between the wiring pattern 63 and the edge of the substrate 12. The ground layer 24 is provided along the edge of the substrate 12 in order to ensure a large exposed region 24a (expanded to the vicinity of the edge).

  FIG. 7 shows the housing 11 of the semiconductor device 1 in an exploded manner. The housing 11 includes a base 21 and a cover 22. The base 21 is formed by bending a plate material into a bowl shape. FIG. 8 shows a plan view of the base 21. As shown in FIGS. 7 and 8, the base 21 has a recessed portion 64 (projecting portion) that is recessed toward the substrate 12. The recess 64 faces the plurality of semiconductor memory chips 13 and the controller chip 14. A heat conductive sheet 28 is interposed between the recess 64 and the semiconductor memory chip 13 and the controller chip 14.

  Thereby, a part of the heat from the semiconductor memory chip 13 and the controller chip 14 is dissipated to the housing 11 through the heat conductive sheet 28. In addition, by providing the recess 64 to reduce the distance between the housing 11 and the semiconductor memory chip 13 and the controller chip 14, the heat conductive sheet 28 can be thinned and heat dissipation can be improved. it can.

  FIG. 9 shows a plan view of the cover 22. As shown in FIGS. 7 and 9, the housing 11 (cover 22) has a first region 71 facing the controller chip 14 and a second region 72 facing the electric double layer capacitor 61. The first contact portion 41 is provided in the first region 71 and contacts the second surface 12 b of the substrate 12 on the back side of the controller chip 14. The second contact portion 42 is provided in the second region 72 and contacts the second surface 12 b of the substrate 12 on the back side of the electric double layer capacitor 61.

  As shown in FIGS. 7 and 9, a slit 73 is provided between the first region 71 and the second region 72. Thereby, the heat transmitted from the substrate 12 to the first region 71 of the housing 11 by the first contact portion 41 is not easily transmitted to the second region 72 of the housing 11. Note that the housing 11 may be provided with a groove instead of the slit 73.

  FIG. 10 shows a mounting structure of the semiconductor device 1. The host device 2 has a plurality of connectors 81 to which the semiconductor device 1 is connected. The plurality of connectors 81 are arranged at substantially equal intervals in the vertical direction, for example. The plurality of semiconductor devices 1 are respectively connected to the connectors 81 of the host device 2 and are arranged substantially parallel to the vertical direction.

  The host device 2 has a fan 82 on the opposite side of the connector 81 with the semiconductor device 1 interposed therebetween. The fan 82 sends air to the second end portion 11b (rear end portion) of the semiconductor device 1 in which the electric double layer capacitor 61 is accommodated.

  According to such a configuration, the heat dissipation of the semiconductor device 1 can be improved as in the first embodiment.

  In the present embodiment, the semiconductor device 1 further includes an electric double layer capacitor 61 mounted on the second end portion 26 b of the substrate 12. Here, when the housing 11 has the contact portions 41 and 42, heat from the controller chip 14 and the semiconductor memory chip 13 may be transmitted to the electric double layer capacitor 61 through the housing 11.

  Therefore, in the present embodiment, the housing 11 has a first region 71 facing the controller chip 14 and a second region 72 facing the electric double layer capacitor 61, and the first region 71, the second region 72, A slit 73 is provided therebetween. For this reason, the heat transferred from the substrate 12 to the first region 71 of the housing 11 by the first contact portion 41 is not easily transferred to the electric double layer capacitor 61. Thereby, the electric double layer capacitor 61 can be protected from heat. Thereby, the malfunction of the electric double layer capacitor 61 can be prevented, and the reliability of the semiconductor device 1 can be improved.

  Further, when the second contact portion 42 is in contact with the second surface 12b of the substrate 12 on the back side of the electric double layer capacitor 61, the heat in the vicinity of the electric double layer capacitor 61 can be released to the casing 11, so that the electric double layer capacitor The temperature rise of 61 can be further suppressed. Further, when the host device 2 includes the fan 82 that cools the second end portion 11b (or the second region 72) of the housing 11 as in the present embodiment, the temperature increase of the electric double layer capacitor 61 is further suppressed. Can do.

(Fourth embodiment)
FIG. 11 shows the second surface 12b of the substrate 12 according to the fourth embodiment. The substrate 12 according to the present embodiment has a solid layer of the ground layer 24 on the outermost layer of the second surface 12b of the substrate 12. In the present embodiment, the ground layer 24 has an exposed region 24 a on substantially the entire second surface 12 b of the substrate 12. For convenience of explanation, the exposed region 24a in the figure is hatched. The exposed region 24a has a size that is, for example, half or more of the area of the substrate 12. On the other hand, the housing 11 has a contact portion 41 having a size corresponding to the outer shape of the exposed region 24 a of the ground layer 24. That is, in this embodiment, the housing 11 and the substrate 12 are in contact with each other over substantially the entire area of the substrate 12.

  According to such a configuration, the heat dissipation of the semiconductor device 1 can be improved as in the first embodiment. Furthermore, according to the present embodiment, the contact area between the housing 11 and the substrate 12 can be further increased, so that the heat dissipation of the semiconductor device 1 can be further improved.

(Fifth embodiment)
FIG. 12 is a partially exploded view of the semiconductor device 1 according to the fifth embodiment. A plurality of semiconductor memory chips 13 and a controller chip 14 are mounted on the first surface 12 a of the substrate 12. For convenience of explanation, illustration of the controller chip 14 is omitted.

  In the present embodiment, a temperature sensor 91 is further mounted on the first surface 12 a of the substrate 12. The contact portion 41 of the housing 11 is in contact with the substrate 12 on the back side of the temperature sensor 91. In other words, the portion of the substrate 12 on which the temperature sensor 91 is located is soaked with the housing 11 by the contact portion 41 and approaches the temperature of the housing 11.

  According to such a configuration, the heat dissipation of the semiconductor device 1 can be improved as in the first embodiment.

  The host device 2 is generally designed based on the temperature state of the housing 11 of the semiconductor device 1. Here, the temperature detected by the temperature sensor 91 is the temperature of the substrate 12, not the temperature of the housing 11. Therefore, in order to estimate the temperature of the housing | casing 11, it is possible to arrange | position a temperature sensor in the several places of the board | substrate 12, for example, and complement the temperature of the housing | casing 11 from those parameters. However, in this case, a program for complementing the temperature of the housing 11 is required, and the semiconductor device 1 is complicated.

  Therefore, in the present embodiment, the contact portion 41 of the housing 11 is in contact with the substrate 12 on the back side of the temperature sensor 91. For this reason, the temperature sensor 91 can directly detect a temperature close to the temperature of the housing 11 via the contact portion 41. Thereby, the complicated complementary calculation of the temperature of the housing | casing 11 can be abbreviate | omitted or simplified, and the number of the temperature sensors 91 can also be reduced. Thereby, the cost of the semiconductor device 1 can be reduced.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

  The contact portions 41 and 42 of the housing 11 are not limited to those that are joined to the substrate 12 with the solder 51, but may be those that simply contact the substrate 12. The contact portions 41 and 42 are not limited to those in contact with the ground layer 24 of the substrate 12, and may be in contact with places other than the ground layer 24.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Host device, 11 ... Housing | casing, 12 ... Board | substrate, 12a ... 1st surface, 12b ... 2nd surface, 13 ... Semiconductor memory chip, 14 ... Controller chip, 15 ... Connector, 24 ... Ground layer , 26a ... first end portion, 26b ... second end portion, 26c ... center portion, 41, 42 ... contact portion, 51 ... solder, 61 ... electric double layer capacitor, 71 ... first region, 72 ... second region, 73 ... Slit, 91 ... Temperature sensor.

Claims (10)

A housing,
A substrate that is housed in the housing and includes a first surface and a second surface located on the opposite side of the first surface;
A connector provided on the substrate and connectable to a host device;
A plurality of semiconductor memory chips mounted on the first surface of the substrate;
A controller chip mounted on the first surface of the substrate, for transmitting and receiving signals to and from the host device, and for controlling the plurality of semiconductor memory chips;
With
The housing includes a contact portion that protrudes toward the substrate and has a contact portion in contact with the first surface or the second surface of the substrate at a position away from the plurality of semiconductor memory chips and the controller chip. In the description of claim 1,
The housing is a semiconductor device made of metal. In the description of claim 1 or claim 2,
The substrate has a ground layer exposed on a surface of the substrate;
The contact portion is a semiconductor device in contact with a ground layer of the substrate. In the description of claim 3,
The contact portion is a semiconductor device bonded to a ground layer of the substrate with solder. In any one of Claims 1 to 4,
The contact portion is a semiconductor device in contact with the first surface of the substrate at a position between one of the plurality of semiconductor memory chips and the controller chip. In any one of Claims 1 to 4,
The contact portion is a semiconductor device in contact with the second surface of the substrate. In any one of Claims 1 thru | or 6,
The board has a first end provided with the connector, and a second end located on the opposite side of the first end,
The contact portion is a semiconductor device in contact with the substrate at a position between a central portion and a second end portion of the substrate. In any one of Claims 1 to 7,
An electric double layer capacitor mounted on the substrate;
The housing has a first region facing the controller chip and a second region facing the electric double layer capacitor, and a slit is provided between the first region and the second region. Semiconductor device. In any one of Claims 1 to 8,
A temperature sensor mounted on the substrate;
The contact portion is a semiconductor device in contact with the substrate at a position on the back side of the temperature sensor. A housing,
A substrate housed in the housing;
A semiconductor chip mounted on the substrate;
With
The said housing | casing has a part which contact | connected the said board | substrate in the position which removed the said semiconductor chip.

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