JP2015126155A - Thin film capacitor - Google Patents

Thin film capacitor Download PDF

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JP2015126155A
JP2015126155A JP2013270787A JP2013270787A JP2015126155A JP 2015126155 A JP2015126155 A JP 2015126155A JP 2013270787 A JP2013270787 A JP 2013270787A JP 2013270787 A JP2013270787 A JP 2013270787A JP 2015126155 A JP2015126155 A JP 2015126155A
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insulator structure
dielectric layer
defect
thin film
film capacitor
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JP6323005B2 (en
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淳司 青谷
Junji Aotani
淳司 青谷
矢野 義彦
Yoshihiko Yano
義彦 矢野
泰伸 及川
Yasunobu Oikawa
泰伸 及川
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TDK Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a thin film capacitor in which degradation of breakdown voltage performance is prevented.SOLUTION: A thin film capacitor 1 includes a lower electrode 2, a dielectric layer 3 provided on the lower electrode, and an upper electrode 4 formed on the dielectric layer, and has an insulator structure 5 enclosing a defect 6 included in a part of the dielectric layer. The outermost part of the insulator structure has a tapered cross-sectional shape. The tapered cross-sectional shape of the insulator structure has (1) a tangent in contact with the position of 50% of the maximum height of the insulator structure at the outermost part thereof, and (2) a tapered cross-sectional angle where the angle formed by the dielectric layer and a line, i.e., the interface with the upper electrode, is smaller than 25 degrees. The outermost part of the insulator structure is not in contact with the end of a defect, and the distance from the end of a defect to the outermost part of the insulator structure is 20-150 times of the thickness of a dielectric film.

Description

本発明は薄膜キャパシタに関する。 The present invention relates to a thin film capacitor.

近年の各種電子機器では、電子部品を実装するスペースが縮小される傾向にある。このためキャパシタ(いわゆる「コンデンサ」をいう。)では素子の低背化が要求されている。
キャパシタの低背化には誘電体層を薄くすることが有効である。誘電体層厚を薄くしたキャパシタとして、スパッタリング法等の薄膜形成技術を用いて誘電体層を形成したキャパシタ(以下、「薄膜キャパシタ」という。)が知られている(特許文献1参照。)。特許文献1に記載の薄膜キャパシタは、ベース基板上に、第1の電極層、誘電体層、第2の電極層をこの順に積層して形成されている。
In recent electronic devices, the space for mounting electronic components tends to be reduced. For this reason, a capacitor (referred to as a “capacitor”) is required to have a low-profile element.
Thinning the dielectric layer is effective for reducing the height of the capacitor. As a capacitor having a thin dielectric layer, a capacitor having a dielectric layer formed by using a thin film forming technique such as sputtering (hereinafter referred to as “thin film capacitor”) is known (see Patent Document 1). The thin film capacitor described in Patent Document 1 is formed by laminating a first electrode layer, a dielectric layer, and a second electrode layer in this order on a base substrate.

従来の薄膜キャパシタでは、誘電体層厚を薄くしていくと、誘電体層に欠陥が生じて短絡不良が発生したり、リーク電流が増加したり、耐電圧が低下したりするといった問題があった。ここで「欠陥」とは、誘電体層上や誘電体層内部に存在する、異物や誘電体のクラック、ピンホールなどのような誘電体の正常な状態とは異なる部位のことをいう。 In the conventional thin film capacitor, when the dielectric layer thickness is reduced, defects occur in the dielectric layer, causing a short circuit failure, increasing a leakage current, and decreasing a withstand voltage. It was. Here, the “defect” means a portion different from the normal state of the dielectric, such as a foreign matter, a dielectric crack, or a pinhole, existing on the dielectric layer or inside the dielectric layer.

特許文献1では、短絡不良の発生、リーク電流の増加、耐電圧の低下という問題は、誘電体層に存在するピンホール部や結晶粒界に起因して発生するとの考えを示している。特許文献1は、この問題の解決手段として、誘電体層のピンホール部や結晶粒界と第1の電極層の間に、第1の電極層を構成する材料を酸化させて絶縁層を形成する技術を開示している。 Japanese Patent Application Laid-Open No. 2004-228561 suggests that the problems of occurrence of short-circuit failure, increase in leakage current, and decrease in withstand voltage are caused by pinhole portions and crystal grain boundaries existing in the dielectric layer. In Patent Document 1, as a means for solving this problem, an insulating layer is formed by oxidizing the material constituting the first electrode layer between the pinhole portion of the dielectric layer or the grain boundary and the first electrode layer. The technology to do is disclosed.

特許文献2は、下層の導体パターン上に、絶縁層または低誘電体層を積層し、この絶縁層等の上に上層の導体パターンを積層してなる多層配線基板における絶縁層等の欠損部分を補修する技術を開示している。この技術では、絶縁層等の形成後に、下層の導体パターンを一方の電極とした電着法を用いて、絶縁層等の欠損部分に、エポキシ樹脂等の絶縁性材料を付着させている。 In Patent Document 2, an insulating layer or a low dielectric layer is laminated on a lower conductor pattern, and a defective portion such as an insulating layer in a multilayer wiring board in which an upper conductor pattern is laminated on the insulating layer or the like is disclosed. The technology to repair is disclosed. In this technique, after formation of an insulating layer or the like, an insulating material such as an epoxy resin is attached to a deficient portion of the insulating layer or the like by using an electrodeposition method in which a lower conductive pattern is one electrode.

特許文献3は、誘電体層のピンホール部などに対して電気泳動法を用いた樹脂絶縁物を形成する製造方法を開示している。 Patent Document 3 discloses a manufacturing method for forming a resin insulator using an electrophoresis method on a pinhole portion or the like of a dielectric layer.

特開2002−26266号公報JP 2002-26266 A 特開2002−185148号公報JP 2002-185148 A 特開2008−160040号公報JP 2008-160040 A

特許文献1乃至3の発明者らが開示するように、誘電体層の欠陥をなんらかの絶縁体構造物でコーティングし、耐圧性能を向上させようとする技術は知られている。しかし、本発明者らはこのようなコーティングをおこなっても薄膜キャパシタに耐圧性能が十分に得られない場合があることを見いだした。 As disclosed by the inventors of Patent Documents 1 to 3, a technique for improving the breakdown voltage performance by coating a defect in a dielectric layer with some insulator structure is known. However, the present inventors have found that even with such coating, the thin film capacitor may not have sufficient withstand voltage performance.

例えば、絶縁体構造物最外部が急峻なテーパー断面角度を有する場合は、あるいは、絶縁体構造物の端部から欠陥の端部までの距離を近接させざるを得ない場合は、絶縁体構造物に蓄えられた電荷が、絶縁体構造物と誘電体層との界面を伝わって欠陥に達してしまい、薄膜キャパシタの耐圧は低下する。 For example, when the outermost part of the insulator structure has a steep taper section angle, or when the distance from the end of the insulator structure to the end of the defect must be close, the insulator structure The electric charge stored in is transmitted to the interface between the insulator structure and the dielectric layer and reaches a defect, so that the breakdown voltage of the thin film capacitor is lowered.

本発明は、上記知見に鑑みてなされたものであり、耐圧性能を向上させた薄膜キャパシタを提供することを目的とする。 The present invention has been made in view of the above knowledge, and an object thereof is to provide a thin film capacitor having improved withstand voltage performance.

上記の課題を解決する薄膜キャパシタは、下部電極と、下部電極上に設けられた誘電体層と、誘電体層上に形成された上部電極とを備える。薄膜キャパシタの誘電体層には欠陥が含まれている。薄膜キャパシタの誘電体層と上部電極層との界面には絶縁体構造物が形成されている。この絶縁体構造物は、欠陥を上部電極に対して露出しないよう内包する。また、絶縁体構造物の断面構造は、(1)絶縁体構造物の端部であってかつ絶縁体構造物の最大高さの50%の位置に接する接線と、(2)誘電体層と上部電極との界面である線と、が成す角度(以下、これを「テーパー断面角度」という。)が25度よりも小となる、なだらかなテーパー断面角度を有している。薄膜キャパシタをこの構造とすることにより、絶縁体構造物と誘電体層との界面における電荷の移動を抑制する効果が得られる。この効果の原因は必ずしも明らかではないが、発明者らは、第一には絶縁体構造物の最外部と欠陥とが乖離しているため絶縁体構造物と誘電体層との界面を移動する電荷が欠陥に至る前に消費されること、第二に絶縁体構造物の最外部がなだらかな形状を有しているため電界集中が生じにくくなっていること、これら二つによるものと考えている。この効果の結果、本願発明の実施により薄膜キャパシタの短絡不良を防止し、充分な容量等の特性を確保することができる。このような絶縁体構造物は、電気泳動法を用いた電着樹脂の形成によって実現される。また、電気泳動法によれば、電流リークの原因となる欠陥に対して選択的に絶縁体構造物を形成できる。 A thin film capacitor that solves the above problem includes a lower electrode, a dielectric layer provided on the lower electrode, and an upper electrode formed on the dielectric layer. The dielectric layer of the thin film capacitor contains defects. An insulator structure is formed at the interface between the dielectric layer and the upper electrode layer of the thin film capacitor. This insulator structure includes a defect so as not to be exposed to the upper electrode. The cross-sectional structure of the insulator structure is as follows: (1) a tangent line that is at the end of the insulator structure and touches 50% of the maximum height of the insulator structure; and (2) a dielectric layer; An angle formed by a line that is an interface with the upper electrode (hereinafter referred to as a “taper section angle”) has a gentle taper section angle that is smaller than 25 degrees. By adopting this structure for the thin film capacitor, an effect of suppressing the movement of charges at the interface between the insulator structure and the dielectric layer can be obtained. Although the cause of this effect is not necessarily clear, the inventors first move the interface between the insulator structure and the dielectric layer because the outermost part of the insulator structure is separated from the defect. The charge is consumed before it reaches the defect, and secondly, the outermost part of the insulator structure has a gentle shape, so electric field concentration is less likely to occur. Yes. As a result of this effect, short circuit failure of the thin film capacitor can be prevented by implementing the present invention, and characteristics such as sufficient capacity can be secured. Such an insulator structure is realized by forming an electrodeposition resin using an electrophoresis method. Moreover, according to the electrophoresis method, an insulator structure can be selectively formed with respect to a defect that causes current leakage.

欠陥の端部から絶縁体構造物の最外部までの最短距離は、誘電体層の厚みの20倍以上150倍以下である。絶縁体構造物の最外部に蓄積された電荷は、誘電体層の厚さ方向(電気抵抗値R1を有する)と、絶縁体構造物と誘電体層との界面方向(電気抵抗値R2を有する)と、に移動する可能性がある。本発明者らは、シミュレーションおよび実験を通じてこれらの電気抵抗を検討した。抵抗値R1とR2との関係は、誘電体層および絶縁物構造体の材料種類によって変動はあるものの、おおむね抵抗値R1がR2の約150倍であった。欠陥の端部から絶縁体構造物の最外部までの最短距離(以下、この距離を「Lmin」と表記する。)が、誘電体層の厚みの150倍を超えた場合、薄膜キャパシタに短絡やリーク電流が生じる確率が増加する。これは絶縁体構造物の最外部に蓄積した電荷が、相対的に電気抵抗が低い誘電体層の厚み方向へ流れようとするためと考えられる。薄膜キャパシタ製品の見地からも、絶縁体抵抗物の大きさは小さいほうが好ましい。面積が大きいと薄膜キャパシタの容量を損なう傾向があるためである。また、薄膜キャパシタに微細パターニングを施す場合に樹脂が障害となる場合がある。ただし、Lminが誘電体層の厚みの20倍を下回った場合も、薄膜キャパシタに短絡やリーク電流が生じる確率が増加する。これは平面方向での電荷消費が十分でなく欠陥に電荷が到達してしまうためと考えられる。 The shortest distance from the edge of the defect to the outermost part of the insulator structure is not less than 20 times and not more than 150 times the thickness of the dielectric layer. The charge accumulated in the outermost part of the insulator structure has a thickness direction of the dielectric layer (having an electric resistance value R1) and an interface direction (electric resistance value R2) between the insulator structure and the dielectric layer. ) And may move on. The inventors examined these electric resistances through simulations and experiments. Although the relationship between the resistance values R1 and R2 varies depending on the material types of the dielectric layer and the insulator structure, the resistance value R1 is generally about 150 times that of R2. When the shortest distance from the edge of the defect to the outermost part of the insulator structure (hereinafter, this distance is expressed as “L min ”) exceeds 150 times the thickness of the dielectric layer, it is short-circuited to the thin film capacitor. And the probability of leakage current increases. This is presumably because the charge accumulated on the outermost part of the insulator structure tends to flow in the thickness direction of the dielectric layer having a relatively low electrical resistance. From the viewpoint of thin film capacitor products, it is preferable that the size of the insulator resistor is small. This is because if the area is large, the capacity of the thin film capacitor tends to be impaired. Further, the resin may become an obstacle when fine patterning is performed on the thin film capacitor. However, even when L min is less than 20 times the thickness of the dielectric layer, the probability of a short circuit or leakage current occurring in the thin film capacitor increases. This is presumably because the charge consumption in the planar direction is not sufficient and the charge reaches the defect.

テーパー断面角度は、1度以上10度以下であることが好ましい。10度を超える角度の場合は、最外部での電荷の蓄積が大きくなり短絡やリーク電流が生じる可能性がある。また、1度未満の角度の場合は、膜の密着不良が発生する場合があり、電荷の蓄積が広範囲におよぶため、やはり短絡やリーク電流が生じる可能性がある。 The taper cross-sectional angle is preferably 1 degree or more and 10 degrees or less. In the case of an angle exceeding 10 degrees, charge accumulation at the outermost part is increased, which may cause a short circuit or a leakage current. When the angle is less than 1 degree, film adhesion failure may occur, and charge accumulation is wide-ranging, which may cause a short circuit or a leakage current.

本発明の薄膜キャパシタによれば、短絡不良を防止した薄膜キャパシタを提供することができる。 According to the thin film capacitor of the present invention, it is possible to provide a thin film capacitor in which short circuit failure is prevented.

本発明の実施形態に係る薄膜キャパシタを示した模式断面図である。1 is a schematic cross-sectional view showing a thin film capacitor according to an embodiment of the present invention. 本発明の実施形態に係る電着部分の光学顕微鏡による観察像である。It is an observation image by the optical microscope of the electrodeposition part which concerns on embodiment of this invention. 本発明の実施形態に係る電着部分のSEM(走査型電子顕微鏡)による断面観察像である。It is a cross-sectional observation image by SEM (scanning electron microscope) of the electrodeposition part which concerns on embodiment of this invention. 本発明の実施形態に係る電着装置の概略図である。It is the schematic of the electrodeposition apparatus which concerns on embodiment of this invention.

以下、図面を参照して、本発明の好適な実施形態について説明する。なお、同一又は同等の要素については同一の符号を付し、説明が重複する場合にはその説明を省略する。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected about the same or equivalent element, and the description is abbreviate | omitted when description overlaps.

図1は、本発明の実施形態における薄膜キャパシタの断面図である。薄膜キャパシタ1は、下部電極2、下部電極2上に形成された誘電体層3、さらにその上に形成された上部電極4により構成されている。 FIG. 1 is a cross-sectional view of a thin film capacitor according to an embodiment of the present invention. The thin film capacitor 1 includes a lower electrode 2, a dielectric layer 3 formed on the lower electrode 2, and an upper electrode 4 formed thereon.

本実施形態における下部電極2の材料は、公知の導電性材料を適宜選択することができる。公知の導電性材料とは、たとえば、金属、金属酸化物、導電性有機材料などをいう。特に、下部電極2は低電気抵抗であることが望ましく、機械的強度が高いことが望ましいため、金属材料を用いることが好ましい。中でも、NiやCuは電気抵抗の低い比較的強靭な金属材料であるため好ましい。特に、高温負荷信頼性および耐湿負荷信頼性の見地から、少なくともNiを含んだ導電体であることが望ましい。ここでいうNiを含んだ導電体とは純Ni(Ni99.9%以上)のこと、もしくはNi系の合金のことをいう。Ni系の合金の場合、例えばPt、Pd、Ir、Ru、Rhなどの貴金属元素を含むことが望ましく、その含有量は50wt%以下が望ましい。このような含有率の範囲内であれば、純Niを使用した場合と同等な薄膜キャパシタ1の高温負荷信頼性および耐湿負荷信頼性が得られる。 As a material of the lower electrode 2 in the present embodiment, a known conductive material can be appropriately selected. A well-known conductive material means a metal, a metal oxide, a conductive organic material etc., for example. In particular, since the lower electrode 2 desirably has a low electrical resistance and desirably has a high mechanical strength, it is preferable to use a metal material. Among these, Ni and Cu are preferable because they are relatively tough metal materials having low electrical resistance. In particular, from the viewpoint of high temperature load reliability and moisture resistance load reliability, a conductor containing at least Ni is desirable. Here, the Ni-containing conductor means pure Ni (Ni 99.9% or more) or a Ni-based alloy. In the case of a Ni-based alloy, it is desirable to include a noble metal element such as Pt, Pd, Ir, Ru, Rh, for example, and the content is desirably 50 wt% or less. If it is in the range of such a content rate, the high temperature load reliability and moisture-proof load reliability of the thin film capacitor 1 equivalent to the case where pure Ni is used will be obtained.

本実施形態における下部電極2の形態は、金属を含む導電性の箔、金属を含む焼結体あるいは任意の基板上に形成された導電性薄膜など、各種の形態を選択することができる。下部電極2は、特に金属多結晶体よりなるNi金属箔であることが好ましい。金属箔にすることで、誘電体層との熱膨張係数の差を小さくすることが可能となり、薄膜キャパシタ1の容量の減少を抑制することが可能となる。導電性薄膜としては、例えば、Si基板やセラミック基板(図示せず)の上に、下部電極2としてスパッタリングや蒸着等によってNi電極層を形成して用いてもよい。このような形態の場合、基板は誘電体層3との熱膨張係数差が小さな材料を選択することが望ましい。基板には、例えばNi膜つきのSi基板、Ni膜つきのセラミック基板などを用いることができる。これにより、熱膨張係数差に起因する薄膜キャパシタ1の容量低下を抑制することができる。 The form of the lower electrode 2 in this embodiment can select various forms, such as the electroconductive foil containing a metal, the sintered compact containing a metal, or the electroconductive thin film formed on arbitrary board | substrates. The lower electrode 2 is particularly preferably a Ni metal foil made of a metal polycrystal. By using the metal foil, it becomes possible to reduce the difference in thermal expansion coefficient from the dielectric layer, and to suppress the decrease in the capacity of the thin film capacitor 1. As the conductive thin film, for example, a Ni electrode layer may be formed as the lower electrode 2 by sputtering or vapor deposition on a Si substrate or a ceramic substrate (not shown). In such a form, it is desirable to select a material having a small difference in thermal expansion coefficient from the dielectric layer 3 for the substrate. As the substrate, for example, a Si substrate with a Ni film, a ceramic substrate with a Ni film, or the like can be used. Thereby, the capacity | capacitance fall of the thin film capacitor 1 resulting from a thermal expansion coefficient difference can be suppressed.

本実施形態における下部電極2の形態は、さらに下部電極2と誘電体層3との間には異なる導電性材料を介在させたものであってもよい。あるいは、多層電極構造であってもよい。多層電極構造としては、誘電体層3と接する面側にNi電極層を配置した多層電極膜とすることができる。このような多層電極層は、例えばCu金属箔にNi電極層をスパッタリングや蒸着等によって形成し積み重ねた構造であってもよい。ただし、Ni電極層と誘電体層3とが接している場合は、薄膜キャパシタ1の高温負荷信頼性および耐湿負荷信頼性がさらに向上する。 The form of the lower electrode 2 in the present embodiment may further include a different conductive material interposed between the lower electrode 2 and the dielectric layer 3. Alternatively, a multilayer electrode structure may be used. The multilayer electrode structure may be a multilayer electrode film in which a Ni electrode layer is disposed on the side in contact with the dielectric layer 3. Such a multilayer electrode layer may have a structure in which, for example, a Ni electrode layer is formed on a Cu metal foil by sputtering or vapor deposition and stacked. However, when the Ni electrode layer and the dielectric layer 3 are in contact with each other, the high temperature load reliability and moisture resistance load reliability of the thin film capacitor 1 are further improved.

本実施形態における誘電体層3の材料は、誘電率の大きいペロブスカイト型の酸化物誘電体が好ましい。ペロブスカイト型の誘電体の中でも、鉛を含まないチタン酸バリウム系の誘電体が環境保全の見地から好ましい。チタン酸バリウム系の誘電体の場合、Baサイトの一部をCa、Srなどのアルカリ土類で置換したものを用いてもよい。またTiサイトの一部をZr、Sn、Hfなどの元素で置換したものを用いてもよい。さらに、この誘電体に希土類元素やMn、V、Nb、Taなどを添加してもよい。 The material of the dielectric layer 3 in this embodiment is preferably a perovskite oxide dielectric having a large dielectric constant. Among the perovskite-type dielectrics, a lead-free barium titanate-based dielectric is preferable from the viewpoint of environmental protection. In the case of a barium titanate-based dielectric material, a Ba site partially substituted with an alkaline earth such as Ca or Sr may be used. Moreover, you may use what substituted a part of Ti site by elements, such as Zr, Sn, and Hf. Further, rare earth elements, Mn, V, Nb, Ta, or the like may be added to the dielectric.

本実施形態における誘電体層3の形成は、薄膜形成で通常使用される方法、例えば溶液の塗布、スパッタリング、蒸着、PLD(Pulse Laser Deposition)、CVDなど適宜用いることができる。 The formation of the dielectric layer 3 in the present embodiment can be appropriately performed by a method usually used in thin film formation, such as solution coating, sputtering, vapor deposition, PLD (Pulse Laser Deposition), and CVD.

本実施形態における誘電体層3の構造は、膜厚が1000nm以下の薄膜であることが好ましい。1000nmを超える場合、単位面積あたりの容量値が減少してしまう虞がある。また膜厚の下限は特にないが、薄くなるに従い絶縁抵抗値が小さくなる。そのため50nm以上は必要と考えられる。以上の絶縁抵抗値と容量の関係を考慮し、薄膜キャパシタ1の好ましい誘電体層3の膜厚の範囲は250nmから1000nmであると考えられる。なお、本実施形態における誘電体層3には、確率論的に回避困難な欠陥が内包されている。 The structure of the dielectric layer 3 in the present embodiment is preferably a thin film having a thickness of 1000 nm or less. If it exceeds 1000 nm, the capacitance value per unit area may decrease. There is no particular lower limit to the film thickness, but the insulation resistance value decreases as the thickness decreases. Therefore, 50 nm or more is considered necessary. Considering the above relationship between the insulation resistance value and the capacitance, it is considered that the preferable thickness range of the dielectric layer 3 of the thin film capacitor 1 is 250 nm to 1000 nm. Note that the dielectric layer 3 in the present embodiment contains defects that are difficult to avoid stochastically.

本実施形態では、誘電体層3を形成した後に絶縁体構造物5を形成する。誘電体層3の表面は、絶縁体構造物5を形成する前に表面処理あるいは物理洗浄等をおこなっておくことが好ましい。表面処理としては酸やアルカリによるエッチング、プラズマによるエッチングなどをおこなってもよい。物理洗浄としては超音波洗浄や研磨などをおこなってもよい。これらの処理により、誘電体層3と絶縁体構造物5との界面状態が良好になるため長期的に電気特性が安定となる。また、後述する絶縁体構造物5の形成工程において、絶縁体構造物5の形成を誘電体層3の欠陥に対して集中させるよう、選択性を発揮させることができる。 In the present embodiment, the insulator structure 5 is formed after the dielectric layer 3 is formed. The surface of the dielectric layer 3 is preferably subjected to surface treatment or physical cleaning before the insulator structure 5 is formed. As the surface treatment, etching with acid or alkali, etching with plasma, or the like may be performed. As the physical cleaning, ultrasonic cleaning or polishing may be performed. By these treatments, the interface state between the dielectric layer 3 and the insulator structure 5 becomes good, so that the electrical characteristics become stable in the long term. In addition, in the step of forming the insulator structure 5 to be described later, selectivity can be exhibited so that the formation of the insulator structure 5 is concentrated on the defects of the dielectric layer 3.

本実施形態における絶縁体構造物5の材料は、高電気抵抗の樹脂材料であることが好ましい。絶縁体構造物5そのものが高電気抵抗の柔軟な構造となることにより、完成後の薄膜キャパシタ1の使用を通じて誘電体層3との界面の電気状態が変化しにくくなるためである。このような樹脂材料は、公知の高電気抵抗の樹脂材料から適宜選択することができる。具体的には、アクリル樹脂、エポキシ樹脂、フッ素樹脂、ウレタン樹脂、アミド樹脂、フェノール樹脂、PEEK樹脂、ポリカーボネート樹脂、ポリブタジエン樹脂、ポリイミド樹脂等の樹脂材料の中から選択することができる。これらの樹脂材料は、単独で、あるいは、二種以上を組み合わせて用いてもよい。 The material of the insulator structure 5 in the present embodiment is preferably a resin material with high electrical resistance. This is because the insulator structure 5 itself has a flexible structure with high electrical resistance, so that the electrical state at the interface with the dielectric layer 3 is hardly changed through the use of the thin film capacitor 1 after completion. Such a resin material can be appropriately selected from known high electrical resistance resin materials. Specifically, it can be selected from resin materials such as acrylic resin, epoxy resin, fluorine resin, urethane resin, amide resin, phenol resin, PEEK resin, polycarbonate resin, polybutadiene resin, and polyimide resin. These resin materials may be used alone or in combination of two or more.

本実施形態における絶縁体構造物5の構造は、誘電体層3の欠陥を略中心においた絶縁体のパッチ状構造となっている。本実施形態に係る代表的な絶縁体構造物5の形状を図2および図3に示す。図2は、本実施形態の絶縁体構造物5を上面から見た光学顕微鏡による観察像である。誘電体層3には不純物粒子が付着後に剥離してできた欠陥6が存在するところ、絶縁体構造物5は、欠陥6が略中心に位置するような略円形のパッチ形状として誘電体層3の上に形成されている。欠陥6の端部と絶縁体構造物5の最外部とが形成するLminは、図2のような平面の観察写真から読み取ることができる。本実施形態の絶縁体構造物5は、図2中の矢印に示すとおり40μmである。欠陥6が不規則な形状、例えば比較的長距離に及ぶ傷などであった場合、欠陥の形状に応じて長円状や曲線状のパッチ形状として形成される場合がある。その場合のLminは、欠陥6の端部と絶縁体構造物5の最外部との最短距離を読み取ることで定義できる。読み取るべき位置は、絶縁体構造物5から欠陥6の方向へ、最も電荷が流れやすい箇所として経験的に判断することができる。図3は、本実施形態の絶縁体構造物5のSEM(走査型電子顕微鏡)による断面観察像である。断面観察は、欠陥6を中心に下部電極2、誘電体層3および絶縁体構造物5を切断した断面についておこなっている。図2および図3に例示する本実施形態の絶縁体構造物5の一例では、上述のとおりLminが40μmであり、誘電体層3の膜厚が1μmであるため、誘電体層3の膜厚とLminとの比率は40倍となる。本発明の実施による薄膜キャパシタの絶縁耐圧低下を、より効果的に抑制できる範囲である。特に特徴的な点として、絶縁体構造物5が、(1)欠陥6を完全に覆うように形成された膜厚の均一な薄層であること、(2)パッチ形状端部においてなだらかなテーパー断面角度を有すること、がわかる。特に(2)については、誘電体層表面に対して約5度程度のテーパー断面角度となっている。 The structure of the insulator structure 5 in the present embodiment is an insulator patch-like structure with the defect of the dielectric layer 3 approximately at the center. The shape of a typical insulator structure 5 according to this embodiment is shown in FIGS. FIG. 2 is an image observed by an optical microscope when the insulator structure 5 of the present embodiment is viewed from above. The dielectric layer 3 has a defect 6 formed by peeling off after the impurity particles are adhered, and the insulator structure 5 is formed in a substantially circular patch shape with the defect 6 positioned substantially at the center. Is formed on top. L min formed by the end of the defect 6 and the outermost part of the insulator structure 5 can be read from a planar observation photograph as shown in FIG. The insulator structure 5 of this embodiment is 40 μm as shown by the arrow in FIG. When the defect 6 has an irregular shape, for example, a scratch extending over a relatively long distance, it may be formed as an elliptical or curved patch shape according to the shape of the defect. In this case, L min can be defined by reading the shortest distance between the end of the defect 6 and the outermost part of the insulator structure 5. The position to be read can be determined empirically as the position where the electric charge flows most easily from the insulator structure 5 toward the defect 6. FIG. 3 is a cross-sectional observation image of the insulator structure 5 of the present embodiment using an SEM (scanning electron microscope). The cross-section observation is performed on a cross section obtained by cutting the lower electrode 2, the dielectric layer 3, and the insulator structure 5 around the defect 6. In the example of the insulator structure 5 of this embodiment illustrated in FIG. 2 and FIG. 3, L min is 40 μm and the film thickness of the dielectric layer 3 is 1 μm as described above. The ratio of thickness to L min is 40 times. This is a range in which the reduction in dielectric strength of the thin film capacitor according to the implementation of the present invention can be more effectively suppressed. In particular, the insulator structure 5 is (1) a thin thin film having a uniform film thickness so as to completely cover the defect 6, and (2) a gentle taper at the patch-shaped end. It can be seen that it has a cross-sectional angle. In particular, (2) has a taper cross-sectional angle of about 5 degrees with respect to the surface of the dielectric layer.

本実施形態における絶縁体構造物5に見られる上記(1)と(2)とのごとき独特の形状は、純水を溶媒とし、上記の樹脂材料のモノマーを分散させて実施する電気泳動法により、誘電体層3の表面に樹脂材料を電着して形成することができる。ただし、本実施形態の電気泳動法は、従来の樹脂材料の電着形成とは異なる装置の構造であり、形成条件である。図4に、本発明の実施形態に係る電着装置の概略図を示す。具体的には、(A)電気泳動法に用いるアノード電極8を、電極本体であるSUS系材料表面に、アルミナやシリカあるいは酸化鉄等の酸化物からなる不動体被膜を形成した構造とすること、(B)電着溶液中の樹脂材料含有量を、0.1wt%以上1.0wt%以下の低濃度とする製造条件を用いること、である。 The unique shapes such as (1) and (2) seen in the insulator structure 5 in the present embodiment are obtained by electrophoresis using pure water as a solvent and dispersing the monomer of the resin material. The resin material can be formed by electrodeposition on the surface of the dielectric layer 3. However, the electrophoresis method of the present embodiment is a structure of an apparatus different from the conventional electrodeposition formation of a resin material, and is a forming condition. FIG. 4 shows a schematic diagram of an electrodeposition apparatus according to an embodiment of the present invention. Specifically, (A) the anode electrode 8 used in the electrophoresis method has a structure in which an immobile film made of oxide such as alumina, silica, or iron oxide is formed on the surface of a SUS material that is an electrode body. And (B) using a production condition for setting the resin material content in the electrodeposition solution to a low concentration of 0.1 wt% or more and 1.0 wt% or less.

上記の要件(A)と(B)とを組み合わせた電着泳動法によって、本実施形態における絶縁体構造物5の形状が得られる原因は必ずしも明らかではない。本発明者らは、研究を通じて以下のようにメカニズムを推測している。 The reason why the shape of the insulator structure 5 in the present embodiment is obtained by the electrodeposition electrophoresis method combining the above requirements (A) and (B) is not necessarily clear. The present inventors presume the mechanism as follows through research.

要件(A)により、電着溶液中の樹脂材料モノマーからの電子引き抜き反応が抑制され、極性モノマーの割合が低下する。極性モノマーは誘電体層3の電界が最大である欠陥6に集まろうとする。他の非極性モノマーは、極性モノマーに引きずられるように誘電体層3の表面に移動するが、欠陥6に吸引されるほどの電気的ポテンシャルを有するわけではないため、欠陥6に到達する前に誘電体層3上に吸着される。非極性モノマーの運動エネルギーは、電着溶液中の集団としてはある分布を持っている。そのため、絶縁体構造物5の形状は、非極性モノマーの運動エネルギー分布に応じた、面方向と厚み方向との広がりをもつ。この結果、本実施形態の絶縁体構造物5は、誘電体層3において、欠陥6を略中心に配して端部がテーパー形状となった略円形のパッチ状形状を呈する。 By the requirement (A), the electron extraction reaction from the resin material monomer in the electrodeposition solution is suppressed, and the ratio of the polar monomer is reduced. The polar monomer tends to collect in the defect 6 where the electric field of the dielectric layer 3 is maximum. Other non-polar monomers move to the surface of the dielectric layer 3 to be dragged by the polar monomers, but do not have an electrical potential to be attracted to the defect 6, so that before reaching the defect 6 Adsorbed on the dielectric layer 3. The kinetic energy of the nonpolar monomer has a certain distribution as a group in the electrodeposition solution. Therefore, the shape of the insulator structure 5 has a spread in the plane direction and the thickness direction according to the kinetic energy distribution of the nonpolar monomer. As a result, the insulator structure 5 of the present embodiment has a substantially circular patch-like shape in which the defect 6 is arranged at the approximate center and the end is tapered in the dielectric layer 3.

なお、絶縁体構造物5のテーパー断面角度は電流の強弱によっても変化する。高電流ではテーパー断面角度が大きくなり、低電流ではテーパー断面角度が小さくなる傾向がある。この結果は、極性モノマーが欠陥6に吸引されるポテンシャルが増減することによって非極性モノマーが到達できる誘電体層3の面積も変化するためと考えられる。本実施形態では、樹脂材料の電気泳動法として低い電流(1〜50mA)で電着を実施している。 Note that the taper cross-sectional angle of the insulator structure 5 also changes depending on the strength of the current. The taper cross-sectional angle tends to increase at high currents, and the taper cross-sectional angle tends to decrease at low currents. This result is considered to be because the area of the dielectric layer 3 that the nonpolar monomer can reach changes as the potential at which the polar monomer is attracted to the defect 6 increases or decreases. In this embodiment, electrodeposition is performed with a low current (1 to 50 mA) as an electrophoretic method of the resin material.

要件(B)により、電着溶液中の過剰なモノマー会合が抑制される。本実施形態における電気泳動法は、純水の溶媒中に樹脂材料のモノマーを分散させておこなう。この場合、モノマーの濃度が高ければ溶媒中でモノマー同士の会合が起こり、モノマーが集合体として誘電体層3の表面に運ばれる場合がある。集合体としてのモノマーには極性モノマーが含まれうるため、多くのモノマーが欠陥6の付近に堆積する可能性がある。電着溶液中の樹脂材料含有量を、0.1wt%以上1.0wt%以下の低濃度とすることにより、溶媒中でのモノマーの会合確率が低下するため、モノマーが集合体でなく単体で誘電体層3の表面に移動する確率が高くなる。この結果、絶縁体構造物5の形状は、モノマーの運動エネルギー分布のみに応じた、面方向と厚み方向との広がりをもち、欠陥6を略中心に配して最外部がテーパー形状となった略円形のパッチ状形状を呈する。 The requirement (B) suppresses excessive monomer association in the electrodeposition solution. The electrophoresis method in the present embodiment is performed by dispersing a monomer of a resin material in a solvent of pure water. In this case, if the concentration of the monomer is high, association between the monomers occurs in the solvent, and the monomer may be carried to the surface of the dielectric layer 3 as an aggregate. Since the monomer as an aggregate may include a polar monomer, a large amount of monomer may be deposited in the vicinity of the defect 6. By reducing the resin material content in the electrodeposition solution to a low concentration of 0.1 wt% or more and 1.0 wt% or less, the association probability of the monomer in the solvent is lowered, so that the monomer is not an aggregate but a single substance. The probability of moving to the surface of the dielectric layer 3 is increased. As a result, the shape of the insulator structure 5 has a spread in the surface direction and the thickness direction according to only the kinetic energy distribution of the monomer, and the outermost portion has a tapered shape with the defect 6 disposed substantially at the center. Presents a substantially circular patch shape.

なお、上記のように電着溶液中の樹脂材料含有量を調整するほか、電着溶液中に適量の分散剤を添加してもよい。このような分散剤には、公知の界面活性剤を適宜用いることができる。特に、界面活性剤であるアルキルグルコシドやポリエチレングリコール、脂肪酸ナトリウムなどを用いることができる。あるいは、超音波撹拌によって樹脂材料のモノマーを分散させてもよい。 In addition to adjusting the resin material content in the electrodeposition solution as described above, an appropriate amount of a dispersant may be added to the electrodeposition solution. As such a dispersant, a known surfactant can be appropriately used. In particular, surfactants such as alkyl glucoside, polyethylene glycol, and fatty acid sodium can be used. Alternatively, the monomer of the resin material may be dispersed by ultrasonic stirring.

本実施形態の薄膜キャパシタ1では、絶縁体構造物5を形成した後に上部電極4を形成する。本実施形態の上部電極4の材料は、公知の導電性材料を適宜選択することができる。公知の導電性材料とは、たとえば、金属、金属酸化物、導電性有機材料などをいい、これらを適宜選択することができる。特に、上部電極4は低電気抵抗であること、機械的強度が高いことが好ましい。そのため、金属を用いることが好ましい。中でもNiやCuは電気抵抗の低い比較的強靭な金属材料であるため好ましい。上部電極4は、Ni電極層あるいはCu電極層の単層からなっていてもよいが、Ni電極層とCu電極層の二層構造であってもよい。上部電極4と誘電体層3あるいは絶縁体構造物5との間には、異なる導電性材料を介在させてもよい。上部電極4にNi電極層を含む場合は、信頼性の見地から、Ni電極層側が誘電体層3に接触していることが望ましい。上部電極4の全部または一部にNi電極層を用いる場合、下部電極層1と同様に純NiもしくはNi系の合金を用いることができる。Ni系の合金である場合、例えばPt、Pd、Ir、Ru、Rhなどの貴金属元素を含むことが望ましく、その含有量は50wt%以下が望ましい。さらにその厚みは、0.1μm以上2.0μm以下が好ましい範囲である。 In the thin film capacitor 1 of the present embodiment, the upper electrode 4 is formed after the insulator structure 5 is formed. As a material of the upper electrode 4 of the present embodiment, a known conductive material can be appropriately selected. A well-known electroconductive material means a metal, a metal oxide, a conductive organic material etc., for example, These can be selected suitably. In particular, it is preferable that the upper electrode 4 has a low electrical resistance and a high mechanical strength. Therefore, it is preferable to use a metal. Among these, Ni and Cu are preferable because they are relatively tough metal materials having low electric resistance. The upper electrode 4 may be a single layer of a Ni electrode layer or a Cu electrode layer, but may have a two-layer structure of a Ni electrode layer and a Cu electrode layer. Different conductive materials may be interposed between the upper electrode 4 and the dielectric layer 3 or the insulator structure 5. When the upper electrode 4 includes an Ni electrode layer, it is desirable that the Ni electrode layer side is in contact with the dielectric layer 3 from the viewpoint of reliability. When a Ni electrode layer is used for all or part of the upper electrode 4, pure Ni or a Ni-based alloy can be used as in the lower electrode layer 1. In the case of a Ni-based alloy, it is desirable to contain a noble metal element such as Pt, Pd, Ir, Ru, Rh, and the content is desirably 50 wt% or less. Further, the thickness is preferably in the range of 0.1 μm to 2.0 μm.

本実施形態のNi電極層の上には、Cu電極層が形成されていてもよい。ここでいうCu電極層は純Cu(Cu99.9%以上)、もしくはCu系の合金が好ましい。合金の場合、例えばPt、Pd、Ir、Ru、Rhなどの貴金属元素を含むことが望ましく、その含有量は50wt%以下が望ましい。CuはAuやAgと抵抗率が同等で、工業的に使用し易い特徴がある。そのため電子機器の配線に多く使用されている。またその抵抗率が比較的小さいため、薄膜キャパシタの電極層として使用する場合、等価直列抵抗(ESR)を減少させるといった効果がある。 A Cu electrode layer may be formed on the Ni electrode layer of the present embodiment. The Cu electrode layer here is preferably pure Cu (Cu 99.9% or more) or a Cu-based alloy. In the case of an alloy, it is desirable to include a noble metal element such as Pt, Pd, Ir, Ru, and Rh, and the content is desirably 50 wt% or less. Cu has the same resistivity as Au and Ag, and is characterized by being easy to use industrially. Therefore, it is often used for wiring of electronic equipment. Further, since the resistivity is relatively small, when used as an electrode layer of a thin film capacitor, there is an effect of reducing the equivalent series resistance (ESR).

上部電極4の形成にあたっては、薄膜形成で通常使用される方法、例えば溶液の塗布、スパッタリング、蒸着、PLD(Pulse Laser Deposition)、CVDなど適宜用いることができる。 In forming the upper electrode 4, a method usually used in thin film formation, for example, application of a solution, sputtering, vapor deposition, PLD (Pulse Laser Deposition), CVD, or the like can be used as appropriate.

以上、本発明の好適な実施形態を説明したが、本発明は上述の実施形態に限定されるものではない。 The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments.

以下、実施例を挙げて本発明について具体的に説明する。ただし、本発明は以下の実施例に限定されるものではない。 Hereinafter, the present invention will be specifically described with reference to examples. However, the present invention is not limited to the following examples.

(実施例1)
100mm×100mmの大きさのNi金属箔上に誘電体層(BaTiO系誘電体)をスパッタリング法により800nmの厚みで成膜した。その後アニールし、Ni金属箔上の誘電体層を結晶化させた。絶縁物構造体を形成する前処理として、スクラブ洗浄により、異物などを除去した。
Example 1
A dielectric layer (BaTiO 3 dielectric) was formed to a thickness of 800 nm on a Ni metal foil having a size of 100 mm × 100 mm by a sputtering method. Thereafter, annealing was performed to crystallize the dielectric layer on the Ni metal foil. As a pretreatment for forming the insulator structure, foreign matters and the like were removed by scrub cleaning.

結晶化した誘電体層を備えたNi金属箔を、アノード電極としてSUS系材料にアルミナ不動体被膜を形成した電極を備え、電解液として純水にイミド系樹脂を1wt%含有した電解液を供えた電着槽に浸漬した。Ni箔を電着液に浸漬した状態で、電着の状況を目視観察しながら電流35mAで電圧を適宜制御しながら電着を実施し、200℃のオーブンでキュアさせて絶縁体構造物を形成した。ここまでの試料から複数の絶縁体構造物の部分を分取し、外観を光学顕微鏡で、断面を電子顕微鏡でそれぞれ観察したところ、絶縁体構造物の形状は、最大膜厚が1.2μm、テーパー断面角度が18度、絶縁体構造物の最外部から欠陥の端部までの最短距離が36μm(誘電体厚みの約30倍)であった。その後、上部電極層としてNiとCuとを、この順でそれぞれスパッタリング法により成膜した。 A Ni metal foil having a crystallized dielectric layer is provided as an anode electrode, an electrode in which an alumina non-moving body coating is formed on a SUS material, and an electrolytic solution containing 1 wt% of an imide resin in pure water is provided as an electrolytic solution. It was immersed in an electrodeposition bath. With the Ni foil immersed in the electrodeposition solution, electrodeposition is performed while the voltage is appropriately controlled at a current of 35 mA while visually observing the electrodeposition, and cured in an oven at 200 ° C. to form an insulator structure. did. A portion of a plurality of insulator structures was separated from the sample so far, and the appearance was observed with an optical microscope and the cross section was observed with an electron microscope. The shape of the insulator structure had a maximum film thickness of 1.2 μm, The taper section angle was 18 degrees, and the shortest distance from the outermost part of the insulator structure to the edge of the defect was 36 μm (about 30 times the dielectric thickness). Thereafter, Ni and Cu were formed as an upper electrode layer in this order by sputtering.

上部電極層形成後、上部電極層のパターニングを行い、340℃の真空中でアニールを行った。このアニールは、Cu電極層の粒子成長のために行った。パターニングを実施した5mm×5mmのキャパシタ素子100個について、以下に示す容量値、絶縁抵抗値の測定を行った。 After the formation of the upper electrode layer, the upper electrode layer was patterned and annealed in a vacuum at 340 ° C. This annealing was performed for grain growth of the Cu electrode layer. With respect to 100 capacitor elements of 5 mm × 5 mm subjected to patterning, the following capacitance values and insulation resistance values were measured.

容量値はAgilent社製LCRメーター4284Aを使用し、1kHz、1Vrms、室温(25℃)にて測定を行った。絶縁抵抗値はAgilent社製4339B高抵抗計を使用し、DC4V、室温(25℃)での測定を行った。 The capacitance value was measured using an Agilent LCR meter 4284A at 1 kHz, 1 Vrms, and room temperature (25 ° C.). The insulation resistance value was measured at 4 V DC and room temperature (25 ° C.) using an Agilent 4339B high resistance meter.

その結果、測定点の90%(90/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。 As a result, a non-defective product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained at 90% (90/100 pcs) of the measurement points.

(実施例2)
ポリイミド濃度0.8%、電流30mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が42μm(誘電体厚みの35倍)、テーパー断面角度は15度であり、測定点の93%(93/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 2)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.8% and a current of 30 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 42 μm (35 times the dielectric thickness), the taper cross-sectional angle is 15 degrees, and the measurement point is 93% (93/100 pcs). A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例3)
ポリイミド濃度0.6%、電流25mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が48μm(誘電体厚みの40倍)、テーパー断面角度は10度であり、測定点の98%(98/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 3)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.6% and a current of 25 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 48 μm (40 times the dielectric thickness), the taper section angle is 10 degrees, and 98% (98/100 pcs) of the measurement point. A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例4)
ポリイミド濃度0.5%、電流20mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が60μm(誘電体厚みの50倍)、テーパー断面角度は8度であり、測定点の100%(100/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
Example 4
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.5% and a current of 20 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 60 μm (50 times the dielectric thickness), the taper section angle is 8 degrees, and 100% of the measurement point (100/100 pcs). A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例5)
ポリイミド濃度0.4%、電流15mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が84μm(誘電体厚みの70倍)、テーパー断面角度は5度であり、測定点の99%(99/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 5)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.4% and a current of 15 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 84 μm (70 times the dielectric thickness), the taper cross-sectional angle is 5 degrees, and 99% (99/100 pcs) of the measurement point. A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例6)
ポリイミド濃度0.3%、電流10mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が108μm(誘電体厚みの90倍)、テーパー断面角度は3度であり、測定点の97%(97/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 6)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.3% and a current of 10 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 108 μm (90 times the dielectric thickness), the taper section angle is 3 degrees, and 97% (97/100 pcs) of the measurement point. A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例7)
ポリイミド濃度0.2%、電流5mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が120μm(誘電体厚みの100倍)、テーパー断面角度は1度であり、測定点の94%(94/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 7)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.2% and a current of 5 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 120 μm (100 times the dielectric thickness), the taper cross section angle is 1 degree, and 94% (94/100 pcs) of the measurement point. A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例8)
ポリイミド濃度0.1%、電流2mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が144μm(誘電体厚みの120倍)、テーパー断面角度は0.5度であり、測定点の91%(91/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 8)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.1% and a current of 2 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect was 144 μm (120 times the dielectric thickness), the taper cross-sectional angle was 0.5 degrees, and 91% of measurement points (91/100 pcs) ), A non-defective product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例9)
ポリイミド濃度3%、電流50mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が24μm(誘電体厚みの20倍)、テーパー断面角度は23度であり、測定点の75%(75/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
Example 9
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 3% and a current of 50 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 24 μm (20 times the dielectric thickness), the taper cross-sectional angle is 23 degrees, and 75% (75/100 pcs) of the measurement point. A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例10)
ポリイミド濃度2%、電流40mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が30μm(誘電体厚みの25倍)、テーパー断面角度は21度であり、測定点の85%(85/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 10)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 2% and a current of 40 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 30 μm (25 times the dielectric thickness), the taper cross-sectional angle is 21 degrees, and 85% (85/100 pcs) of the measurement point. A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例11)
ポリイミド濃度0.08%、電流1mAで電着した以外は実施例1と同様に作製、測定を実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が276μm(誘電体厚みの130倍)、テーパー断面角度は0.4度であり、測定点の83%(83/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 11)
Fabrication and measurement were performed in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.08% and a current of 1 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect was 276 μm (130 times the dielectric thickness), the taper cross-sectional angle was 0.4 degrees, and 83% (83/100 pcs) of the measurement point ), A non-defective product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(実施例12)
ポリイミド濃度0.06%、電流0.5mAで電着した以外は実施例1と同様に作製、実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が180μm(誘電体厚みの150倍)、テーパー断面角度は0.3度であり、測定点の77%(77/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。
(Example 12)
It was produced and carried out in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.06% and a current of 0.5 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 180 μm (150 times the dielectric thickness), the taper cross-sectional angle is 0.3 degree, and 77% (77/100 pcs) of the measurement point. ), A non-defective product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained.

(比較例1)
ポリイミド濃度10%、電流80mAで電着した以外は実施例1と同様に作製、実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が12μm(誘電体厚みの10倍)、テーパー断面角度は28度であり、測定点の3%(3/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。これは、平面方向から電荷が誘電体層の欠陥に流れてしまったことが原因と考えられる。
(Comparative Example 1)
It was produced and carried out in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 10% and a current of 80 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 12 μm (10 times the dielectric thickness), the taper section angle is 28 degrees, and 3% (3/100 pcs) of the measurement point. A good product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained. This is considered to be caused by charges flowing from the planar direction to defects in the dielectric layer.

(比較例2)
ポリイミド濃度0.8%、電流0.3mAで電着した以外は実施例1と同様に作製、実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が240μm(誘電体厚みの200倍)、テーパー断面角度は0.3度であり、測定点の5%(5/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。これは、絶縁体構造物が大き過ぎたため、電荷が相対的に抵抗の低い誘電体層の欠陥に流れてしまったことが原因と考えられる。
(Comparative Example 2)
It was produced and carried out in the same manner as in Example 1 except that electrodeposition was performed at a polyimide concentration of 0.8% and a current of 0.3 mA. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 240 μm (200 times the dielectric thickness), the taper cross-sectional angle is 0.3 degrees, and 5% of the measurement point (5/100 pcs) ), A non-defective product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained. This is probably because the insulator structure was too large, and the charge flowed to defects in the dielectric layer having a relatively low resistance.

(比較例3)
表面(誘電体層の方向を向いた面)に不導体皮膜を形成しないアノード電極を用いた以外は実施例1と同様に作製、実施した。その結果、絶縁体構造物の最外部から欠陥の端部までの最短距離が6μm(誘電体厚みの約5倍)、テーパー断面角度は43度であり、測定点の1%(1/100pcs)で、容量値2.5×10−7F以上、絶縁抵抗値5×10+8Ω以上の良品が得られた。これは、テーパー断面角度が急だったため、絶縁体構造物の最外部を起点として、電荷が誘電体層の欠陥に流れてしまったことが原因と考えられる。
(Comparative Example 3)
It was produced and carried out in the same manner as in Example 1 except that an anode electrode that did not form a nonconductive film on the surface (the surface facing the direction of the dielectric layer) was used. As a result, the shortest distance from the outermost part of the insulator structure to the edge of the defect is 6 μm (about 5 times the dielectric thickness), the taper cross-sectional angle is 43 degrees, and 1% of measurement points (1/100 pcs) Thus, a non-defective product having a capacitance value of 2.5 × 10 −7 F or more and an insulation resistance value of 5 × 10 +8 Ω or more was obtained. This is probably because the taper cross-sectional angle was steep and the charge flowed into the dielectric layer defect starting from the outermost part of the insulator structure.

以上説明した一連の実施例と比較例とを表1にまとめる。 Table 1 summarizes the series of examples and comparative examples described above.

本発明者らは、実施例と比較例とを通じ、本発明の実施により得られる薄膜キャパシタは、良好な耐圧性能を有していることを確認した。 The inventors of the present invention have confirmed through the examples and comparative examples that the thin film capacitor obtained by the implementation of the present invention has a good withstand voltage performance.

1 薄膜コンデンサ
2 下部電極
3 誘電体層
4 上部電極
5 絶縁体構造物
6 誘電体層の欠陥
7 電着装置
8 アノード電極
9 カソード電極
10 電着用試料(下部電極2および誘電体層3を設けた被成膜体)
11 電着槽
DESCRIPTION OF SYMBOLS 1 Thin film capacitor 2 Lower electrode 3 Dielectric layer 4 Upper electrode 5 Insulator structure 6 Defect of dielectric layer 7 Electrodeposition apparatus 8 Anode electrode 9 Cathode electrode 10 Electrodeposition sample (lower electrode 2 and dielectric layer 3 were provided (Deposition body)
11 Electrodeposition tank

Claims (2)

下部電極と、前記下部電極上に設けられた誘電体層と、前記誘電体層上に形成された上部電極とを備え、
前記誘電体層は欠陥を含み、
前記誘電体層と前記上部電極層との界面には絶縁体構造物が形成されており、
前記絶縁体構造物は、前記欠陥を前記上部電極に対して露出しないよう内包し、
前記絶縁体構造物の断面構造は、(1)絶縁体構造物の端部であってかつ絶縁体構造物の最大高さの50%の位置に接する接線と、(2)誘電体層と上部電極との界面である線と、が成す角度が1度以上25度よりも小であるテーパー断面角度を有しており、
前記欠陥端部から絶縁体構造物の最外部までの距離は、誘電体膜の厚みの20倍以上150倍以下である
ことを特徴とする薄膜キャパシタ。
A lower electrode, a dielectric layer provided on the lower electrode, and an upper electrode formed on the dielectric layer,
The dielectric layer includes defects;
An insulator structure is formed at the interface between the dielectric layer and the upper electrode layer,
The insulator structure includes the defect so as not to be exposed to the upper electrode,
The cross-sectional structure of the insulator structure is as follows: (1) a tangent line at the end of the insulator structure and in contact with 50% of the maximum height of the insulator structure; and (2) a dielectric layer and an upper portion. The angle formed by the line that is the interface with the electrode has a taper cross-sectional angle that is 1 degree or more and less than 25 degrees;
The distance from the defect end to the outermost part of the insulator structure is 20 to 150 times the thickness of the dielectric film.
前記テーパー断面角度は1度以上10度以下であることを特徴とする請求項1に記載の薄膜キャパシタ。 2. The thin film capacitor according to claim 1, wherein the taper cross-sectional angle is not less than 1 degree and not more than 10 degrees.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016025099A (en) * 2014-07-16 2016-02-08 Tdk株式会社 Thin film capacitor
JP2017076717A (en) * 2015-10-15 2017-04-20 Tdk株式会社 Electronic device sheet

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004040604A1 (en) * 2002-10-30 2004-05-13 Mitsui Mining & Smelting Co.,Ltd. Copper foil with dielectric layer for formation of capacitor layer, copper-clad laminate for formation of capacitor layer using such copper foil with dielectric layer, and method for producing such copper foil with dielectric layer for formation of capacitor layer
JP2007189199A (en) * 2005-12-12 2007-07-26 Tdk Corp Capacitor and method of manufacturing same
JP2008160040A (en) * 2006-12-26 2008-07-10 Tdk Corp Manufacturing method of capacitor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004040604A1 (en) * 2002-10-30 2004-05-13 Mitsui Mining & Smelting Co.,Ltd. Copper foil with dielectric layer for formation of capacitor layer, copper-clad laminate for formation of capacitor layer using such copper foil with dielectric layer, and method for producing such copper foil with dielectric layer for formation of capacitor layer
US20060057420A1 (en) * 2002-10-30 2006-03-16 Toshiko Yokota Copper foil provided with dielectric layer for forming capacitor layer, copper clad laminate for formation of capacitor layer using such such copper foil with dielectric layer, and method for producing such copper foil with dielectric layer for formation of capacitor layer
JP2007189199A (en) * 2005-12-12 2007-07-26 Tdk Corp Capacitor and method of manufacturing same
JP2008160040A (en) * 2006-12-26 2008-07-10 Tdk Corp Manufacturing method of capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016025099A (en) * 2014-07-16 2016-02-08 Tdk株式会社 Thin film capacitor
JP2017076717A (en) * 2015-10-15 2017-04-20 Tdk株式会社 Electronic device sheet

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