JP2015121945A - Cache device, computer with cache device, and cache control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times snoop is performed with respect to a memory exclusively used by one processor for a predetermined period of time in a multiprocessor system.SOLUTION: Cache devices are provided in correspondence with the processors in a computer which comprises: a memory unit including shared pages divided into pages with blocks and shared by a plural processors and exclusive pages exclusively used by one processor for a predetermined period of time; and a plurality of processors. The cache devices comprise management means and cache arrays, the management means 1) receiving from its corresponding processor an address of an area in the exclusive pages, sending a snoop request for a page including the area to other devices, and storing the address of the block including the area and the latest data in a cache array of the own device, and 2) receiving a snoop request for a page from other devices, and deleting all the blocks contained in the specified page from the cache array of the own device.

Description

  The present invention relates to a cache device, a computer including the cache device, and a cache control method, and more particularly to a cache device that maintains cache coherency, a computer including the cache device, and a cache control method.

  A multiprocessor device having a cache memory corresponding to a processor needs to maintain coherency between cache memories. Techniques for this purpose include the following.

  Patent Document 1 discloses a fine-grained snoop filter that manages information representing a processor having a copy of memory data in a cache unit, and a data copy of the division unit is cached in the processor for each division unit larger than the cache unit. A computer system comprising a coarse-grained snoop filter indicating that This computer system uses both filters to reduce the number of snoops issued to processors other than the processor holding the memory copy.

  Patent Document 2 discloses a multiprocessor device that controls coherency in a directory system. This apparatus registers a data sharing state in a directory in units of sublines obtained by dividing a cache line, and invalidates the cache memory in units of cache lines or sublines according to the state. This apparatus thereby reduces the number of invalidation processes.

  Patent Document 3 discloses a system that maintains cache coherency for an accelerator that does not access the same data as a CPU (Central Processing Unit).

  Patent Document 4 discloses a multiprocessor system that uses a compressed directory to maintain cache coherency. This system thereby reduces directory requirements.

  Patent Document 5 discloses a disk cache control method for the purpose of suppressing the number of write backs even if dirty data is discontinuously present in a page.

  Patent Document 6 discloses a computer having shared memory management means and dedicated memory management means.

JP 2008-3 ADDRESS CONVERTER 10414 Japanese Patent No. 3875749 JP 20 Memory Control Unit 12181860 JP-A-8-263374 JP 2006-163474 A JP 2009-087189 A

  In the technique of Patent Document 1, it is necessary to snoop for each cache unit (cache line), and the number of snoops is large, resulting in performance degradation. The present invention aims to solve this problem. None of the techniques of Patent Documents 2 to 6 are related to the control of the number of snoops.

A cache device according to an embodiment of the present invention is divided into pages including a plurality of blocks, a storage device including a shared page shared by a plurality of processors and an exclusive page occupied by any processor for a certain period of time, A cache device provided in correspondence with a processor in a computer comprising the plurality of processors,
1) The address of the area in the exclusive page is received from the corresponding processor, the snoop request for the page including the area is transmitted to another apparatus, and the address of the block including the area and the latest data are stored in the cache array of the own apparatus. 2) management means for receiving a page snoop request from another device and deleting all blocks included in the specified page from the cache array of the own device, and the cache array.

A cache control method according to an embodiment of the present invention includes a storage device that is divided into pages including a plurality of blocks and includes a shared page shared by a plurality of processors and an exclusive page occupied by any processor for a certain period of time. In a cache device provided in correspondence with a processor in a computer comprising the plurality of processors,
1) The address of the area in the exclusive page is received from the corresponding processor, the snoop request for the page including the area is transmitted to another apparatus, and the address of the block including the area and the latest data are stored in the cache array of the own apparatus. 2) When a page snoop request is received from another device, all blocks included in the designated page are deleted from the cache array of the own device.

  According to the present invention, in a multiprocessor system, the number of snoops can be reduced for a memory occupied by a certain processor for a certain period.

FIG. 1 is a diagram illustrating an example of a shared memory space and an exclusive memory space used by a process. FIG. 2 shows the relationship between the memory space and the address. FIG. 3 is a configuration diagram of the computer 506 on which the cache device 100 according to the first embodiment is mounted. FIG. 4 is a configuration diagram of the inside of the cache device 100 and its periphery. FIG. 5 is a diagram illustrating data stored in the page table entry of the computer 506. FIG. 6 is a diagram illustrating an example of an access operation of the storage device 505 by the processor 122. FIG. 7 is a diagram illustrating a determination table related to the snoop operation performed by the management unit 120. FIG. 8 is a configuration diagram of the cache device 100 according to the second embodiment.

<First Embodiment>
Before describing the configuration and operation of the cache device 100 of the present embodiment, a basic concept regarding the present embodiment will be described.

  In an information processing apparatus having a multiprocessor configuration, there are two types of memory space accessed by each processor (a process operating on the processor). One is a shared memory space that may be accessed by a plurality of processors simultaneously, and the other is an exclusive memory space that is accessed exclusively by a single processor for a certain period of time.

  The shared memory space is a space used for control between a plurality of processors. For example, the shared memory space is a space for executing processing for managing the execution order of processes executed by each processor, the access order of memories, shared resources, and the like. The shared memory space is required to have a latency higher than the access bandwidth in terms of performance.

  The exclusive memory space is a space that is guaranteed to be used exclusively for a certain period, and only a single processor (process) is accessed at the same time during the period. The exclusive memory space requires an access bandwidth in terms of performance.

  Here, the certain period means, for example, while a child process exists, while a child process occupies a certain processor, or while a child process is executed only on a processor with which the child process is executed. The term “while the child process occupies a certain processor” means, for example, that the child process is being executed without interruption.

  FIG. 1 is a diagram illustrating an example of a shared memory space and an exclusive memory space used by a process. The shared memory space is shared by the parent (upper) process and the child (lower) process, and the exclusive memory space is used by the child (lower) process.

  The parent process manages shared resources, manages the creation and completion of child processes, and provides a memory space that can be accessed by multiple processors and processes. Each child process is assigned an individual memory space, and further assigned to an individual processor for a certain period. An OS (Operating System) that controls processes avoids mutual interference between child processes by assigning individual processors and memory spaces to the child processes. Furthermore, the OS thereby maximizes the processing performance of the child process, as well as the performance and scalability efficiency of the multiprocessor system.

  A system having a cache manages a cache state for a memory for each data management size (eg, 128 bytes) of the cache. When a certain processor (process) accesses the memory, the cache monitors (snoops) the state of the cache (including the hierarchical cache) on the other processor and performs an operation of maintaining the coherency of the cache. In order to maintain this coherency, the system has sufficient bandwidth for snoops so as not to hinder the throughput of memory access and achieves a short latency. The implementation of the coherency function, the implementation of an interface between LSI (Large Scale Integration), and the implementation of a high-speed operation interface require a technology cost in terms of LSI circuit scale, physical pin number investment, power consumption associated with high-speed operation, etc. An increase is incurred.

  In order to cope with this problem, the cache device 100 according to the present embodiment separately manages the shared memory space and the exclusive memory space. FIG. 2 shows the relationship between the memory space and the address in order to explain this management difference.

  The cache device 100 according to the present embodiment manages the shared memory space in units of cache blocks. For example, the block size is 128 bytes, and the memory space size is 1 terabyte (address length is 40 bits). In this case, the cache device 100 sets the address used for snoop as a 33-bit block address (FIG. 2A) and the snoop execution unit as a block. The number of snoops required for continuous access to a 256 megabyte space is approximately 2 million.

  On the other hand, the cache device 100 manages the exclusive memory space in page units including a predetermined number of cache block units. For example, when the page size is 16 megabytes and the memory space size is 1 terabyte, the cache device 100 sets the address used for snoop as a 16-bit page address (FIG. 2B) and the snoop execution unit as a page. To do. The number of snoops required for continuous access to the 256 megabyte space is 16.

  The cache device 100 of the present embodiment has the following features.

  First, the cache device 100 distinguishes between the shared memory space and the exclusive memory space. This distinction is made, for example, on a page basis. The page table entry stores a flag for this distinction. This flag can be specified by software (application and OS). The cache device 100 distinguishes the type of space every memory access. The cache device 100 makes the address management size of snoop tags, directory tags, etc. necessary for cache coherency control variable, and increases the management size in the case of exclusive memory space. The management size is, for example, a block size (128 bytes) for the shared memory space and a page size (16 megabytes) for the exclusive memory space.

  Further, the cache device 100 also supports control requests with a large management size, such as cache invalidation processing and eviction processing. That is, the cache device 100 handles the management size of the cache body (data management) and the snoop / tag separately, and executes invalidation and eviction of a plurality of blocks with one control request.

  In addition, the cache device 100 is provided with a function for notifying and ensuring the completion of the processing associated with the cache invalidation described above. That is, the cache device 100 has a completion guarantee function in order to maintain coherency and access ordering (order).

(Configuration of this embodiment)
Hereinafter, the configuration of the cache device 100 of the present embodiment will be described. FIG. 3 is a configuration diagram of a computer 506 equipped with the cache device 100 of the present embodiment.

  The computer 506 includes a storage device 505 and a plurality of LSIs 501 connected to the storage device 505. The LSI 501 includes a cache device 100, a memory control unit 121, and one or more processors 122. The LSIs 501 are connected to each other via the cache device 100.

  FIG. 4 is a configuration diagram of the inside of the cache device 100 and its periphery. The cache device 100 includes a cache array 117, a page address array 110, and a management unit 120.

  The management unit 120 includes a physical address holding unit 105, a snoop control unit 106, a snoop address holding unit 107, a selector 108, a page address holding unit 109, a page hit / miss determination unit 111, a page control unit 112, a burst control unit 113, a block An address holding unit 114, a selector 115, a block address holding unit 116, a cache hit / miss determination unit 118, and a cache control unit 119 are provided.

  The processor 122 connected to the cache device 100 includes an instruction decoding unit 101, a logical address generation unit 102, an address conversion control unit 103, and an address conversion unit 104. It should be noted that only the components closely related to the cache device 100 are shown here for the processor 122.

  The instruction decoding unit 101 of the processor 122 decodes an instruction to be executed and decodes a necessary operation. The logical address generation unit 102 generates a logical address to be accessed when access to the storage device 505 is required as a result of decoding the instruction by the instruction decoding unit 101. The address translation control unit 103 controls registration, update, and the like for the address translation unit 104. The address conversion unit 104 stores a physical address corresponding to the logical address. The address translation unit 104 is also called a TLB (Translation Look-aside Buffer).

  The physical address holding unit 105 of the cache device 100 holds the physical address generated by the address conversion unit 104, and the snoop address holding unit 107 holds the address included in the snoop request. The selector 108 selects one of the physical address holding unit 105 and the snoop address holding unit 107 and outputs an address and an S / E flag (described later) stored in the selected one. The page address holding unit 109 holds an address for indexing the page address array 110.

  The page address array 110 holds a plurality of page addresses and holds status information of each page. The page address array 110 holds an S / E flag. Although holding the S / E flag is not essential, it can be used for a function for detecting contradiction or error in the page entry table managed by the OS. For example, the page hit / miss determination unit 111 sends a snoop request for S / E flag = 0 (shared memory space) from another cache device 100 to a page registered with the S / E flag = 1 (exclusive memory space). May be notified to the OS as an exception. The page address array 110 operates in cooperation with the cache array 117. When a block is registered in the cache array 117, the page control unit 112 registers the page to which the block belongs in the page address array 110.

  The page hit / miss determination unit 111 determines whether the page address held in the page address holding unit 109 is registered in the page address array 110 (hit / miss). The page control unit 112 controls registration, update, and the like for the page address array 110. Further, the page control unit 112 issues a cache state control instruction for a plurality of blocks belonging to the corresponding page to the burst control unit 113 in accordance with the control of the page address array 110. Further, the page control unit 112 issues an instruction to the snoop control unit (output) 106 according to the state of the page.

  The burst control unit 113 receives a control instruction from the page control unit 112, controls block addresses corresponding to the number of blocks belonging to the page, and performs processing such as expelling the block from the cache array 117. The burst control unit 113 has a function of notifying the page control unit 112 and the snoop control unit (output) 106 that all the control related to the corresponding block is completed.

  The block address holding unit 114 holds the block address generated by the burst control unit 113. The selector 115 selects either the address selected by the selector 108 or the address held by the block address holding unit 114. The block address holding unit 116 holds an address for indexing the cache array 117.

  The cache array 117 is a so-called cache memory, and stores a block address and a copy of the block data in pairs. The cache array 117 includes an address array and a data array. The cache hit / miss determination unit 118 determines whether or not the block address held by the block address holding unit 116 is registered in the cache array 117 (hit / miss).

  The cache control unit 119 controls registration, update, etc. for the cache array 117. Further, the cache control unit 119 notifies the snoop control unit (output) 106 of the snoop result and notifies the page control unit 112 of an access request when access to the memory in the storage device 505 is necessary.

  Note that the snoop control unit (input) 106 accepts a snoop request from another LSI 501 regarding a snoop operation necessary for maintaining coherency between caches. The snoop control unit (output) 106 outputs a snoop request to the other LSI 501. One or both of the snoop control unit (input) 106 and the snoop control unit (output) 106 may be referred to as the snoop control unit 106. The snoop control unit 106 receives from the burst control unit 113 a notification that all the control related to the block has been completed, and notifies (outputs) the completion to the snoop request source LSI 501. The memory control unit 121 performs access control for the storage device 505.

  In the figure, an element to which “S / E” is added receives, stores, or outputs an S / E flag described later.

  FIG. 5 is a diagram illustrating data stored in the page table entry of the computer 506. A page table entry is created and managed by the OS for each logical address.

  The page table entry stores a physical address, an S / E flag, an R / W flag, and a P flag. When the storage device 505 having the corresponding logical address is accessed and the page table entry is referenced, the logical address, physical address, and S / E flag are stored in the address conversion unit 104.

  The P (Present) flag indicates whether a page is loaded in the storage device 505. The R / W (Read / Write) flag indicates whether a page can be read / written.

  The S / E (Share / Exclusion) flag indicates whether the page is a shared memory space or an exclusive memory space. The physical address is the physical address of the page in the storage device 505 assigned to the logical address corresponding to this page entry.

  The page entry may include other information, or some information such as an R / W flag may be absent. For example, the S / E flag may be provided separately for a set of pages, for example, corresponding to a segment. Further, whether the shared memory space or the exclusive memory space can be determined depending on whether the value of the logical address is larger or smaller than the threshold value.

(Operation of this embodiment)
Before describing the operation of the cache device 100 according to the present embodiment, an example of an access operation of the memory in the storage device 505 by the processor 122 used in the description will be described. FIG. 6 is a diagram illustrating an example of an access operation of the storage device 505 by the processor 122.

  In this example, the processor 122 1) sequentially reads the values of the memory space of 8 bytes each continuous from address A (8 bytes × n times), and 2) executes the operation on the read values (8 bytes × 3) Write the operation results in order from address B to the continuous space (bytes x n times). The area accessed by the processor 122 is assumed to access a sufficiently large area for the cache array 117.

  In the above operation 1), the processor 122 executes a read request (8 bytes) at address A to the cache array 117. As a result of indexing the cache array 117, when it is determined that the address A does not exist on the cache array 117 (miss), the cache device 100 performs a read (a) operation on the memory in the storage device 505. Then, the snoop (c) operation to the other cache device 100 is executed. By snooping, it is checked whether or not the memory contents of the storage device 505 are the latest. If the contents are the latest, the contents stored in the memory of the storage device 505 are not the latest. Is the reply data.

  When read (a) reply data to the memory is returned, the cache device 100 registers the data in the cache array 117 of the device itself and returns the data to the processor 122 as well. The coherency control between these cache devices 100 may be a general control method. Usually, the operations (a) and (c) are generally executed in a cache management unit (for example, 128 bytes).

  In the above 2) operation, the processor 122 executes an operation using the data (8 bytes) obtained in the above 1) operation.

  In the above 3) operation, the processor 122 executes a write request (8 bytes) at address B to the cache using the result data (8 bytes) calculated in the above 2) operation as a write date. As an example of the store-through control method, the cache device 100 writes to the storage device 505 when it is determined that the B address does not exist on the cache array 117 as a result of indexing the cache array 117 (miss). The operation (b) is executed, and a snoop (c) operation to another cache device 100 is executed. By snooping the other cache device 100, it is notified that the data on the cache array 117 of the other cache device 100 has been updated, and the data existing on the other cache device 100 is invalidated.

  The coherency control method between these cache devices 100 may be a store-in method. The cache device 100 performs the normal operation (b) in the write request unit (8 bytes) in the case of the store-through method, and in the cache management unit (for example, 128 bytes) in the case of the store-in method. In the case of the store-in method, a read request is issued because it is necessary to bring the target block onto the cache instead of writing (b). This is common in the store-in method and will not be described. The cache device 100 performs the normal operation (c) in cache management units (for example, 128 bytes).

  The above-described operation is a description of one 8-byte operation, but the processor 122 taken as an example executes this operation n times. Therefore, in order to exert such performance of the processor 122, the read (a) performance (mainly bandwidth and access time) for the storage device 505, the write (b) performance (mainly bandwidth), the processor 122 Computing performance and index / registration performance (bandwidth and access time) of the cache device 100 are required. At the same time, the snoop (c) operation necessary for coherency control with other cache devices 100 also requires a corresponding band.

  Hereinafter, the operation of the cache device 100 of the present embodiment will be described. First, the instruction decoding unit 101 in FIG. 4 decodes an instruction to be executed inside the processor 122 and decodes an operation required by the instruction. As a result of decoding the instruction, when it is determined that the storage device 505 needs to be accessed, the logical address generation unit 102 generates a logical address of the memory to be accessed. The address translation control unit 103 indexes the address translation unit 104 with the generated logical address.

  The address translation control unit 103 obtains a physical address corresponding to the logical address by indexing. The association between the logical address and the physical address is generally managed by the OS executed by the computer 506. The OS prepares a page table including a plurality of page table entries as shown in FIG. The address conversion unit 104 holds part or all of the page table. When a part of the address is managed by the address translation unit 104, a physical address corresponding to the logical address may not exist on the address translation unit 104. In that case, the address translation control unit 103 extracts corresponding information from the page table entry group managed by the OS and stores it in the address translation unit 104. If the page table entry group managed by the OS does not exist, the address translation control unit 103 notifies the OS by an interrupt or the like and requests creation of a page table entry.

  The address translation control unit 103 carries around the S / E flag included in the page table entry managed by the OS and stores it in the address translation unit 104. Therefore, each page table entry information stored in the address conversion unit 104 includes this S / E flag.

  The physical address holding unit 105 holds a physical address obtained as a result of indexing the address conversion unit 104. This physical address holding unit 105 also carries and holds information on the S / E flag obtained as a result of the index of the address conversion unit 104.

  The physical address of the physical address holding unit 105 passes through the selector 108 and is sent to the page address holding unit 109 to index the page address array 110. The selector 108 and the page address holding unit 109 also hold S / E flag information. At the same time, in order to index the cache array 117, the physical address of the physical address holding unit 105 is sent to the block address holding unit 116 through the selector 108 and the selector 115.

  The page address array 110 holds a plurality of page addresses and holds the state of each page. The page address array 110 operates in cooperation with the cache array 117. That is, the page control unit 112 and the cache control unit 119 control the registration operation so that the page to which the block registered in the cache array 117 belongs is registered in the page address array 110. The page address array 110 is otherwise the same as a general address array.

  The page address array 110 searches whether the page address held in the page address holding unit 109 is registered in itself. The page hit / miss determination unit 111 determines whether a page to be accessed is registered in the page address array 110. The determination result of the page hit / miss determination unit 111 is sent to the page control unit 112 together with the page address.

  The page control unit 112 controls the registration update operation of the page address array 110 based on the determination result of the page hit / miss determination unit 111. The page hit / miss determination unit 111 and the page control unit 112 carry and hold information on the S / E flag. Further, when registering the page address in the page address array 110, the page control unit 112 also registers the information of the carried S / E flag. Further, the page control unit 112 determines a unit for executing snoop according to the state of the carried S / E flag.

  The cache array 117 is the same as a general cache array 117 (address array and data array). The cache array 117 searches whether the block address held by the block address holding unit 116 is registered in itself. The cache hit / miss determination unit 118 determines whether or not a block to be accessed is registered in the cache array 117. The determination result of the cache hit / miss determination unit 118 is sent to the cache control unit 119 together with the block address.

  The cache control unit 119 controls the registration update operation of the cache array 117 based on the determination result of the cache hit / miss determination unit 118. Further, when the memory access is necessary, the cache control unit 119 notifies the memory control unit 121 of a memory access request. The memory control unit 121 executes access (read / write, etc.) to the storage device 505 in response to a request. This is a general memory access function.

  The information of the page control unit 112 and the information of the cache control unit 119 are sent to the snoop control unit (output) 106, and the snoop control unit (output) 106 from which the snoop request is transmitted to the other cache cache device 100, When the snoop request is output, the S / E flag information is output.

  FIG. 7 is a diagram illustrating a determination table related to the snoop operation performed by the management unit 120. In this figure, it is assumed that the management unit 120 uses the MESI protocol as the cache control protocol. The management unit 120 may use other protocols, but the details of the operation differ. In this embodiment, one cache hierarchy is used for the sake of simplicity of explanation, but there may be a plurality of cache hierarchies. The management unit 120 may follow a prescribed cache coherency control protocol in each layer. The management unit 120 executes control for a transitional state associated with the transition of the cache status, but is not described here because it is an event that should be considered and solved in a general apparatus.

The cache state defined by the MESI protocol includes the following states.
M: Modified (Data exists only in the cache and has been changed from the value in main memory)
E: Exclusive (data exists only in the cache, but matches the value in main memory)
S: Share (the same data exists in other caches in the system)
I: Invalid (This cache line is invalid. A cache miss state is the same)
The snoop control unit (output) 106, the page control unit 112, and the cache control unit 119 operate according to this table. The table in FIG. 7 is roughly divided into two columns. The column labeled “state” describes the condition regarding the instruction and the state of the page address array 110 and the cache array 117 before the instruction is executed. A column labeled “determination and processing” describes a unit of snoop operation, necessity of the operation, and states of the page address array 110 and the cache array 117 after execution of the instruction.

  The rows in the table of FIG. 7 correspond to possible “state” combinations. The table rows are roughly divided into two groups. Nos. 1-1 to 1-24 correspond to the state when the shared memory space (S / E flag = 0) is accessed, and Nos. 2-1 to 2 -24 corresponds to the state when the exclusive memory space (S / E flag = 1) is accessed. The states and operations of Nos. 1-1 to 1-24 are not specific to the present embodiment except for the page address array 110.

  Hereinafter, the table of FIG. 7 will be described by taking as an example the case where the processor 122 sequentially reads values in a continuous memory space from a predetermined address A (FIG. 6). First, the operation when accessing the shared memory space will be described.

1-1
Considering the first read operation for the address A which is the head of the page, the data at the address does not exist in the page address array 110 or the cache array 117. This state is one of Nos. 1-9 to 1-12 in the table of FIG. 7 (S / E flag = 0, memory access = read, own page address array 110 = miss, own cache array 117 = I ) Is applicable. In this case, the management unit 120 executes a snoop operation (including issuing a snoop request) on the other cache device 100 in order to recognize the state of the other cache device 100.

  In this case, since the S / E flag = 0 (shared memory space), the snoop processing unit is a block having a cache management size (eg, 128 bytes). The other cache device 100 notifies the snoop request source of the snoop result. The notified result corresponds to the description in the columns of “state”, “array state”, and “other cache” in the table. When the cache array 117 has the latest data (M state), the other cache device 100 writes the latest data to the storage device 505.

  Thereafter, the management unit 120 issues a read request for the corresponding block to the storage device 505. Note that the latest data of the corresponding block may be included in the notification of the snoop result and notified to the request source from another cache device 100. Operations such as the snoop operation, the state transition of the own cache, and the state transition of the other cache device 100 are as defined in the MESI protocol.

  Regardless of the state of the other cache device 100, the management unit 120 registers the corresponding page address in the page address array 110 of the own device. At that time, the management unit 120 also registers the value of the S / E flag (0 in this case) carried around with the read request in the page address array 110 together.

1-2
Subsequently, the processor 122 issues a read request for address A + address 8. At this time, the page address of the address is already registered in the page address array 110, and data of the address exists in the cache array 117. This state is one of Nos. 1-2 to 1-4 in the table of FIG. 7 (S / E flag = 0, memory access = read, own page address array 110 = hit, own cache array 117 = E or S).

  In this case, since the read request has hit the cache array 117, a snoop operation for the other cache device 100 does not occur. This state is the same for the leads up to the subsequent address A + 120.

1-3
Subsequently, the processor 122 issues a read request for address A + 128. At this time, the page address of the address is registered in the page address array 110, but the data of the address does not exist in the cache array 117. This is because the address belongs to the next block. This state is one of Nos. 1-5 to 1-8 in the table of FIG. 7 (S / E flag = 0, memory access = read, own page address array 110 = hit, own cache array 117 = I) Is applicable. In this case, the management unit 120 performs a snoop operation on the other cache device 100 in order to recognize the state of the other cache device 100.

  In this case, since the S / E flag = 0 (shared memory space), the snoop processing unit is a block having the cache management size. The other cache device 100 notifies the snoop request source of the snoop result. The notified result corresponds to the description in the columns of “state”, “array state”, and “other cache” in the table. When the cache array 117 has the latest data (M state), the other cache device 100 writes the latest data to the storage device 505.

  Thereafter, the management unit 120 issues a read request for the corresponding block to the storage device 505. Note that the latest data may be included in the notification of the result of the snoop and notified from the other cache device 100 to the request source. Operations such as the snoop operation, the state transition of the own cache, and the state transition of the other cache device 100 are as defined in the MESI protocol. Note that the page address is already registered in its own page address array 110, and therefore no update is necessary.

1-4
For subsequent accesses, the management unit 120 performs the above-described operation 1-2 when accessing a block already stored in the cache array 117, and the above-described operation when accessing a new block beyond the stored block. The operation of 1-3 is executed. Furthermore, the management unit 120 executes the above-described operation 1-1 when accessing a new page beyond the page.

1-5
Regarding the write operation, the process according to the state is defined in the table of FIG. The snoop processing unit is a block unit that is the management size of the cache. Detailed description is omitted.

  Next, the operation of the management unit 120 when accessing the exclusive memory space (S / E flag = 1) will be described.

2-1
Considering the first read operation for address A, the data at the address does not exist in the page address array 110 or the cache array 117. This state is one of Nos. 2-9 to 2-12 in the table of FIG. 7 (S / E flag = 1, memory access = read, own page address array 110 = miss, own cache array 117 = I) Is applicable. In this case, the management unit 120 executes a snoop operation (including issuing a snoop request) on the other cache device 100 in order to recognize the state of the other cache device 100.

  In this case, since the S / E flag = 1 (exclusive memory space), the snoop processing unit is a page (eg, 16 megabytes). The other cache device 100 notifies the snoop request source of the snoop result. The notified result corresponds to the description in the columns of “state”, “array state”, and “other cache” in the table. When the cache array 117 has the latest data (M state), the other cache device 100 writes the latest data to the storage device 505.

  Operations such as the snoop operation, the state transition of the own cache, and the state transition of the other cache device 100 are different from the general MESI protocol. In other words, the other cache device 100 evicts all the blocks belonging to the page address received by the snoop request from the cache array 117 and updates the cache status to I. Thereafter, the other cache device 100 notifies the snoop request source cache device 100 that the eviction of all blocks of the page has been completed.

  Thereafter, the snoop request source management unit 120 issues a read request for the corresponding block to the storage device 505. Even in the case of a snoop request in units of pages, the management unit 120 of the snoop request source notifies the other cache device 100 of the block address, and from there, the latest data of the corresponding block is used to notify the snoop result. You may receive including.

  Regardless of the state of the other cache device 100, the management unit 120 determines whether or not the page address array 110 of the own device has completed eviction of the corresponding page address and all pages of the corresponding page of the other cache device 100. Register the information to be managed. At this time, the management unit 120 registers the value of the S / E flag (1 in this case) that was carried along with the read request together with the page address array 110. The management unit 120 updates the status of the own cache array 117 to E. The reason is that all blocks of the corresponding page are evicted from the cache array 117 of the other cache device 100.

2-2
Subsequently, the processor 122 issues a read request for address A + address 8. At this time, the page address of the address is already registered in the page address array 110, and data of the address exists in the cache array 117. This state corresponds to the No. 2-2 state (S / E flag = 1, memory access = read, own page address array 110 = hit, own cache array 117 = E). When the S / E flag = 1, the cache array 117 does not transition to S, so there is no state (No. 2-3 to 2-4 in the table of FIG. 7) that the cache array 117 is S.

  In this case, since the read request has hit the cache array 117, a snoop operation for the other cache device 100 does not occur. This state is the same for the leads up to the subsequent address A + 120.

2-3
Subsequently, the processor 122 issues a read request for address A + 128. At this time, the page address of the address is registered in the page address array 110, but the data of the address does not exist in the cache array 117. This is because the address belongs to the next block. This state corresponds to the No. 2-8 state (S / E flag = 1, memory access = read, own page address array 110 = hit, own cache array 117 = I) in the table of FIG. A state in which the target address of the read request hits the page address array 110 of its own device means that not all blocks of the corresponding page already exist on the other cache device 100. Therefore, inevitably, the state of the block of the cache array 117 of the other cache device 100 is I, and there is no other state (No. 2-5 to 2-7 in the table of FIG. 7).

  Thereafter, the management unit 120 issues a read request for the corresponding block to the storage device 505. Since the state of the block in the cache array 117 of the other cache device 100 is already I, the snoop operation for the other cache device 100 is not necessary. Note that the page address is already registered in its own page address array 110, and therefore no update is necessary.

2-4
For subsequent accesses, the management unit 120 performs the above-described operation 2-2 when accessing a block already stored in the cache array 117, and the above-described operation when accessing a new block beyond the stored block. The operation of 2-3 is executed. Furthermore, the management unit 120 executes the above-described operation 2-1 when accessing a new page beyond the page.

2-5
Regarding the write operation, the process according to the state is defined in the table of FIG. A snoop processing unit is a page. Detailed description is omitted.

  Next, returning to FIG. 4, the snoop operation in the other cache device 100 will be described.

  The snoop control unit (input) 106 of all the other cache devices 100 receives the snoop request issued by the snoop request source cache device 100. The snoop control unit (input) 106 also receives S / E flag information. The received snoop request is sent to the snoop address holding unit 107 snoop address holding unit. The snoop address holding unit 107 also carries and holds the S / E flag information together.

  The snoop address of the snoop address holding unit 107 passes through the selector 108 selector and is sent to the page address holding unit 109 for indexing the page address array 110. The selector 108 and the page address holding unit 109 carry and hold information on the S / E flag. At the same time, in order to index the cache array 117, the physical address held by the snoop address holding unit 107 is sent to the block address holding unit 116 through the selector 108 and the selector 115.

  When the value of the S / E flag carried around with the snoop request address is 0 (shared memory space), the operation performed by the management unit 120 in response to the snoop request is a general snoop operation (for example, during a general MESI protocol). (Snoop operation). Note that the management unit 120 may check whether there is any contradiction or the like in the state of the page address array 110 and the cache array 117.

  When the value of the S / E flag carried around with the snoop request address is 1 (exclusive memory space), the page address array 110 is indexed by the page address held in the page address holding unit 109, and the page hit / miss judgment unit 111 is indexed. However, it is determined whether or not the page accessed by the processor 122 is registered in the page address array 110. The page hit / miss determination unit 111 sends the determination result together with the address to the page control unit 112.

  When the determination result of the page hit / miss determination unit 111 is a miss, the cache array 117 does not hold the block of the corresponding page. Therefore, the page control unit 112 controls the snoop control unit (output) 106 so as to return other cache status = I as the snoop result.

  On the other hand, when the determination result of the page hit / miss determination unit 111 is a hit, the management unit 120 drives out all the blocks of the page from the cache array 117. The page address array 110 finally invalidates the corresponding page address, but holds information for managing whether or not all the blocks of the corresponding page in the cache array 117 have been evicted. The reason is to control the transient state of eviction.

  The page control unit 112 notifies the burst control unit 113 of the page address to be evicted. The burst control unit 113 generates block addresses in order from the first block in the page based on the received page address, sequentially sends the block address to the block address holding unit 114, and instructs to eject the corresponding block from the cache array 117. . The block address held by the block address holding unit 114 passes through the selector 115 and is sent to the block address holding unit 116. The cache array 117 is indexed by the block address held in the block address holding unit 116, and the cache hit / miss determination unit 118 determines whether or not a block to be accessed is registered in the cache array 117.

  The determination result of the cache hit / miss determination unit 118 is sent to the cache control unit 119 together with the address. The cache control unit 119 controls the registration update operation of the cache array 117 based on the determination result of the cache hit / miss determination unit 118.

  This update operation is the same as, for example, the update operation during a general MESI protocol. Briefly describing the MESI protocol as an example, when the status of the cache array 117 is equal to I, the cache control unit 119 does nothing because there is no block to be evicted on the cache array 117. When status = E or S, the cache control unit 119 invalidates the cache status (the status is set to I) because the eviction block exists on the cache array 117 (the data is in the same state as the memory contents). Update). In the case of status = M, since the data on the cache is the only data, the cache control unit 119 writes the data back to the storage device 505 and invalidates the cache status (updates the status to I).

  The burst control unit 113 continues the process until all the blocks of the corresponding page have been evicted, and when the evicting of all the blocks is completed, notifies the page control unit 112 and the snoop control unit (output) 106 of the completion. To do. The snoop control unit (output) 106 notifies the snoop request source cache device 100 that all block eviction of the page has been completed. The page address array 110 of the snoop request source cache device 100 receives this completion notification, and updates the information for managing whether or not all blocks of the corresponding page of the other cache device 100 are completed to indicate the completion of the eviction. To do.

  Note that in an actual apparatus, it is necessary to consider that a physical distance and time are required to execute the described operation (waiting for completion of processing, etc.). In this respect, since it depends on the design of each device, and the solutions vary depending on the design, the implementation means is not mentioned here.

  The cache device 100 according to the present embodiment can reduce the number of snoops in the exclusive memory space. Specifically, in the example of sequentially reading the values in the continuous memory space from address A, the operation when the S / E flag = 0 (shared memory space) and the snoop when the S / E flag = 1 (exclusive memory space) The comparison of the number of times is as follows.

When S / E flag = 0 (shared memory space): Snoop every time a block is crossed
1-1) No.1-9 ~ 1-12 Snoop
1-2) No. 1-2 to 1-4 Not required
1-3) No.1-5 ~ 1-8 Snoop
1-4) After that, repeat 1-2) → 1-3) and go to 1-1) if the page is exceeded. S / E flag = 1 (exclusive memory space)… Snoop only when the page is exceeded
2-1) No.2-9 ~ 2-12 Snoop
2-2) No.2-2 Not required
2-3) No.2-8 Not required
2-4) After that, repeat 2) → 3) and go to 1) when the page is exceeded Technology costs such as power consumption associated with investment and high-speed operation can be reduced.

  The reason for such an effect is that the management unit 120 performs snoop of the exclusive memory space in units of pages.

  The present invention can be applied not only to the snoop cache control method but also to the directory control method. The distinction as to whether the memory in the storage device 505 is a shared memory space or an exclusive memory space may be given in units different from pages.

<Second Embodiment>
FIG. 8 is a configuration diagram of the cache device 100 according to the present embodiment.

  The cache device 100 is divided into pages including a plurality of blocks, a storage device 505 including a shared page shared by the plurality of processors 122 and an exclusive page occupied by any processor 122 for a certain period of time, and a plurality of processors 122 Are provided in correspondence with the processor 122.

  The cache device 100 includes a management unit 120 and a cache array 117.

  The management unit 120 receives the address of the area in the exclusive page from the corresponding processor 122, transmits a snoop request for the page including the area to the other device, and sends the address of the block including the area and the latest data of the own device. Register in the cache array 117. The management eve 120 further receives a page snoop request from another device, and deletes all blocks included in the designated page from the cache array 117 of the own device.

  The cache device 100 according to the present embodiment can reduce the number of snoops in the exclusive memory space. The reason for such an effect is that the management unit 120 performs snoop of the exclusive memory space in units of pages.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

100 cache device
101 Instruction decode section
102 Logical address generator
103 Address translation controller
104 Address converter
105 Physical address holding unit
106 Snoop control unit
106 Snoop control unit (input)
106 Snoop control unit (output)
107 Snoop address holding unit
108 selector
109 Page address holding section
110 page address array
111 Page hit / miss judgment section
112 Page control
113 Burst controller
114 Block address holding section
115 selector
116 Block address holding section
117 cache array
118 Cache hit / miss judgment section
119 Cache control unit
121 Memory controller
122 processor
501 LSI
505 storage device
506 computer

Claims (7)

A computer comprising: a shared page divided into pages including a plurality of blocks and shared by a plurality of processors; a storage device including an exclusive page occupied by any processor for a certain period; and the plurality of processors. A cache device provided corresponding to
1) The address of the area in the exclusive page is received from the corresponding processor, the snoop request for the page including the area is transmitted to another apparatus, and the address of the block including the area and the latest data are stored in the cache array of the own apparatus. 2) a cache device comprising: a management unit that receives a snoop request for a page from another device and deletes all blocks included in the designated page from the cache array of the own device; and the cache array . The cache device further includes a page address array,
The management means 1) if the address of the page including the area is not registered in the page address array, registers it in the page address array and sends a page snoop request to another device. 2) 2. The cache device according to claim 1, wherein if the address of the page including the area is registered in the page address array, a page snoop request is not transmitted to another device. The management means includes
1) The address of the area in the shared page is received from the corresponding processor, the snoop request for the block including the area is transmitted to another apparatus, and the address of the block including the area and the latest data are stored in the cache array of the own apparatus. And 2) receiving a block snoop request from another device, and deleting the designated block from the cache array of the own device. A plurality of processors comprising address conversion means for storing logical addresses, physical addresses, and shared page or exclusive page distinction information;
The storage device;
4. A computer comprising: the cache device according to claim 1, wherein the physical address and the distinction information are acquired from the address conversion unit when the storage device is accessed by a logical address of a processor. A computer comprising: a shared page divided into pages including a plurality of blocks and shared by a plurality of processors; a storage device including an exclusive page occupied by any processor for a certain period; and the plurality of processors. In the cache device provided corresponding to
1) The address of the area in the exclusive page is received from the corresponding processor, the snoop request for the page including the area is transmitted to another apparatus, and the address of the block including the area and the latest data are stored in the cache array of the own apparatus. 2) A cache control method for receiving a page snoop request from another device and deleting all blocks included in the specified page from the cache array of the own device.   1) If the address of the page including the area is not registered in the page address array, register the address in the page address array and send a page snoop request to another device. 2) The page including the area 6. The cache control method according to claim 5, wherein if the address is registered in the page address array, a page snoop request is not transmitted to another device. 1) The address of the area in the shared page is received from the corresponding processor, the snoop request for the block including the area is transmitted to another apparatus, and the address of the block including the area and the latest data are stored in the cache array of the own apparatus. And 2) receiving a block snoop request from another device and deleting the designated block from the cache array of the own device.

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