JP2015119307A - Relaxation oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a relaxation oscillator with satisfactory noise characteristics applicable to one or two comparators with small power consumption.SOLUTION: A relaxation oscillator (1) includes: an oscillation circuit (10) that increases and decreases the signal level of first and second oscillation signals (OSCa, OSCb) responding to a transition of the signal level of a reference clock (CLKout); a comparison circuit (22) that performs first and second operations to compare the signal level of each of the first and second oscillation signals and a first comparison voltage, which is turned OFF during periods other than these operation periods; an oscillation control circuit (20) that controls the reference clock to make a logical transition based on the operation results of the first and second operation; and a fixing circuit (24) that fixes the output of the comparison circuit to a predetermined logical value during the OFF period of the comparison circuit.

Description

  The present disclosure relates to a relaxation oscillator that generates a reference clock.

  In an integrated circuit or the like, an oscillator that oscillates at a constant frequency is used for generation of a clock signal of a microcomputer or the like, transmission / reception of communication, a timer function, or the like. Conventionally, crystal oscillators have been widely used as oscillators. A crystal oscillator can create a highly accurate oscillation period, but it is difficult to integrate, so it needs to be mounted as an external element. Therefore, it cannot be said that the crystal oscillator is excellent from the viewpoint of cost and integration. In addition, the crystal oscillator has a power problem such that it takes time to start up and is difficult to apply to an application that realizes ultra-low power by intermittent operation that is frequently turned on and off.

  In recent years, attention has been focused on a relaxation oscillator that can be realized by a complementary metal-oxide semiconductor (CMOS) circuit. The relaxation oscillator can be integrated and fast turned on and off, and can operate at a relatively low power. Therefore, it can be said that the relaxation oscillator is suitable as a reference oscillator that does not require high frequency accuracy.

  In general, the relaxation oscillator has a problem that the trade-off between power and accuracy is not good. The relaxation oscillator is susceptible to thermal noise and flicker noise. Therefore, for example, in order to reduce thermal noise, it is conceivable to increase the current of a comparator or the like that is a circuit element, but in this case, the power of the relaxation oscillator increases.

  On the other hand, a relaxation oscillator in which two comparators are operated complementarily at low power is disclosed (for example, see Patent Document 1). According to this, since the power of each comparator can be reduced alternately, the power consumption of the relaxation oscillator can be reduced.

US Patent No. 7,863,992 specification

Hui Tian and AbbasEl Gamal, 'Analysis of 1 / f Noisein Switched MOSFET Circuits', IEEE Transactions on circuits and systems-II: Analog and digital signal processing, Vol.48, No.2, Feb. 2001, P.151-157

  However, although the relaxation oscillator of Patent Document 1 alternately reduces the power of the two comparators, the power is not completely turned off, so there is a limit to reducing power consumption. When it is completely turned off, the output of the comparator becomes indeterminate, and it is considered that it does not operate correctly as an oscillator.

  Further, this relaxation oscillator does not take the above-described countermeasure against flicker noise, and there is a possibility that jitter characteristics deteriorate when dealing with a low frequency where flicker noise is a problem. Further, this relaxation oscillator is premised on the use of two comparators operating in a complementary manner, and cannot be applied to a case where there is one comparator.

  In view of the above, it is an object of the present disclosure to provide a relaxation oscillator that can be applied to either one or two comparators, can further reduce power consumption, and has good noise characteristics. .

  In order to solve the above problems, the present invention has taken the following solutions. In other words, the relaxation oscillator that generates the reference clock increases the signal level of the first oscillation signal and decreases the signal level of the second oscillation signal in response to the transition of the signal level of the reference clock. An oscillation circuit that alternately performs an operation of increasing the signal level of the second oscillation signal and decreasing the signal level of the first oscillation signal; and the signal level of the first oscillation signal and the first comparison voltage The first operation for outputting a signal according to the comparison result, the signal level of the second oscillation signal and the first comparison voltage are compared, and the signal according to the comparison result is A comparison circuit that is turned off during a period other than the period during which the first and second operations are performed, and the output of the comparison circuit is the first operation. Oscillation signal signal If the bell indicates that the first comparison voltage has been reached, the signal level of the reference clock is shifted to the first logic level, while the signal level of the second oscillation signal is changed to the first comparison voltage. In the case of indicating that the voltage has been reached, an oscillation control circuit for transitioning the signal level of the reference clock to a second logic level, and an output of the comparison circuit during the off period of the comparison circuit And a fixed circuit to be fixed to.

  According to this, when the oscillation circuit is performing an operation of increasing the signal level of the first oscillation signal, the comparison circuit detects that the signal level of the first oscillation signal has become the first comparison voltage. Then, the oscillation control circuit changes the signal level of the reference clock to the first logic level. On the other hand, when the oscillation circuit is performing an operation of increasing the signal level of the second oscillation signal, the comparison circuit detects that the signal level of the second oscillation signal has become the first comparison voltage. The oscillation control circuit changes the signal level of the reference clock to the second logic level.

  The comparison circuit is controlled so as to be in an off state in a period other than the period in which the first and second operations are performed, that is, in a period in which neither of the first and second operations is performed. Note that the comparison circuit being in the OFF state is a state in which, for example, the current path from the power source to the ground is interrupted in the circuit, and no power is consumed.

  In the fixed circuit, when the comparison circuit is in an off state, the output of the comparison circuit is set to a predetermined logical value, for example, at least one of the first and second oscillation signals is less than the first comparison voltage. Can be fixed to a logical value indicating.

  As described above, according to the relaxation oscillator, one comparison circuit can be used. In addition, since the comparison circuit can be turned off without power consumption, further reduction in power consumption can be achieved. Further, when the comparison circuit performs the first and second operations, the current necessary for these operations can be intensively supplied to the comparison circuit, so that thermal noise can be suppressed. Even when the comparison circuit is controlled to be off, the output of the comparison circuit is fixed to a predetermined logic value, so that the malfunction of the relaxation oscillator due to the output becoming unstable can be suppressed.

  In addition, it can be said that it is desirable that a relaxation oscillator that can be realized by a CMOS circuit can suppress flicker noise that is particularly affected in a low frequency region. Therefore, the inventor of the present application has paid attention to the technique shown in Non-Patent Document 2 in which a trap that causes flicker noise can be emptied with high probability when the transistor is turned off.

  By applying this technique to the relaxation oscillator according to the present disclosure, flicker noise can be obtained by completely turning off the comparison circuit when the first and second operations are not performed, and hence the transistors constituting the comparison circuit. It was thought that it can suppress effectively. That is, with the relaxation oscillator according to the present disclosure, it is possible to obtain the effects of both low power consumption and good noise characteristics.

  According to the present disclosure, it is possible to provide a relaxation oscillator that can be applied to either one or two comparators, can further reduce power consumption, and has good noise characteristics.

FIG. 1 is a configuration diagram of a relaxation oscillator according to the first embodiment. FIG. 2 is a circuit diagram showing a configuration example of the delay circuit of FIG. FIG. 3 is a circuit diagram showing a configuration example of the comparison circuit and the fixed circuit of FIG. FIG. 4 is a timing chart showing an operation example of the relaxation oscillator of FIG. FIG. 5 is a circuit diagram showing another example of the fixed circuit of FIG. FIG. 6 is a configuration diagram of a relaxation oscillator according to the second embodiment. FIG. 7 is a timing chart showing an operation example of the relaxation oscillator of FIG. FIG. 8 is a configuration diagram of a relaxation oscillator according to the third embodiment.

<First Embodiment>
FIG. 1 is a configuration diagram of a relaxation oscillator according to the first embodiment. The relaxation oscillator 1 according to the present embodiment generates a reference clock CLKout, and includes an oscillation circuit 10 and an oscillation control circuit 20.

  The oscillation circuit 10 outputs, for example, the clock CKa as the reference clock CLKout among the clocks CKa and CKb having a frequency corresponding to the time constant. The signal levels of the clocks CKa and CKb fluctuate complementarily.

  The oscillation circuit 10 includes a first signal generation circuit 12 that generates a signal OSCa that is a first oscillation signal, and a second signal generation circuit 14 that generates a signal OSCb that is a second oscillation signal.

  The signal generation circuit 12 includes a PMOS (positive channel metal oxide semiconductor) transistor Tpa, a resistance element Ra, an NMOS (negative channel metal oxide semiconductor) transistor Tna, and a capacitive element Ca.

  One end of the transistor Tpa is connected to the power supply VDD, and the clock CKa, that is, the reference clock CLKout is supplied to the gate. The resistance element Ra is connected to the other end of the transistor Tpa. The transistor Tna is connected between the resistance element Ra and the power supply VSS, and the clock CKa is supplied to the gate. The capacitive element Ca is connected between the connection node of the resistance element Ra and the transistor Tna and the power supply VSS. Then, the potential of this connection node is output as signal OSCa.

  The signal generation circuit 14 includes a PMOS transistor Tpb, a resistance element Rb, an NMOS transistor Tnb, and a capacitance element Cb.

  One end of the transistor Tpb is connected to the power supply VDD, and the clock CKb is supplied to the gate. The resistance element Rb is connected to the other end of the transistor Tpb. The transistor Tnb is connected between the resistance element Rb and the power source VSS, and the clock CKb is supplied to the gate. The capacitive element Cb is connected between the connection node of the resistance element Rb and the transistor Tnb and the power supply VSS. Then, the potential of this connection node is output as a signal OSCb.

  The oscillation circuit 10 may output the clock CKb as the reference clock CLKout.

  The oscillation control circuit 20 includes two delay circuits Da and Db, a comparison circuit 22, a fixed circuit 24, and a latch circuit 26.

  The delay circuit Da outputs a signal POFFa obtained by delaying either the rising edge or falling edge timing of the clock CKa. In the present embodiment, for example, the delay circuit Da generates a signal POFFa obtained by delaying the timing at which the clock CKa changes from the H level to the L level by a predetermined time. The delay circuit Da is configured not to delay the timing when the clock CKa changes from L level to H level.

  The delay circuit Db outputs a signal POFFb obtained by delaying either the rising edge or falling edge timing of the clock CKb. In the present embodiment, for example, the delay circuit Db generates a signal POFFb obtained by delaying the timing at which the clock CKb changes from the H level to the L level by a predetermined time. The delay circuit Db is configured not to delay the timing when the clock CKb changes from the L level to the H level.

  The delay circuits Da and Db include, for example, an RC circuit 30 as shown in FIG. FIG. 2 is a circuit diagram of the delay circuit of FIG. Each of the delay circuits Da and Db includes, for example, an RC circuit 30, a buffer circuit 32, and an OR circuit 38. Since the delay circuits Da and Db have the same configuration, the delay circuit Da will be described.

  The RC circuit 30 includes a variable resistance element 34 having one end connected to the output of the buffer circuit 32, and a variable capacitance element 36 connected between the other end of the variable resistance element 34 and the ground.

  The clock CKa is input as it is to one input terminal of the OR circuit 38, and the clock CKa is input to the other input terminal via the buffer circuit 32 and the RC circuit 30. Then, the output of the OR circuit 38 becomes the signal POFFa. The delay circuit Db receives the clock CKb and outputs a signal POFFb.

  By configuring the delay circuits Da and Db as shown in FIG. 2, the signals POFFa and POFFb can be generated from the clocks CKa and CKb based on the time constant determined by R and C. Further, since the values of R and C can be adjusted by using the variable resistance element 34 and the variable capacitance element 36 in the RC circuit 30, it becomes easy to cope with a temperature change of the relaxation oscillator 1 and the like. Further, by realizing the delay circuits Da and Db by a circuit including the RC circuit 30, it is possible to reduce power consumption.

  Note that the delay circuits Da and Db may be realized by a buffer circuit or the like. The RC circuit 30 may include a resistance element and a capacitance element instead of the variable resistance element 34 and the variable capacitance element 36.

  Returning to FIG. 1, the comparison circuit 22 compares the voltage Vref, which is the first comparison voltage, with the signal OSCa, and the voltage Vref, with the signal OSCb, and outputs a signal corresponding to each comparison result. The comparison circuit 22 includes a first comparator CMPa and a second comparator CMPb.

  Comparator CMPa receives signal OSCa at its inverting input terminal and voltage Vref at its non-inverting input terminal, and is on / off controlled in accordance with signal POFFa. Specifically, when the signal POFFa is at the L level, the comparator CMPa compares the signal level of the signal OSCa with the voltage Vref and performs a first operation of outputting a signal according to the comparison result, while the signal POFFa is When it is at the H level, it is turned off.

  In the first operation, when the signal level of the signal OSCa reaches the voltage Vref, the comparator CMPa sets the output to the L level, for example, while when the signal level of the signal OSCa is less than the voltage Vref, the output is set to the H level, for example. To.

  The comparator CMPb receives the signal OSCb at the inverting input terminal and the voltage Vref at the non-inverting input terminal, and is on / off controlled according to the signal POFFb. Specifically, when the signal POFFb is at the L level, the comparator CMPb compares the signal level of the signal OSCb with the voltage Vref and performs a second operation of outputting a signal according to the comparison result, while the signal POFFb is When it is at the H level, it is turned off.

  In the second operation, when the signal level of the signal OSCb reaches the voltage Vref, the comparator CMPb sets the output to the L level, for example. On the other hand, when the signal level of the signal OSCb is less than the voltage Vref, the comparator CMPb sets the output to the H level, for example. To.

  Note that the comparators CMPa and CMPb are in the off state, as will be described in detail in FIG. 3, but the current path from the power source to the ground is cut off in the comparators CMPa and CMPb, and the power consumption is almost zero. This is the state.

  The fixed circuit 24 outputs the output of the comparator CMPa as a signal OUTa when the comparator CMPa performs the first operation, and outputs the output of the comparator CMPb when the comparator CMPb performs the second operation. Is output as a signal OUTb. The fixed circuit 24 fixes the outputs of the comparators CMPa and CMPb as predetermined logic values, for example, at the H level when the comparators CMPa and CMPb are in the off state, that is, when the signals POFFa and POFFb are at the H level. Output signals OUTa and OUTb.

  FIG. 3 is a circuit diagram illustrating a configuration example of the comparison circuit and the fixed circuit. The configurations of the comparators CMPa and CMPb are the same, and the configurations of the fixed circuit 24a that can fix the output of the comparator CMPa and the fixed circuit 24b that can fix the output of the comparator CMPb are also the same. The comparator CMPa and the fixed circuit 24a will be described.

  The comparator CMPa can output a signal Vouta having a logical value corresponding to the comparison result between the voltage Vref and the signal OSCa. The comparator CMPa also supplies a current source by NMOS transistors TnI1 to TnI3 capable of interrupting a current path between the power supply VDD and the power supply VSS and a voltage supplied to the gates of these transistors TnI1 to TnI3 as a voltage Vbias or a power supply. Switches SW1 and SW2 for switching to VSS.

  In the comparator CMPa, for example, when the signal POFFa is at L level and the signal PONa that is the inverted signal thereof is at H level, the switch SW1 is turned on and the switch SW2 is turned off, so that the transistors TnI1 to TnI3 are turned on. Therefore, a current path is formed between the power supply VDD and the power supply VSS. At this time, when the signal level of the signal OSCa reaches the voltage Vref, the signal Vouta becomes the L level, and when the signal level of the signal OSCa is less than the voltage Vref, the signal Vouta becomes the H level.

  When the signal POFFa is at the H level and the signal PONa is at the L level, the switch SW1 is turned off and the switch SW2 is turned on, so that the transistors TnI1 to TnI3 are turned off, and the current path between the power supply VDD and the power supply VSS is cut off. Is done. As a result, the comparator CMPa is turned off.

  The fixed circuit 24a can be composed of a transistor that pulls up the signal Vouta. Specifically, the fixed circuit 24a includes a PMOS transistor Tp connected to the power supply VDD and receiving a signal PONa at the gate. Accordingly, the fixed circuit 24a outputs the signal OUTa at the H level when the signal PONa is at the L level, that is, when the comparator CMPa is in the off state, while the signal Vouta is output from the signal OUTa when the signal PONa is at the H level. Output as.

  As described above, since the fixed circuit 24a outputs the signal OUTa in which the signal Vouta is fixed at the H level in the off period of the comparator CMPa, the output of the comparator CMPa in the off state becomes indefinite. 1 does not malfunction.

  In FIG. 3, when the last character of each code is read from “a” to “b”, the configuration of the comparator CMPb and the fixed circuit 24 b and signals are obtained.

  Further, the comparison circuit 22 and the fixed circuit 24 may be configured by one circuit. That is, the comparison circuit 22 (each of the comparators CMPa and CMPb) may have a function capable of fixing its output to a predetermined logical value when it is in the off state.

  Returning to FIG. 1, the latch circuit 26 has two NAND circuits NDa and NDb, and receives the signals OUTa and OUTb and the clocks CKa and CKb and outputs the clocks CKa and CKb. The latch circuit 26 transitions the clocks CKa and CKb in response to the transition of the signals OUTa and OUTb.

  Next, the operation of the relaxation oscillator 1 according to the present embodiment will be described with reference to FIG.

  FIG. 4 is a timing chart showing the operation of the relaxation oscillator of FIG. At time T0, since the signals POFFa and POFFb are H, the comparison circuit 22, that is, the comparators CMPa and CMPb are in the off state. Therefore, since the fixing circuit 24 fixes the output of the comparison circuit 22, the signals OUTa and OUTb are at the H level.

  At time T0, the clock CKa changes from the H level to the L level, and the clock CKb changes from the L level to the H level.

  Since the capacitive element Ca is gradually charged when the clock CKa becomes the L level, the signal level of the signal OSCa gradually increases, while the capacitive element Cb is discharged when the clock CKb becomes the H level. Therefore, the signal level of the signal OSCb decreases and becomes L level.

  Thereafter, the signal POFFa becomes L level after a predetermined time delay from the timing (time T0) when the clock CKa becomes L level. As a result, the off period of the comparator CMPa ends, and the comparator CMPa starts the first operation.

  When it is detected by the first operation of the comparator CMPa that the signal OSCa has reached the voltage Vref at time T1, the signal OUTa becomes L level. On the other hand, since the comparator CMPb is in the off state, the fixed circuit 24 continues to output the H level signal OUTb.

  When the signal OUTa becomes L level, the clock CKa becomes H level and the clock CKb becomes L level.

  When the clock CKa becomes H level, the capacitive element Ca is discharged, and the signal level of the signal OSCa decreases. Further, when the clock CKa becomes H level, the signal POFFa also becomes H level.

  When the signal level of the signal OSCa decreases and becomes less than the voltage Vref, the signal OUTa becomes H level.

  When the first operation is completed, the comparator CMPa is turned off, so that the signal OUTa is fixed to the H level by the fixing circuit 24. That is, the fixing circuit 24 fixes the signal OUTa to the H level during the off period of the comparator CMPa.

  Further, when the clock CKb becomes L level, the capacitive element Cb is gradually charged, so that the signal level of the signal OSCb gradually increases.

  Then, the signal POFFb becomes L level with a predetermined time delay from the timing when the clock CKb becomes L level. As a result, the off period of the comparator CMPb ends, and the comparator CMPb starts the second operation.

  When the second operation of the comparator CMPb detects that the signal OSCb has reached the voltage Vref at time T2, the signal OUTb becomes L level. On the other hand, since the comparator CMPa is in the off state, the fixed circuit 24 continues to output the H level signal OUTa.

  When the signal OUTb becomes L level, the clock CKb becomes H level and the clock CKa becomes L level.

  When the clock CKb becomes H level, the capacitive element Cb is discharged, and the signal level of the signal OSCb decreases. Further, when the clock CKb becomes H level, the signal POFFb also becomes H level.

  When the signal level of the signal OSCb decreases and becomes less than the voltage Vref, the signal OUTb becomes H level.

  Further, since the comparator CMPb is turned off when the second operation is completed, the signal OUTb is fixed to the H level by the fixing circuit 24. That is, the fixing circuit 24 fixes the signal OUTb to the H level in the off period of the comparator CMPb.

  Thereafter, the above-described operation is repeated.

  As described above, according to the relaxation oscillator 1 according to the present embodiment, the comparison circuit 22 alternately performs the first and second operations, and in the comparison circuit 22 in the off period other than the period in which the first and second operations are performed. The current flowing between the power source and the ground is controlled to be completely turned off. Therefore, the power consumption of the relaxation oscillator 1 can be further reduced.

  Here, Patent Document 1 discloses a relaxation oscillator that can generate a clock by operating two comparators in a complementary manner. In this oscillator, the power consumption of the entire oscillator is reduced by operating the two comparators alternately at low power.

  However, in the technique of Patent Document 1, each comparator is operated with low power, but each comparator is not completely turned off. That is, since the power consumed by each comparator is not zero, there is a limit to reducing the power consumption. This is because if the comparator is turned off, the output becomes unstable and the relaxation oscillator malfunctions.

  On the other hand, in the relaxation oscillator 1 according to the present embodiment, the comparators CMPa and CMPb can be completely turned off in the off period other than the period in which the comparison circuit 22 performs the first and second operations. Further, even if the comparators CMPa and CMPb are completely turned off, the output of the comparators CMPa and CMPb can be fixed to a logical value such that the relaxation oscillator 1 operates normally by the fixing circuit 24.

  Therefore, the relaxation oscillator 1 according to the present embodiment can achieve lower power consumption than the relaxation oscillator of Patent Document 1 while maintaining normal operation as an oscillator.

  Further, in the relaxation oscillator realized by the CMOS circuit, it is preferable to take countermeasures against flicker noise, which is a problem particularly in the low frequency region, but the relaxation oscillator disclosed in Patent Document 1 does not take such countermeasures.

  Therefore, the inventor of the present application paid attention to Non-Patent Document 1. The technique of Non-Patent Document 1 is that when a transistor is turned off, a trap that causes flicker noise can be emptied with high probability (see particularly FIG. 1).

  Therefore, the inventor of the present application considers that not only the power consumption of the relaxation oscillator 1 but also the flicker noise can be effectively suppressed by turning off the transistor, that is, completely turning off the comparators CMPa and CMPb. It was.

  In the relaxation oscillator of Patent Document 1, the two comparators are merely operated at low power alternately, and are not completely turned off. Therefore, even if the technique of Non-Patent Document 1 is considered, the effect of suppressing flicker noise is achieved. I can't get it.

  On the other hand, in the present embodiment, the comparators CMPa and CMPb are completely turned off during the period when the first and second operations described above are not performed. More specifically, the transistors TnI1 to TnI3 included in the comparison circuit 22 are turned off to cut off the current path between the power supply and the ground. Therefore, as shown in FIG. 4, the off periods of the comparators CMPa and CMPb with respect to the operation period of the relaxation oscillator 1 can be made dominant.

  Thereby, in the relaxation oscillator 1 according to the present embodiment, flicker noise can be effectively suppressed in addition to further reduction in power consumption.

  Further, for example, by assigning a part of the power that can be reduced by turning off the comparison circuit 22 to the first and second operations of the comparison circuit 22, the heat consumption of the relaxation oscillator 1 is not significantly changed. Noise can be suppressed.

  Therefore, according to the relaxation oscillator 1 according to the present embodiment, power consumption can be effectively reduced, and good noise characteristics can be obtained, so that jitter performance can be improved.

  In the relaxation oscillator 1 according to the present embodiment, the delay circuits Da and Db may be omitted.

  Further, the fixed circuit 24 shown in FIG. 3 may be realized by an OR circuit as shown in FIG. In this way, the fixing circuit 24 masks the output of the comparison circuit 22 so as to fix the output of the comparison circuit 22 to a logic value indicating that the signals OSCa and OSCb are less than the voltage Vref when the comparison circuit 22 is in the OFF state. You may comprise.

  That is, the fixing circuit 24 only needs to fix the output of the comparison circuit 22 to a predetermined logical value during the off period of the comparison circuit 22.

  Further, the delay amounts of the clocks CKa and CKb by the delay circuits Da and Db may be set based on the periods during which the comparators CMPa and CMPb should perform the first and second operations, respectively.

  Each of the delay circuits Da and Db only needs to be able to notify the comparators CMPa and CMPb that the predetermined time has passed, and the comparators CMPa and CMPb receive the notifications from the delay circuits Da and Db, respectively. The first and second operations may be started.

<Second Embodiment>
FIG. 6 is a configuration diagram of a relaxation oscillator according to the second embodiment. In addition, the common code | symbol in FIG. 1 and FIG. 6 shows the same element or signal. In the present embodiment, differences from the first embodiment will be mainly described.

  In the relaxation oscillator 1 according to the present embodiment, the delay circuit Da has a sub-comparator CMPsub, and the delay circuit Db has a sub-comparator CMPsubb.

  The sub-comparator CMPsuba compares the signal OSCa with the voltage Vrefsub as a second comparison voltage lower than the voltage Vref, and outputs a signal POFFa corresponding to the comparison result. For example, the sub-comparator CMPsuba outputs an H level signal POFFa when the signal level of the signal OSCa is less than the voltage Vrefsub, while outputting an L level signal POFFa when the signal level of the signal OSCa becomes equal to or higher than the voltage Vrefsub. To do.

  The sub-comparator CMPsubb compares the signal OSCb with the voltage Vrefsub and outputs a signal POFFb corresponding to the comparison result. For example, the sub-comparator CMPsubb outputs an H level signal POFFb when the signal level of the signal OSCb is less than the voltage Vrefsub, while outputting an L level signal POFFb when the signal level of the signal OSCb becomes equal to or higher than the voltage Vrefsub. To do.

  The sub-comparators CMPsuba and CMPsubb generate timing signals for turning on and off the comparators CMPa and CMPb. However, since the accuracy of the timing signals may be relatively low, the power consumption of the sub-comparators CMPsuba and CMPsubb is reduced. can do.

  Next, the operation of the relaxation oscillator 1 according to this embodiment will be described with reference to FIG. The difference between FIG. 4 and FIG. 7 will be mainly described.

  After time T0, when the signal OSCa gradually increases and reaches the voltage Vrefsub, the sub-comparator CMPsuba outputs an L level signal POFFa. As a result, the off period of the comparator CMPa ends, and the comparator CMPa starts the first operation.

  When signal OSCa reaches voltage Vref at time T1, signal OUTa goes to L level. When the signal OUTa becomes L level, the clock CKa becomes H level and the signal OSCa decreases. When the signal OSCa falls below the voltage Vrefsub, the signal POFFa becomes H level.

  After time T1, when the signal OSCb gradually increases and reaches the voltage Vrefsub, the sub-comparator CMPsubb outputs an L-level signal POFFb. As a result, the off period of the comparator CMPb ends, and the comparator CMPb starts the second operation.

  When signal OSCb reaches voltage Vref at time T2, signal OUTb attains L level. When the signal OUTb becomes L level, the clock CKb becomes H level and the signal OSCb decreases. When the signal OSCb falls below the voltage Vrefsub, the signal POFFb becomes H level.

  As described above, the delay circuits Da and Db may be configured by the sub-comparators CMPsuba and CMPsubb that operate with low power as in the present embodiment.

  As a result, the transition timings of the signals POFFa and POFFb are less likely to depend on process variations and the like, so that the accuracy of the operation timings of the comparators CMPa and CMPb can be improved, and the power consumption of the relaxation oscillator 1 can be further reduced. Can be planned.

<Third Embodiment>
FIG. 8 is a configuration diagram of a relaxation oscillator according to the third embodiment. In addition, the common code | symbol in FIG. 1 and FIG. 8 shows the same element or signal. In the present embodiment, differences from the first embodiment will be mainly described.

  As shown in FIG. 8, the relaxation oscillator 1 according to the present disclosure can be applied even when one comparator CMP is used.

  Specifically, the oscillation control circuit 20 includes two delay circuits Da and Db, a comparison circuit 22, a latch circuit 26, a selector 28, and switches SWa1, SWa2, SWb1, and SWb2.

  The comparison circuit 22 includes a single comparator CMP that performs the above-described first and second operations. In the present embodiment, the comparator CMP is configured by combining the comparison circuit 22 and the fixed circuit 24 shown in FIG. That is, the comparator CMP has a function of fixing the output to a predetermined logical value when in the off state.

  When the clock CKa is at the L level and the clock CKb is at the H level, the comparator CMP performs a first operation of comparing the signal level of the signal OSCa with the voltage Vref and outputting a signal corresponding to the comparison result. On the other hand, when the clock CKb is at the L level and the clock CKa is at the H level, the comparator CMP performs a second operation of comparing the signal level of the signal OSCb with the voltage Vref and outputting a signal corresponding to the comparison result. The comparator CMP is turned off during a period other than the period during which the first and second operations are performed.

  For example, the selector 28 is configured to be able to switch between the straight output or the cross output according to the clock CKb. Specifically, when the clock CKb is at the H level, the selector 28 is straight-connected as shown by a solid line, and the NAND circuit NDb with the power supply VDD (H level) as the signal OUTb and the output from the comparator CMP with the signal OUTa. Output to the circuit NDa. On the other hand, when the clock CKb is at the L level, cross connection is made as indicated by a broken line, and the power supply VDD is output as the signal OUTa to the NAND circuit NDa, and the output of the comparator CMP is output as the signal OUTb to the NAND circuit NDb.

  The switches SWa1 and SWa2 are turned on when the clock CKa is at H level, for example, and turned off when the clock CKa is at L level. Further, the switches SWb1 and SWb2 are turned on when the clock CKb is at H level, for example, and turned off when the clock CKb is at L level.

  The timing chart showing the operation of the relaxation oscillator 1 according to the present embodiment is the same as FIG.

  As described above, according to the present embodiment, since the relaxation oscillator 1 can be applied even when one comparator CMP is used, the circuit area of the relaxation oscillator 1 can be reduced and the power consumption can be reduced. .

  Here, since the relaxation oscillator of Patent Document 1 is premised on the use of two comparators, it cannot be applied to a case where there is one comparator, and there is a limit to circuit area saving and power consumption reduction.

  On the other hand, since the relaxation oscillator 1 according to the present embodiment can be realized by using one comparator, it is possible to achieve the same effect as the first embodiment and the circuit area saving.

  In the present embodiment, the delay circuits Da and Db may be configured by sub-comparators CMPsuba and CMPsubb shown in FIG.

  In addition, the logical value in each component in each of the above embodiments is an example, and for example, a logical value signal obtained by inverting the logical value of each signal of the entire circuit described above may be handled. In this case, the fixed circuit 24 may include a transistor connected to the power supply VSS and pulling down the output of the comparison circuit 22.

  In each of the above embodiments, the fixed circuit 24 has been described as releasing the fixed output of the comparison circuit 22 at the end of the off period of the comparison circuit 22, but the comparison is delayed after the end of the off period. The fixing of the output of the circuit 22 may be released. For example, after the comparison circuit 22 can normally perform the first and second operations, the fixing circuit 24 releases the fixation of the output of the comparison circuit 22 and outputs the output of the comparison circuit 22 as it is. You may make it do. As a result, the operation of the comparison circuit 22 and thus the operation of the relaxation oscillator 1 can be stabilized.

  The relaxation oscillator according to the present disclosure can be applied to either one or two comparators, and can further reduce power consumption and improve noise characteristics. Therefore, a reference oscillator for a microcomputer, a battery-driven communication device, and the like Useful for.

DESCRIPTION OF SYMBOLS 1 Relaxation oscillator 10 Oscillation circuit 20 Oscillation control circuit 22 Comparison circuit 24 Fixed circuit 30 RC circuit 34 Variable resistance element 36 Variable capacitance element CMP, CMPa, CMPb Comparator CMPsuba, CMPsubb Sub-comparator Da, Db Delay circuit Vref Voltage (first Comparison voltage)
Vrefsub voltage (second comparison voltage)
OSCa signal (first oscillation signal)
OSCb signal (second oscillation signal)
CLKout, CKa Reference clock

Claims (10)

A relaxation oscillator that generates a reference clock,
In response to the transition of the signal level of the reference clock, an operation of increasing the signal level of the first oscillation signal and decreasing the signal level of the second oscillation signal, and increasing the signal level of the second oscillation signal And an oscillation circuit that alternately performs an operation for reducing the signal level of the first oscillation signal; and
A first operation for comparing a signal level of the first oscillation signal with a first comparison voltage and outputting a signal corresponding to the comparison result; a signal level of the second oscillation signal; The comparison that is compared with the comparison voltage and can perform the second operation of outputting a signal according to the comparison result, while being turned off in a period other than the period of performing the first and second operations And when the output of the comparison circuit indicates that the signal level of the first oscillation signal has reached the first comparison voltage, the signal level of the reference clock is set to the first logic level. An oscillation control circuit for transitioning the signal level of the reference clock to a second logic level when the signal level of the second oscillation signal indicates that the first comparison voltage has been reached. ,
A relaxation oscillator comprising: a fixed circuit that fixes an output of the comparison circuit to a predetermined logical value during an off period of the comparison circuit. The relaxation oscillator of claim 1,
The comparison circuit is
A first comparator that performs the first operation while being turned off in a period other than the period for performing the first operation;
A second comparator that performs the second operation and is turned off in a period other than a period for performing the second operation,
The fixed circuit is
In the off period of the first comparator, the output of the first comparator is used as the predetermined logic value to indicate that the signal level of the first oscillation signal is less than the first comparison voltage. Fixed to a logical value,
In the off period of the second comparator, the output of the second comparator is used as the predetermined logic value to indicate that the signal level of the second oscillation signal is less than the first comparison voltage. A relaxation oscillator characterized by being fixed to a logical value. The relaxation oscillator of claim 1,
The comparison circuit includes a comparator that performs the first and second operations, and is turned off in a period other than a period in which the first and second operations are performed.
In the off-period of the comparator, the fixed circuit uses the output of the comparator as the predetermined logic value, and the signal level of one of the first and second oscillation signals is less than the first comparison voltage. A relaxation oscillator characterized by being fixed to a logical value indicating that The relaxation oscillator of claim 1,
The relaxation oscillator is characterized in that the off period of the comparison circuit ends after a predetermined time has elapsed since the signal level of the reference clock transitioned to the first logic level. The relaxation oscillator of claim 4,
A relaxation oscillator comprising a delay circuit for notifying the comparison circuit that the predetermined time has elapsed. The relaxation oscillator of claim 5,
The relaxation oscillator includes an RC circuit having a resistance element and a capacitance element. The relaxation oscillator of claim 1,
Comparison between the second comparison voltage lower than the first comparison voltage and the signal level of the first oscillation signal, and comparison between the second comparison voltage and the signal level of the second oscillation signal And a sub-comparator that outputs a signal corresponding to each comparison result,
The comparison circuit starts the first operation when the output of the sub-comparator indicates that the signal level of the first oscillation signal has reached the second comparison voltage; A relaxation oscillator characterized by starting the second operation when a signal level of an oscillation signal indicates that the second comparison voltage has been reached. The relaxation oscillator of claim 1,
The relaxation oscillator includes a transistor for pulling up or pulling down an output of the comparison circuit. The relaxation oscillator of claim 1,
The relaxation oscillator includes a logic circuit that masks an output of the comparison circuit. The relaxation oscillator of claim 1,
A relaxation oscillator, wherein a current path connecting a power source and a ground is cut off in the comparison circuit during an off period of the comparison circuit.

Images