JP2015103622A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device which substantially inhibits threshold shift in an insulation film and reduces imperfect switching operations to prevent device damages and ensure high reliability.SOLUTION: A semiconductor device comprises: a compound semiconductor laminated structure 2; a gate insulation film 4 formed on the compound semiconductor laminated structure 2; and a gate electrode 7 formed on the gate insulation film 4. In the gate insulation film 4, first parts 4a where a direction of threshold shift in a principal surface of the gate insulation film 4, which is caused by application of voltage from the gate electrode 7 is positive and second parts 4b where a direction of the threshold shift is negative are alternately arranged in parallel with each other.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN that is a nitride semiconductor is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, GaN is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT (GaN-HEMT), AlGaN / GaN.HEMT using GaN as an electron transit layer and AlGaN as an electron supply layer has attracted attention. In AlGaN / GaN.HEMT, strain caused by the difference in lattice constant between GaN and AlGaN is generated in AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization of AlGaN. Therefore, it is expected as a high-efficiency power device for high-efficiency switching elements, electric vehicles and the like.

JP 2011-199286 A JP 2010-50280 A

  In a so-called MIS type GaN-HEMT or the like having a gate insulating film under the gate electrode, when operating by actually applying a high voltage, the threshold during operation fluctuates to the positive side or the negative side from the design value ( Shift). In this case, there is a problem that the switch operation is incomplete and the device is destroyed. The threshold shift occurs depending on whether the trap level of the gate insulating film emits or captures electrons, and the shift direction (positive side or negative side) differs depending on the insulating material of the gate insulating film.

  The present invention has been made in view of the above problems, and a highly reliable semiconductor device that substantially suppresses threshold fluctuations in an insulating film, reduces incomplete switching operation, and suppresses device destruction, and the semiconductor device An object is to provide a manufacturing method.

  One embodiment of a semiconductor device includes a semiconductor region, an insulating film formed above the semiconductor region, and an electrode formed above the insulating film, and the insulating film is within a main surface of the insulating film. The first portion in which the direction of threshold fluctuation caused by the application of the voltage from the electrode is positive and the second portion in which the direction of threshold fluctuation is negative are alternately arranged in parallel.

  One embodiment of a method for manufacturing a semiconductor device includes a step of forming an insulating film above a semiconductor region, and a step of forming an electrode above the insulating film, the insulating film being in a main surface of the insulating film. The first portion in which the direction of threshold fluctuation caused by the application of the voltage from the electrode is positive and the second portion in which the direction of threshold fluctuation is negative are alternately arranged in parallel.

  According to the above aspects, a highly reliable semiconductor device that substantially suppresses threshold fluctuation in the insulating film, reduces incomplete switching operation, and suppresses device destruction is realized.

FIG. 5 is a schematic cross-sectional view showing a method of manufacturing the MIS-type AlGaN / GaN HEMT according to the first embodiment in the order of steps. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1, illustrating a method of manufacturing an AlGaN / GaN HEMT according to the first embodiment of the MIS type in order of processes. It is a schematic sectional drawing which shows the formation method of the gate insulating film in 1st Embodiment in order of a process. FIG. 6 is a characteristic diagram showing a relationship between a gate voltage Vg and a drain current Id in a MIS type AlGaN / GaN HEMT according to a comparative example. FIG. 6 is a characteristic diagram showing a relationship between a gate voltage Vg and a drain current Id in an MIS type AlGaN / GaN HEMT according to an example of the first embodiment. FIG. 6 is a characteristic diagram illustrating a relationship between a gate voltage Vg and a drain current Id in an MIS type AlGaN / GaN HEMT according to another example of the first embodiment. It is a figure which shows the table | surface of the threshold value fluctuation | variation in the MIS type AlGaN / GaN * HEMT by the other example of 1st Embodiment. It is a schematic diagram for demonstrating the mechanism of the effect produced by 1st Embodiment. It is a schematic sectional drawing which shows the main processes of the manufacturing method of AlGaN / GaN * HEMT by 2nd Embodiment. It is a schematic sectional drawing which shows the formation method of the gate insulating film in 2nd Embodiment to process order. It is a connection diagram which shows schematic structure of the power supply device by 3rd Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 4th Embodiment.

(First embodiment)
In the present embodiment, an MIS type AlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
1 to 2 are schematic cross-sectional views showing a method of manufacturing a MIS type AlGaN / GaN.HEMT according to the first embodiment in the order of steps.

First, as shown in FIG. 1A, a compound semiconductor multilayer structure 2 is formed on, for example, a Si substrate 1 as a growth substrate. As the growth substrate, an SiC substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the Si substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.
The compound semiconductor multilayer structure 2 includes a buffer layer 2a, an electron transit layer 2b, and an electron supply layer 2c.

  In the completed AlGaN / GaN HEMT, two-dimensional electron gas (2DEG) is generated in the vicinity of the interface between the electron transit layer 2b and the electron supply layer 2c during the operation. The 2DEG is generated based on a difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 2b and the compound semiconductor (here, AlGaN) of the electron supply layer 2c.

Specifically, the following compound semiconductors are grown on the Si substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.
On the Si substrate 1, AlN is grown to a thickness of about 100 nm, i (intentional undoped) -GaN to a thickness of about 1 μm, and n-AlGaN to a thickness of about 30 nm. Thereby, the buffer layer 2a, the electron transit layer 2b, and the electron supply layer 2c are formed. As the buffer layer 2a, AlGaN may be used instead of AlN, or GaN may be grown at a low temperature. Further, for example, thin AlGaN may be formed as a spacer layer between the electron transit layer 2b and the electron supply layer 2c. For example, thin n-GaN may be formed on the electron supply layer 2c as a cap layer.

As growth conditions for AlN, a mixed gas of trimethylaluminum (TMAl) gas and ammonia (NH ₃ ) gas is used as a source gas. As a growth condition for GaN, a mixed gas of trimethylgallium (TMGa) gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of TMAl gas as an Al source and TMGa gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of NH ₃ gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing AlGaN or the like as n-type, for example, SiH ₄ gas containing, for example, Si as an n-type impurity is added to the source gas at a predetermined flow rate, and AlGaN is doped with Si. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

Subsequently, as shown in FIG. 1B, an element isolation structure 3 is formed. In FIG. 1C and thereafter, illustration of the element isolation structure 3 is omitted.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor multilayer structure 2. Thereby, the element isolation structure 3 is formed in the compound semiconductor multilayer structure 2 and the surface layer portion of the Si substrate 1. An active region is defined on the compound semiconductor stacked structure 2 by the element isolation structure 3.
The element isolation may be performed by using, for example, an STI (Shallow Trench Isolation) method instead of the above-described implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor multilayer structure 2.

Subsequently, a gate insulating film 4 is formed on the compound semiconductor multilayer structure 2 as shown in FIG.
In the main surface, the gate insulating film 4 includes a first portion 4a in which the direction of threshold fluctuation caused by application of a voltage from the gate electrode is positive, and a second portion 4b in which the direction of threshold fluctuation is negative. Are alternately arranged in parallel. In the present embodiment, the first portion 4a and the second portion are formed along the longitudinal direction (gate width direction) in the short direction (gate length direction) of the gate electrode at the portion where the gate electrode is to be formed in the gate insulating film 4. 4b are alternately arranged in parallel.

The insulating material of the first portion 4a is one selected from SiO ₂ , AlN, Al ₂ O ₃ , and HfO ₂ as a material whose threshold fluctuation direction is positive. In the present embodiment, for example, SiO ₂ is used. The insulating material of the second portion 4b is, for example, SiN as a material whose threshold fluctuation direction is negative.

Hereinafter, a method of forming the gate insulating film 4 will be described in detail with reference to FIG. In each drawing of FIG. 3, only the portion above the electron supply layer 2 c of the compound semiconductor multilayer structure 2 is illustrated.
First, as shown in FIG. 3A, the first insulating film 11 is formed on the electron supply layer 2c.
Specifically, SiN, which is the insulating material of the second portion, is deposited to a thickness of about 100 nm, for example, by plasma CVD, for example. Thereby, the first insulating film 11 is formed.

Next, as shown in FIG. 3B, a plurality of through grooves 11 a are formed in the first insulating film 11.
Specifically, a resist is applied to the surface of the first insulating film 11. The resist is processed by lithography, and a plurality of openings are formed in the resist to expose the surface of the first insulating film 11 corresponding to the part where the through groove is to be formed. Thus, a resist mask having the opening is formed. Using this resist mask, the first insulating film 11 is removed by dry etching until the surface of the electron supply layer 2c is exposed. As a result, a plurality of through grooves 11a are formed in the first insulating film 11 where the gate electrode is to be formed. The through grooves 11a have a pitch of, for example, about 100 nm to about 150 nm (the width of the through grooves 11a and the distance between the through grooves 11a are approximately the same value of about 100 nm to 150 nm) in the gate length direction of the gate electrode. The stripes are formed in parallel along the gate width direction.
The resist mask is removed by ashing or wet processing.

Next, as shown in FIG. 3C, a second insulating film 12 is formed on the first insulating film 11.
Specifically, for example, SiO ₂ which is an insulating material of the first portion is deposited on the first insulating film 11 so as to fill the inside of the through groove 11a by plasma CVD, for example. Thereby, the second insulating film 12 is formed.

Next, as shown in FIG. 3D, the second insulating film 12 on the first insulating film 11 is removed.
More specifically, for example, by plasma etching, the second insulating film 12 is removed by etching the portion on the first insulating film 11 while leaving only the portion filling the inside of the through groove 11a. The portion formed by filling the through groove 11a with SiO ₂ is the first portion 4a, and the SiN portion between the first portions 4a is the second portion 4b.
As described above, the gate insulating film 4 is formed in which the first portions 4a and the second portions 4b are alternately arranged in parallel at the portion where the gate electrode is to be formed.

Subsequently, as shown in FIG. 2A, the source electrode 5 and the drain electrode 6 are formed.
Specifically, first, the electrode through grooves 4A and 4B are formed in the gate insulating film 4 at the site where the source electrode and the drain electrode are to be formed.
A resist is applied to the surface of the compound semiconductor multilayer structure 2. The resist is processed by lithography, and an opening is formed in the resist to expose the surface of the compound semiconductor multilayer structure 2 corresponding to the site where the source and drain electrodes are to be formed. Thus, a resist mask having the opening is formed.

Using this resist mask, the source electrode and drain electrode formation planned portions of the gate insulating film 4 are removed by dry etching until the surface of the electron supply layer 2c is exposed. As described above, the electrode through grooves 4A and 4B are formed in the gate insulating film 4 so as to expose the portions where the source and drain electrodes are to be formed on the surface of the electron supply layer 2c.
The resist mask is removed by ashing or wet processing.

A resist mask for forming the source electrode and the drain electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor multilayer structure 2 to form openings that expose the electrode through grooves 4A and 4B. Thus, a resist mask having the opening is formed.
Using this resist mask, for example, Ta / Al (the lower layer is Ta and the upper layer is Al) is deposited as an electrode material on the resist mask including the inside of the opening through which the electrode through grooves 4A and 4B are exposed, for example, by vapor deposition. To do. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thereafter, the Si substrate 1 is heat-treated in a nitrogen atmosphere, for example, at a temperature of about 400 ° C. to 1000 ° C., for example, about 600 ° C., and the remaining Ta / Al is brought into ohmic contact with the electron supply layer 2c. If ohmic contact with the Ta / Al electron supply layer 2c is obtained, heat treatment may be unnecessary. As a result, the source electrode 5 and the drain electrode 6 are formed in which the electrode through grooves 4A and 4B are embedded with part of the electrode material.

Subsequently, as shown in FIG. 2B, a gate electrode 7 is formed.
Specifically, first, a resist mask for forming the gate electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied on the gate insulating film 4 to form openings for exposing the first and second portions 4a and 4b (parts where the gate electrode is to be formed) of the gate insulating film 4. Thus, a resist mask having the opening is formed.

  Using this resist mask, as an electrode material, for example, Ni / Au (the lower layer is Ni and the upper layer is Au), for example, an opening that exposes the first and second portions 4a and 4b of the gate insulating film 4 by vapor deposition. Deposit on the resist mask including the inside. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 7 is formed on the first and second portions 4a and 4b of the gate insulating film 4.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 5, drain electrode 6, and gate electrode 7, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. Then, the MIS type AlGaN / GaN HEMT according to the present embodiment is formed.

  Hereinafter, simulation experiments conducted to explain the operational effects of the MIS type AlGaN / GaN HEMT according to the present embodiment based on the comparison with the comparative example will be described.

First, Comparative Example 1 and Comparative Example 2 are presented as comparative examples of the present embodiment. In Comparative Example 1, an AlGaN / GaN HEMT having a single insulating material, which is a single-layer gate insulating film made of SiN, is used in which the direction of threshold fluctuation caused by voltage application is negative. In Comparative Example 2, an AlGaN / GaN HEMT having a single insulating material having a positive threshold fluctuation direction, here, a single-layer gate insulating film made of AlN having the same properties as SiO ₂ was used.

The relationship between the gate voltage Vg and the drain current Id in AlGaN / GaN.HEMT was examined by simulation.
In Comparative Example 1, as shown in FIG. 4A, it was confirmed that when a voltage of about 400 V was applied to the terminal of the drain electrode, the threshold value shifted greatly to the negative side. In Comparative Example 2, as shown in FIG. 4B, it was confirmed that when a voltage of about 400 V was applied to the terminal of the drain electrode, the threshold value shifted greatly to the positive side.

  As the AlGaN / GaN HEMT according to the present embodiment, a HEMT having a gate insulating film in which a first portion whose threshold fluctuation direction is positive is AlN and a second portion whose threshold fluctuation direction is negative is SiN. Present. In this embodiment, as shown in FIG. 5, even when a voltage of about 400 V is applied to the drain electrode terminal, the threshold is hardly changed, and fluctuations in the threshold before and after the voltage application are suppressed. Was confirmed.

Further, as the AlGaN / GaN HEMT according to the present embodiment, the first portion whose threshold fluctuation direction is positive is SiO ₂ , and the _second portion whose threshold fluctuation direction is negative is SiN. We present a HEMT with In the present embodiment, the thickness of the gate insulating film is about 50 nm, and the first portion and the second portion are alternately arranged at a pitch of about 100 nm. The drain current was calculated by setting the drain voltage to 20V and sweeping the gate voltage from + 1V to -15V. From the calculation result, the gate voltage at which the drain current is 1 μA / mm was set as the threshold value.

The simulation result is shown in FIG. In FIG. 6, the characteristics in the initial state, the characteristics in which the threshold value is shifted by + 1V and the second part Si ₂ are + 1V, and the SiO _{2 in} the first part is + 2V, The characteristic of the state where the threshold value of SiN in the portion 2 is shifted by −2V is shown. Even if the threshold voltage variation of 2V occurs in the first part and the second part by using the gate insulating film having a structure in which the first part and the second part are alternately arranged as in the present embodiment. It was confirmed that the amount of variation in the threshold value was reduced and the variation in threshold value from the initial state was suppressed.

In the gate insulating film of this embodiment, the threshold shift of the same magnitude is not necessarily generated in the first part and the second part. Therefore, when the shift amount of the threshold value is different between the SiO ₂ of the first portion and the SiN of the second portion, the threshold value was calculated within the range of the shift amount within 2V. The result is shown in FIG. In FIG. 7, (a) shows the threshold shift amount, and (b) shows the difference from the initial value. As shown in FIG. 7, when threshold shifts having different magnitudes occur in each of the first part and the second part, it was confirmed that the threshold fluctuation from the initial state was suppressed to a small level.

Based on the result of the above simulation experiment, the mechanism of the effect produced by this embodiment is demonstrated.
As shown in FIG. 8, the insulating material of the second part, such as SiN, is stable in a state where electrons are trapped in the trap level. When a high voltage is applied to this, the trapped electrons are emitted. Electrons are easily attracted to the channel due to the influence of electrons being removed, and as a result, the threshold value shifts from the initial value to the negative side.
On the other hand, the insulating material of the first portion, such as SiO ₂ and AlN, is stable in the absence of electrons at the trap level. When a high voltage is applied to this, electrons are trapped. The electrons in the channel are moved away due to the trapped electrons, and as a result, the threshold value shifts from the initial value to the positive side.

  The threshold fluctuation occurs due to electron capture or electron emission of the gate insulating film. As in Comparative Examples 1 and 2 described above, the gate insulating film has a positive or negative threshold fluctuation caused by voltage application due to its insulating material. The trap order is unavoidable for the gate insulating film, and it is extremely difficult to bring this threshold fluctuation close to zero. In this embodiment, paying attention to this fact, the gate insulating film is configured by alternately arranging the first portion where the positive threshold fluctuation occurs due to the voltage application and the second part where the negative threshold fluctuation occurs. The threshold fluctuations are offset between adjacent portions to suppress the threshold fluctuations in the entire film.

  As described above, according to the present embodiment, a highly reliable MIS-type AlGaN / GaN that substantially suppresses threshold fluctuation in the gate insulating film, reduces incomplete switching operation, and suppresses device destruction. -HEMT is realized.

(Second Embodiment)
In the present embodiment, as in the first embodiment, MIS type AlGaN / GaN HEMT is disclosed, but is different in that the configuration of the gate insulating film is different. In addition, about the same thing as the structural member of 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
FIG. 9 is a schematic cross-sectional view showing the main steps of the method of manufacturing the MIS type AlGaN / GaN HEMT according to the second embodiment.

In the present embodiment, as in the first embodiment, first, the steps of FIGS. 1A to 1B are performed. At this time, an element isolation structure 3 that defines an active region on the compound semiconductor multilayer structure 2 is formed.
Subsequently, as illustrated in FIG. 9A, a gate insulating film 21 is formed on the compound semiconductor multilayer structure 2.
The main surface of the gate insulating film 21 includes a first portion 21a in which the direction of threshold fluctuation caused by application of a voltage from the gate electrode is positive, and a second portion 21b in which the direction of threshold fluctuation is negative. Are alternately arranged in parallel. In the present embodiment, the first portion 21 a and the second portion are formed along the longitudinal direction (gate width direction) in the short direction (gate length direction) of the gate electrode at the portion where the gate electrode is to be formed in the gate insulating film 21. 21b are alternately arranged in parallel.

  The insulating materials of the first portion 21a and the second portion 21b are both SiON. As the oxygen content of SiON increases, the threshold shift increases in the positive direction, and as the oxygen content decreases, the threshold shift increases in the negative direction. The SiON in the first portion 21a has a higher oxygen content than the SiON in the second portion 21b. For example, the oxygen content of the first portion 21a is 50% or more, and the oxygen content of the second portion 21b is less than 50%.

Hereinafter, a method for forming the gate insulating film 21 will be described in detail with reference to FIG. In each drawing of FIG. 10, only the portion above the electron supply layer 2 c of the compound semiconductor multilayer structure 2 is illustrated.
First, as shown in FIG. 10A, a first insulating film 22 is formed on the electron supply layer 2c.
Specifically, SiON having a small oxygen content, which is an insulating material of the second portion, is deposited to a thickness of, for example, about 100 nm by, for example, plasma CVD. Thereby, the first insulating film 22 is formed.

Next, as shown in FIG. 10B, a plurality of through grooves 22 a are formed in the first insulating film 22.
Specifically, a resist is applied to the surface of the first insulating film 22. The resist is processed by lithography, and a plurality of openings are formed in the resist to expose the surface of the first insulating film 22 corresponding to the portion where the through groove is to be formed. Thus, a resist mask having the opening is formed. Using this resist mask, the first insulating film 22 is removed by dry etching until the surface of the electron supply layer 2c is exposed. As described above, a plurality of through grooves 22a are formed in the gate electrode formation scheduled portion of the first insulating film 22. The through grooves 22a have a pitch of, for example, about 100 nm to about 150 nm (the width of the through grooves 22a and the distance between the through grooves 22a are approximately the same value of about 100 nm to 150 nm) in the gate length direction of the gate electrode. The stripes are formed in parallel along the gate width direction.
The resist mask is removed by ashing or wet processing.

Next, as shown in FIG. 10C, a second insulating film 23 is formed on the first insulating film 22.
Specifically, for example, SiON having a high oxygen content, which is an insulating material of the first portion, is deposited on the first insulating film 22 so as to fill the through groove 22a by plasma CVD. Thereby, the second insulating film 23 is formed.

Next, as shown in FIG. 10D, the second insulating film 23 on the first insulating film 22 is removed.
Specifically, for example, by plasma etching, the portion of the second insulating film 23 on the first insulating film 22 is removed by etching while leaving only the portion filling the inside of the through groove 22a. A portion formed by filling the inside of the through groove 22a with SiON having a high oxygen content is a first portion 21a, and a portion of SiON having a low oxygen content between the first portions 21a is a second portion 21b.
As described above, the gate insulating film 21 in which the first portions 21a and the second portions 21b are alternately arranged in parallel is formed at the portion where the gate electrode is to be formed.

  Thereafter, similarly to the first embodiment, the processes of FIGS. 2A to 2B are performed. A state corresponding to FIG. 2B is shown in FIG.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 5, drain electrode 6, and gate electrode 7, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. Then, the MIS type AlGaN / GaN HEMT according to the present embodiment is formed.

  As described above, according to the present embodiment, a highly reliable MIS-type AlGaN / GaN that substantially suppresses threshold fluctuation in the gate insulating film, reduces incomplete switching operation, and suppresses device destruction. -HEMT is realized.

(Third embodiment)
In the present embodiment, a power supply device to which the AlGaN / GaN HEMT according to the first or second embodiment is applied is disclosed.
FIG. 11 is a connection diagram illustrating a schematic configuration of the power supply device according to the third embodiment.

The power supply device according to this embodiment includes a high-voltage primary circuit 31 and a low-voltage secondary circuit 32, and a transformer 33 disposed between the primary circuit 31 and the secondary circuit 32. The
The primary circuit 31 includes an AC power supply 34, a so-called bridge rectifier circuit 35, and a plurality (four in this case) of switching elements 36a, 36b, 36c, and 36d. The bridge rectifier circuit 35 includes a switching element 36e.
The secondary side circuit 32 includes a plurality (three in this case) of switching elements 37a, 37b, and 37c.

  In the present embodiment, the switching elements 36a, 36b, 36c, 36d, and 36e of the primary side circuit 31 are the AlGaN / GaN HEMTs of the first or second embodiment. On the other hand, the switching elements 37a, 37b, and 37c of the secondary circuit 32 are normal MIS • FETs using silicon.

  In the present embodiment, a highly reliable MIS type AlGaN / GaN HEMT that substantially suppresses threshold fluctuations in the gate insulating film, reduces incomplete switching operation, and suppresses device destruction is applied to a high-voltage circuit. To do. As a result, a highly reliable high-power power supply circuit is realized.

(Fourth embodiment)
In the present embodiment, a high-frequency amplifier to which the AlGaN / GaN HEMT according to the first or second embodiment is applied is disclosed.
FIG. 12 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the fourth embodiment.

The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 41, mixers 42a and 42b, and a power amplifier 43.
The digital predistortion circuit 41 compensates for nonlinear distortion of the input signal. The mixer 42a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 43 amplifies the input signal mixed with the AC signal, and includes the AlGaN / GaN HEMT according to the first or second embodiment. In FIG. 12, for example, by switching the switch, the output-side signal is mixed with the AC signal by the mixer 42b and sent to the digital predistortion circuit 41.

  In this embodiment, a highly reliable MIS type AlGaN / GaN HEMT that substantially suppresses threshold fluctuations in the gate insulating film, reduces incomplete switching operation, and suppresses device destruction is applied to a high-frequency amplifier. To do. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first to fourth embodiments, AlGaN / GaN.HEMT is exemplified as the compound semiconductor device. As a compound semiconductor device, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

・ Other HEMT examples 1
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first to fourth embodiments described above, the electron transit layer is formed of i-GaN and the electron supply layer is formed of n-InAlN. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by the spontaneous polarization of InAlN.

  According to this example, similarly to the AlGaN / GaN HEMT described above, a highly reliable MIS type that substantially suppresses threshold fluctuations in the gate insulating film, reduces incomplete switching operation, and suppresses device destruction. InAlN / GaN.HEMT is realized.

・ Other HEMT examples 2
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first to fourth embodiments described above, the electron transit layer is formed of i-GaN and the electron supply layer is formed of n-InAlGaN.

  According to this example, similarly to the AlGaN / GaN HEMT described above, a highly reliable MIS type that substantially suppresses threshold fluctuations in the gate insulating film, reduces incomplete switching operation, and suppresses device destruction. InAlGaN / GaN.HEMT is realized.

  Hereinafter, various aspects of the semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as additional notes.

(Appendix 1) a semiconductor region;
An insulating film formed above the semiconductor region;
An electrode formed above the insulating film, and
In the main surface of the insulating film, the insulating film includes a first portion in which a direction of threshold fluctuation caused by application of a voltage from the electrode is positive, and a second portion in which the direction of threshold fluctuation is negative. Is alternately arranged in parallel.

  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the insulating film is configured such that the first portion and the second portion are alternately arranged in parallel along a short direction of the electrode. .

(Supplementary Note 3) The insulating layer, the insulating material of the first portion is SiO _2, AlN, Al ₂ O _3, 1 kind selected from HfO _2, said second portion is SiN The semiconductor device according to appendix 1 or 2, which is characterized.

  (Supplementary Note 4) The insulating film is such that the insulating material of the first portion and the second portion is both SiON, and the first portion has a higher oxygen content than the second portion. The semiconductor device according to appendix 1 or 2, which is characterized.

(Appendix 5) Forming an insulating film above the semiconductor region;
Forming an electrode above the insulating film,
In the main surface of the insulating film, the insulating film includes a first portion in which a direction of threshold fluctuation caused by application of a voltage from the electrode is positive, and a second portion in which the direction of threshold fluctuation is negative. Are alternately arranged in parallel, and a method for manufacturing a semiconductor device.

  (Supplementary note 6) The semiconductor device according to supplementary note 5, wherein the insulating film is configured such that the first portion and the second portion are alternately arranged in parallel along a short direction of the electrode. Manufacturing method.

(Supplementary Note 7) The insulating layer, the insulating material of the first portion is SiO _2, AlN, Al ₂ O _3, 1 kind selected from HfO _2, the insulating material of the second portion of SiN 7. A method for manufacturing a semiconductor device according to appendix 5 or 6, wherein:

  (Additional remark 8) As for the said insulating film, both the insulating material of the said 1st part and the said 2nd part is SiON, and the said 1st part has a higher oxygen content than the said 2nd part. The method for manufacturing a semiconductor device according to appendix 5 or 6, wherein the method is characterized in that:

(Supplementary note 9) A power supply circuit including a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A semiconductor region;
An insulating film formed above the semiconductor region;
An electrode formed above the insulating film, and
In the main surface of the insulating film, the insulating film includes a first portion in which a direction of threshold fluctuation caused by application of a voltage from the electrode is positive, and a second portion in which the direction of threshold fluctuation is negative. Are alternately arranged in parallel.

(Appendix 10) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A semiconductor region;
An insulating film formed above the semiconductor region;
An electrode formed above the insulating film, and
In the main surface of the insulating film, the insulating film includes a first portion in which a direction of threshold fluctuation caused by application of a voltage from the electrode is positive, and a second portion in which the direction of threshold fluctuation is negative. Are arranged alternately in parallel.

DESCRIPTION OF SYMBOLS 1 Si substrate 2 Compound semiconductor laminated structure 2a Buffer layer 2b Electron transit layer 2c Electron supply layer 3 Element isolation structure 4, 21 Gate insulating film 4a, 21a First part 4b, 21b Second part 4A, 4B, 21A, 21B Electrode through groove 5 Source electrode 6 Drain electrode 7 Gate electrodes 11 and 22 First insulating films 11a and 22a Through grooves 12 and 23 Second insulating film 31 Primary side circuit 32 Secondary side circuit 33 Transformer 34 AC power supply 35 Bridge Rectifier circuit 36a, 36b, 36c, 36d, 36e, 37a, 37b, 37c Switching element 41 Digital predistortion circuit 42a, 42b Mixer 43 Power amplifier

Claims (8)

A semiconductor region;
An insulating film formed above the semiconductor region;
An electrode formed above the insulating film, and
In the main surface of the insulating film, the insulating film includes a first portion in which a direction of threshold fluctuation caused by application of a voltage from the electrode is positive, and a second portion in which the direction of threshold fluctuation is negative. Is alternately arranged in parallel.   2. The semiconductor device according to claim 1, wherein the insulating film includes the first portion and the second portion that are alternately arranged in parallel along a short direction of the electrode. In the insulating film, the insulating material of the first portion is one selected from SiO ₂ , AlN, Al ₂ O ₃ , and HfO ₂ , and the second portion is SiN. Item 3. The semiconductor device according to Item 1 or 2.   The insulating film is characterized in that both of the insulating materials of the first portion and the second portion are SiON, and the first portion has a higher oxygen content than the second portion. Item 3. The semiconductor device according to Item 1 or 2. Forming an insulating film above the semiconductor region;
Forming an electrode above the insulating film,
In the main surface of the insulating film, the insulating film includes a first portion in which a direction of threshold fluctuation caused by application of a voltage from the electrode is positive, and a second portion in which the direction of threshold fluctuation is negative. Are alternately arranged in parallel, and a method for manufacturing a semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the insulating film is formed by alternately arranging the first portion and the second portion along a short direction of the electrode. . In the insulating film, the insulating material of the first portion is one selected from SiO ₂ , AlN, Al ₂ O ₃ , and HfO ₂ , and the insulating material of the second portion is SiN. A method for manufacturing a semiconductor device according to claim 5 or 6.   The insulating film is characterized in that both of the insulating materials of the first portion and the second portion are SiON, and the first portion has a higher oxygen content than the second portion. Item 7. A method for manufacturing a semiconductor device according to Item 5 or 6.

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