JP2015100006A - Injection-type phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To widen the lock range of an injection-type phase synchronization circuit.SOLUTION: An injection-type phase synchronization circuit includes: a reference signal source 1; a control-voltage generation circuit (a phase comparison circuit 21, a charge pump 22, a filter 23, and a divider 24) generating a control voltage Vfor controlling the frequency of an output signal fof the injection-type phase synchronization circuit by using a reference signal ffrom the reference signal source 1 and the output signal f; a harmonic mixer 3 mixing the reference signal fand the output signal f; a band-pass filter 4 passing only the frequency of the output signal ffrom a signal outputted from the harmonic mixer 3; and an injection-type synchronous oscillator 5 generating the output signal fby the frequency of a signal fpassed through the band-pass filter 4 and the control voltage V.

Description

  The present invention relates to an injection type phase locked loop circuit.

  Phase locked loops (PLLs) used for frequency control in communication transmission / reception circuits include ring type, LC type, and injection locking type.

  In the ring type and LC type, an increase in power consumption is essentially inevitable for improving the phase noise.

  FIG. 10 is a diagram illustrating an injection type phase locked loop according to Conventional Example 1, and FIG. 11 is a diagram illustrating a frequency spectrum of each part in Conventional Example 1.

As shown in FIG. 10, in the injection type phase locked loop circuit, a signal f _inj having the same frequency is generated from a reference signal f _ref of a reference signal source by a pulse signal source and the like, and this is _supplied to an injection type synchronous oscillator. the output signal _{f o} having N times the frequency of the frequency signal _{f inj} (frequency of the reference signal _{f ref)} is obtained.

Phase noise of the output signal f _o, regardless of the power consumption and determined by the phase noise of the reference signal source, the use of a low-noise reference signal source, it is possible to reduce power consumption and low noise.

However, when the signal f _inj is applied to the injection synchronous oscillator, as shown in FIG. 11, inside the signal f _inj and the output signal f _o of the injection synchronous oscillator cause intermodulation, many of the output signal f _o Spurious occurs.

Figure 12 is a diagram showing the relationship between the frequency of the control voltage _{V ctrl} and the output signal _{f o} in the prior art 1.

Frequency of the output signal _{f o} is the predetermined interval in the control voltage _{V ctrl} (lock range) is locked to N times the frequency of the signal _{f inj.} However, if the lock range is not reached, there is a possibility of being erroneously locked to (N + 1) times or (N-1) times.

  The injection type synchronous oscillator can remove high-frequency harmonics with a built-in filter, but cannot remove low-frequency harmonics. Therefore, spurious due to this lower frequency harmonic occurs (FIG. 11), and jitter increases.

  FIG. 13 is a diagram illustrating an injection-type phase locked loop according to Conventional Example 2, and FIG. 14 is a diagram illustrating a frequency spectrum of each part in Conventional Example 2.

For example, by providing a high-pass filter as shown in FIG. 13, lower frequency harmonics in the signal _finj are reduced and spurious are also reduced as shown in FIG.

  However, the above-mentioned erroneous lock must be avoided, so that the cut-off frequency cannot be made sufficiently high.

Figure 15 is a diagram showing the relationship between the frequency of the control voltage _{V ctrl} and the output signal _{f o} in the conventional example 2.

As shown in FIG. 15, the lock range is narrower than in the first conventional example. Further, in order to strictly control the phase of the output signal f _o, the higher the gain of the feedback signal f _inj, the stability of the output signal f _o decreases.

Jri Lee, "Study of Subharmonically Injection-Locked PLLs", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 5, pp. 1539-1553, MAY 2009 Sang-Yi Li et al., “Low Phase Noise Ring VCO Type PLL Using Injection Locking”, 2010 IEICE Electronics Society Conference, C-12-36, September 2010 Sang_yeop Lee et al., "A Multi-Band Quadrature Clock Generator WithHigh-Pass-Filtered Pulse Injection Technique", IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 23, NO. 2, pp. 96-98, FEBRUARY 2013

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an injection type phase locked loop circuit capable of widening the lock range.

  In order to solve the above-described problems, the present invention provides a reference signal source and a control voltage for controlling the frequency of an output signal in the injection type phase locked loop in the injection type phase locked loop from the reference signal source. A control voltage generation circuit that generates using a reference signal and the output signal, a harmonic mixer that mixes the reference signal and the output signal, and only the frequency of the output signal from the signal output from the harmonic mixer And an injection locked oscillator that generates the output signal based on the frequency of the signal that has passed through the bandpass filter and the control voltage.

  According to the present invention, the lock range of the injection type phase locked loop can be widened.

It is a figure which shows the injection type phase locked loop circuit concerning 1st Embodiment. It is a figure which shows the frequency spectrum of each part in FIG. It is a diagram showing the relationship between the frequency of the control voltage V _ctrl and the output signal f _o in the first embodiment. It is a figure which shows the injection type | mold phase-locked loop concerning 2nd Embodiment. It is a figure which shows the injection type | mold phase locked loop circuit concerning 3rd Embodiment. It is a figure which shows the injection type phase locked loop circuit which concerns on 4th Embodiment. It is a figure which shows the injection type | mold phase-locked loop concerning 5th Embodiment. It is a figure which shows the injection type | mold phase-locked loop concerning 6th Embodiment. It is a figure which shows the dominance for every characteristic about the injection | pouring type phase-locked loop circuit which concerns on each embodiment, and the conventional injection | pouring type | mold phase-locked loop circuit. It is a figure which shows the injection type | mold phase locked loop circuit concerning the prior art example 1. FIG. It is a figure which shows the frequency spectrum of each part in the prior art example 1. FIG. It is a diagram showing the relationship between the frequency of the control voltage V _ctrl and the output signal f _o in the prior art 1. It is a figure which shows the injection type | mold phase-locked loop concerning the prior art example 2. FIG. It is a figure which shows the frequency spectrum of each part in the prior art example 2. FIG. It is a diagram showing the relationship between the frequency of the control voltage V _ctrl and the output signal f _o in the conventional example 2.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the present embodiment, the same or similar components are assigned the same reference numerals, and redundant description is omitted.

  FIG. 1 is a diagram showing an injection type phase locked loop circuit according to the first embodiment.

Injection phase synchronizing circuit includes a reference signal source 1, the injection phase the control voltage V _ctrl for controlling the frequency of the output signal f _o in the synchronization circuit, the reference signal from the reference signal source 1 f _ref and the output signal f control voltage generating circuit for generating by using the _o (phase comparison circuit 21, a charge pump 22, filter 23 and frequency divider 24), a harmonic mixer 3 for mixing a reference signal _{f ref} and the output signal _{f o,} a bandpass filter 4 which passes only the frequency of the output signal f _o from the signal output from the harmonic mixer 3, an output signal f _o by the frequency of the signal f _inj which has passed through the band-pass filter 4 and the control voltage V _ctrl And an injection type synchronous oscillator 5 to be generated.

  The injection type phase locked loop circuit is composed of two systems of feedback, so-called charge pump PLL feedback and injection locked signal generation feedback.

The charge pump PLL feedback includes the reference signal source 1, the frequency divider 24 that _divides the output signal fo by the frequency division ratio N, the phase comparison circuit 21 that compares the output of the frequency divider 24 and the reference signal f _ref , and the phase comparison The circuit includes a charge pump 22 that converts the output of the circuit 21 into a current signal, and a filter 23 that passes the DC component of the current signal, converts it into a voltage signal, and outputs the voltage signal to the injection type synchronous oscillator 5. The charge pump PLL feedback, the frequency of the output signal f _o is controlled to be N (frequency division ratio) times the frequency of the reference signal f _ref.

Injection locked signal generator feedback, composed of a harmonic mixer 3, a bandpass filter 4 which passes only the frequency of the output signal f _o from the signal output from the harmonic mixer 3 for mixing a reference signal f _ref and the output signal f _o Is done.

  FIG. 2 is a diagram showing the frequency spectrum of each part in FIG.

The reference signal f _ref and the output signal f _o has a harmonic due to the nonlinearity of the circuit. With a signal having a harmonic as the signal f _inj, harmonics generated in the output signal f _o. Therefore, harmonics other than the frequency of the output signal f _o by the band-pass filter 4 is reduced. Thereby reduce jitter in the output signal f _o.

Figure 3 is a diagram showing the relationship between the frequency of the control voltage _{V ctrl} and the output signal _{f o.}

As described above, the frequency of the signal f _inj is the same as the frequency of the output signal f _o. In the conventional example, since N times the frequency of the signal f _inj is the frequency of the output signal f _o, the frequency of the signal f _inj is higher than the conventional example. Lock range (range of the control voltage _{V ctrl,} which can be fixed to N times the frequency of the reference signal _{f ref} of the frequency of the output signal _{f o)} is, since widely depending on the frequency of the signal _{f inj,} it wider lock range. Therefore, can be fixed to N times the frequency of the reference signal _{f ref} of the frequency of the control voltage _{V ctrl} is slightly displaced even if the output signal _{f o.} That is, it is possible to prevent erroneous lock. The frequency of the output signal _{f o,} because a short time the frequency of the signal _{f inj,} time from powered on until the frequency of the output signal _{f o} is the frequency of the signal _{f inj,} i.e., PLL settling time Can be shortened.

  FIG. 4 is a diagram showing an injection type phase locked loop circuit according to the second embodiment.

  In the first embodiment, the phase comparison circuit 21, the charge pump 22, the filter 23, and the frequency divider 24 are used as the control voltage generation circuit. However, the phase locked loop (PLL), the frequency locked loop (FLL), and the delay Other configurations such as Locked Loop (DLL) may be used. Also, such a configuration may be used in the embodiments described later.

  FIG. 5 is a diagram showing an injection type phase locked loop circuit according to the third embodiment.

The injection type phase locked loop circuit includes a pulse signal source 6 that increases the harmonic power of the reference signal f _{ref in} comparison with the first embodiment, and the harmonic mixer 3 includes the increased reference signal f _ref. characterized by mixing the output signal f _o and '.

Thus, the strength of the frequency of the output signal f _o in the signal from the harmonic mixer 3 is increased, thereby enabling more stable phase synchronization.

Note that, as the pulse width of the reference signal f _ref ′ output from the pulse signal source 6 is reduced, the harmonic power in the reference signal f _ref ′ increases, and the intensity of the signal f _inj increases.

In particular, this becomes more prominent as the ratio (f _o / f _ref ) of the frequency of the output signal f _o and the reference signal f _ref increases.

  FIG. 6 is a diagram showing an injection type phase locked loop circuit according to the fourth embodiment.

  The injection type phase locked loop circuit is characterized in that the harmonic mixer 3 and the band pass filter 4 have an adjustment function in comparison with the first embodiment.

Harmonic mixer 3 and the band-pass filter 4, (N times the frequency of the reference signal f _ref) frequency of the output signal f _o is adjusted to securely pass through the band pass filter 4. This is effective when the power of the signal f _inj (having a frequency N times that of the reference signal f _ref ) is insufficient to obtain stable synchronization.

  FIG. 7 is a diagram showing an injection type phase locked loop circuit according to the fifth embodiment.

Injection phase synchronization circuit, in comparison with the fourth embodiment, the jitter detection circuit 7 for detecting the jitter of the output signal f _o, on the basis of a signal from the jitter detection circuit 7, so jitter is reduced A harmonic mixer 3 and a controller 8 that adjusts the band-pass filter 4 are provided. In this injection type phase locked loop circuit, for example, the harmonic mixer 3 and the band pass filter 4 are automatically adjusted so that the signal f _inj has a frequency that minimizes the jitter.

  FIG. 8 is a diagram showing an injection type phase locked loop circuit according to the fifth embodiment.

In the injection type phase locked loop circuit, the frequency divider 24 _divides the quadrature component Q of the output signal fo in comparison with the first embodiment, and the harmonic mixer 3 receives the reference signal f _ref. is intended to mix the in-phase component I of the output signal _{f o,} bandpass filter 4, the signal MI after mixing of the reference signal _{f ref-phase} component I, the reference signal _{f ref} quadrature component _f ref -Q of it is intended to pass only the frequency of the output signal f _o from the signal M after adding the signal MQ after mixing the quadrature component Q and.

Moreover, the injection locking oscillator, and the quadrature component detecting circuit 9 for detecting the quadrature component _{f ref} -Q, and harmonic mixer 10 for mixing the orthogonal component _{f ref} -Q and quadrature component Q, the reference signal _{f ref-phase} component And an adder 11 that adds the signal MI after mixing I and the signal after mixing the quadrature component f _ref -Q and the quadrature component Q.

According to this injection phase synchronization circuit, compared with the first embodiment, since the harmonics in the signal (signal M) to the bandpass filter 4 is reduced, the intensity of the output signal f _o increases, synchronization is stable To do.

  FIG. 9 is a diagram showing superiority or inferiority for each characteristic of the injection type phase locked loop according to each embodiment and the injection type phase locked loop of the conventional example.

  In Conventional Example 1, all of jitter, spurious, lock range, and erroneous lock are bad, and in Conventional Example 2, spurious is slightly improved.

  In the first embodiment and the second embodiment, good characteristics are obtained with respect to spurious, lock range, and erroneous lock, and jitter is also improved from the conventional example.

  In the third embodiment, good characteristics are obtained with respect to the lock range and erroneous lock, the jitter is also improved from the conventional example, and the spurious is improved from the conventional example 1.

  In the fourth embodiment, good characteristics can be obtained with respect to jitter, spurious, lock range, and erroneous lock.

  In the fifth embodiment, good characteristics can be obtained with respect to spurious, lock range, and erroneous lock, and even better characteristics can be obtained with respect to jitter.

  In the sixth embodiment, good characteristics can be obtained for jitter, lock range, and erroneous lock, and even better characteristics can be obtained for spurious.

DESCRIPTION OF SYMBOLS 1 ... Reference signal source 3 ... Harmonic mixer 4 ... Band pass filter 5 ... Injection type | mold synchronous oscillator 6 ... Pulse signal source 7 ... Jitter detection circuit 8 ... Controller 9 ... Orthogonal component detection circuit 10 ... Harmonic mixer 11 ... Adder 21 ... Phase comparison circuit 22 ... Charge pump 23 ... Filter 24 ... Frequency divider

Claims (5)

In the injection type phase locked loop,
A reference signal source;
A control voltage generation circuit for generating a control voltage for controlling the frequency of the output signal in the injection type phase locked loop circuit using the reference signal from the reference signal source and the output signal;
A harmonic mixer for mixing the reference signal and the output signal;
A bandpass filter that passes only the frequency of the output signal from the signal output from the harmonic mixer;
An injection-type phase-locked circuit comprising: an injection-locked oscillator that generates the output signal based on the frequency of the signal that has passed through the band-pass filter and the control voltage. A pulse signal source for increasing the power of harmonics of the reference signal from the reference signal source,
2. The injection type phase locked loop circuit according to claim 1, wherein the harmonic mixer mixes the increased reference signal and the output signal.   2. The injection type phase locked loop circuit according to claim 1, wherein the harmonic mixer and the band pass filter have an adjustment function. A jitter detection circuit for detecting jitter of the output signal;
The injection type phase locked loop circuit according to claim 3, further comprising: a controller that adjusts the harmonic mixer and the band pass filter so that the jitter is reduced based on a signal from the jitter detection circuit. The injection type phase locked loop circuit is
A frequency divider for dividing the orthogonal component of the output signal;
The harmonic mixer is for mixing the reference signal and the in-phase component of the output signal,
The bandpass filter is obtained by adding the signal after mixing the in-phase component of the reference signal and the output signal, and the signal after adding the signal obtained by mixing the quadrature component of the reference signal and the quadrature component of the output signal. It only allows the frequency of the output signal to pass,
The injection type phase locked loop circuit is
An orthogonal component detection circuit for detecting an orthogonal component of the reference signal;
A second harmonic mixer for mixing the orthogonal component of the reference signal and the orthogonal component of the output signal;
An adder that adds a signal obtained by mixing the reference signal and the in-phase component of the output signal, a quadrature component of the reference signal, and a signal obtained by mixing the quadrature component of the output signal; The injection type phase locked loop circuit according to claim 1.