JP2015095525A - Semiconductor circuit device manufacturing method and semiconductor circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor circuit device and a semiconductor circuit device, which is a reference voltage circuit device used in the space and which can reduce fluctuation in reference voltage.SOLUTION: A semiconductor circuit device manufacturing method comprises the steps of: manufacturing a reference voltage circuit device composed of a depression MOSFET and an enhancement MOSFET; subsequently measuring a threshold voltage of each of the depression MOSFET and the enhancement MOSFET; subsequently, after exposure to radiation, measuring each a threshold voltage of each of the depression MOSFET and the enhancement MOSFET again; subsequently calculating a fluctuation amount of the threshold voltage of each of the depression MOSFET and the enhancement MOSFET after exposure to radiation; and subsequently manufacturing a reference voltage circuit device having the element size suitable for use in the space based on the fluctuation amount of the threshold voltage.

Description

  The present invention relates to a method for manufacturing a semiconductor circuit device and a semiconductor circuit device.

  In order to stabilize circuit operations such as a DC (Direct Current) / DC converter IC (Integrated Circuit), a reference voltage circuit device that outputs a predetermined reference voltage is used. As a circuit configuration of the reference voltage circuit device, a band gap reference method in which a diode and a resistance element are connected in series and a method in which two MOSFETs (Metal Oxide Field Effect Transistor) are connected in series are known.

  The reference voltage circuit device of the band gap reference method has advantages such as a small temperature fluctuation and a large total dose resistance (TID) of radiation resistance, but has a large power consumption and initial characteristics. Disadvantages such as large variations in

  On the other hand, a reference voltage circuit device of a system in which two MOSFETs are connected in series has small variations in power consumption and initial characteristics, and excellent single event characteristics (SEE: Single Event Effect) among radiation resistance. While having advantages, it has disadvantages such as large temperature fluctuation and small TID resistance.

  When the above-described reference voltage circuit device is used in a large amount of radiation, for example, in outer space, it is important that TID characteristics and SEE characteristics are excellent in radiation resistance. Here, the TID characteristic means that when the gate oxide film is irradiated with radiation, electron-hole pairs are generated in the gate oxide film, and the electrons or holes are in contact with the silicon in the gate oxide film. A phenomenon that accumulates as fixed charges at the interface. For example, when a positive bias voltage is applied to the gate oxide film, holes move to the interface with silicon in the gate oxide film and accumulate as positive fixed charges. As a result, in the n-type MOSFET, the threshold voltage decreases and the leakage current between the source electrode and the drain electrode increases.

  The SEE characteristic is that when high energy particles such as protons and heavy particles scattered from space enter the silicon substrate, the plasma filament that is an aggregate of high-density electron / hole pairs along the track A phenomenon that is formed. For example, when a well formed in a semiconductor device has a positive potential, the well and the substrate are short-circuited through a plasma filament that is a conductor. The time is on the order of picoseconds.

  In the reference voltage circuit device of the band gap reference method, a very small electromotive force is utilized by utilizing a characteristic that a difference between a plurality of thermoelectromotive forces and a single diode formed on the surface of the silicon substrate shows a positive electromotive force. Is amplified and output as a reference voltage. For this reason, when a plasma filament with SEE characteristics is formed inside the reference voltage circuit device and the well potential is lowered to the substrate potential, the time for the well potential to recover tends to be longer. As a method for solving such a problem, a method of shortening the plasma filament by reducing the thickness of the silicon substrate has been proposed, but the cost increases.

On the other hand, in a reference voltage circuit device in which two MOSFETs are connected in series, the threshold voltage of the MOSFET varies depending on the TID characteristics. The amount of fluctuation of the threshold voltage of the MOSFET due to irradiation with radiation depends on the thickness of the gate oxide film. When the absorbed dose of radiation is 1 kGy (1 × 10 ⁵ RAD), the amount of change in the threshold voltage of the MOSFET is, for example, about −100 mV when the thickness of the gate oxide film is 20 nm, and the thickness of the gate oxide film is 10 nm, for example. Is reported to be on the order of −10 mV (see, for example, Patent Document 1 (FIG. 8) below). By setting the thickness of the gate oxide film to about 10 nm, the problem due to the TID characteristic when the radiation is applied is solved.

  As a reference voltage circuit device, a power supply voltage is applied to a series circuit of a depletion type FET and resistance means, and a connection point between the depletion type FET and resistance means is used as an output terminal. An apparatus has been proposed in which the value of the resistance means is set so as to be within the constant current characteristic region of the FET (see, for example, Patent Document 2 below).

As a circuit device that reduces variations in the output voltage of the reference voltage circuit device, a depletion type MOSFET and an enhancement type MOSFET are connected in series, the depletion type MOSFET is at the high potential side terminal, and the enhancement type MOSFET is at the low potential side In the MOS reference voltage circuit in which the connection points of both MOSFETs and the gates of both MOSFETs are connected to the output terminal, respectively, the surface concentration of the channel region of the depletion type MOSFET is 1 × 10 ¹⁶ cm ^−3. As described above, an apparatus in the range of 1 × 10 ¹⁷ cm ⁻³ or less has been proposed (for example, see Patent Document 3 below).

  As another device, the following device has been proposed. The first transistor is a depletion type transistor formed in the p-well of the n-type substrate, the gate and source are connected, and the substrate gate is connected to the ground voltage. The second and third transistors have the same substrate and channel dope impurity concentrations and are formed in p-wells of the n-type substrate, the second transistor has a high-concentration n-type gate, and the third transistor has a high concentration. Has a p-type gate. The gates of the second and third transistors and the substrate gate of the second transistor are connected to the connection parts of the second and third transistors, respectively, and the substrate gate of the third transistor is connected to the ground voltage (for example, (See Patent Document 4 below.)

The following devices have been proposed as reference voltage circuit devices with improved radiation resistance. A polysilicon layer is deposited on a silicon substrate through an oxide film, and mesa etching is performed to form a gate oxide film and a gate electrode. Then, impurity ions are implanted into the silicon substrate, and heat treatment is performed to form source and drain impurities. In a method of manufacturing an insulated gate semiconductor device configured by forming a diffusion region, as a method for suppressing an impurity contained in a gate electrode from diffusing into a gate oxide film and increasing an impurity concentration in the gate oxide film A method for setting the impurity concentration in the gate electrode to 5 × 10 ^{18 to} 5 × 10 ²⁰ cm ⁻³ , a method for depositing a silicide layer on the surface of the gate electrode, and a heat treatment for forming source and drain impurity diffusion regions Manufactured by a method including at least one of the methods in which the step is performed at a temperature of 900 ° C. or less (for example, Patent Document 5 below) Ether.).

  As another device, the following device has been proposed. An SOI substrate composed of a supporting substrate, an insulating film, and a plurality of island-like semiconductor layers is used, a gate oxide film is provided on each semiconductor layer, and a gate electrode is provided on each of the semiconductor layers so as to cross the semiconductor layer. A channel type semiconductor device and a p channel type semiconductor device are formed. A first boundary region film is provided in a peripheral region of the semiconductor layer between the gate electrode of the p-channel semiconductor device and the semiconductor layer, and the semiconductor layer between the gate electrode of the n-channel semiconductor device and the semiconductor layer Is provided with a second boundary region film having a thickness smaller than that of the first boundary region film, and the film pressure of each of the first and second boundary region films is larger than the film thickness of the gate oxide film ( For example, see the following Patent Document 6.)

JP-A-10-200199 Japanese Patent Publication No.54-1014 JP 2003-31678 A JP 2007-66043 A JP-A-1-214170 JP-A-9-205214

  However, as a result of extensive research by the inventor, it has been found that the following problems occur. When the thickness of the gate oxide film of the reference voltage circuit device is about 10 nm, the gate voltage that can be applied to the gate electrode is lowered by reducing the thickness of the gate oxide film. For this reason, the reliability of the reference voltage circuit device is lowered, and there is a possibility that the characteristics of the reference voltage circuit device cannot be exhibited depending on applications.

  Therefore, it is desirable to suppress the electric field strength in the vicinity of the gate electrode to about 3.5 MV / cm or less, and since the voltage of the logic circuit mounting the reference voltage circuit device is generally 5 V, the thickness of the gate oxide film is It is desirable that the thickness be about 20 nm. However, when the thickness of the gate oxide film is about 20 nm, as described above, the threshold voltage of the MOSFET largely fluctuates due to the TID characteristics, resulting in a problem that the output voltage of the reference voltage circuit device varies.

  Further, in the conventional reference voltage circuit device (see, for example, Patent Document 2), the impurity concentration of the substrate surface on the depletion type MOSFET side is lower than that on the enhancement type MOSFET side. For this reason, the amount of variation in the threshold voltage of the depletion type MOSFET and the amount of variation in the threshold voltage of the enhancement type MOSFET differ from each other when the radiation is applied. As a result, there is a problem that the output voltage of the reference voltage circuit device is reduced by several percent from the preset output voltage when radiation is being applied.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor circuit device and a semiconductor circuit device capable of reducing variations in reference voltage in order to eliminate the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a semiconductor circuit device according to the present invention is a method for manufacturing a semiconductor circuit device in which a depletion type MOSFET and an enhancement type MOSFET are connected in series. A first measurement step of measuring respective threshold voltages of the depletion type MOSFET and the enhancement type MOSFET, an irradiation step of irradiating the depletion type MOSFET and the enhancement type MOSFET with radiation, and after irradiation A second measurement step of measuring the respective threshold voltages of the depletion type MOSFET and the enhancement type MOSFET, and a plurality of threshold voltages measured by the first measurement step and the second measurement step Based on Calculation for calculating the element size in which the potential difference between the connection point of the compression type MOSFET and the enhancement type MOSFET and the source of the enhancement type MOSFET is equal before and when the radiation is applied And a manufacturing step of manufacturing the depletion type MOSFET and the enhancement type MOSFET adjusted to the element size calculated by the calculation step.

  In the semiconductor circuit device manufacturing method according to the present invention, in the above-described invention, the calculation step calculates the channel length of the depletion type MOSFET or the channel length of the enhancement type MOSFET.

  In the method of manufacturing a semiconductor circuit device according to the present invention, the thickness of each gate oxide film of the depletion type MOSFET and the enhancement type MOSFET is 10 nm or more in the above-described invention.

  In addition, the method for manufacturing a semiconductor circuit device according to the present invention is characterized in that, in the above-described invention, the depletion type MOSFET and the enhancement type MOSFET are integrated on the same substrate in the manufacturing step.

  In the method for manufacturing a semiconductor circuit device according to the present invention, in the above-described invention, the source and gate of the depletion type MOSFET are connected to the drain and gate of the enhancement type MOSFET, and the drain of the depletion type MOSFET is The enhancement type MOSFET is connected to a high potential side terminal, and the source of the enhancement type MOSFET is connected to the low potential side terminal.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor circuit device according to the present invention is a semiconductor circuit device in which a depletion type MOSFET and an enhancement type MOSFET are connected in series, and the depletion type The potential difference between the connection point of the MOSFET and the enhancement MOSFET and the source of the enhancement MOSFET is the element size that is close to the potential difference before the radiation is irradiated when radiation is irradiated. The element dimension is a dimension based on a variation amount of each threshold voltage of the depletion type MOSFET and the enhancement type MOSFET in a state in which radiation is irradiated.

  In the semiconductor circuit device according to the present invention, the potential difference between the connection point of the depletion-type MOSFET and the enhancement-type MOSFET and the source of the enhancement-type MOSFET is the same as that in the above-described invention. It has the same element size as that in the irradiated state.

  In the semiconductor circuit device according to the present invention as set forth in the invention described above, the element size is the channel length of the depletion type MOSFET or the enhancement type MOSFET channel length.

  The semiconductor circuit device according to the present invention is characterized in that, in the above-mentioned invention, the thickness of each gate oxide film of the depletion type MOSFET and the enhancement type MOSFET is 10 nm or more.

  The semiconductor circuit device according to the present invention is characterized in that, in the above-described invention, the depletion type MOSFET and the enhancement type MOSFET are integrated on the same substrate.

  In the semiconductor circuit device according to the present invention, the source and gate of the depletion type MOSFET are connected to the drain and gate of the enhancement type MOSFET, and the drain of the depletion type MOSFET is on the high potential side. The enhancement type MOSFET is connected to a terminal, and a source of the enhancement type MOSFET is connected to a low potential side terminal.

  According to the above-described invention, the reference voltage circuit device is produced again based on the fluctuation amount of the threshold voltage before and after the radiation irradiation of each of the depletion type MOSFET and the enhancement type MOSFET. At this time, the reference voltage circuit in which the connection point between the depletion type MOSFET and the enhancement type MOSFET and the potential difference between the sources of the enhancement type MOSFET are substantially equal before the radiation is applied and when the radiation is applied. Make the device. Thereby, it is possible to manufacture a reference voltage circuit device in which the output voltage does not substantially vary until the absorbed dose of radiation reaches an arbitrary absorbed dose.

  Further, according to the above-described invention, the output voltage of the reference voltage circuit device when radiation is being irradiated is substantially equal to the output voltage before radiation is irradiated. That is, until the absorbed dose of radiation reaches an arbitrary absorbed dose, the output voltage of the reference voltage circuit device hardly varies.

  According to the method for manufacturing a semiconductor circuit device and the semiconductor circuit device according to the present invention, it is possible to reduce variations in the reference voltage.

1 is a circuit diagram showing a configuration of a semiconductor circuit device according to an embodiment; It is sectional drawing which shows the structure of the semiconductor circuit device concerning embodiment. FIG. 2 is an explanatory diagram showing a channel length and a channel width of the MOSFET shown in FIG. 1. 3 is a flowchart showing a method for manufacturing a semiconductor circuit device according to an embodiment. It is a characteristic view which shows the electrical property of the depletion type MOSFET concerning embodiment. It is a characteristic view which shows the electrical property of the enhancement type MOSFET concerning embodiment.

  Exemplary embodiments of a method of manufacturing a semiconductor circuit device and a semiconductor circuit device according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
FIG. 1 is a circuit diagram illustrating a configuration of a semiconductor circuit device according to an embodiment. The semiconductor circuit device shown in FIG. 1 is a reference voltage circuit device in which a depletion type MOSFET 1 and an enhancement type MOSFET 2 are connected in series and a difference between these threshold voltages Vth is output as a reference voltage. The depletion type MOSFET 1 and the enhancement type MOSFET 2 are connected in series between the high potential side terminal Vs and the low potential side terminal Gnd. The high potential side terminal Vs has a power supply potential, for example. The low potential side terminal Gnd has a ground potential, for example. The depletion type MOSFET 1 is formed as a constant current source.

  Specifically, the high potential side terminal Vs is electrically connected to the drain of the depletion type MOSFET 1. The low potential side terminal Gnd is electrically connected to the source of the enhancement type MOSFET 2. The low potential side terminal Gnd is electrically connected to a substrate on which the depletion type MOSFET 1 and the enhancement type MOSFET 2 are provided. The output terminal Vref is electrically connected to the source and gate of the depletion type MOSFET 1 and the drain and gate of the enhancement type MOSFET 2.

  The depletion type MOSFET 1 operates as a constant current source, and a potential difference between an output terminal Vref which is a connection portion between the depletion type MOSFET 1 and the enhancement type MOSFET 2 and a source of the enhancement type MOSFET 2 is output as the output voltage Vout. For example, when the power supply voltage applied to the high potential side terminal Vs is 3V or more, the output voltage Vout of the reference voltage circuit device is 1V.

FIG. 2 is a cross-sectional view illustrating the structure of the semiconductor circuit device according to the embodiment. As shown in FIG. 2, in the semiconductor circuit device according to the embodiment, a p-well region 12 is provided on a surface layer of a p-substrate 11. The impurity concentration of the p substrate 11 and the p well region 12 may be equal. The surface concentration of the p well region 12 may be, for example, 1 × 10 ¹⁵ cm ⁻³ . A depletion type MOSFET 1 and an enhancement type MOSFET 2 are provided on the surface layer of the p well region 12. First to third n ⁺ regions 13 to 15 are provided apart from each other in part of the surface layer of the p-well region 12.

In the depletion type MOSFET 1, the first n ⁺ region 13 is an n ⁺ drain region, and the second n ⁺ region 14 is an n ⁺ source region. The n depletion region 16 is provided in a part of the surface layer of the p well region 12 so as to be in contact with the first n ⁺ region 13 and the second n ⁺ region 14. The surface concentration of the n depletion region 16 may be 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less. Since the n depletion region 16 is provided, the threshold voltage of the depletion type MOSFET 1 is set lower than the threshold voltage of the enhancement type MOSFET 2.

  A gate electrode 18 is provided on the n depletion region 16 via a gate oxide film 17. The thickness of the gate oxide film 17 is preferably 10 nm or more, for example. This is because the gate voltage that can be applied to the gate electrode can be increased, and the reliability of the reference voltage circuit device can be improved.

In the enhancement type MOSFET 2, the second n ⁺ region 14 is an n ⁺ drain region, and the third n ⁺ region 15 is an n ⁺ source region. On the p-well region 12, a gate electrode 20 is provided across the second n ⁺ region 14 to the third n ⁺ region 15 via a gate oxide film 19. The thickness of the gate oxide film 19 is preferably 10 nm or more, for example. The reason is the same as that of the gate oxide film 17 of the depletion type MOSFET 1.

In the depletion type MOSFET 1 and the enhancement type MOSFET 2, the p well region 12 and the second n ⁺ region 14 are common regions. The output terminal Vref includes the second n ⁺ region 14 (the n ⁺ source region of the depletion type MOSFET 1 and the n ⁺ drain region of the enhancement type MOSFET ² ), the gate electrode 18 of the depletion type MOSFET 1, and the gate electrode 20 of the enhancement type MOSFET 2. , Electrically connected.

The high potential side terminal Vs is electrically connected to the first n ⁺ region 13 (the n ⁺ drain region of the depletion type MOSFET 1). The low potential side terminal Gnd is electrically connected to the third n ⁺ region 15 (the n ⁺ source region of the enhancement type MOSFET ² ). The field oxide film 21 is provided in a part of the surface layer of the p-well region 12 and separates the depletion type MOSFET 1 and the enhancement type MOSFET 2 from other elements not shown.

  The depletion-type MOSFET 1 and the enhancement-type MOSFET 2 are the difference in potential between the connection point between the depletion-type MOSFET 1 and the enhancement-type MOSFET 2 and the source of the enhancement-type MOSFET 2 when the radiation is irradiated. The element dimensions are close to. Specifically, the potential difference between the connection point of the depletion type MOSFET 1 and the enhancement type MOSFET 2 and the source of the enhancement type MOSFET 2 is substantially equal to the potential difference before the radiation is irradiated when the radiation is irradiated. The amount of change between the potential difference before the radiation is applied and the potential difference when the radiation is applied is, for example, less than 1%. This element size is set based on the amount of fluctuation of the threshold voltage of the depletion type MOSFET 1 and the enhancement type MOSFET 2 that are irradiated with radiation.

Specifically, the element dimensions of the depletion type MOSFET 1 and the enhancement type MOSFET 2 are the threshold voltage variation ΔV _thD before and after irradiation of the depletion type MOSFET 1 and the threshold voltage variation of the enhancement type MOSFET 2 before and after radiation irradiation. _Is set based on the quantity _ΔVthE .

  Here, the element dimensions are the channel length Ld and channel width Wd of the depletion type MOSFET 1 and the channel length Le and channel width We of the enhancement type MOSFET 2.

FIG. 3 is an explanatory diagram showing the channel length and channel width of the MOSFET shown in FIG. The channel length Ld is the width of the channel region formed between the source region (second n ⁺ region 14) and the drain region (first n ⁺ region 13) of the depletion type MOSFET 1 in the direction in which the drain / source current flows. It is. The channel width Wd is the width of the channel region of the depletion type MOSFET 1 in the direction perpendicular to the channel length Ld. Similarly, the channel length Le is the width of the channel region of the enhancement type MOSFET 2 in the direction in which the drain / source current flows. The channel width We is a width of the channel region of the enhancement type MOSFET 2 in a direction perpendicular to the channel length Le (not shown).

Specifically, for example, the channel length Ld of the depletion type MOSFET 1 has a dimension that satisfies the following expressions (1) and (2). Here, ΔV _thD is the fluctuation amount of the threshold voltage of the depletion type MOSFET 1 after radiation irradiation. ΔV _thE is the amount of change in the threshold voltage of the enhancement type MOSFET 2 after irradiation.

  Similarly, the channel width Wd of the depletion type MOSFET 1, the channel length Le and the channel width We of the enhancement type MOSFET 2, the left side of the above equation (2) is the channel width Wd of the depletion type MOSFET 1, the channel length Le of the enhancement type MOSFET 2, and It is set so as to satisfy the expression developed so as to be the channel width We.

  As described above, by producing the reference voltage circuit device with the element size satisfying the above expressions (1) and (2), it is possible to suppress the output voltage from being varied when the radiation is being applied. . The reason will be described later.

  Next, a method for manufacturing the semiconductor circuit device shown in FIG. 1 will be described. FIG. 4 is a flowchart illustrating a method of manufacturing the semiconductor circuit device according to the embodiment. First, a depletion type MOSFET 1 and an enhancement type MOSFET 2 are formed on a substrate. Next, the source and gate of the depletion type MOSFET 1 are connected to the drain and gate of the enhancement type MOSFET 2. Further, the drain of the depletion type MOSFET 1 is connected to the high potential side terminal Vs, and the source of the enhancement type MOSFET 2 is connected to the low potential side terminal Gnd. That is, the reference voltage circuit device in which the depletion type MOSFET 1 and the enhancement type MOSFET 2 are connected in series is manufactured (step S1).

  Here, the channel length Ld and the channel width Wd of the depletion type MOSFET 1 may be 130 μm and 10 μm, respectively. The channel length Le and the channel width We of the enhancement type MOSFET 2 may be 160 μm and 12 μm, respectively. Further, the depletion type MOSFET 1 and the enhancement type MOSFET 2 may be integrated on the same substrate (see FIG. 2) or may be formed on different substrates. In addition, the reference voltage circuit device is manufactured by general processes and conditions.

  Next, the respective threshold voltages of the depletion type MOSFET 1 and the enhancement type MOSFET 2 fabricated in step S1 are measured using a general parameter analyzer (first measurement process: step S2).

  Specifically, in step S2, the potential difference between the source and drain of the depletion type MOSFET 1 is set to 5 V, and then a voltage is applied to the gate of the depletion type MOSFET 1. Then, the gate voltage of the depletion type MOSFET 1 is increased, and the gate voltage when the drain-source current Ids becomes 100 μA is measured as the threshold voltage of the depletion type MOSFET 1. The threshold voltage of the enhancement type MOSFET 2 is also measured by the same method.

  In step S2, the potential difference between the output terminal Vref and the low potential side terminal Gnd is measured as the output voltage Vout. Specifically, the high potential side terminal Vs is set to the power supply voltage potential 5V, for example, and the low potential side terminal Gnd is set to the ground potential, for example. Then, the potential difference between the connection point (output terminal Vref) between the depletion type MOSFET 1 and the enhancement type MOSFET 2 and the source (low potential side terminal Gnd) of the enhancement type MOSFET 2 is measured.

  Next, radiation is applied to the depletion type MOSFET 1 and enhancement type MOSFET 2 fabricated in step S1 (irradiation process: step S3). In step S3, for example, the artificial radioisotope of cobalt having a mass number of 60 (cobalt 60) may be used as a radiation source, and γ rays may be irradiated at an absorbed dose of 1 kGy / Hr for 1 hour.

  In step S3, the reference voltage circuit device is operated under the following voltage application conditions during radiation irradiation, for example. The high potential side terminal Vs of the reference voltage circuit device is set to the power supply voltage potential 5V, and the low potential side terminal Gnd is set to the ground potential, for example. That is, a voltage of 5 V is applied to the drain of the depletion type MOSFET 1 immediately after the operation of the reference voltage circuit device is started, and the source of the enhancement type MOSFET 2 is grounded. In the depletion type MOSFET 1, when the voltage is not applied to the gate, the source and drain are in a conductive state (hereinafter referred to as “normally on”), so that a voltage of 5 V is applied to the drain of the enhancement type MOSFET 2. Is done. Thereafter, the enhancement-type MOSFET 2 is operated until the gate potential becomes 1V.

  Next, the respective threshold voltages of the depletion type MOSFET 1 and the enhancement type MOSFET 2 after the irradiation step are measured using a general parameter analyzer (second measurement step: step S4). The measurement method and measurement conditions are the same as in step S2.

  Next, using the above equations (1) and (2), the optimum element size of the reference voltage circuit device to be used in the space irradiated with radiation is calculated (calculation step: step S5). For example, of the channel length Ld and the channel width Wd of the depletion type MOSFET 1 and the channel length Le and the channel width We of the enhancement type MOSFET 2, the dimensions of the part to be adjusted by the reference voltage circuit device to be manufactured in the later process are calculated. Preferably, the dimension of the channel length Ld of the depletion type MOSFET 1 or the channel length Le of the enhancement type MOSFET 2 is calculated. The reason is that element design can be easily performed. Here, the optimum element size of the reference voltage circuit device is that the potential difference between the connection point between the depletion type MOSFET 1 and the enhancement type MOSFET 2 and the source of the enhancement type MOSFET 2 is irradiated with radiation before and after radiation. The element dimensions are the same in the state. A specific calculation method will be described later.

  Next, a reference voltage circuit device composed of a depletion type MOSFET 1 and an enhancement type MOSFET 2 is produced again based on the element dimensions of the reference voltage circuit device calculated in step S5 (production process: step S6). That is, a reference voltage circuit device having an element size different from that of the reference voltage circuit device manufactured in step S1 is manufactured. The reference voltage circuit device is manufactured by general processes and conditions.

  Next, the electrical characteristics of the reference voltage circuit device manufactured in step S6 are confirmed (step S7). Specifically, the output voltage of the reference voltage circuit device before optimization measured in step S2 is compared with the output voltage of the reference voltage circuit device after optimization measured in step S7. The measurement method is the same as in step S2. Thereby, a reference voltage circuit device in which the output voltage does not fluctuate due to radiation irradiation is completed.

  As described above, according to the embodiment, the reference voltage circuit device is produced again based on the threshold voltage fluctuation amount before and after the radiation irradiation of the depletion type MOSFET 1 and the enhancement type MOSFET 2. At this time, the reference voltage circuit in which the potential difference between the connection point between the depletion type MOSFET 1 and the enhancement type MOSFET 2 and the source of the enhancement type MOSFET 2 is substantially equal before and when the radiation is applied. Make the device. Thereby, it is possible to manufacture a reference voltage circuit device in which the output voltage does not substantially vary until the absorbed dose of radiation reaches an arbitrary absorbed dose. Therefore, variations in the reference voltage can be reduced.

  Further, in the reference voltage circuit device, the potential difference between the connection point between the depletion type MOSFET 1 and the enhancement type MOSFET 2 and the source of the enhancement type MOSFET 2 is the same between before the radiation is applied and when the radiation is applied. The element dimensions are as follows. This element size is calculated based on the respective threshold voltages of the depletion type MOSFET 1 and the enhancement type MOSFET 2. For this reason, the output voltage of the reference voltage circuit device in a state in which radiation is irradiated is substantially equal to the output voltage before irradiation with radiation. That is, until the absorbed dose of radiation reaches an arbitrary absorbed dose, the output voltage of the reference voltage circuit device hardly varies. Therefore, variations in the reference voltage can be reduced.

  Further, even when fixed charges are accumulated in the gate oxide films 17 and 19 in the state of being irradiated with radiation, the variation in the reference voltage can be reduced as described above. For this reason, the total dose (TID) tolerance can be increased.

  Further, the gate oxide films 17 and 19 can be 10 nm or more. Therefore, the reference voltage circuit device according to the embodiment can be manufactured using a conventional manufacturing apparatus or manufacturing method. Thereby, manufacturing cost can be reduced. In addition, the strength of the reference voltage circuit device can be improved.

  Further, by setting the gate oxide films 17 and 19 to 10 nm or more, the gate oxide films 17 and 19 can be manufactured together with other insulating films, and the number of manufacturing steps can be reduced. Thereby, manufacturing cost can be reduced.

(Reference voltage of reference voltage circuit device)
The reason why the variation in the reference voltage can be reduced by manufacturing the reference voltage circuit device with the element dimensions satisfying the above expressions (1) and (2) when the radiation is applied. . The output voltage V _out1 before radiation irradiation of the reference voltage circuit device (see FIG. 1) is expressed by the following equation (3).

Here, V _thD1 is the threshold voltage of the depletion type MOSFET 1 before radiation irradiation. V _thE1 is a threshold voltage of the enhancement type MOSFET 2 before radiation irradiation. Further, βd = Ld / Wd and βe = Le / We.

When the coefficient other than the threshold voltage V _thD1 of the depletion type MOSFET 1 before radiation irradiation in the second term on the right side of the above expression (3) is replaced with the coefficient K as shown in the following expression (4), the above (3) The expression is expressed by the following expression (5).

Similarly, the output voltage V _out2 after irradiation of the reference voltage circuit device is _expressed by the following equation (6).

Here, V _thD2 is the threshold voltage of the depletion type MOSFET 1 after radiation irradiation. V _thE2 is the threshold voltage of the enhancement type MOSFET 2 after radiation irradiation.

In the conventional reference voltage circuit device, when radiation is applied, the threshold voltage of the depletion type MOSFET 1 and the threshold voltage of the enhancement type MOSFET 2 are lowered, and the output voltage varies. The output voltage fluctuation amount ΔV _out is a difference between the output voltage V _out1 before radiation irradiation and the output voltage V _out2 after radiation irradiation. Therefore, from the above equations (5) and (6), the fluctuation amount ΔV _out of the output voltage is expressed by the following equation (7).

In the above equation (7), the variation amount of the threshold voltage (V _thD1 −V _thD2 ) of the depletion type MOSFET 1 after irradiation is ΔV _thD, and the variation amount of the threshold voltage of the enhancement type MOSFET 2 after irradiation ( V _thE1 −V _thE2 ) is ΔV _thE .

In the present embodiment, the coefficient K in the above equation (7) is adjusted so that the output power V _out when radiation is being applied is equal to the output voltage before radiation irradiation. Specifically, the coefficient K is adjusted so that the output voltage fluctuation amount ΔV _out = 0 in the equation (7). That is, it can be seen that the coefficient K needs to satisfy the above equation (1).

  Further, since the above equation (4) is βd = Ld / Wd and βe = Le / We, the channel length Ld and channel width Wd of the depletion type MOSFET 1 and the channel length Le and channel width We of the enhancement type MOSFET 2 are Any one of the solutions can be converted into an equation including the coefficient K. When the channel length Ld of the depletion type MOSFET 1 is taken as a solution, the above equation (2) is obtained.

Thus, by setting the channel length Ld and channel width Wd of the depletion type MOSFET 1 and the channel length Le and channel width We of the enhancement type MOSFET 2 so as to satisfy the above expressions (1) and (2), the above ( 7) The variation amount ΔV _out = 0 of the output voltage in the equation can be set.

(Relationship between accumulated charge and threshold voltage)
The relationship between the amount of charge accumulated in the gate oxide film due to radiation and the threshold voltage of the reference voltage circuit device will be described. The threshold voltage Vt of the MOSFET is generally expressed by the following equation (8).

Here, Q _B is the total amount of acceptor charges in the depletion layer on the silicon substrate surface. C _ox is a gate oxide film capacitance. φs is the surface potential of silicon when the conductivity type of the silicon substrate surface is inverted. φs is about 0.8V.

When the fixed charge generated at the interface between the gate oxide film and the silicon substrate due to radiation irradiation is Q _Rad , the relationship between the accumulated charge amount due to radiation and the threshold voltage of the MOSFET is ) Expression.

  That is, the threshold voltage Vt of the MOSFET is proportional to the radiation dose. The output voltage of the reference voltage circuit device is the difference between the threshold voltage of the depletion type MOSFET 1 and the threshold voltage of the enhancement type MOSFET 2. For this reason, it is estimated that the output voltage of the reference voltage circuit device is also proportional to the radiation dose.

Therefore, for example, according to the above-described embodiment, in the above-described irradiation process (see step S3 in FIG. 4), after irradiating γ rays with an absorbed dose of 1 kGy / Hr for 1 hour, the threshold voltage before and after this radiation irradiation is set. It is assumed that the element dimensions of the depletion type MOSFET 1 and the enhancement type MOSFET 2 are manufactured with the element dimensions calculated based on the above. In this case, the absorbed dose of 1 kGy is set so that the output voltage of the reference voltage circuit device does not substantially fluctuate (output voltage fluctuation amount ΔV _out = 0). Until 1 reaches 1 kGy, it is presumed that the proportional relationship of the output voltage fluctuation amount ΔV _out = 0 holds. Therefore, it can be seen that, in actual use, the output voltage of the reference voltage circuit device does not substantially vary until the absorbed dose of radiation irradiated to the reference voltage circuit device reaches 1 kGy.

Further, from the above equations (8) and (9), as described above, the proportional relationship between the radiation dose and the output voltage of the reference voltage circuit device is established even at an arbitrary absorbed dose such as 2 kGy or 3 kGy. For this reason, this Embodiment is applicable in arbitrary absorbed dose. Therefore, it is possible to prevent the output power V _out from being substantially changed regardless of the absorbed dose of radiation applied to the reference voltage circuit device.

(Example)
A specific method for manufacturing the reference voltage circuit device will be described. FIG. 5 is a characteristic diagram showing electrical characteristics of the depletion type MOSFET according to the embodiment. FIG. 6 is a characteristic diagram showing electrical characteristics of the enhancement type MOSFET according to the embodiment. 5 and 6 show the relationship between the drain-source voltage Vds and the drain-source current Ids. In accordance with the embodiment, the reference voltage circuit device was manufactured to produce a reference voltage circuit device having an optimized element size for use in a space irradiated with radiation.

  First, a depletion type MOSFET 1 and an enhancement type MOSFET 2 were produced. The channel length Ld and the channel width Wd of the depletion type MOSFET 1 were 130 μm and 10 μm, respectively. The channel length Le and the channel width We of the enhancement type MOSFET 2 were 160 μm and 12 μm, respectively.

  Next, the first measurement process was performed, and the respective threshold voltages of the depletion type MOSFET 1 and the enhancement type MOSFET 2 were measured. The potential difference between the drain and source was 5 V, and the gate voltage when the drain-source current Ids was 100 μA was defined as the threshold voltage. The gate of the depletion type MOSFET 1 is a source potential. The enhancement type MOSFET 2 gate has a drain potential.

  Further, the drain-source voltage Vds and the drain-source current Ids of the depletion type MOSFET 1 and the enhancement type MOSFET 2 at this time were measured (dotted lines in FIGS. 5 and 6: before γ-ray irradiation). From the results shown in FIG. 5, it can be seen that in the depletion type MOSFET 1, when the drain-source voltage Vds exceeds 0.6 V, the drain-source current Ids becomes constant at 1.3 μA and becomes saturated.

  Further, from the results shown in FIG. 6, it can be seen that in the enhancement type MOSFET 2, the drain-source voltage Vds becomes 1.32 V when the drain-source current Ids of 1.3 μA flows. That is, the output voltage Vout of the reference voltage circuit device is 1.32V, and 1.32V is output as the reference voltage.

  Next, an irradiation process was performed. Specifically, the reference voltage circuit device was irradiated with γ rays using cobalt 60 as a radiation source at an absorbed dose of 1 kGy / Hr for 1 hour. A second measurement was then performed. The method for measuring the threshold voltage is the same as in the first measurement (solid line in FIGS. 5 and 6: after γ-ray irradiation). As shown in FIG. 5, it can be seen that the drain-source current Ids of the depletion type MOSFET 1 is constant at 1.5 μA and is saturated.

  Further, from the result shown in FIG. 6, it can be seen that in the enhancement type MOSFET 2, the drain-source voltage Vds becomes 1.32 V when the drain-source current Ids of 1.5 μA flows. That is, the output voltage Vout of the reference voltage circuit device fluctuated from 1.32 V to 1.31 V by irradiation with radiation, and the voltage fluctuation amount became −10 mV.

At this time, the fluctuation amount ΔV _thD of the threshold voltage of the depletion type MOSFET 1 was 62 mV. Further, the variation amount ΔV _thE of the threshold voltage of the enhancement type MOSFET ₂ was _{52 mV} . It has been found that the threshold voltages of the depletion type MOSFET 1 and the enhancement type MOSFET 2 both decrease and the current driving capability increases.

In a general reference voltage circuit device used in a place where the amount of radiation is small, for example, near the ground, the threshold voltage variation (ΔV _thD and ΔV _thE ) is small. _Therefore , considering the dimensional variation in the process, The coefficient K in the above equation (7) is adjusted to the vicinity of 1. For this reason, the fluctuation amount ΔV _out of the output voltage after radiation irradiation is 10 mV (= −52 + 1 × {− (− 62)}) from the above equation (7). That is, it can be seen that the variation amount of the output voltage is 10 mV, similarly to the results derived from the characteristic diagrams shown in FIGS.

  Therefore, the ratio (βd) between the channel length Ld and the channel width Wd of the depletion type MOSFET 1 and the enhancement type MOSFET 2 so as to cancel out the increase in the drain-source voltage Vds that increases as the drain-source current Ids increases. It can be seen that the reference voltage does not change if the ratio (βe) of the channel length Le and the channel width We is adjusted. That is, in the above formulas (1) and (2), by adjusting the coefficient K and calculating the element dimensions of the depletion type MOSFET 1 and the enhancement type MOSFET 2, variations in the reference voltage can be reduced.

  Specifically, the coefficient K is 0.838 (= −52 / −62) from the above equation (1). From the above equation (2), when the channel width Wd of the depletion type MOSFET 1 is 10 μm and the channel length Le and the channel width We of the enhancement type MOSFET 2 are 160 μm and 12 μm, respectively, the channel length Ld of the depletion type MOSFET 1 is 189 μm ( = (10/12) × 160 / (0.838 × 0.838)).

  In the above description, the present invention describes an example in which the channel length of the depletion type MOSFET 1 or the channel length of the enhancement type MOSFET 2 is adjusted based on the above formulas (1) and (2). However, the channel width of the depletion type MOSFET 1 or the channel width of the enhancement type MOSFET 2 may be adjusted. The element dimensions of the semiconductor circuit device can be variously changed.

  As described above, the method for manufacturing a semiconductor circuit device and the semiconductor circuit device according to the present invention are useful for a reference voltage circuit device that is used in, for example, a DC / DC converter IC that is used in outer space with a large radiation dose. .

1 Depletion type MOSFET
2 Enhancement type MOSFET
Vs High potential side terminal Vref Output terminal Gnd Low potential side terminal

Claims (11)

A method of manufacturing a semiconductor circuit device in which a depletion type MOSFET and an enhancement type MOSFET are connected in series,
A first measuring step of measuring respective threshold voltages of the depletion type MOSFET and the enhancement type MOSFET;
An irradiation step of irradiating the depletion type MOSFET and the enhancement type MOSFET with radiation;
A second measurement step of measuring respective threshold voltages of the depletion type MOSFET and the enhancement type MOSFET after irradiation;
Based on a plurality of threshold voltages measured in the first measurement step and the second measurement step, a potential difference between a connection point between the depletion type MOSFET and the enhancement type MOSFET and a source of the enhancement type MOSFET is obtained. A calculation step of calculating an element size that is equal between before irradiation with radiation and when irradiated with radiation;
A manufacturing process for manufacturing the depletion type MOSFET and the enhancement type MOSFET adjusted to the element size calculated by the calculation process;
A method for manufacturing a semiconductor circuit device, comprising:   2. The method of manufacturing a semiconductor circuit device according to claim 1, wherein in the calculation step, a channel length of the depletion type MOSFET or a channel length of the enhancement type MOSFET is calculated.   3. The method of manufacturing a semiconductor circuit device according to claim 1, wherein a thickness of each gate oxide film of the depletion type MOSFET and the enhancement type MOSFET is 10 nm or more. 4.   4. The method of manufacturing a semiconductor circuit device according to claim 1, wherein, in the manufacturing step, the depletion type MOSFET and the enhancement type MOSFET are integrated on the same substrate. The source and gate of the depletion type MOSFET are connected to the drain and gate of the enhancement type MOSFET,
The drain of the depletion type MOSFET is connected to the high potential side terminal,
5. The method of manufacturing a semiconductor circuit device according to claim 1, wherein a source of the enhancement type MOSFET is connected to a low potential side terminal. A semiconductor circuit device in which a depletion type MOSFET and an enhancement type MOSFET are connected in series,
An element size in which a potential difference between a connection point of the depletion type MOSFET and the enhancement type MOSFET and a source of the enhancement type MOSFET is close to a potential difference before the radiation is irradiated when the radiation is irradiated. And
2. The semiconductor circuit device according to claim 1, wherein the element dimension is a dimension based on a variation amount of a threshold voltage of each of the depletion type MOSFET and the enhancement type MOSFET in a state where radiation is irradiated.   The potential difference between the connection point of the depletion type MOSFET and the enhancement type MOSFET and the source of the enhancement type MOSFET has the same element size before irradiation with radiation and when irradiated with radiation. The semiconductor circuit device according to claim 6.   8. The semiconductor circuit device according to claim 6, wherein the element size is a channel length of the depletion type MOSFET or a channel length of the enhancement type MOSFET.   9. The semiconductor circuit device according to claim 6, wherein the thickness of each gate oxide film of the depletion type MOSFET and the enhancement type MOSFET is 10 nm or more.   10. The semiconductor circuit device according to claim 6, wherein the depletion type MOSFET and the enhancement type MOSFET are integrated on the same substrate. The source and gate of the depletion type MOSFET are connected to the drain and gate of the enhancement type MOSFET,
The drain of the depletion type MOSFET is connected to the high potential side terminal,
11. The semiconductor circuit device according to claim 6, wherein a source of the enhancement type MOSFET is connected to a low potential side terminal.

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