JP2015092382A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device which can prevent a shortage of electric power during operation.SOLUTION: An information processing device includes a nonvolatile storage unit, an electric power storage unit, and a power supply control unit. The electric power storage unit is means for supplying electric power to a main storage unit. The power supply control unit controls electric power supply to the main storage unit. The power supply control unit controls to supply electric power from the electric power storage unit to the main storage unit when the amount of electric power of the electric power storage unit recovers to a preset threshold or more.

Description

  Embodiments described herein relate generally to an information processing apparatus.

  In embedded devices such as consumer electronics, in order to reduce power consumption, there is a technology that dynamically lowers the operating voltage of the processor or reduces the operating frequency when the processor of the embedded device is low. Are known. Also known is a technique for shutting off power to a device that does not generate access within a specified time.

  Furthermore, there is a method in which when there is no input from the user (for example, keyboard input) within a certain time, the state shifts to a state called sleep and power consumption is reduced. The sleep state is a state in which the operating frequency and supply voltage of the processor are lowered, the processor is shifted to the low power consumption mode, and the power consumption is lowered. In this method, since the processor state and volatile memory information are stored in each device, it is possible to return to the normal state in a short time when there is an input from the user.

  Unlike the sleep state, the processor and memory information is stored in a nonvolatile storage device (for example, a hard disk), and then the power to the processor and the memory is turned off, resulting in a state of lower power consumption than the sleep state. There is a dormant state. It is assumed that, for example, the user presses the power button when in the hibernation state. In this case, the embedded device determines that the user has instructed a transition from the hibernation state to the normal state. The embedded device reads the state of the processor stored in the storage device, writes it back to the processor, writes back the information in the memory from the storage device, and returns to the state before the hibernation state.

  In this way, a technique for reducing power consumption when the user is not using it has been considered. The transition to the sleep state or the hibernation state in order to reduce power consumption occurs when no input is made by the user within a preset time.

  On the other hand, even during input from the user, there are times when the processor or device is not operating in units of several milliseconds. For example, the human typing time is about once every several tens of milliseconds. For this reason, when the user is typing using the keyboard, the time until the key is pressed may be in a state where there is no task to be processed by the processor, that is, in an idle state. If the power of the processor and memory can be shut off in this time unit of several milliseconds, the power of the processor and memory can be shut down without waiting until a preset time elapses as in the past. Therefore, further power saving can be realized.

David Meisner et al, “PowerNap: Eliminting Server Idle Power”, in ACM ASPLOS, 2009

  However, in the prior art, when the processor is turned on, the specifications of the processor and the memory are determined based on the assumption that the memory is also turned on. For this reason, the situation where the power of the memory is cut off when the power of the processor is turned on and the memory cannot be accessed when accessed from the processor is not considered.

  In a conventional system, it is not expected that only the power of the memory will be turned off. Therefore, in order to reduce the power consumption of the system by turning off the power of the memory, the processor side may have the power of the memory turned off. In consideration of the fact that there is a possibility of access, a means for grasping the state on the memory side is required.

  An information processing apparatus according to an embodiment includes a nonvolatile storage unit, a power storage unit, and a power supply control unit. The power storage unit is means for supplying power to the main storage unit. The power control unit controls power supply to the main storage unit. In addition, the power supply control unit performs control so that power is supplied from the power storage unit to the main storage unit when the power amount of the power storage unit recovers to a predetermined threshold value or more.

1 is a block diagram of an information processing apparatus according to a first embodiment. The flowchart of the return process in 1st Embodiment. The block diagram which shows the information processing apparatus concerning the modification of 1st Embodiment. The block diagram of the information processing apparatus concerning 2nd Embodiment. The flowchart of the return process in 2nd Embodiment. The block diagram of the information processing apparatus concerning the modification of 2nd Embodiment. The block diagram of the information processing apparatus concerning 3rd Embodiment. The flowchart of the power supply control process in 3rd Embodiment. The flowchart of the return process concerning a modification.

  Exemplary embodiments of an information processing apparatus according to the present invention will be described below in detail with reference to the accompanying drawings.

(First embodiment)
The information processing apparatus according to the first embodiment connects a part of a memory bus that connects a processor and a nonvolatile memory to a state monitoring unit that monitors the state of the memory. When returning from the sleep state, the processor inquires of the state monitoring unit about the state of the memory, and accesses the memory after the memory becomes accessible.

  FIG. 1 is a block diagram illustrating an example of the configuration of the information processing apparatus 100 according to the first embodiment. As illustrated in FIG. 1, the information processing apparatus 100 includes a processor 110, a memory 130, and a state monitoring unit 120.

  The memory 130 is a non-volatile storage unit used as a main storage memory of the processor 110. The state monitoring unit 120 determines the state of the memory 130 and transmits the determination result to the processor 110.

  The processor 110 and the state monitoring unit 120 are connected by a bus 51b to which some addresses for state monitoring are assigned in the entire memory bus. The memory 130 and the processor 110 are connected by a bus 51a other than the bus 51b in the entire memory bus. The state monitoring unit 120 and the memory 130 are connected by a bus 51c to which an address corresponding to the bus 51b is assigned. Note that the bus 51a and the bus 51b, or the bus 51a and the bus 51c correspond to one memory bus.

  The processor 110 includes a memory 111. The memory 111 is a volatile or non-volatile memory. For example, the memory 111 is configured by a cache memory or a storage unit for storing a program having a small size.

  The processor 110 executes an operating system and application software. The processor 110 uses a memory 130 as a main storage memory. The processor 110 also controls the power supply for each unit in the information processing apparatus 100. For example, the processor 110 controls power supply (power on) and power cutoff (power cutoff) to the memory 130.

  In order for the processor 110 to turn on or off the power of the memory 130 within the idle time of the processor 110, which occurs in units of several milliseconds, it is necessary to move the information stored in the memory 130 to another storage device. There is no room. Therefore, a non-volatile memory in which retained information is not erased even when the power is turned off is essential. For this reason, in this embodiment, a non-volatile memory is used as the memory 130. Therefore, when the processor 110 enters an idle state, the power of the memory 130 can be immediately shut down without saving the information in the memory 130. Thereby, the power supply of the memory 130 can be shut off even in a short time, and the power consumption of the information processing apparatus 100 can be reduced.

  Although omitted in FIG. 1, the information processing apparatus 100 may include a data input unit such as a keyboard, a mouse, a touch panel, and a network interface (I / F), as in a normal personal computer. . The information processing apparatus 100 may include a display unit such as a liquid crystal display for displaying data.

  Next, details of the state monitoring unit 120 will be described. The state monitoring unit 120 includes a reception unit 121, a determination unit 122, and a transmission unit 123. The receiving unit 121 receives an inquiry as to whether or not the memory 130 is accessible from the processor 110 via the bus 51b. Then, the reception unit 121 notifies the determination unit 122 that it has received an inquiry as to whether the memory 130 is accessible. The inquiry includes a time when the processor 110 starts supplying power to the memory 130 (power-on time). In addition to the inquiry, the processor 110 may notify the state monitoring unit 120 of the power-on time.

  The determination unit 122 determines whether the memory 130 is accessible when an inquiry is received (when a notification indicating that an inquiry about whether the memory 130 is accessible is received from the reception unit 121). For example, the determination unit 122 determines whether the memory 130 is accessible by using a time (startup time) from when power supply to the memory 130 is started until the memory 130 starts up. Further, the determination unit 122 may have a function of counting the number of clocks of the state monitoring unit 120 after the supply of power to the memory 130 is started. Then, when the reception unit 121 receives an inquiry from the processor 110 as to whether the memory 130 is accessible, the determination unit 122 may determine that access is possible from the number of clocks. The determination unit 122 notifies the transmission unit 123 of the determination result.

  For example, the state monitoring unit 120 inputs the activation time of the memory 130 in advance and stores it in an internal storage unit (not shown). When receiving an inquiry as to whether access is possible, the determination unit 122 determines whether a time corresponding to the activation time has elapsed from the notified power-on time. The determination unit 122 determines that the memory 130 is accessible when a time corresponding to the activation time has elapsed from the power-on time. The reference time is not limited to the power-on time. For example, the determination may be made based on the time when the inquiry is received.

  The transmission unit 123 transmits the determination result by the determination unit 122, that is, information indicating whether the memory 130 is accessible to the processor 110 via the bus 51b.

  Next, the operation at the time of low power consumption of the information processing apparatus 100 using the nonvolatile memory 130 as the main memory will be described.

  When waiting for input of data from a keyboard or network (not shown), there is no process to be processed, so the processor 110 transitions to an idle state. Since the processor 110 is in an idle state, access to the memory 130 does not occur, and the power supply of the memory 130 can be shut off.

  Therefore, the processor 110 confirms that a program (power control program) necessary for power control of the memory 130 is stored in the memory 111 when transitioning to the idle state. When the power control program is not stored in the memory 111, the power control program is read from the memory 130 and stored in the memory 111 in the processor 110.

  Next, the processor 110 controls the power supply of the memory 130 by executing the power supply control program, and shuts off the power supply of the memory 130. At this time, since the memory 130 is a nonvolatile memory, stored information is not erased even when the power is turned off.

  As described above, when the memory 130 is a non-volatile memory, the power of the memory 130 can be quickly shut down without saving information in the memory 130. Further, when access from the processor 110 to the memory 130 does not occur, the power consumption of the information processing apparatus 100 can be reduced by immediately turning off the power of the memory 130. As described above, even when the power of the memory is cut off from the state where the power of the processor is turned on, the processor can correctly access the memory.

  Next, an operation when data is input to the processor 110 when the memory 130 is powered off will be described. FIG. 2 is a flowchart showing the overall flow of the return processing in the first embodiment. The return process represents a process of transitioning from the idle state to the normal state.

  When data is input to the processor 110, the processor 110 transitions from the idle state to the normal state (step S101). The processor 110 turns on the power to the memory 130 in accordance with the power control program stored in the memory 111.

  Care must be taken when turning on the main memory while the processor is operating. In the prior art, there is no means for the processor to check the state of the main memory in the memory bus connecting the processor and the main memory. This is because in the conventional information processing apparatus, only the power supply of the main memory is not shut off, and there is a precondition that the main memory is always accessible when the processor is operating. For this reason, the processor cannot know that the main memory is accessible. Also, under this precondition, the processor may send a read or write request to the main memory through the memory bus when data to be processed is input before the main memory is ready. is there.

  On the other hand, the main memory cannot respond to an access request from the outside for a certain period of time after the power is turned on until the internal circuit is stabilized. That is, the main memory cannot receive a read or write request for a certain time.

  As described above, if an access occurs from the processor 110 before the preparation after the activation of the memory 130 is completed, the memory 130 cannot respond normally. For this reason, for example, the processor 110 cannot read the program from the memory 130 normally, and may enter an illegal instruction error state when trying to execute a program that does not operate normally. As a result, the processor 110 executes an interrupt process corresponding to the illegal instruction process. Every time the processor 110 is in an idle state and the power of the memory 130 is shut off, if interrupt processing for processing an illegal instruction error is executed, useless power is consumed.

  Therefore, in the present embodiment, the state monitoring unit 120 that inputs the time from when the memory 130 is turned on to when it is activated is used. Hereinafter, returning to FIG.

  When the processor 110 transitions from the idle state to the normal state, first, in order to grasp the state of the memory 130, the processor 110 inquires of the state monitoring unit 120 about the state of the memory 130 (step S102). The receiving unit 121 of the state monitoring unit 120 receives the inquiry. The determination unit 122 is notified that the inquiry has been received. The determination unit 122 determines whether or not the memory 130 is in a responsive (accessible) state (step S103). For example, the determination unit 122 determines whether the startup time of the memory 130 has elapsed since the power-on time. The determination unit 122 determines that the memory 130 is accessible when a time corresponding to the activation time has elapsed from the power-on time. Further, the determination unit 122 determines that the memory 130 is not accessible before the time corresponding to the activation time elapses from the power-on time.

  The determination unit 122 may have a function of counting the number of clocks of the state monitoring unit after the supply of power to the memory 130 is started. Then, when the reception unit 121 receives an inquiry from the processor 110 as to whether the memory 130 is accessible, the determination unit 122 may determine that access is possible from the number of clocks.

  When the memory 130 is accessible (step S103: Yes), the transmission unit 123 notifies the processor 110 that the memory 130 is accessible (step S104). When the memory 130 is not accessible (step S103: No), the transmission unit 123 notifies the processor 110 that the memory 130 is not accessible (step S105).

  The state monitoring unit 120 may have the following functions in addition to the above functions. For example, the memory 130 may need to be set around the interface at startup. Therefore, the state monitoring unit 120 may be configured to control the bus necessary for setting when the memory 130 is activated and set the interface of the memory 130.

(Modification)
In FIG. 1, the state monitoring unit 120 is connected between the processor 110 and the memory 130. If it is not necessary to set an interface for the memory 130 and the processor 110 is equipped with a communication interface such as I2C or UART (Universal Asynchronous Receiver Transmitter), the state monitoring unit 120 includes a processor as shown in FIG. 110 and the memory 130 may not be connected.

  FIG. 3 is a block diagram illustrating an example of the configuration of the information processing apparatus 100-1 according to the modification of the first embodiment. As illustrated in FIG. 3, the information processing apparatus 100-1 includes a processor 110-1, a memory 130, and a state monitoring unit 120-1. In addition, the structural part provided with the function similar to FIG. 1 attaches | subjects the same code | symbol, and abbreviate | omits description.

  The processor 110-1 is different from the processor 110 in FIG. 1 in that the processor 110-1 is connected to the state monitoring unit 120-1 through an interface 52 such as UART. Similarly, the state monitoring unit 120-1 is different from the state monitoring unit 120 of FIG. 1 in that it is connected to the processor 110-1 by the interface 52. The bus 51 corresponds to a bus obtained by integrating the bus 51a and the bus 51b and the bus 51a and the bus 51c in FIG.

  The receiving unit 121-1 is different from the receiving unit 121 of FIG. 1 in that it receives an inquiry from the processor 110-1 through the interface 52. The transmission unit 123-1 is different from the transmission unit 123 of FIG. 1 in that the determination result is transmitted to the processor 110-1 via the interface 52. That is, this modification is configured to receive the power-on time from the processor 110-1 through UART or the like and to answer the inquiry about the state of the memory 130 from the processor 110.

(Second Embodiment)
FIG. 4 is a block diagram illustrating an example of the configuration of the information processing apparatus 200 according to the second embodiment. As illustrated in FIG. 4, the information processing apparatus 200 includes a processor 210, a memory 230, a state monitoring unit 120, and a power supply control unit 240.

  The second embodiment is different from the first embodiment in that the functions of the processor 210 and the memory 230 and the power supply control unit 240 are added. Since other configurations and functions are the same as those in FIG. 1 which is a block diagram of the information processing apparatus 100 according to the first embodiment, the same reference numerals are given, and description thereof is omitted here.

  The processor 210 and the memory 230 are connected to the power supply control unit 240 by signal lines 61 and 62, respectively.

  In the second embodiment, the power control unit 240 manages the power of the processor 210 and the memory 230. The power control unit 240 is connected by a signal line 61 so as to be able to communicate with the processor 210. When the power supply control unit 240 receives an instruction from the processor 210 that the power of the processor 210 and the memory 230 may be cut off via the signal line 61, the power supply control unit 240 cuts off the power of the processor 210, the memory 230, and the state monitoring unit 120. Or a function capable of stepping down and stepping up to an arbitrary voltage.

  When the processor 210 is in a data input waiting state, it sends an instruction to lower the supply voltage to the processor 210 or an instruction to shut off the power, and an instruction to shut off the power of the state monitoring unit 120 and the memory 230 to the power control unit 240. To do.

  When the processor 210 instructs the power supply control unit 240 to turn off the power of the processor 210 or to set the voltage in the power saving mode operation in which the information in the processor 210 is not held, the information in the processor 210 is first stored in the memory. 230 needs to be evacuated. For this reason, information necessary for the next startup of the processor 210 is written in the memory 230 first, and then an instruction to turn off the power of the processor 210 is sent to the power control unit 240. If the power supply voltage of the processor 210 is lowered to the lower limit at which the information in the processor 210 is held, it is not necessary to save the information in the processor 210. In this case, as soon as the processor 210 enters the idle state, the processor 210 sends an instruction to the power supply control unit 240 to cut down the supply voltage to the processor 210 and shut off the power supply to the state monitoring unit 120 and the memory 230.

  Next, when key input from the user or data from the network arrives, the power supply control unit 240 boosts the power supply voltages of the processor 210, the state monitoring unit 120, and the memory 230. The power control unit 240 holds information related to the activation time of the devices managed by the power control unit 240 in advance. At the time of boosting the power supply voltage, the power supply control unit 240 boosts the power supply voltage in order from the device that takes time to start based on the stored information.

  In addition, the processor 210 may issue an instruction to reduce the power supply voltage only for the memory 230. In this case, the power supply control unit 240 steps down only the power supply voltage of the memory 230, and boosts the power supply voltage of the memory 230 when an instruction to boost the voltage of the memory 230 is received from the processor 210. As described above, when the power of the memory 230 is shut off while the processor 210 is running, the problem described in the first embodiment occurs. For this reason, the state monitoring unit 120 is used so that no trouble occurs when the memory 230 is turned on.

  Next, a return process performed by the information processing apparatus 200 according to the second embodiment configured as described above will be described with reference to FIG. FIG. 5 is a flowchart showing the overall flow of the return processing in the second embodiment.

  The processor 210 instructs the power supply control unit 240 to increase the voltage of the memory 230 (step S201). The power supply control unit 240 boosts the power supply voltage of the memory 230 according to the instruction (step S202). Thereafter, the processor 210 inquires of the state monitoring unit 120 about the state of the memory 230, and accesses it when it is accessible (steps S203 to S206).

  Since the processing from step S203 to step S206 is the same as the processing from step S102 to step S105 in the information processing apparatus 100 according to the first embodiment, the description thereof is omitted.

(Modification)
The state monitoring unit 120 of FIG. 4 is connected between the processor 210 and the memory 230, but the state monitoring unit 120 includes the processor 210, the memory 230, and the like as in the modification of the first embodiment (FIG. 3). It may not be connected between. FIG. 6 is a block diagram showing an example of the configuration of the information processing apparatus 200-1 according to the modified example of the second embodiment configured as described above. Each component in FIG. 6 has the same function as the component in FIG. 3 or FIG. As shown in FIG. 6, this modification is configured to receive a power-on time from the processor 210-1 through a UART or the like and to answer an inquiry about the state of the memory 230 from the processor 210-1.

(Third embodiment)
FIG. 7 is a block diagram illustrating an example of the configuration of the information processing apparatus 300 according to the third embodiment. As illustrated in FIG. 7, the information processing apparatus 300 includes a processor 210, a memory 230, a state monitoring unit 120, a power supply control unit 340, a solar battery 351, and a secondary battery 352. In the third embodiment, a solar battery 351 and a secondary battery 352, which are power generation devices, are further added to the structure of the second embodiment (FIG. 4).

  As described above, the information processing apparatus 300 includes the solar battery 351 and operates using the power generated by the solar battery 351 and the power stored in the secondary battery 352.

  The solar cell 351 converts light energy into electric power and outputs it. The secondary battery 352 functions as a power storage unit that stores the power output from the solar cell 351 and supplies the stored power to each component of the information processing apparatus 300 including the processor 210 and the memory 230. The point that the power supply control unit 340 further has a function of controlling the power supply of each component according to the amount of power generated by the solar battery 351 and the amount of power stored in the secondary battery 352 is the same as that of the power supply control unit 240 of the second embodiment. Is different.

  The solar cell 351 used as a power generation device in this embodiment generally has an unstable power generation amount. Further, the power generation amount of the solar battery 351 and the surplus power consumption consumed by the processor 210 and the memory 230 are used for charging the secondary battery 352. For this reason, the electric energy which the secondary battery 352 has changes depending on a user's utilization condition and the electric power generation amount of the solar cell 351. Therefore, in the case of driving with the solar battery 351 and the secondary battery 352, there is a possibility that electric power necessary for the operation of the information processing apparatus 300 cannot be obtained.

  Thus, when the power supply is unstable and necessary power cannot be obtained, it is necessary to quickly shift the processor 210 and the memory 230 to the low power consumption mode. In addition, in order to safely interrupt the state of the information processing apparatus 300, it is necessary to perform control to save information necessary for restarting when the power becomes the minimum. Furthermore, the control must be performed so that the power is started when the power becomes startable again.

  The operation of the information processing apparatus 300 that obtains necessary power from the solar battery 351 or the secondary battery 352 using the solar battery 351 that is an unstable power generation apparatus as described above will be described below.

  A case will be described in which there is sufficient power for the information processing apparatus 300 to operate during operation, and the processor 210 shifts to a sleep state in order to reduce power consumption. Even when the power generation amount of the solar battery 351 or the electric power stored in the secondary battery 352 is sufficient, the power of the processor 210 and the memory 230 is shut off when the processor 210 is in an idle state.

  When data to be processed by the processor 210 such as a keyboard input from the user is sent, the power supply control unit 340 confirms the power of the solar battery 351 and the secondary battery 352, and the power necessary for starting the power supply is confirmed. In some cases, the power supply voltages of the processor 210, the memory 230, and the state monitoring unit 120 are boosted to activate these devices.

  When the power necessary for the information processing apparatus 300 to operate cannot be obtained, that is, the power generated by the solar battery 351 and the power stored in the secondary battery 352 are small, and the information processing apparatus 300 is activated. If it is determined that the power cannot be continued, the power control unit 340 starts preparations for shutting off the power of the processor 210 and the memory 230. First, the power supply control unit 340 notifies the processor 210 of an interrupt. The processor 210 saves the internal state of the processor 210 to the memory 230 in response to an interrupt from the power control unit 340. When the information in the processor 210 is saved in the memory 230, the processor 210 notifies the power supply control unit 340 that the internal information has been saved normally through the signal line 61. As a result, the processor 210 can safely shut off the power.

  The power supply control unit 340 reduces the power supply voltage of the processor 210, the memory 230, and the state monitoring unit 120 after receiving a notification from the processor 210 that the power supply is ready to be cut off. As a result, the information processing apparatus 300 enters a sleep state.

  It is assumed that there is a key input from the user in this sleep state. Hereinafter, the processing in this case will be described with reference to FIG. FIG. 8 is a flowchart showing the overall flow of the power supply control process in the third embodiment.

  When the power supply control unit 340 is activated by the power of the solar battery 351 or the secondary battery 352, the power supply control unit 340 uses the input from the user as a trigger to change the power of the secondary battery 352 to the processor 210 and the memory. Check if the power is enough to start 230. For example, the power supply control unit 340 determines whether or not the amount of power stored in the secondary battery 352 is greater than a threshold value for power amount (step S301). The threshold value is determined in advance as, for example, the minimum amount of power required for starting the processor 210, the memory 230, the state monitoring unit 120, and the power supply control unit 340.

  When the amount of power of the secondary battery 352 is equal to or less than the threshold (step S301: No), the input from the user is ignored, and the power supply control unit 340 maintains the state of the information processing device 300 in the sleep state (step S303). After the secondary battery 352 has stored enough power to start up the information processing apparatus 300, when a startup event of the information processing apparatus 300 is sent to the power supply control unit 340, that is, the amount of power of the secondary battery is When larger than the threshold value (step S301: Yes), the power supply control unit 340 activates the processor 210, the memory 230, and the state monitoring unit 120 (steps up the power supply voltage) (step S302), and transitions from the sleep state to the normal state. To do.

  Even if the power generation amount of the solar battery 351 is sufficient, the power supply control unit 340 does not activate the information processing apparatus 300 when the charge amount of the secondary battery 352 is insufficient. This is because the power stored in the secondary battery 352 can be used as stable power, but the power generated by the solar battery 351 is unstable and the power generation amount may be insufficient during startup. For this reason, the power supply control unit 340 refers to the power stored in the secondary battery 352 when starting up, and when the power is insufficient, the solar battery 351 is sufficient to start up. The power supply voltage of the processor 210 and the memory 230 is not boosted until power is stored.

  As described above, when the unstable solar battery 351 is mounted, the sleep state is continued and the secondary battery 352 is stored if the power stored in the secondary battery 352 is equal to or lower than a certain level. The processor 210 and the memory 230 are activated when the power recovered to a certain value or more. As described above, when the unstable solar cell 351 is provided, the information processing apparatus 300 continues to operate normally even when the power is insufficient due to the control not to start up until the power recovers. It becomes possible.

  As described above, according to the first to third embodiments, since the nonvolatile memory is used as the main memory, it is not necessary to save information when the power is turned off. For this reason, the power consumption can be further reduced by immediately shutting off the power supply of the main memory when there is no access to the main memory. Further, when the main memory is activated after the power is turned off, it is determined whether the main memory is accessible, and control is performed so that the main memory is accessed when the main memory is accessible. As a result, it is possible to avoid an error state due to unauthorized reading of information from the main memory.

(Modification)
In each of the above embodiments, when the memory 130 is not accessible, the processor 110 is notified that the memory 130 is inaccessible. On the other hand, the determination may be repeated without notifying the processor 110 until the memory 130 becomes accessible.

  In the present modification, the state monitoring unit 120 determines the state of the memory 130 and transmits to the processor 110 that access is possible only when the memory 130 is accessible. For example, the transmission unit 123 transmits that the memory 130 is accessible to the processor 110 via the bus 51b only when the determination result by the determination unit 122 is transmitted, that is, when the memory 130 is accessible. To do.

  FIG. 9 is a flowchart showing the overall flow of the return processing in the modified example configured as described above. Steps S401 and S402 are the same as steps S101 and S102 in FIG.

  In this modification, when the determination unit 122 determines that the memory 130 is not accessible (step S403: No), the determination unit 122 repeats the determination until the accessible state is reached. When the memory 130 becomes accessible (step S403: Yes), the determination unit 122 notifies the transmission unit 123 of a determination result indicating that the memory 130 is accessible. Receiving the notification of the determination result, the transmission unit 123 notifies the processor 110 that the memory 130 is accessible (step S404).

  A program executed by the information processing apparatus according to the first to third embodiments is a file in an installable format or an executable format, and is a CD-ROM (Compact Disk Read Only Memory), a flexible disk (FD), a CD. -Recorded on a computer-readable recording medium such as R (Compact Disk Recordable), DVD (Digital Versatile Disk), etc., and provided as a computer program product.

  The program executed by the information processing apparatus according to the first to third embodiments is stored on a computer connected to a network such as the Internet and is provided by being downloaded via the network. Also good. Moreover, you may comprise so that the program run with the information processing apparatus concerning 1st-3rd embodiment may be provided or distributed via networks, such as the internet.

  Moreover, you may comprise so that the program of 1st-3rd embodiment may be previously incorporated in ROM etc. and provided.

  The program executed by the information processing apparatus according to the first to third embodiments has a module configuration including the above-described units (state monitoring units), and the CPU (processor) stores the above as actual hardware. By reading and executing the program from the medium, the above-described units are loaded onto the main storage device, and the above-described units are generated on the main storage device.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

51a, 51b, 51c Bus 52 Interface 61, 62 Signal line 100, 200, 300 Information processing device 110, 210 Processor 111 Memory 120 State monitoring unit 121 Reception unit 122 Determination unit 123 Transmission unit 130, 230 Memory 240, 340 Power supply control unit 351 Solar cell 352 Secondary battery

Claims (18)

A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
The power supply control unit does not start the main storage unit and the processor until the power amount of the power storage unit recovers to a predetermined threshold value or higher, and the power amount of the power storage unit is equal to or higher than a predetermined threshold value. To recover power from the power storage unit to the main storage unit and the processor,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
When there is data input, the power control unit does not start the main storage unit and the processor until the power amount of the power storage unit recovers to a predetermined threshold or more, and the power amount of the power storage unit Is restored to a predetermined threshold or more, control to supply power from the power storage unit to the main storage unit and the processor,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
When there is an input from a user, the power supply control unit does not start the main storage unit and the processor until the power amount of the power storage unit recovers to a predetermined threshold or more, and the power storage unit If the amount of power has recovered to a predetermined threshold or more, control to supply power from the power storage unit to the main storage unit and the processor,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
When there is input of data to be processed by the processor, the power control unit does not start the main storage unit and the processor until the power amount of the power storage unit recovers to a predetermined threshold value or more. If the power amount of the power storage unit has recovered to a predetermined threshold or more, control to supply power from the power storage unit to the main storage unit and the processor,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
The power supply control unit does not increase the power supply voltage of the main storage unit and the processor until the power amount of the power storage unit recovers to a predetermined threshold or more, and the power amount of the power storage unit is determined in advance. When recovering to the threshold value or higher, the power supply voltage of the main memory unit and the processor is boosted,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
When the power amount of the power storage unit does not recover to a predetermined threshold or more, the sleep state is maintained, and when the power amount of the power storage unit recovers to a predetermined threshold value or more, the main storage unit and An information processing apparatus that boosts the power supply voltage of the processor to change from a sleep state to a normal state. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
When the power amount of the power storage unit does not recover to a predetermined threshold or more, the sleep state is maintained, and when the power amount of the power storage unit recovers to a predetermined threshold value or more, the main storage unit and An information processing apparatus that recovers from a sleep state by boosting a power supply voltage of the processor. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
When the power amount of the power storage unit does not recover to a predetermined threshold or more, the sleep state is maintained, and when the power amount of the power storage unit recovers to a predetermined threshold value or more, the main storage unit and An information processing apparatus that supplies power to the processor to change from a sleep state to a normal state. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
When the power amount of the power storage unit does not recover to a predetermined threshold or more, the sleep state is maintained, and when the power amount of the power storage unit recovers to a predetermined threshold value or more, the main storage unit and An information processing apparatus that supplies power to the processor to return from a sleep state. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
The power control unit controls the power storage unit to supply power from the power storage unit to the main memory unit and the processor that are not activated when the power amount of the power storage unit recovers to a predetermined threshold value or more. ,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
When there is data input, the power supply control unit, from the power storage unit to the main memory unit and the processor that are not activated, if the power amount of the power storage unit has recovered to a predetermined threshold value or more Control to supply power,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
When there is an input from a user, the power control unit may store the power storage in the main memory unit and the processor that are not activated if the power amount of the power storage unit has recovered to a predetermined threshold value or more. Supply power from the
The processor is activated when power is supplied from the power storage unit.
Information processing device to be controlled. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit;
A power generation unit for supplying generated power to the power storage unit;
A power supply control unit that controls supply of power to the main storage unit,
When there is input of data to be processed by the processor, the power control unit, if the power amount of the power storage unit has recovered to a predetermined threshold or more, the main storage unit that has not been activated and Controlling the processor to supply power from the power storage unit,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying generated power to the power storage unit;
A power control unit that controls supply of power to the main storage unit and the processor,
The power supply control unit boosts the power supply voltage of the main storage unit and the processor that are not activated when the power amount of the power storage unit recovers to a predetermined threshold value or more,
The processor is activated when power is supplied from the power storage unit.
Information processing device. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
An information processing apparatus that boosts the power supply voltage of the main storage unit and the processor that are not activated to change from a sleep state to a normal state when the power amount of the power storage unit recovers to a predetermined threshold value or more. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
An information processing apparatus that boosts the power supply voltage of the main storage unit and the processor that have not been activated and recovers from a sleep state when the amount of power of the power storage unit recovers to a predetermined threshold value or more. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
An information processing apparatus that supplies power to the main storage unit and the processor that have not been activated to change from a sleep state to a normal state when the power amount of the power storage unit recovers to a predetermined threshold value or more. A processor;
A non-volatile main storage unit for storing information necessary for starting up the processor;
A power storage unit for supplying power to the main storage unit and the processor;
A power generation unit for supplying the generated power to the power storage unit,
An information processing apparatus that supplies power to the main storage unit and the processor that are not activated to return from a sleep state when the amount of power of the power storage unit recovers to a predetermined threshold value or more.

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