JP2015083960A - Abnormality detection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an abnormality detection device capable of appropriately detecting open abnormality of a conductive member provided between adjacent cell groups.SOLUTION: A protection diode 32 is provided between a pair of electric paths L5 and L6 to be connected to both ends of a between-stack wire SP, and a Zener diode 70a is provided at a bypass path 70 for causing short circuit between the pair of electric paths L5 and L6. A controller 50 (abnormality determination means 50a) determines whether or not open abnormality is present in the between-stack wire SP, on the basis of either a potential difference between both ends of the bypass path 70 or voltage between terminals of a capacitor 44 when an input side switch group 42 is operated so as to allow a discharge current of the capacitor 44 to flow from the sixth electric path L6 on a high potential side of the between-stack wire SP (or the bypass path 70) to the fifth electric path L5 on its low potential side through either the between-stack wire SP or the bypass path 70 in a state where the capacitor 44 is charged with prescribed voltage.

Description

  The present invention relates to an abnormality detection device applied to an assembled battery formed by connecting a plurality of cell groups, which are serially connected bodies of a plurality of battery cells, in series.

  Conventionally, a battery monitoring device that monitors battery cells in each cell group constituting an assembled battery is known (see, for example, Patent Document 1).

  This Patent Document 1 discloses a battery monitoring device including a plurality of monitoring ICs that monitor whether or not the voltage between terminals of a unit battery is within a normal voltage range, with one or a plurality of battery cells constituting a cell group as a unit battery. Has been. This battery monitoring device takes into account the maintainability of the assembled battery that is at a high voltage, and between adjacent cell groups, between the negative terminal of the high potential side cell group and the positive terminal of the low potential side cell group. In addition, a conductive member such as a service plug is interposed.

JP 2011-112475 A

  By the way, in patent document 1, the open abnormality of the electrically-conductive member by which the conduction | electrical_connection state between adjacent cell groups is interrupted | blocked is not considered in particular.

  Therefore, the present inventors examined an abnormality detection device that can detect an open abnormality of a conductive member. Hereinafter, the battery pack abnormality detection device under study by the present inventors will be described with reference to FIGS. 33 and 34. FIG. FIG. 33 is a schematic circuit diagram showing an examination example 1 of the abnormality detection apparatus under investigation by the inventors, and FIG. 34 is an examination example 2 of the abnormality detection apparatus under examination by the inventors. FIG.

  The abnormality detection device BMU shown in FIG. 33 includes two cell groups CG1 and CG2 which are a series connection body of a plurality of battery cells, and the cell groups CG1 and CG2 are connected in series via a conductive member SP. Applies to assembled batteries.

  The abnormality detection device BMU includes monitoring ICs connected to both ends of unit batteries BC1 to BC7 made up of a predetermined number of battery cells in each cell group CG1 and CG2 via electric paths L1 to L10. This monitoring IC is provided for each predetermined number of unit cells BC1 to BC7, monitors the voltage between the terminals of each unit cell BC1 to BC7, and outputs the monitoring result to the microcomputer. In the abnormality detection device BMU of the present study example, the conductive member SP is provided between the pair of electrical paths L3 and L4 connected to the adjacent monitoring IC among the plurality of electrical paths L1 to L10.

  Further, the abnormality detection device BMU includes a flying capacitor type voltage detection circuit VSC that detects the voltage across the terminals of the series connection body of the unit batteries BC1 to BC7 corresponding to each monitoring IC and outputs the detection result to the microcomputer. ing. The voltage detection circuit VSC turns on the output switches SWa and SWb after turning on the input switches SW1 and SW2, thereby sandwiching the conductive member SP and the cell group CG1 connected in series to the conductive member SP. The potential difference between L1 and L4 can be detected.

  Further, in the abnormality detection device BMU according to Study Example 1, in order to detect an open abnormality of the conductive member SP, a Zener diode ZD is provided between the pair of electric paths L3 and L4 connected to both ends of the conductive member SP. Are short-circuited by the bypass path LB.

  In the abnormality detection device BMU configured as described above, when the open abnormality of the conductive member SP has not occurred, when the input switches SW1 and SW2 are turned on, the discharge current of the cell group CG1 flows through the conductive member SP. The flying capacitor C is charged. At this time, the voltage between the terminals of the flying capacitor C becomes a value (≈Vb) equivalent to the battery voltage Vb of the cell group CG1.

  On the other hand, when the open abnormality of the conductive member SP has occurred, when the input switches SW1 and SW2 are turned on, the discharge current of the cell group CG1 flows through the Zener diode ZD, and the flying capacitor C is charged (see FIG. 33). At this time, the voltage across the terminals of the flying capacitor C is a value obtained by subtracting the breakdown voltage Vz of the Zener diode ZD from the battery voltage Vb of the cell group CG1 (= Vb−Vz).

  As described above, in the abnormality detection device BMU of the examination example 1, the voltage between the terminals of the flying capacitor C when the input switches SW1 and SW2 are turned on varies depending on whether or not the conductive member SP is open. Therefore, it is possible to determine whether or not there is an open abnormality of the conductive member SP based on the voltage across the terminals of the flying capacitor C when the input switches SW1 and SW2 are turned on.

  However, for example, as in Study Example 2 shown in FIG. 34, the conductive member SP is provided between the pair of electrical paths L5 and L6 connected to a single monitoring IC among the plurality of electrical paths L1 to L10. In the configuration, the presence or absence of the open abnormality of the conductive member SP cannot be determined by the above-described method.

  Explaining this point, in Study Example 2, when the open abnormality of the conductive member SP occurs, when the input switches SW1 and SW2 are turned on, the discharge current of the cell group CG1 bypasses the bypass path LB. It flows to the protection diode D provided inside the monitoring IC (see the broken line arrow in FIG. 34). At this time, since the forward voltage Vf of the protection diode D is very small compared to the breakdown voltage Vz of the Zener diode ZD, the voltage across the terminals of the flying capacitor C is almost equal to the battery voltage Vb of the cell group CG1. (≈Vb). The protection diode D is a current protection element that protects the monitoring IC from an overcurrent. Among the pair of electrical paths L5 and L6 connected to both ends of the conductive member SP, the anode is connected to the electrical path L5 on the low potential side. The cathode is connected to the electric path L6 on the high potential side.

  As described above, in the abnormality detection device BMU of the examination example 2, even when the open abnormality of the conductive member SP occurs, the voltage across the terminals of the flying capacitor C when the input switches SW1 and SW2 are turned on is normal compared to the normal state. Almost no change. For this reason, the presence or absence of the open abnormality of the conductive member SP cannot be determined based on the voltage across the terminals of the flying capacitor C when the input switches SW1 and SW2 are turned on.

  In addition, not only the structure shown in the examination example 2, but only the flow of current from the low-potential side electrical path to the high-potential side path among the pair of electrical paths connected to both ends of the conductive member SP is allowed. When the current protection element is provided, it cannot be determined whether the conductive member SP has an open abnormality.

  In the study examples 1 and 2, the example in which the Zener diode ZD is provided in the bypass path LB has been described. However, the present invention is not limited to this, and the case where the capacitor (capacitor) is provided in the bypass path LH is not limited thereto. Cannot determine whether there is an open error.

  An object of the present invention is to provide an abnormality detection device capable of appropriately detecting an open abnormality of a conductive member provided between adjacent cell groups.

  The present invention is applied to an assembled battery (10) formed by connecting a plurality of cell groups (CG1, CG2), which are series connection bodies in which a plurality of battery cells are connected in series, and provided between adjacent cell groups. The present invention is directed to an abnormality detection device that detects an open abnormality of a conductive member (SP).

  In order to achieve the above object, according to the first aspect of the present invention, unit batteries (BC1 to BC6) defined by either a single battery cell in a cell group or a predetermined number of battery cells connected in series. Provided between a plurality of electrical paths (L1 to L10) connected to both ends and a pair of electrical paths (L5, L6) connected to both ends of the conductive member among the plurality of electrical paths. A current protection element (32) that allows only a current flow from the low-potential side electrical path (L5) to the high-potential side electrical path (L6) in the path, and at both ends of the conductive member among the plurality of electrical paths. A bypass path (70) for short-circuiting the first electrical path (L6) having a potential higher than the high potential side and the second electrical path (L5) having a potential lower than the low potential side at both ends of the conductive member; Set in the bypass path A Zener diode (70a) having a cathode connected to the first electric path and an anode connected to the second electric path, and a detection circuit (46, 46) for detecting a voltage between terminals of the flying capacitor (44). 48) capacitor voltage detection means (40) comprising an input side switch group (42) for charging the battery voltage of one or more unit cells to the flying capacitor via a plurality of electrical paths; And an abnormality determining means (50a) for determining presence / absence of an open abnormality of the conductive member. Then, the abnormality determining means is configured to supply the second electric power from the first electric path side through either the conductive member or the bypass path in a state where a voltage equal to or higher than a predetermined reference voltage is charged to the flying capacitor. Determining whether there is an open abnormality in the conductive member based on the potential difference at both ends of the bypass path when the input side switch group is operated so that the discharging current of the flying capacitor flows to the path side or the voltage across the terminals of the flying capacitor It is characterized by.

  First, the second electric path side having a potential lower than the electric path on the low potential side from the first electric path side having a potential higher than the electric path on the high potential side in the pair of electric paths connected to both ends of the conductive member. By causing the discharging current of the flying capacitor to flow, the discharging current can be passed through either the conductive member or the bypass path instead of the current protection element.

  Then, the discharging current of the flying capacitor flows to the bypass path side when the conductive member having an open abnormality in the conductive member is abnormal, and flows to the conductive member side when the conductive member has no open abnormality in the conductive member.

  When the discharge current of the flying capacitor flows to the bypass path, the potential difference at both ends of the bypass path and the voltage across the flying capacitor at the time of discharge are affected by the influence of the breakdown voltage of the Zener diode (the Zener voltage). On the other hand, it deviates greatly.

  For this reason, even if a current protection element is provided between a pair of electrical paths connected to both ends of the conductive member, the open abnormality of the conductive member is caused based on the potential difference at both ends of the bypass path or the voltage across the terminals of the flying capacitor. It is possible to appropriately determine whether or not there is.

  Further, as in the third aspect of the invention, the flying capacitor discharge current is allowed to flow even when the bypass capacitor (72) is connected to the bypass path between the first electric path and the second electric path. Thus, the discharge current can flow through either the conductive member or the bypass path instead of the current protection element. Then, the discharging current of the flying capacitor flows to the bypass path side when the conductive member having an open abnormality in the conductive member is abnormal, and flows to the conductive member side when the conductive member has no open abnormality in the conductive member.

  When the discharging current of the flying capacitor flows to the bypass path, the bypass capacitor is charged, so that the potential difference at both ends of the bypass path and the voltage between the terminals of the flying capacitor during discharge greatly deviate from the normal state of the conductive member. To do.

  For this reason, even if a current protection element is provided between a pair of electrical paths connected to both ends of the conductive member, the open abnormality of the conductive member is caused based on the potential difference at both ends of the bypass path or the voltage across the terminals of the flying capacitor. It is possible to appropriately determine whether or not there is.

  In addition, the code | symbol in the parenthesis of each means described in this column and the claim shows an example of a correspondence relationship with the specific means described in the embodiment described later.

It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 1st Embodiment. It is a timing chart which shows the voltage change etc. at the time of the abnormality determination process of 1st Embodiment. It is explanatory drawing for demonstrating the charge path | route at the time of the abnormality determination process of 1st Embodiment. It is explanatory drawing for demonstrating the discharge path | route at the time of the abnormality determination process of 1st Embodiment. It is a timing chart which shows the voltage change etc. at the time of the abnormality determination process of 2nd Embodiment. It is a timing chart which shows the voltage change etc. at the time of the abnormality determination process of 3rd Embodiment. It is a timing chart which shows the voltage change etc. at the time of the abnormality determination process of 4th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 5th Embodiment. It is explanatory drawing for demonstrating the charge path | route at the time of the abnormality determination process of 5th Embodiment. It is explanatory drawing for demonstrating the discharge path | route at the time of the abnormality determination process of 5th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 6th Embodiment. It is explanatory drawing for demonstrating the charge path | route at the time of the abnormality determination process of 6th Embodiment. It is explanatory drawing for demonstrating the discharge path | route at the time of the abnormality determination process of 6th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 7th Embodiment. It is explanatory drawing for demonstrating the charge path | route at the time of the abnormality determination process of 7th Embodiment. It is explanatory drawing for demonstrating the discharge path | route at the time of the abnormality determination process of 7th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 8th Embodiment. It is explanatory drawing for demonstrating the charge path | route at the time of the abnormality determination process of 8th Embodiment. It is explanatory drawing for demonstrating the discharge path | route at the time of the abnormality determination process of 8th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 9th Embodiment. It is explanatory drawing for demonstrating the charge path | route at the time of the abnormality determination process of 9th Embodiment. It is explanatory drawing for demonstrating the discharge path | route at the time of the abnormality determination process of 9th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 10th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on 10th Embodiment. It is a figure for demonstrating the disconnection detection of each electric path which connects between each cell and battery monitoring unit which concern on 10th Embodiment. It is a figure for demonstrating control of disconnection detection of each electric path which connects between each cell and battery monitoring unit which concern on 10th Embodiment. It is a figure for demonstrating the disconnection detection of each electric path which connects between each cell and battery monitoring unit which concern on 10th Embodiment. It is a figure for demonstrating control of disconnection detection of each electric path which connects between each cell and battery monitoring unit which concern on 10th Embodiment. It is a figure for demonstrating control of disconnection detection of each electric path which connects between each cell and battery monitoring unit which concern on 10th Embodiment. It is a whole block diagram of the assembled battery and battery monitoring unit which concern on other embodiment (1). It is a whole block diagram of the assembled battery and battery monitoring unit which concern on other embodiment (2). It is a whole block diagram of the assembled battery and battery monitoring unit which concern on other embodiment (3). It is a typical circuit diagram which shows the example 1 of an assembled battery and abnormality detection apparatus. It is a typical circuit diagram which shows the example 2 of an assembled battery and abnormality detection apparatus.

  Embodiments of the present invention will be described below with reference to the drawings. Note that, in each of the following embodiments, parts that are the same as or equivalent to the matters described in the preceding embodiment are denoted by the same reference numerals, and the description thereof may be omitted. Moreover, in each embodiment, when only a part of the component is described, the component described in the preceding embodiment can be applied to the other part of the component.

(First embodiment)
In the present embodiment, the abnormality detection device according to the present invention is applied to a battery monitoring unit 20 that monitors a high-voltage battery that constitutes a power source of a motor generator as an in-vehicle main machine.

  As shown in FIG. 1, an assembled battery 10 that is a high-voltage battery is a series in which a plurality of battery cells composed of secondary batteries such as lithium ion batteries are connected in series so that the voltage between terminals is, for example, 100 V or more. It consists of a connection body. In addition, the assembled battery 10 of this embodiment functions also as a storage battery which stores the electric power produced | generated by the regeneration control of a motor generator in addition to the function as a power supply which supplies electric power to a motor generator.

  Incidentally, in the present embodiment, as the assembled battery 10, a battery in which a first cell group CG1 and a second cell group CG2 that are serially connected bodies of a plurality of battery cells are connected in series is illustrated. Each cell group CG1 and CG2 is configured as a battery stack in which battery cells are stacked.

  The cell groups CG1 and CG2 are connected in series via inter-stack wires SP which are “conductive members”. This inter-stack wire SP connects the positive terminal of the first cell group CG1 on the low potential side and the negative terminal of the second cell group CG2 on the high potential side. The inter-stack wire SP also functions as a service plug that cuts off the continuity between the cell groups CG1 and CG2 when the assembled battery 10 is maintained.

  Each cell group CG1 and CG2 is composed of unit batteries defined by either one or two adjacent battery cells. Incidentally, in the present embodiment, the first cell group CG1 is configured by unit batteries BC1 to BC3 and the like, and the second cell group CG2 is configured by unit batteries BC4 to BC6 and the like. Hereinafter, the unit batteries constituting the first cell group CG1 are referred to as first to third unit batteries BC1 to BC3, and the unit batteries constituting the second cell group CG are referred to as fourth to sixth unit batteries BC4 to BC6. In the present embodiment, the description will be made assuming that the charging capacity, the open voltage, the internal resistance, and the like of each battery cell constituting the assembled battery 10 are the same.

  The battery monitoring unit 20 functions as a monitoring device that monitors the state of the assembled battery 10 for each of the unit batteries BC1 to BC6, and also functions as an abnormality detection device that detects an open abnormality of the inter-stack wire SP.

  The battery monitoring unit 20 of the present embodiment includes a plurality of electrical paths L1 to L10, first to third monitoring ICs 30a to 30c, a voltage detection unit 40, a control device 50, and the like connected to both ends of each of the unit batteries BC1 to BC6. It has.

  Each of the monitoring ICs 30a to 30c is provided for each monitoring block in which a plurality (two in this example) of unit cells are connected in series, and detects the voltage between terminals of each unit battery constituting the monitoring block. It is an integrated circuit that monitors whether the voltage of the battery is within an appropriate voltage range.

  In the present embodiment, the first monitoring IC 30a is provided corresponding to the first and second unit batteries BC1 and BC2, the second monitoring IC 30b is provided corresponding to the third and fourth unit batteries BC3 and BC4, and the first 3 illustrates an example in which the three monitoring ICs 30c are provided corresponding to the fifth and sixth unit batteries BC5 and BC6.

  Specifically, the first monitoring IC 30a includes first and second electric paths L1 and L2 connected to both ends of the first unit battery BC1 and a third electric path connected to the positive terminal of the second unit battery BC2. It is connected to the first and second unit batteries BC1 and BC2 via L3. The first monitoring IC 30a detects the voltage between the terminals of the first and second unit batteries BC1 and BC2 via the first to third electric paths L1 to L3 connected to the first monitoring IC 30a.

  The second monitoring IC 30b includes fourth and fifth electric paths L4 and L5 connected to both ends of the third unit battery BC3, and sixth and seventh electric paths L6 and L7 connected to both ends of the fourth unit battery BC4. To the third and fourth unit batteries BC3 and BC4. The second monitoring IC 30b detects the voltage between the terminals of the third and fourth unit batteries BC3 and BC4 via the fourth to seventh electric paths L4 to L7 connected to the second monitoring IC 30b.

  The third monitoring IC 30c is connected to both ends of the fifth unit battery BC5 via the eighth and ninth electric paths L8 and L9 and the tenth electric path L10 connected to the positive terminal of the sixth unit battery BC6. It is connected to the fifth and sixth unit batteries BC5 and BC6. The third monitoring IC 30c detects the inter-terminal voltages of the fifth and sixth unit batteries BC5 and BC6 via the eighth to tenth electric paths L8 to L10 connected to the third monitoring IC 30c.

  Each of the monitoring ICs 30a to 30c monitors the voltage between terminals of each unit battery constituting the monitoring block in accordance with a control signal from the control device 50. The monitoring ICs 30a to 30c of the present embodiment are connected by a serial line SL (daisy chain connection) so that a control signal from the control device 50 is sequentially transmitted from the monitoring IC on the high potential side to the monitoring IC on the low potential side. ing.

  In the present embodiment, among the monitoring ICs 30a to 30c, the monitoring IC 30c on the highest potential side and the monitoring IC 30a on the lowest potential side are connected to the control device 50 via the insulating elements 51 and 52 configured by photocouplers or the like. It is connected.

  As described above, the monitoring ICs 30a to 30c and the control device 50 are connected by the daisy chain method, so that the insulating elements 51 and 52 that secure the insulation between the monitoring ICs 30a to 30c and the control device 50 are provided. It becomes possible to suppress the number as much as possible.

  Here, the third unit battery BC3 constituting the first cell group CG1 and the fourth unit battery BC4 constituting the second cell group CG2 are connected in series via the inter-stack wire SP. The second monitoring IC 30b is connected to both ends of the inter-stack wire SP via the fifth and sixth electric paths L5 and L6.

  The second monitoring IC 30b of the present embodiment is configured to be able to detect a potential difference (a voltage between terminals of the inter-stack wire SP) at both ends of a bypass path 70 described later via the fifth and sixth electric paths L5 and L6. Yes. In the following, when the potential difference between both ends of the bypass path 70 matches the terminal voltage of the inter-stack wire SP, the potential difference between both ends of the bypass path 70 may be referred to as the inter-terminal voltage of the inter-stack wire SP. .

  Further, the second monitoring IC 30b of the present embodiment is configured to be able to detect a voltage in a shorter time than a voltage detection unit 40 described later. In the present embodiment, the second monitoring IC 30b constitutes “potential difference detection means” that detects a potential difference at both ends of a bypass path 70 described later.

  Further, the second monitoring IC 30b includes a protection diode 32 as a current protection element in order to avoid an overcurrent from flowing in through a pair of electrical paths L5 and L6 connected to both ends of the inter-stack wire SP. Has been. The protection diode 32 only allows current flow from the fifth electric path L5 on the low potential side to the sixth electric path L6 on the high potential side in the pair of electric paths L5 and L6 connected to both ends of the inter-stack wire SP. It is allowed and the reverse current flow is prohibited.

  In the present embodiment, between the sixth electric path L6 having the same potential as the terminal on the high potential side of the inter-stack wire SP and the fifth electric path L5 having the same potential as the terminal on the low potential side of the inter-stack wire SP. In addition, a bypass path 70 for short-circuiting the electrical paths L5 and L6 is provided.

  The bypass path 70 is provided in order to prevent an overvoltage from being applied to the monitoring IC side when the inter-stack wire SP is in an open state (open state). In the present embodiment, the sixth electrical path L6 constitutes a “first electrical path” in which the potential is higher than the high potential side of the inter-stack wire SP, and the fifth electrical path L5 is a low level of the inter-stack wire SP. A “second electrical path” having a potential lower than the potential side is configured.

  In the present embodiment, a pair of Zener diodes 70 a and 70 b are provided in the bypass path 70. Each zener diode 70a, 70b has a potential difference between a pair of electrical paths L5, L6 connected to both ends of the bypass path 70 (both ends of the inter-stack wire SP) when the inter-stack wire SP is in an open state (open state). Is maintained at a constant voltage.

  The first Zener diode 70a has a cathode connected to the sixth electric path L6 and an anode connected to the fifth electric path L5 via the second Zener diode 70b. The second Zener diode 70b has an anode connected to the fifth electric path L5 and a cathode connected to the sixth electric path L6 via the first Zener diode 70a.

  In addition, each Zener diode 70a, 70b of this embodiment has a breakdown voltage (Zener voltage) larger than, for example, a voltage between terminals of the inter-stack wire SP, and a withstand voltage (for example, 10V) (for example, about 8.2V).

  Subsequently, the voltage detection unit 40 detects the inter-terminal voltage of each of the cell groups CG1 and CG2, and is configured by a so-called flying capacitor type voltage detection circuit.

  The voltage detection unit 40 includes an input side switch group 42, a flying capacitor 44, a pair of output switches SWa and SWb, a differential amplifier circuit 46, and an AD converter 48. In the present embodiment, the voltage detection unit 40 constitutes “capacitor voltage detection means”.

  The input side switch group 42 is a circuit for charging the flying capacitor 44 with the inter-terminal voltage of one or more unit cells via the electric paths L1 to L10 and the like. The input side switch group 42 of the present embodiment includes a first input line Lα connected to one end A (positive terminal) of the flying capacitor 44 and a first input line Lα connected to the other end B (negative terminal) of the flying capacitor 44. The voltage between the terminals of the cell groups CG1 and CG2 is charged in the flying capacitor 44 via the two-input line Lβ.

  More specifically, the input side switch group 42 includes first to fifth input switches SW1 to SW5 (for example, SSR: Solid State Relay).

  The first input switch SW1 has one end connected to the first electric path L1 having the same potential as the negative terminal of the first cell group CG1 via the resistor R1, and the other end connected to the first input line Lα. . The second input switch SW2 has one end connected to the first electric path L1 via the resistor R2 and the other end connected to the second input line Lβ.

  The third input switch SW3 has one end connected to the fifth electric path L5 having the same potential as the positive terminal of the first cell group CG1 via the resistor R3, and the other end connected to the first input line Lα. . The fourth input switch SW4 has one end connected to the sixth electric path L6 having the same potential as the negative terminal of the second cell group CG2 via the resistor R4, and the other end connected to the second input line Lβ. ing. The fifth input switch SW5 has one end connected to the tenth electrical path L10 having the same potential as the positive terminal of the second cell group CG2 via the resistor R5, and the other end connected to the first input line Lα. ing.

  The switches SW1 to SW5 constituting the input side switch group 42 of the present embodiment are switched to an open state (on) or a closed state (off) in accordance with a control signal from the control device 50 described later.

  The input side switch group 42 of the present embodiment stacks the discharge current of the flying capacitor 44 by opening / closing the input switches SW1 to SW5 while the flying capacitor 44 is charged with a predetermined voltage (reverse polarity voltage). It is possible to form a discharge path that flows from the electrical path connected to the high potential side of the inter-wire SP to the electrical path connected to the low potential side.

  For example, when the voltage at which the positive terminal A is “−” and the negative terminal B is “+” is charged with respect to the flying capacitor 44, the input switches SW 3 and SW 4 are turned on to discharge the flying capacitor 44. A discharge path that allows current to flow from the sixth electric path L6 side to the fifth electric path L5 side via the inter-stack wire SP or the bypass path 70 can be formed. Hereinafter, the relationship in which the positive terminal A of the flying capacitor 44 is “−” and the negative terminal B is “+” is referred to as “reverse polarity”, and the positive terminal A of the flying capacitor 44 is “+” and the negative terminal B is The relationship of “−” is called “positive polarity”.

  Subsequently, the pair of output switches SWa and SWb (for example, SSR) are connected to both ends A and B of the flying capacitor 44 and the input side of the differential amplifier circuit 46, and the inter-terminal voltage Vc of the flying capacitor 44 is connected. Is output to the input side of the differential amplifier circuit 46.

  The differential amplifier circuit 46 is a circuit that amplifies and outputs a potential difference (terminal voltage) between both ends A and B of the flying capacitor 44. The AD converter (A / D) 48 is a circuit that converts the output voltage (analog signal) output from the differential amplifier circuit 46 into a digital signal and outputs the digital signal to the control device 50. In the present embodiment, the differential amplifier circuit 46 and the AD converter 48 constitute a “detection circuit” that detects the voltage across the terminals of the flying capacitor 44.

  The control device 50 is a microcomputer including a CPU and a memory constituting a storage unit, and is a control unit that executes various processes according to a program stored in the memory.

  The control device 50 according to the present embodiment can acquire the inter-terminal voltage for each unit battery and the potential difference between both ends of the bypass path 70 by controlling the monitoring ICs 30a to 30c.

  Moreover, the control apparatus 50 of this embodiment can acquire the voltage between terminals of each cell group CG1 and CG2 by controlling the voltage detection unit 40. Hereinafter, processing when the control device 50 acquires the inter-terminal voltages of the cell groups CG1 and CG2 using the voltage detection unit 40 will be described.

  For example, when acquiring the voltage between the terminals of the first cell group CG1, the control device 50 turns on the input switches SW2 and SW3 and supplies the voltage between the terminals of the first cell group CG1 (positive voltage) to the flying capacitor 44. To charge. When the charging of the flying capacitor 44 is completed, the control device 50 turns off the input switches SW2 and SW3 and turns on the output switches SWa and SWb. As a result, the voltage across the terminals of the flying capacitor 44 is amplified by the differential amplifier circuit 46, converted into a digital signal by the AD converter 48, and output to the control device 50. And in the control apparatus 50, the detection voltage of the voltage detection unit 40 is converted into a battery voltage, and the voltage between terminals of 1st cell group CG1 is acquired.

  On the other hand, when acquiring the inter-terminal voltage of the second cell group CG2, the control device 50 turns on the input switches SW4 and SW5 and supplies the voltage across the terminal of the second cell group CG2 (positive voltage) to the flying capacitor 44. To charge. When charging of the flying capacitor 44 is completed, the control device 50 turns off the input switches SW4 and SW5 and turns on the output switches SWa and SWb. As a result, the voltage across the terminals of the flying capacitor 44 is amplified by the differential amplifier circuit 46, converted into a digital signal by the AD converter 48, and output to the control device 50. And in the control apparatus 50, the detection voltage of the voltage detection unit 40 is converted into a battery voltage, and the voltage between terminals of 2nd cell group CG2 is acquired.

  In addition, the control device 50 of the present embodiment can execute an abnormality determination process for determining whether there is an open abnormality of the inter-stack wire SP. In the present embodiment, the configuration (software and hardware) for executing the abnormality determination process in the control device 50 constitutes the abnormality determination means 50a.

  Hereinafter, a method for detecting an open abnormality of the inter-stack wire SP according to the present embodiment will be described. First, in a state where the flying capacitor 44 is charged with a voltage equal to or higher than a predetermined reference voltage, the discharge current of the flying capacitor 44 is connected to the high potential side of the inter-stack wire SP by opening / closing the input side switch group 42. Discharge paths that flow from the electrical paths L6 to L10 to the electrical paths L1 to L5 connected to the low potential side are formed.

  When the open abnormality of the inter-stack wire SP does not occur, the discharge path of the flying capacitor 44 becomes a discharge path through which the inter-stack wire SP flows. In this case, the inter-terminal voltage Vd of the inter-stack wire SP hardly varies. The inter-terminal voltage Vc of the flying capacitor 44 converges to zero with time.

  On the other hand, when an open abnormality of the inter-stack wire SP occurs, the discharge current of the flying capacitor 44 becomes a discharge path that flows to the bypass path 70 side. In this case, the voltage Vd between the terminals of the inter-stack wire SP is held at a value near the breakdown voltage Vz by the first Zener diode 70a. Then, the inter-terminal voltage Vc of the flying capacitor 44 converges to a value near the breakdown voltage Vz of the first Zener diode 70a as time elapses. In addition, when the discharge current of the flying capacitor 44 is caused to flow from the electrical path connected to the high potential side of the inter-stack wire SP to the electrical path connected to the low potential side, a current is passed through the protection diode 32 built in the monitoring IC 30b. Not flowing.

  As described above, when the discharge current of the flying capacitor 44 flows from the electrical path connected to the high potential side of the inter-stack wire SP to the electrical path connected to the low potential side, depending on whether there is an open abnormality of the inter-stack wire SP, The inter-stack wire SP and the inter-terminal voltage of the flying capacitor 44 are greatly separated.

  Therefore, the voltage between the terminals of the inter-stack wire SP (bypass path 70) when the discharge current of the flying capacitor 44 flows from the electric path connected to the high potential side of the inter-stack wire SP to the electric path connected to the low potential side. Based on the potential difference between both ends of the first and second terminals) and the voltage between the terminals of the flying capacitor 44, it is possible to determine whether or not there is an open abnormality in the inter-stack wire SP.

  Then, the specific example of the abnormality determination process which the control apparatus 50 of this embodiment performs is demonstrated using FIGS. This abnormality determination process is executed when the vehicle is started or according to an external command or the like.

  As shown in the first stage of FIG. 2, the control device 50 first sets the voltage between the terminals of the first cell group CG1 to the reverse polarity with respect to the flying capacitor 44 (the positive terminal A is “−” and the negative terminal B is “−”. The first and fourth input switches SW1 and SW4 are turned on (time t1) so as to be charged at “+”).

  Thereby, for example, as indicated by the broken line arrow in FIG. 3, the fifth electric path L5 → the protection diode 32 → the second input line Lβ → the flying capacitor 44 → the first input line Lα → the first electric line from the first cell group CG1. A charging path (closed circuit) through which current flows to the path L1 is formed. When no open abnormality occurs in the inter-stack wire SP, a charging path through which a current flows to the inter-stack wire SP instead of the protection diode 32 is formed.

  At this time, since the discharging current of the first cell group CG1 flows from the negative terminal B side to the positive terminal A side, the flying capacitor 44 is charged with a voltage having a reverse polarity. As a result, the terminal voltage of the flying capacitor 44 gradually decreases as shown by the thick solid line in the fourth stage of FIG.

  In addition, when an open abnormality occurs in the inter-stack wire SP, the discharge current of the assembled battery 10 flows to the protective diode 32. Therefore, the inter-stack wire SP inter-terminal voltage Vd is the fifth solid line in FIG. As shown, the forward voltage Vf of the protection diode 32 decreases.

  The control device 50 according to the present embodiment sets the effective value Vτ in the inter-terminal voltage of the first cell group CG1 as a “reference voltage”, and the first and fourth voltages are charged until a reverse polarity voltage that is equal to or higher than the reference voltage is charged. The input switches SW1 and SW4 are kept on.

  Specifically, the control device 50 has elapsed time from the timing (time t1) when the input switches SW1 and SW4 are turned on exceeds the time longer than the time constant τ (time t1 to time t2) of the charging path. The input switches SW1 and SW4 are kept on until time t1 to time t3.

  Then, the control device 50 turns off the first and fourth input switches SW1 and SW4 in a state where the flying capacitor 44 is charged with a voltage equal to or higher than the effective value Vτ in the inter-terminal voltage Vd of the first cell group CG1. The third and fourth input switches SW3 and SW4 are turned on (time t3).

  The control device 50 holds the third and fourth input switches SW3 and SW4 on until the voltage stored in the flying capacitor 44 is sufficiently discharged (time t3 to time t4). Specifically, the control device 50 determines that the elapsed time from the timing when the input switches SW3 and SW4 are turned on (time t3) is longer than the time constant of the discharge path described later (the voltage stored in the flying capacitor 44). The input switches SW3 and SW4 are held on until the time required for discharging the current exceeds (time t3 to time t4).

  At this time, when the open abnormality does not occur in the inter-stack wire SP, the flying capacitor 44 changes from the second input line Lβ → the sixth electric path L6 → the inter-stack wire SP → the fifth electric path L5 → the first input line Lα. A discharge path (closed circuit) through which current flows is formed.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the above-described inter-stack wire SP. At this time, the inter-terminal voltage Vd of the inter-stack wire SP hardly varies as shown by the thick broken line in the fifth stage of FIG. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to zero as time passes as indicated by the fourth thick broken line in FIG. 2 (time t4).

  On the other hand, when an open abnormality occurs in the inter-stack wire SP, as shown by the broken line arrow in FIG. 4, the second input line Lβ → the sixth electric path L6 → the bypass path 70 → the fifth electric line from the flying capacitor 44. A discharge path (closed circuit) through which a current flows from the path L5 to the first input line Lα is formed. The discharge current from the flying capacitor 44 flows from the sixth electric path L6 side having the same potential as the high potential side terminal in the inter-stack wire SP to the fifth electric path L5 having the same potential as the low potential side terminal. Therefore, the discharge current does not flow through the protection diode 32.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the bypass path 70 described above. At this time, the inter-terminal voltage Vd of the inter-stack wire SP is obtained by changing the forward voltage Vf of the protective diode 32 from the absolute value of the breakdown voltage Vz of the first Zener diode 70a, as shown by the fifth solid line in FIG. The subtracted value (= − | Vz−Vf |) is held (| Vz | >> Vf |).

  Then, the inter-terminal voltage Vc of the flying capacitor 44 changes from the breakdown voltage Vz of the first Zener diode 70a to the forward direction of the protection diode 32 as time passes, as shown by the thick solid line in the fourth stage of FIG. It converges to a voltage obtained by subtracting the voltage Vf (time t4).

  Subsequently, after the input side switch group 42 is operated so that the discharging current of the flying capacitor 44 flows from the sixth electric path L6 side to the fifth electric path L5 side, the control device 50 causes the discharging current of the flying capacitor 44 to change. When a time longer than the time constant of the flowing discharge path has elapsed, the detection value of the voltage detection unit 40 is acquired. Note that “when a time longer than the time constant of the discharge path through which the discharge current of the flying capacitor 44 flows” means the timing at which the voltage stored in the flying capacitor 44 is discharged more than its effective value.

  Specifically, after the voltage stored in the flying capacitor 44 is sufficiently discharged, the control device 50 turns off the switches SW3 and SW4, turns on the output switches SWa and SWb, and turns on the terminals of the flying capacitor 44. A digital signal indicating the inter-voltage Vc is acquired.

  Then, the control device 50 converts the digital signal acquired from the voltage detection unit 40 into the terminal voltage Vc of the flying capacitor 44. In addition, after acquiring the digital signal from the voltage detection unit 40, the control apparatus 50 turns off the output switches SWa and SWb (time t5).

  Subsequently, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value Vth1, and determines whether there is an open abnormality of the inter-stack wire SP. Note that the determination threshold Vth1 of the present embodiment is a value within a range larger than “− | Vz−Vf |” and smaller than “zero” (for example, Vth1 = − | Vz), as shown in the fourth row of FIG. / 2 |).

  Specifically, the control device 50 determines that no open abnormality has occurred when the inter-terminal voltage Vc of the flying capacitor 44 is greater than the determination threshold value Vth1, and ends the abnormality determination process.

  On the other hand, when the inter-terminal voltage Vc of the flying capacitor 44 is equal to or lower than the determination threshold Vth1, the control device 50 determines that an open abnormality of the inter-stack wire SP has occurred, and ends the abnormality determination process. When it is determined that an open abnormality has occurred, it is desirable to execute a process for notifying a higher-level control device or the like that supervises the vehicle control or a process for notifying the user or the like.

  Incidentally, the time T1 required for the abnormality determination process of the present embodiment is the charging time of the flying capacitor 44 (time t1 to time t3), the discharging time of the flying capacitor 44 (time t3 to time t4), and the voltage from the voltage detection unit 40. This is the total time from the acquisition time (time t4 to time t5). The time T1 required for the abnormality determination process is a period from the start to the end of the control of the voltage detection unit 40 in the abnormality determination process.

  In the present embodiment described above, the discharge current of the flying capacitor 44 is reduced from the electric path L6 connected to the high potential side of the inter-stack wire SP in the abnormality detection process for detecting the open abnormality of the inter-stack wire SP. It is made to flow to the electric path L5 connected to the side.

  According to this, the discharge current of the flying capacitor 44 is not transmitted through the inter-stack wire SP and the bypass path 70 provided with the first Zener diode 70a, instead of the protection diode 32 built in the second monitoring IC 30b. Can be shed.

  Then, the discharge current of the flying capacitor 44 flows to the bypass path 70 side when the open abnormality occurs in the inter-stack wire SP, and when the open abnormality does not occur in the inter-stack wire SP, the inter-stack wire SP side To flow.

  When the discharge current of the flying capacitor 44 flows to the bypass path 70 side, due to the influence of the breakdown voltage Vz of the first Zener diode 70a, the voltage Vd between the terminals of the inter-stack wire SP and the voltage between the terminals of the flying capacitor 44 when the discharge is completed. Vc greatly deviates from the normal state of the inter-stack wire SP.

  For this reason, even if the protection diode 32 is provided in the pair of electrical paths L5 and L6 connected to both ends of the inter-stack wire SP, the open abnormality of the inter-stack wire SP is based on the voltage between the terminals of the flying capacitor 44. The presence or absence of can be determined appropriately.

  Further, in this embodiment, after the third and fourth input switches SW3 and SW4 are turned on, the voltage detection unit 40 has a time longer than the time constant of the discharge path through which the discharge current of the flying capacitor 44 flows. Based on the detection value, it is configured to determine whether there is an open abnormality of the inter-stack wire SP.

  According to this, it is possible to appropriately determine whether or not there is an open abnormality of the inter-stack wire SP by using only the voltage detection unit 40 without using each of the monitoring ICs 30a to 30c. In other words, if the current protection element corresponding to the protection diode 32 is provided in the pair of electrical paths L5 and L6 connected to both ends of the inter-stack wire SP, the inter-stack can be provided without the monitoring ICs 30a to 30c. The presence / absence of an open abnormality of the wire SP can be appropriately determined.

(Second Embodiment)
Next, a second embodiment will be described. In the present embodiment, an example in which part of the abnormality determination process in the first embodiment is changed will be described. In addition, since the structure of the assembled battery 10 and the battery monitoring unit 20 of this embodiment is the same as that of 1st Embodiment, description is abbreviate | omitted.

  Hereinafter, the abnormality determination process executed by the control device 50 of the present embodiment will be described with reference to FIG. First, as shown in the first stage of FIG. 5, the control device 50 turns on the first and fourth input switches SW1 and SW4 (time t1).

  Thereafter, the control device 50 of the present embodiment sets the breakdown voltage Vz of the first Zener diode 70a, which is smaller than the effective value of the inter-terminal voltage of the first cell group CG1, as the “reference voltage”, and the voltage equal to or higher than the reference voltage is reversed. The first and fourth input switches SW1 and SW4 are kept on until charged with polarity.

  Specifically, the control device 50 sets each input switch SW1 for a time longer than the time (time t1 to time tα) required when charging the flying capacitor 44 with the voltage corresponding to the breakdown voltage Vz of the first Zener diode 70a. , SW4 is kept on (time t1 to time t3 ′).

  As a result, the terminal voltage of the flying capacitor 44 gradually decreases as shown by the thick solid line in the fourth stage of FIG. In the present embodiment, the time during which the input switches SW1 and SW4 are kept on is set to be equal to or less than the time constant τ of the charging path.

  Subsequently, the control device 50 turns off the first and fourth input switches SW1 and SW4 in a state where the flying capacitor 44 is charged with a voltage equal to or higher than the breakdown voltage Vz of the first Zener diode 70a. The fourth input switches SW3 and SW4 are turned on (time t3 ′).

  Then, the control device 50 holds the third and fourth input switches SW3 and SW4 on until the voltage stored in the flying capacitor 44 is sufficiently discharged (time t3 ′ to time t4 ′).

  As a result, during normal operation when no open abnormality occurs in the inter-stack wire SP, the inter-terminal voltage Vc of the flying capacitor 44 becomes zero as time passes as shown by the thick broken line in the fourth stage of FIG. Converge (time t4 ').

  On the other hand, when an open abnormality occurs in the inter-stack wire SP, the voltage Vc between the terminals of the flying capacitor 44 is increased with time as shown in the fourth solid line in FIG. The voltage converges to a voltage obtained by subtracting the forward voltage Vf of the protection diode 32 from the breakdown voltage Vz of the diode 70a (time t4 ′).

  After the voltage stored in the flying capacitor 44 is sufficiently discharged, the control device 50 turns off the switches SW3 and SW4 and turns on the output switches SWa and SWb. The terminal voltage Vc is acquired. Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value Vth1, and determines whether there is an open abnormality of the inter-stack wire SP.

  Incidentally, the time T2 required for the abnormality determination process of the present embodiment is the charging time of the flying capacitor 44 (time t1 to time t3 ′), the discharging time of the flying capacitor 44 (time t3 ′ to time t4 ′), and the voltage detection unit 40. Is the total time from the voltage acquisition time (time t4 'to time t5').

  In the present embodiment described above, the flying capacitor 44 is connected from the electrical path L6 connected to the high potential side of the inter-stack wire SP to the electrical path L5 connected to the low potential side depending on whether there is an open abnormality of the inter-stack wire SP. The inter-terminal voltage Vc of the flying capacitor 44 when the discharge current flows greatly deviates.

  Therefore, even if the protective diode 32 is provided in the pair of electric paths L5 and L6 connected to both ends of the inter-stack wire SP, the open abnormality of the inter-stack wire SP is determined based on the voltage between the terminals of the flying capacitor 44. Presence / absence can be determined appropriately.

  In particular, in the present embodiment, the breakdown voltage Vz of the first Zener diode 70a, which is smaller than the effective value of the inter-terminal voltage of the first cell group CG1, is set as a “reference voltage” until a voltage equal to or higher than the reference voltage is charged. The first and fourth input switches SW1 and SW4 are held on.

  For this reason, the time T2 (time t1 to time t5 ′) required for the abnormality determination process is shortened as compared with the first embodiment because the charging time (time t1 to time t3 ′) of the flying capacitor 44 is shortened. (T1> T2).

(Third embodiment)
Next, a third embodiment will be described. In the present embodiment, an example in which part of the abnormality determination process in the first embodiment is changed will be described. In addition, since the structure of the assembled battery 10 and the battery monitoring unit 20 of this embodiment is the same as that of 1st Embodiment, description is abbreviate | omitted.

  In the abnormality determination process of the present embodiment, the terminal of the inter-stack wire SP when the discharge current of the flying capacitor 44 flows from the electrical path connected to the high potential side of the inter-stack wire SP to the electrical path connected to the low potential side. Based on the inter-voltage Vd, the presence / absence of an open abnormality of the inter-stack wire SP is determined.

  Hereinafter, the abnormality determination process executed by the control device 50 of the present embodiment will be described with reference to FIG. First, as shown in the first stage of FIG. 6, the control device 50 turns on the first and fourth input switches SW1 and SW4 (time t1).

  Thereafter, the control device 50 of the present embodiment sets the effective value Vτ of the inter-terminal voltage of the first cell group CG1 as the “reference voltage”, and continues to the first and fourth input switches until a voltage equal to or higher than the reference voltage is charged. SW1 and SW4 are kept on. As a result, the terminal voltage of the flying capacitor 44 gradually decreases as shown by the thick solid line in the fourth stage of FIG.

  Subsequently, the control device 50 turns off the first and fourth input switches SW1 and SW4 in a state where the flying capacitor 44 is charged with a voltage equal to or higher than the effective value Vτ of the voltage across the first cell group CG1. Then, the third and fourth input switches SW3 and SW4 are turned on (time t3).

  At this time, when the open error does not occur in the inter-stack wire SP, the voltage Vd between the terminals of the inter-stack wire SP hardly fluctuates as shown by the fifth thick broken line in FIG.

  On the other hand, when an open abnormality occurs in the inter-stack wire SP, the voltage Vd between the terminals of the inter-stack wire SP is determined from the breakdown voltage Vz of the first Zener diode 70a as shown by the fifth solid line in FIG. A value obtained by subtracting the forward voltage Vf of the protection diode 32 (= | Vz−Vf |).

  After the third and fourth input switches SW3 and SW4 are turned on, the control device 50 starts from the second monitoring IC 30b to the stack before a time longer than the time constant of the discharge path through which the discharging current of the flying capacitor 44 flows. A detection value of the inter-terminal voltage Vd of the wire SP is acquired.

  Specifically, the control device 50 outputs a control signal that instructs the second monitoring IC 30b to detect the voltage Vd between the terminals of the inter-stack wire SP, and the voltage between the terminals of the inter-stack wire SP is output from the second monitoring IC 30b. The detection result of Vd is acquired. In addition, after acquiring the digital signal from the second monitoring IC 30b, the control device 50 turns off the output switches SW3 and SW4 (time tβ).

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vd of the inter-stack wire SP and a preset determination threshold value Vth2, and determines whether there is an open abnormality of the inter-stack wire SP. Note that the determination threshold value Vth2 of this embodiment is a value within a range larger than “zero” and smaller than “| Vz−Vf |” (for example, Vth2 = | Vz / 2) as shown in the fifth row of FIG. |) Is set.

  Specifically, the control device 50 determines that the open abnormality has not occurred when the inter-terminal voltage Vd of the inter-stack wire SP is equal to or less than the determination threshold value Vth2, and ends the abnormality determination process.

  On the other hand, the control device 50 determines that an open abnormality of the inter-stack wire SP has occurred when the inter-terminal voltage Vd of the inter-stack wire SP becomes larger than the determination threshold value Vth1, and ends the abnormality determination process.

  Incidentally, the time T3 required for the abnormality determination process of this embodiment is the sum of the charging time of the flying capacitor 44 (time t1 to time t3) and the voltage acquisition time (time t3 to time tβ) from the second monitoring IC 30b. It will be time.

  In the present embodiment described above, the flying capacitor 44 is connected from the electrical path L6 connected to the high potential side of the inter-stack wire SP to the electrical path L5 connected to the low potential side depending on whether there is an open abnormality of the inter-stack wire SP. The voltage Vd between the terminals of the inter-stack wire SP when the discharge current flows greatly deviates.

  Therefore, even if the protective diode 32 is provided in the pair of electrical paths L5 and L6 connected to both ends of the inter-stack wire SP, the inter-terminal voltage SP of the inter-stack wire SP (potential difference between both ends of the bypass path 70) is obtained. Based on this, it is possible to appropriately determine whether there is an open abnormality in the inter-stack wire SP.

  In particular, in the present embodiment, the detected value of the inter-stack voltage SP of the inter-stack wire SP is acquired from the second monitoring IC 30b before a time longer than the time constant of the discharge path through which the discharge current of the flying capacitor 44 flows. I have to.

  Therefore, there is no need to wait until the flying capacitor 44 is sufficiently discharged, and the time T3 (time t1 to time tβ) required for the abnormality determination process can be shortened as compared with the first embodiment (T1> T3). ).

(Fourth embodiment)
Next, a fourth embodiment will be described. In the present embodiment, an example in which part of the abnormality determination process in the first embodiment is changed will be described. In addition, since the structure of the assembled battery 10 and the battery monitoring unit 20 of this embodiment is the same as that of 1st Embodiment, description is abbreviate | omitted.

  Hereinafter, the abnormality determination process executed by the control device 50 of the present embodiment will be described with reference to FIG. First, as shown in the first stage of FIG. 7, the control device 50 turns on the first and fourth input switches SW1 and SW4 (time t1).

  Thereafter, the control device 50 according to the present embodiment sets the breakdown voltage Vz of the first Zener diode 70a, which is smaller than the effective value of the voltage between the terminals of the first cell group CG1, as the “reference voltage”, and the voltage equal to or higher than the reference voltage is charged. The first and fourth input switches SW1 and SW4 are kept on until the operation is performed. Note that the control device 50 sets the input switches SW1 and SW4 for a time longer than the time (time t1 to time tα) required when charging the flying capacitor 44 with the voltage corresponding to the breakdown voltage Vz of the first Zener diode 70a. It is kept on (time t1 to time t3 ′).

  As a result, the terminal voltage of the flying capacitor 44 gradually decreases as shown by the thick solid line in the fourth stage of FIG. In the present embodiment, the time during which the input switches SW1 and SW4 are kept on is set to be equal to or less than the time constant τ of the charging path.

  Subsequently, the control device 50 turns off the first and fourth input switches SW1 and SW4 in a state where the flying capacitor 44 is charged with a voltage equal to or higher than the breakdown voltage Vz of the first Zener diode 70a. The fourth input switches SW3 and SW4 are turned on (time t3 ′).

  At this time, when the open error is not generated in the inter-stack wire SP, the voltage Vd between the terminals of the inter-stack wire SP hardly changes as shown by the thick broken line in the fifth row in FIG.

   On the other hand, when an open abnormality occurs in the inter-stack wire SP, the voltage Vd between the terminals of the inter-stack wire SP is determined from the breakdown voltage Vz of the first Zener diode 70a as shown by the thick solid line in the fifth stage of FIG. A value obtained by subtracting the forward voltage Vf of the protection diode 32 is obtained.

  After the third and fourth input switches SW3 and SW4 are turned on, the control device 50 starts from the second monitoring IC 30b to the stack before a time longer than the time constant of the discharge path through which the discharging current of the flying capacitor 44 flows. A detection value of the inter-terminal voltage Vd of the wire SP is acquired. The control device 50 acquires the digital signal from the second monitoring IC 30b, and then turns off the output switches SWa and SWb (time tβ ′).

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vd of the inter-stack wire SP and a preset determination threshold value Vth2, and determines whether there is an open abnormality of the inter-stack wire SP.

  Incidentally, the time T4 required for the abnormality determination process of the present embodiment is from the charging time of the flying capacitor 44 (time t1 to time t3 ′) and the voltage acquisition time from the second monitoring IC 30b (time t3 ′ to time tβ ′). It is time to add up.

  In the present embodiment described above, the discharge current of the flying capacitor 44 from the electrical path connected to the high potential side of the interstack wire SP to the electrical path connected to the low potential side depending on the presence or absence of an open abnormality of the interstack wire SP. The inter-stack voltage SP of the inter-stack wire SP is greatly deviated.

  Therefore, even if the protective diode 32 is provided in the pair of electrical paths L5 and L6 connected to both ends of the inter-stack wire SP, the inter-terminal voltage SP of the inter-stack wire SP (potential difference between both ends of the bypass path 70) is obtained. Based on this, it is possible to appropriately determine whether there is an open abnormality in the inter-stack wire SP.

  In particular, in the present embodiment, the breakdown voltage Vz of the first Zener diode 70a, which is smaller than the effective value of the inter-terminal voltage of the first cell group CG1, is set as a “reference voltage” until a voltage equal to or higher than the reference voltage is charged. The first and fourth input switches SW1 and SW4 are held on.

  Furthermore, in this embodiment, the detection value of the inter-stack voltage SP of the inter-stack wire SP is acquired from the second monitoring IC 30b before a time longer than the time constant of the discharge path through which the discharge current of the flying capacitor 44 flows. I have to.

  For this reason, it is not necessary to wait until the flying capacitor 44 is sufficiently discharged, and further, the charging time (time t1 to time t3 ′) of the flying capacitor 44 is shortened compared to the first to third embodiments. The time T4 (time t1 to time tβ ′) required for the abnormality determination process can be shortened (T1> T2, T3> T4).

(Fifth embodiment)
Next, a fifth embodiment will be described. In the present embodiment, an example in which a part of the configuration of the battery monitoring unit 20 in the first embodiment (the input-side switch group 42 of the voltage detection unit 40) is changed will be described. In the present embodiment, description of the same or equivalent parts as in the first embodiment will be omitted or simplified.

  In the input side switch group 42 of the present embodiment, when the flying capacitor 44 is charged with the “positive voltage”, the discharge current of the flying capacitor 44 is changed to the inter-stack wire SP by the opening / closing operation of the input side switch group 42. It is possible to form a discharge path that flows from the electrical path connected to the high potential side to the electrical path connected to the low potential side.

  Specifically, as shown in FIG. 8, the input side switch group 42 of the present embodiment is composed of six switches such as second to fifth input switches SW2 to SW5, and sixth and seventh input switches SW11 and SW12. It is configured.

  The sixth input switch SW11 has one end connected to the fifth electric path L5 having the same potential as the positive terminal of the first cell group CG1 via the resistor R11, and the other end connected to the second input line Lβ. .

  The seventh input switch SW12 has one end connected to the sixth electric path L6 having the same potential as the negative terminal of the second cell group CG2 via the resistor R12, and the other end connected to the first input line Lα. ing.

  Note that the sixth and seventh input switches SW11 and SW12 added in the present embodiment are configured so that the discharging current of the flying capacitor 44 is supplied to the inter-stack wire SP while the flying capacitor 44 is charged with a positive voltage. This is a dedicated switch for flowing from the electrical path connected to the high potential side to the electrical path connected to the low potential side.

  Other configurations are the same as those of the first embodiment, and the abnormality determination process of the present embodiment will be described below with reference to FIGS. 9 and 10.

  First, the control device 50 turns on the second and third input switches SW2 and SW3 so that the flying capacitor 44 is charged with a positive voltage between the terminals of the first cell group CG1.

  As a result, as indicated by the broken line arrow in FIG. 9, a current flows from the first cell group CG1 to the fifth electric path L5 → the first input line Lα → the flying capacitor 44 → the second input line Lβ → the first electric path L1. A charging path (closed circuit) is formed. At this time, since the discharging current of the assembled battery 10 flows from the positive terminal A side to the negative terminal B side, the flying capacitor 44 is charged with a positive voltage.

  Subsequently, the control device 50 sets the effective value Vτ in the inter-terminal voltage of the first cell group CG1 as a “reference voltage”, and continues to charge the second and third input switches SW2 and SW3 until a voltage equal to or higher than the reference voltage is charged. Hold on. The “reference voltage” may be the breakdown voltage Vz of the first Zener diode 70a, as in the second embodiment.

  Subsequently, the control device 50 turns off the second and third input switches SW2 and SW3 and charges the sixth and seventh input switches SW11 and SW12 while the flying capacitor 44 is charged with a voltage equal to or higher than the reference voltage. Turn on. Then, the control device 50 holds the sixth and seventh input switches SW11 and SW12 on until the voltage stored in the flying capacitor 44 is sufficiently discharged.

  At this time, when the open abnormality does not occur in the inter-stack wire SP, the flying capacitor 44 changes from the first input line Lα → the sixth electric path L6 → the inter-stack wire SP → the fifth electric path L5 → the second input line Lβ. A discharge path (closed circuit) through which current flows is formed.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the above-described inter-stack wire SP. At this time, the inter-terminal voltage Vd of the inter-stack wire SP hardly varies. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to zero as time passes.

  On the other hand, when an open abnormality has occurred in the inter-stack wire SP, as shown by the broken line arrow in FIG. 10, the first input line Lα → the sixth electric path L6 → the bypass path 70 → the fifth electric line from the flying capacitor 44. A discharge path (closed circuit) through which a current flows from the path L5 to the second input line Lβ is formed. The discharge current from the flying capacitor 44 flows from the sixth electric path L6 side having the same potential as the high potential side terminal in the inter-stack wire SP to the fifth electric path L5 having the same potential as the low potential side terminal. Therefore, the discharge current does not flow through the protection diode 32.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the bypass path 70 described above. At this time, the inter-terminal voltage Vd of the inter-stack wire SP is held at the breakdown voltage Vz of the first Zener diode 70a. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to the breakdown voltage Vz of the first Zener diode 70a as time elapses.

  Subsequently, after the voltage stored in the flying capacitor 44 is sufficiently discharged, the control device 50 turns off the sixth and seventh switches SW11 and SW12 and turns on the output switches SWa and SWb to detect the voltage. The terminal voltage Vc of the flying capacitor 44 is obtained from the unit 40.

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value, and determines whether there is an open abnormality of the inter-stack wire SP. Note that, as in the third embodiment, the inter-stack wire is based on the inter-terminal voltage Vd (potential difference between both ends of the bypass path 70) of the inter-stack wire SP when the sixth and seventh input switches SW11 and SW12 are turned on. The presence or absence of SP open abnormality may be determined.

  Also in the present embodiment described above, the flying capacitor 44 is transferred from the electrical path L6 connected to the high potential side of the inter-stack wire SP to the electrical path L5 connected to the low potential side depending on whether or not the inter-stack wire SP is open. The terminal-to-terminal voltage Vc of the flying capacitor 44 when a large discharge current flows greatly deviates.

  Therefore, even if the protective diode 32 is provided in the pair of electric paths L5 and L6 connected to both ends of the inter-stack wire SP, the open abnormality of the inter-stack wire SP is determined based on the voltage between the terminals of the flying capacitor 44. Presence / absence can be determined appropriately.

  Here, the abnormality detection process of the first embodiment is configured to detect the voltage charged to the flying capacitor 44 with the reverse polarity, and therefore, it is necessary to expand the dynamic range when the control device 50 acquires the voltage. There is (negative voltage ~ positive voltage).

  On the other hand, in this embodiment, the voltage charged to the flying capacitor 44 with the positive polarity is detected by the abnormality detection process, and it is necessary to detect the voltage charged to the flying capacitor 44 with the reverse polarity. There is no.

  As described above, the control device 50 according to the present embodiment does not need to expand the dynamic range when acquiring the voltage for the abnormality detection process. The detection voltage can be acquired with high accuracy.

  However, in the present embodiment, the number of switches constituting the input side switch group 42 is increased as compared with the configuration of the first embodiment. For this reason, the configuration of the present embodiment is suitable when priority is given to the detection accuracy of the open abnormality of the inter-stack wire SP over the simplification of the battery monitoring unit 20.

(Sixth embodiment)
Next, a sixth embodiment will be described. In the present embodiment, an example in which a part of the configuration of the battery monitoring unit 20 in the first embodiment (the input-side switch group 42 of the voltage detection unit 40) is changed will be described. In the present embodiment, description of the same or equivalent parts as in the first embodiment will be omitted or simplified.

  In the input side switch group 42 of the present embodiment, when the flying capacitor 44 is charged with a positive voltage, an opening / closing operation of the input side switch group 42 causes the discharge current of the flying capacitor 44 to be increased in the inter-stack wire SP. A discharge path that flows from the electrical path L6 connected to the potential side to the electrical path L5 connected to the low potential side can be formed.

  Specifically, as shown in FIG. 11, the input side switch group 42 of the present embodiment includes second, third, and fifth input switches SW2, SW3, and SW5, and eighth and ninth input switches SW21 and SW22. These five switches are used.

  The eighth input switch SW21 has one end connected to the fifth electric path L5 having the same potential as the positive terminal of the first cell group CG1 via the resistor R21, and the other end connected to the second input line Lβ. .

  The ninth input switch SW22 has one end connected to the sixth electric path L6 having the same potential as the negative terminal of the second cell group CG2 via the resistor R22, and the other end connected to the first input line Lα. ing.

  In addition, the eighth and ninth input switches SW21 and SW22 added in the present embodiment are configured so that the discharging current of the flying capacitor 44 is supplied to the inter-stack wire SP while the flying capacitor 44 is charged with a positive voltage. It is a switch for flowing from the electrical path connected to the high potential side to the electrical path connected to the low potential side.

  Other configurations are the same as those of the first embodiment, and the abnormality determination process of the present embodiment will be described below with reference to FIGS. 12 and 13.

  First, the control device 50 turns on the second and third input switches SW2 and SW3 so that the flying capacitor 44 is charged with a positive voltage between the terminals of the first cell group CG1.

  As a result, as indicated by the broken line arrow in FIG. 12, a current flows from the first cell group CG1 to the fifth electric path L5 → the first input line Lα → the flying capacitor 44 → the second input line Lβ → the first electric path L1. A charging path (closed circuit) is formed. At this time, since the discharging current of the assembled battery 10 flows from the positive terminal A side to the negative terminal B side, the flying capacitor 44 is charged with a positive voltage (positive voltage).

  Subsequently, the control device 50 sets the effective value Vτ in the inter-terminal voltage of the first cell group CG1 as a “reference voltage”, and continues to charge the second and third input switches SW2 and SW3 until a voltage equal to or higher than the reference voltage is charged. Hold on. The “reference voltage” may be the breakdown voltage Vz of the first Zener diode 70a, as in the second embodiment.

  Subsequently, the control device 50 turns off the second and third input switches SW2 and SW3 in a state where the flying capacitor 44 is charged with a voltage equal to or higher than the reference voltage, and the eighth and ninth input switches SW21 and SW22. Turn on. The control device 50 holds the eighth and ninth input switches SW21 and SW22 on until the voltage stored in the flying capacitor 44 is sufficiently discharged.

  At this time, when the open abnormality does not occur in the inter-stack wire SP, the flying capacitor 44 changes from the first input line Lα → the sixth electric path L6 → the inter-stack wire SP → the fifth electric path L5 → the second input line Lβ. A discharge path (closed circuit) through which current flows is formed.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the above-described inter-stack wire SP. At this time, the inter-terminal voltage Vd of the inter-stack wire SP hardly varies. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to zero as time passes.

  On the other hand, when an open abnormality has occurred in the inter-stack wire SP, as indicated by a broken line arrow in FIG. 13, the first input line Lα → the sixth electric path L6 → the bypass path 70 → the fifth electric line from the flying capacitor 44. A discharge path (closed circuit) through which a current flows from the path L5 to the second input line Lβ is formed. The discharge current from the flying capacitor 44 flows from the sixth electric path L6 side having the same potential as the high potential side terminal in the inter-stack wire SP to the fifth electric path L5 having the same potential as the low potential side terminal. Therefore, the discharge current does not flow through the protection diode 32.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the bypass path 70 described above. At this time, the inter-terminal voltage Vd of the inter-stack wire SP is held at the breakdown voltage Vz of the first Zener diode 70a. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to the breakdown voltage Vz of the first Zener diode 70a as time elapses.

  Subsequently, after the voltage stored in the flying capacitor 44 is sufficiently discharged, the control device 50 turns off the eighth and ninth switches SW21 and SW22 and turns on the output switches SWa and SWb to detect the voltage. The terminal voltage Vc of the flying capacitor 44 is obtained from the unit 40.

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value, and determines whether there is an open abnormality of the inter-stack wire SP. Note that, as in the third embodiment, the inter-stack wire is based on the inter-terminal voltage Vd (potential difference between both ends of the bypass path 70) of the inter-stack wire SP when the eighth and ninth input switches SW21 and SW22 are turned on. The presence or absence of SP open abnormality may be determined.

  Also in the present embodiment described above, the flying capacitor 44 is transferred from the electrical path L6 connected to the high potential side of the inter-stack wire SP to the electrical path L5 connected to the low potential side depending on whether or not the inter-stack wire SP is open. The terminal-to-terminal voltage Vc of the flying capacitor 44 when a large discharge current flows greatly deviates.

  Therefore, even if the protective diode 32 is provided in the pair of electric paths L5 and L6 connected to both ends of the inter-stack wire SP, the open abnormality of the inter-stack wire SP is determined based on the voltage between the terminals of the flying capacitor 44. Presence / absence can be determined appropriately.

  In the present embodiment, as in the fifth embodiment, the voltage charged to the flying capacitor 44 with positive polarity is detected by the abnormality detection process, and the voltage charged to the flying capacitor 44 with the reverse polarity is detected. There is no need to detect.

  And since the control apparatus 50 of this embodiment does not need to expand the dynamic range at the time of acquiring a voltage for an abnormality detection process, compared with 1st Embodiment, at the time of execution of an abnormality determination process The detection voltage of the voltage detection unit 40 can be acquired with high accuracy.

  Further, in this embodiment, compared to the fifth embodiment, the number of switches constituting the input side switch group 42 is small, and the discharge current of the flying capacitor 44 charged with the positive voltage is used as the inter-stack wire. It is possible to flow from the electrical path connected to the high potential side of the SP to the electrical path connected to the low potential side.

  However, in the present embodiment, when the voltage detection unit 40 detects the voltage between the terminals of the second cell group CG2, the fifth and eighth input switches SW5 and SW21 are turned on, and the voltage between the terminals of the second cell group CG2 is turned on. Is charged in the flying capacitor 44. The closed circuit formed by turning on the fifth and eighth input switches SW5 and SW21 includes the inter-stack wire SP in addition to the second cell group CG2. For this reason, in the configuration of the present embodiment, the voltage detection accuracy when detecting the voltage across the terminals of the second cell group CG2 may be lower than in the first and fifth embodiments.

  For this reason, the configuration of the present embodiment is suitable when priority is given to the detection accuracy of the open abnormality of the inter-stack wire SP and the simplification of the battery monitoring unit 20 over the detection accuracy of the battery voltage between the second cell groups CG2. It is.

(Seventh embodiment)
Next, a seventh embodiment will be described. In the present embodiment, an example in which a part of the configuration of the battery monitoring unit 20 in the first embodiment (the input-side switch group 42 of the voltage detection unit 40) is changed will be described. In the present embodiment, description of the same or equivalent parts as in the first embodiment will be omitted or simplified.

  In the input side switch group 42 of the present embodiment, when the flying capacitor 44 is charged with a reverse polarity voltage, the input side switch group 42 is operated to open and close the discharging current of the flying capacitor 44 to the high level of the inter-stack wire SP. It is possible to form a discharge path that flows from the electrical path connected to the potential side to the electrical path connected to the low potential side.

  Specifically, as shown in FIG. 14, the input-side switch group 42 of the present embodiment includes four switches such as first, third to fifth input switches SW1, SW3 to SW5. Other configurations are the same as those of the first embodiment, and the abnormality determination process of the present embodiment will be described below with reference to FIGS. 15 and 16.

  First, the control device 50 turns on the first and fourth input switches SW1 and SW4 so that the flying capacitor 44 is charged with the terminal voltage of the first cell group CG1 with the reverse polarity.

  As a result, as indicated by a broken line arrow in FIG. 15, a current flows from the first cell group CG1 to the fifth electric path L5 → the second input line Lβ → the flying capacitor 44 → the first input line Lα → the first electric path L1. A charging path (closed circuit) is formed. At this time, since the discharging current of the assembled battery 10 flows from the negative electrode terminal B side to the positive electrode terminal A side, the flying capacitor 44 is charged with a reverse polarity voltage (negative voltage).

  Subsequently, the control device 50 sets the effective value Vτ in the inter-terminal voltage of the first cell group CG1 as a “reference voltage” and charges the first and fourth input switches SW1 and SW4 until a voltage equal to or higher than the reference voltage is charged. Hold on. The “reference voltage” may be the breakdown voltage Vz of the first Zener diode 70a, as in the second embodiment.

  Subsequently, the control device 50 turns off the first and fourth input switches SW1 and SW4 and charges the third and fourth input switches SW3 and SW4 while the flying capacitor 44 is charged with a voltage equal to or higher than the reference voltage. Turn on. Then, the control device 50 holds the third and fourth input switches SW3 and SW4 on until the voltage stored in the flying capacitor 44 is sufficiently discharged.

  At this time, when the open abnormality does not occur in the inter-stack wire SP, the flying capacitor 44 changes from the second input line Lβ → the sixth electric path L6 → the inter-stack wire SP → the fifth electric path L5 → the first input line Lα. A discharge path (closed circuit) through which current flows is formed.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the above-described inter-stack wire SP. At this time, the inter-terminal voltage Vd of the inter-stack wire SP hardly varies. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to zero as time passes.

  On the other hand, when an open abnormality has occurred in the inter-stack wire SP, as shown by a broken line arrow in FIG. 16, the second input line Lβ → the sixth electric path L6 → the bypass path 70 → the fifth electric line from the flying capacitor 44. A discharge path (closed circuit) through which a current flows from the path L5 to the first input line Lα is formed. The discharge current from the flying capacitor 44 flows from the sixth electric path L6 side having the same potential as the high potential side terminal in the inter-stack wire SP to the fifth electric path L5 having the same potential as the low potential side terminal. Therefore, the discharge current does not flow through the protection diode 32.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the bypass path 70 described above. At this time, the inter-terminal voltage Vd of the inter-stack wire SP is held at a value obtained by subtracting the forward voltage Vf of the protection diode 32 from the breakdown voltage Vz of the first Zener diode 70a. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to a voltage obtained by subtracting the forward voltage Vf of the protection diode 32 from the breakdown voltage Vz of the first Zener diode 70a as time elapses.

  Subsequently, after the voltage stored in the flying capacitor 44 is sufficiently discharged, the control device 50 turns off the third and fourth switches SW3 and SW4 and turns on the output switches SWa and SWb to detect the voltage. The terminal voltage Vc of the flying capacitor 44 is obtained from the unit 40.

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value Vth1, and determines whether there is an open abnormality of the inter-stack wire SP. Note that, as in the third embodiment, the inter-stack wire is based on the inter-stack voltage SP (potential difference between both ends of the bypass path 70) of the inter-stack wire SP when the third and fourth input switches SW3 and SW4 are turned on. The presence or absence of SP open abnormality may be determined.

  Also in the present embodiment described above, the flying capacitor 44 is transferred from the electrical path L6 connected to the high potential side of the inter-stack wire SP to the electrical path L5 connected to the low potential side depending on whether or not the inter-stack wire SP is open. The terminal-to-terminal voltage Vc of the flying capacitor 44 when a large discharge current flows greatly deviates.

  Therefore, even if the protective diode 32 is provided in the pair of electric paths L5 and L6 connected to both ends of the inter-stack wire SP, the open abnormality of the inter-stack wire SP is determined based on the voltage between the terminals of the flying capacitor 44. Presence / absence can be determined appropriately.

  In this embodiment, compared with the first, fifth, and sixth embodiments, the number of switches constituting the input side switch group 42 is small, and the discharge current of the flying capacitor 44 is changed to the high potential of the inter-stack wire SP. It is possible to flow from the electrical path connected to the side to the electrical path connected to the low potential side.

  However, in the present embodiment, as in the first embodiment, the voltage charged to the flying capacitor 44 with the reverse polarity is detected by the abnormality detection process, and compared with the fifth and sixth embodiments. Further, the accuracy of the detection voltage of the inter-terminal voltage Vc of the flying capacitor 44 at the time of executing the abnormality determination process is lowered.

  Further, in the present embodiment, when the voltage detection unit 40 detects the voltage between the terminals of the first cell group CG1, the first and fourth input switches SW1 and SW4 are turned on and the voltage between the terminals of the first cell group CG1 is turned on. Is charged in the flying capacitor 44. The closed circuit formed by turning on the first and fourth input switches SW1 and SW4 includes the inter-stack wire SP in addition to the first cell group CG1. For this reason, in the configuration of the present embodiment, the voltage detection accuracy when detecting the voltage across the terminals of the first cell group CG1 may be lower than in the first, fifth, and sixth embodiments.

  For this reason, the configuration of the present embodiment is used when simplification of the battery monitoring unit 20 is given priority over the detection accuracy of the battery voltage between the cell groups CG1 and CG2 and the detection accuracy of the open abnormality of the inter-stack wire SP. Is preferred.

(Eighth embodiment)
Next, an eighth embodiment will be described. This embodiment demonstrates the example which changed a part of structure of the battery monitoring unit 20 in 1st Embodiment. In the present embodiment, description of the same or equivalent parts as in the first embodiment will be omitted or simplified.

  In the present embodiment, as shown in FIG. 17, a bypass capacitor 72 is provided in the bypass path 70. When the inter-stack wire SP is in an open state (open state), the bypass capacitor 72 generates a voltage generated in the pair of electric paths L5 and L6 connected to both ends of the bypass path 70 (both ends of the inter-stack wire SP). It is a capacitor for absorbing.

  Other configurations are the same as those of the first embodiment, and the abnormality determination process of this embodiment will be described below with reference to FIGS. 18 and 19.

  First, the control device 50 turns on the first and fourth input switches SW1 and SW4 so that the flying capacitor 44 is charged with the terminal voltage of the first cell group CG1 with the reverse polarity.

  As a result, as indicated by a broken line arrow in FIG. 18, a current flows from the first cell group CG1 to the fifth electric path L5 → the second input line Lβ → the flying capacitor 44 → the first input line Lα → the first electric path L1. A charging path (closed circuit) is formed. At this time, since the discharging current of the assembled battery 10 flows from the negative electrode terminal B side to the positive electrode terminal A side, the flying capacitor 44 is charged with a reverse polarity voltage (negative voltage).

  The control device 50 according to the present embodiment sets the effective value Vτ in the inter-terminal voltage of the first cell group CG1 as the “reference voltage”, and continues to charge the first and fourth input switches SW1, SW4 is kept on.

  Subsequently, the control device 50 turns off the first and fourth input switches SW1 and SW4 and charges the third and fourth input switches SW3 and SW4 while the flying capacitor 44 is charged with a voltage equal to or higher than the reference voltage. Turn on. Then, the control device 50 holds the third and fourth input switches SW3 and SW4 on until the voltage stored in the flying capacitor 44 is sufficiently discharged.

  At this time, when the open abnormality does not occur in the inter-stack wire SP, the flying capacitor 44 changes from the second input line Lβ → the sixth electric path L6 → the inter-stack wire SP → the fifth electric path L5 → the first input line Lα. A discharge path (closed circuit) through which current flows is formed.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the above-described inter-stack wire SP. At this time, the inter-terminal voltage Vd of the inter-stack wire SP hardly varies. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to zero as time passes.

  On the other hand, when an open abnormality occurs in the inter-stack wire SP, as indicated by the broken line arrow in FIG. 19, the second input line Lβ → the sixth electric path L6 → the bypass path 70 → the fifth electric line from the flying capacitor 44. A discharge path (closed circuit) through which a current flows from the path L5 to the first input line Lα is formed. The discharge current from the flying capacitor 44 flows from the sixth electric path L6 side having the same potential as the high potential side terminal in the inter-stack wire SP to the fifth electric path L5 having the same potential as the low potential side terminal. Therefore, the discharge current does not flow through the protection diode 32.

  Thereby, the electric charge stored in the flying capacitor 44 moves to the bypass capacitor 72 and the bypass capacitor 72 is charged. At this time, the voltage Vd between the terminals of the inter-stack wire SP becomes a value determined by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= Vc ′ × C1 / (C1 + C2)). “Vc ′” is a voltage across the terminals of the flying capacitor 44 when the first and fourth input switches SW 1 and SW 4 are turned on to charge the flying capacitor 44.

  The terminal voltage Vc of the flying capacitor 44 is a value determined by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= Vc ′ × C2 / (C1 + C2)). The voltage between the terminals of the bypass capacitor 72 is also a value determined by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= Vc ′ × C1 / (C1 + C2)).

  Subsequently, after the time required for discharging the flying capacitor 44 has elapsed, the control device 50 turns off the third and fourth switches SW3 and SW4, turns on the output switches SWa and SWb, The voltage Vc between the terminals of the flying capacitor 44 is acquired from the voltage detection unit 40.

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value Vth, and determines whether there is an open abnormality of the inter-stack wire SP. The determination threshold Vth is a value obtained by multiplying the reference voltage when charging the flying capacitor 44 by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= reference voltage × C2 / (C1 + C2). )).

  Also in the present embodiment described above, the flying capacitor 44 is transferred from the electrical path L6 connected to the high potential side of the inter-stack wire SP to the electrical path L5 connected to the low potential side depending on whether or not the inter-stack wire SP is open. The terminal-to-terminal voltage Vc of the flying capacitor 44 when a large discharge current flows greatly deviates.

  Therefore, even if the protective diode 32 is provided in the pair of electric paths L5 and L6 connected to both ends of the inter-stack wire SP, the open abnormality of the inter-stack wire SP is determined based on the voltage between the terminals of the flying capacitor 44. Presence / absence can be determined appropriately.

  In the present embodiment, an example in which the “reference voltage” charged in the flying capacitor 44 is the effective value Vτ in the voltage across the terminals of the first cell group CG1 has been described. However, the “reference voltage” must be “0V”. For example, the voltage may be equal to or lower than the above-described effective value Vτ.

  Further, in this embodiment, the example in which the voltage Vc between the terminals of the flying capacitor 44 is compared with a preset determination threshold value Vth to determine the presence or absence of the open abnormality of the inter-stack wire SP has been described. Not.

  For example, the voltage Vd between terminals of the inter-stack wire SP (potential difference between both ends of the bypass capacitor 72) when the third and fourth input switches SW3 and SW4 are turned on is compared with a predetermined determination threshold value Vth. The presence / absence of an open abnormality of the inter-stack wire SP may be determined. In this case, the determination threshold Vth is a value obtained by multiplying the reference voltage when charging the flying capacitor 44 by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= reference voltage × C1 / ( C1 + C2)).

(Ninth embodiment)
Next, a ninth embodiment will be described. This embodiment demonstrates the example which changed a part of structure of the battery monitoring unit 20 in 6th Embodiment. In the present embodiment, description of the same or equivalent parts as in the first embodiment will be omitted or simplified.

  In the present embodiment, as shown in FIG. 20, a bypass capacitor 72 is provided in the bypass path 70, and a discharge switch 34 for discharging the bypass capacitor 72 is incorporated in the second monitoring IC 30b.

  The discharge switch 34 is provided to release the electric charge stored in the bypass capacitor 72 when an open abnormality occurs in the inter-stack wire SP. The discharge switch 34 of the present embodiment constitutes a discharge switching means that switches between an on state in which the bypass capacitor 72 is discharged and an off state in which the discharge of the bypass capacitor 72 is stopped. Note that the discharge switch 34 of the present embodiment can be switched between an on state and an off state in accordance with a control signal from the control device 50.

  Other configurations are the same as those of the sixth embodiment, and the abnormality determination process of the present embodiment will be described below with reference to FIGS. 21 and 22.

  First, the control device 50 turns on the second and third input switches SW2 and SW3 so that the flying capacitor 44 is charged with a positive voltage between the terminals of the first cell group CG1.

  As a result, as indicated by the broken line arrow in FIG. 21, a current flows from the first cell group CG1 to the fifth electric path L5 → the first input line Lα → the flying capacitor 44 → the second input line Lβ → the first electric path L1. A charging path (closed circuit) is formed. At this time, since the discharging current of the assembled battery 10 flows from the positive terminal A side to the negative terminal B side, the flying capacitor 44 is charged with a positive voltage (positive voltage).

  Further, the control device 50 sets the discharge switch 34 to the on state when the flying capacitor 44 is charged with the voltage across the terminals of the first cell group CG1. Thereby, the bypass capacitor 72 is discharged.

  Subsequently, the control device 50 sets the effective value Vτ in the inter-terminal voltage of the first cell group CG1 as a “reference voltage”, and continues to charge the second and third input switches SW2 and SW3 until a voltage equal to or higher than the reference voltage is charged. Hold on.

  Thereafter, the second and third input switches SW2 and SW3 are turned off, and the eighth and ninth input switches SW21 and SW22 are turned on. The control device 50 holds the eighth and ninth input switches SW21 and SW22 on until the voltage stored in the flying capacitor 44 is sufficiently discharged.

  Further, the control device 50 sets the discharge switch 34 to the OFF state when discharging the flying capacitor 44. As a result, the bypass capacitor 72 is in a chargeable state with the discharge stopped.

  At this time, when the open abnormality does not occur in the inter-stack wire SP, the flying capacitor 44 changes from the first input line Lα → the sixth electric path L6 → the inter-stack wire SP → the fifth electric path L5 → the second input line Lβ. A discharge path (closed circuit) through which current flows is formed.

  Thereby, the voltage stored in the flying capacitor 44 is discharged in the discharge path including the above-described inter-stack wire SP. At this time, the inter-terminal voltage Vd of the inter-stack wire SP hardly varies. Further, the inter-terminal voltage Vc of the flying capacitor 44 converges to zero as time passes.

  On the other hand, when an open abnormality has occurred in the inter-stack wire SP, as shown by the broken line arrow in FIG. 22, the first input line Lα → the sixth electric path L6 → the bypass path 70 → the fifth electric line from the flying capacitor 44. A discharge path (closed circuit) through which a current flows from the path L5 to the second input line Lβ is formed. The discharge current from the flying capacitor 44 flows from the sixth electric path L6 side having the same potential as the high potential side terminal in the inter-stack wire SP to the fifth electric path L5 having the same potential as the low potential side terminal. Therefore, the discharge current does not flow through the protection diode 32.

  Thereby, the electric charge stored in the flying capacitor 44 moves to the bypass capacitor 72 and the bypass capacitor 72 is charged. At this time, the inter-terminal voltage Vd of the inter-stack wire SP is a value determined by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= Vc ′ × C1 / (C1 + C2), as in the eighth embodiment. )). The voltage between the terminals of the bypass capacitor 72 is also a value determined by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= Vc ′ × C1 / (C1 + C2)).

  Subsequently, after the time required for discharging the flying capacitor 44 has elapsed, the control device 50 turns off the third and fourth switches SW3 and SW4, turns on the output switches SWa and SWb, The voltage Vc between the terminals of the flying capacitor 44 is acquired from the voltage detection unit 40.

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value Vth, and determines whether there is an open abnormality of the inter-stack wire SP. The determination threshold Vth is a value obtained by multiplying the reference voltage when charging the flying capacitor 44 by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= reference voltage × C2 / (C1 + C2). )).

  Also in the present embodiment described above, the flying capacitor 44 is transferred from the electrical path L6 connected to the high potential side of the inter-stack wire SP to the electrical path L5 connected to the low potential side depending on whether or not the inter-stack wire SP is open. The terminal-to-terminal voltage Vc of the flying capacitor 44 when a large discharge current flows greatly deviates.

  Therefore, even if the protective diode 32 is provided in the pair of electric paths L5 and L6 connected to both ends of the inter-stack wire SP, the open abnormality of the inter-stack wire SP is determined based on the voltage between the terminals of the flying capacitor 44. Presence / absence can be determined appropriately.

  Further, in the present embodiment, before discharging the flying capacitor 44, the discharge switch 34 is set to the on state and the bypass capacitor 72 is discharged. According to this, even if charges are stored in the bypass capacitor 72 for some reason before the execution of the abnormality detection process, the bypass capacitor 72 can be discharged. Can be determined.

  Here, in a configuration in which a closed circuit is formed by the bypass capacitor 72 and the protection diode 32 as in the eighth embodiment, the bypass capacitor 72 can be discharged when a current flows through the protection diode 32. For this reason, the discharge switch 34 is suitable for a configuration in which a closed circuit is not formed by the bypass capacitor 72 and the protection diode 32.

  In the present embodiment, an example in which the “reference voltage” charged in the flying capacitor 44 is the effective value Vτ in the voltage across the terminals of the first cell group CG1 has been described. However, the “reference voltage” must be “0V”. For example, the voltage may be equal to or lower than the above-described effective value Vτ.

  Further, in this embodiment, the example in which the voltage Vc between the terminals of the flying capacitor 44 is compared with a preset determination threshold value Vth to determine the presence or absence of the open abnormality of the inter-stack wire SP has been described. Not. For example, the voltage Vd between terminals of the inter-stack wire SP when the eighth and ninth input switches SW21 and SW22 are turned on (potential difference between both ends of the bypass capacitor 72) is compared with a preset determination threshold value Vth. The presence / absence of an open abnormality of the inter-stack wire SP may be determined. In this case, the determination threshold Vth is a value obtained by multiplying the reference voltage when charging the flying capacitor 44 by the capacitance ratio of the capacitance C1 of the flying capacitor 44 and the capacitance C2 of the bypass capacitor 72 (= reference voltage × C1 / ( C1 + C2)).

  In the present embodiment, the example in which the discharge switch 34 is built in the second monitoring IC 30b has been described. However, the present invention is not limited to this. For example, the discharge switch 34 may be configured separately from the second monitoring IC 30b. Good.

(10th Embodiment)
Next, a tenth embodiment will be described. This embodiment demonstrates the example which changed a part of structure of the battery monitoring unit 20 in 1st Embodiment. In the present embodiment, description of the same or equivalent parts as in the first embodiment will be omitted or simplified.

  The whole structure of the assembled battery and battery monitoring unit in this embodiment is shown in FIGS. Note that FIG. 23 and FIG. 24 differ only in the current path indicated by the dashed arrow. That is, in FIG. 23, the charging path of the flying capacitor 44 when the inter-stack wire SP is broken is indicated by a broken-line arrow, and FIG. 24 shows the flying when the inter-stack wire SP is broken. The difference is that the discharge path of the capacitor 44 is indicated by a broken line arrow.

  The battery monitoring unit 20 in this embodiment is different from the battery monitoring unit according to the first embodiment in that it further includes resistors R31 to R36, capacitors C31 to C33, and switches SW31 to SW33.

  The switches SW31 and SW33 are provided as equalizing switches that discharge by short-circuiting both terminals of the unit batteries BC3 and BC4, respectively. The switches SW31 to SW33 are turned on or off according to control signals input from the control device 50 via the monitoring IC 30b.

  The battery monitoring unit 20 in the present embodiment detects disconnection of the plurality of electric paths L5 and L6 between the both ends of each of the unit batteries BC3 to BC4 and the battery monitoring unit 20.

  That is, the battery monitoring unit 20 in this embodiment distinguishes and detects the open abnormality of the inter-stack wire SP and the disconnection of the plurality of electrical paths L5 and L6. Thus, by detecting the open abnormality of the inter-stack wire SP and the disconnection of the plurality of electrical paths L5 and L6, the plurality of electrical paths L1 to L1 are detected despite the disconnection occurring in the inter-stack wire SP. It is possible to prevent the wiring of L10 from being replaced or, conversely, the inter-stack wire SP is replaced even though any of the wirings of the plurality of electrical paths L1 to L10 is disconnected. Is possible.

  In addition, a circuit in which a resistor R32, a capacitor C31, and a resistor R31 are connected in series is connected in parallel with the unit battery BC3. A switch SW31 is connected in parallel with the capacitor C31.

  A circuit in which a resistor R34, a capacitor C32, and a resistor R33 are connected in series is connected in parallel with the inter-stack wire SP. A switch SW32 is connected in parallel with the capacitor C32.

  In addition, a circuit in which a resistor R36, a capacitor C33, and a resistor R35 are connected in series is connected in parallel with the unit battery BC4. A switch SW33 is connected in parallel with the capacitor C33.

  Here, determination of the open abnormality of the inter-stack wire SP will be described. In the determination of the open abnormality of the inter-stack wire SP, the switches SW31 to SW33 are kept off. Here, it is assumed that the inter-stack wire SP is broken.

  First, as in the first embodiment, as indicated by the broken line arrow in FIG. 23, the fifth electric path L5 → the protection diode 32 → the second input line Lβ → the flying capacitor 44 → the first input from the first cell group CG1. A charging path (closed circuit) through which current flows from the line Lα to the first electric path L1 is formed, and a voltage at which the positive terminal A is “−” and the negative terminal B is “+” is applied to the flying capacitor 44. In this way, the flying capacitor 44 is charged (negatively charged).

  Next, as shown by a broken line arrow in FIG. 24, a discharge path through which a current flows from the flying capacitor 44 to the second input line Lβ → the sixth electric path L6 → the bypass path 70 → the fifth electric path L5 → the first input line Lα. (Closed circuit) is formed, and the flying capacitor 44 is discharged.

  Then, after a time longer than the time constant of the discharge path through which the discharge current of the flying capacitor 44 flows, the terminal voltage Vc of the flying capacitor 44 is acquired, and the terminal voltage Vc of the flying capacitor 44 and a preset determination are obtained. The magnitude relationship with the threshold value Vth1 is compared to determine whether there is an open abnormality of the inter-stack wire SP.

  Next, detection of disconnection of the electric paths L5 and L6 by the control device 50 will be described with reference to FIGS. 25 and 27 show the region X shown in FIG. 23 extracted.

  First, with reference to FIG. 25 and FIG. 26, detection of disconnection of the electrical paths L5 and L6 when neither the inter-stack wire SP nor the electrical paths L5 and L6 are disconnected will be described.

As shown in the first stage of FIG. 26, the control device 50 turns on the switch SW32 for a certain period, then turns off the switch SW32, and then determines the voltage _VA across the terminals of the capacitor C32 after a certain period has elapsed (t30). 2 Acquired from the monitoring IC 30b.

Here, when neither the inter-stack wire SP nor the electrical paths L5 and L6 are disconnected, the voltage between the terminals of the capacitor C32 becomes 0 V due to the inter-stack wire SP, so that the switch SW32 is turned on after the switch SW32 is turned on for a certain period. After a certain period of time has passed after turning OFF, the voltage V _A between the terminals of the capacitor C32 becomes 0V as shown in the third stage of FIG.

Then, as shown in the second stage of FIG. 26, after the switches SW31 and SW33 are turned on for a certain period of time, the switches SW31 and SW33 are turned off and the fixed period of time elapses (t31), the inter-terminal voltage V of the capacitor C32. _B is acquired from the second monitoring IC 30b.

Here, when neither the inter-stack wire SP nor the electrical paths L5 and L6 are disconnected, the voltage V _A between the terminals of the capacitor C32 at t30 and the voltage V _B between the terminals of the capacitor C32 at t31 are each 0V. The paths L5 and L6 are determined to be normal.

On the other hand, when neither of the electrical paths L5 and L6 is disconnected, but the inter-stack wire SP is disconnected, the switch SW32 is turned on for a certain period, and then the switch SW32 is turned off for a certain period of time (t30). terminal voltage _{V a} of the capacitor C32 of) becomes 0V as shown in the third stage of FIG. 26.

Then, as shown in the second stage of FIG. 26, when the switches SW31 and SW33 are turned on and then the switches SW31 and SW33 are turned off and a certain period of time elapses, a current as indicated by a dotted arrow in FIG. 25 flows. . That is, current flows from the electrical path L7 to the resistor R36, the capacitor C33, the resistor R35, the resistor R34, the capacitor C32, the resistor R33, the resistor R32, the capacitor C31, the resistor R31, and the current path L4. Therefore, the voltage V _B between the terminals of the capacitor C32 is sufficiently small, the magnitude of the difference between the voltage V _A between the terminals of the capacitor C32 and the voltage V _B between the terminals of the capacitor C32 is less than a predetermined value α, and the electrical paths L5 and L6 are Determined as normal.

As described above, regardless of whether there is an open abnormality of the inter-stack wire SP, if neither of the electrical paths L5 and L6 is disconnected, the voltage V _A between the terminals of the capacitor C32 at t30 and the voltage of the capacitor C32 at t31 the magnitude of the difference of the terminal voltage V _B becomes less than predetermined value alpha, the electrical path L5, L6 are determined to be normal.

  Next, a case where the inter-stack wire SP is not disconnected and the electrical path L5 is disconnected will be described with reference to FIGS.

In this case, as shown in the first stage of FIG. 28, when the switch SW32 is turned on, the voltage V _A between the terminals of the capacitor C32 becomes 0V. After the switch SW32 is turned on for a certain period, the electric path L5 is disconnected even after the switch SW32 is turned off, so that the voltage V _A between the terminals of the capacitor C32 becomes 0V. That is, the voltage V _A between the terminals of the capacitor C32 after the switch SW32 is turned on for a certain period and then the switch SW32 is turned off and a certain period has elapsed (t30) becomes 0V as shown in the third stage of FIG.

Next, as shown in the second stage of FIG. 28, when the switches SW31 and SW33 are turned on, a current flows through a path as indicated by a dotted arrow in FIG. That is, a current flows from the electric path L6 to the resistor R34, the capacitor C32, the resistor R32, the switch SW31, the resistor R31, and the current path L4. At this time, the terminal voltage of the unit battery BC3 is applied between the terminals of the capacitor C32. That is, the terminal voltage of the capacitor C32 gradually increases as shown in the third stage of FIG. Therefore, the difference between the terminal voltage V _A of the capacitor C32 at t30 and the terminal voltage V _B of the capacitor C32 at t31 is larger than the predetermined value α, and it is determined that one of the electrical paths L5 and L6 is abnormal. The

Even when the inter-stack wire SP is not disconnected and the electrical path L6 is disconnected, the characteristics between the terminals of the capacitor C32 are as shown in the third row of FIG. Therefore, even when the electric path L6 is disconnected, the magnitude of the difference between the voltage V _A between the terminals of the capacitor C32 at t30 and the voltage V _B between the terminals of the capacitor C32 at t31 is larger than the predetermined value α, and the electric path L5 , L6 is determined to be abnormal.

As described above, the voltage V _A between the terminals of the capacitor C32 after the switch SW32 is turned on and off (t30) and the voltage V _B between the terminals of the capacitor C32 after the switches SW31 and SW33 are turned on and off (t31) are obtained. Then, the disconnection abnormality of the electric paths L5 and L6 is determined based on whether or not the difference between the terminal voltage V _A of the capacitor C32 at t30 and the terminal voltage V _B of the capacitor C32 at t31 is larger than a predetermined value α. can do.

  However, as described above, in the present embodiment, when the inter-stack wire SP is disconnected, the second input line Lβ → the sixth electric path L6 → the bypass path 70 from the flying capacitor 44 as shown by the broken line arrow in FIG. → Fifth electric path L5 → A discharge path (closed circuit) through which current flows to the first input line Lα is formed, and the flying capacitor 44 is discharged (discharged). For this reason, if disconnection detection of the electric paths L5 and L6 is performed during the discharge of the flying capacitor 44, the voltage of each terminal of the capacitor C32 is raised by the discharge current of the flying capacitor 44, and the disconnection of the electric paths L5 and L6 is caused. May be erroneously detected.

  Therefore, in the present embodiment, disconnection of the electrical paths L5 and L6 is not detected during the discharging of the flying capacitor 44. Further, when the flying capacitor 44 is discharged, the capacitor C32 is charged by the discharge current of the flying capacitor 44. Therefore, after the flying capacitor 44 is discharged, the capacitor C32 provided in parallel with the inter-stack wire SP is discharged. Thereafter, disconnection of the electric paths L5 and L6 is detected.

  Here, a specific example of the abnormality determination process executed by the control device 50 of the present embodiment will be described with reference to FIG.

  First, the control device 50 turns on the first and fourth input switches SW1 and SW4. That is, the first and fourth terminals are charged so that the flying capacitor 44 is charged with the terminal voltage of the first cell group CG1 having the reverse polarity (the positive terminal A is “−” and the negative terminal B is “+”). The input switches SW1 and SW4 are turned on.

  As a result, the discharging current of the first cell group CG1 flows to the flying capacitor 44 from the negative terminal B side to the positive terminal A side, and the flying capacitor 44 is charged with a reverse polarity voltage (negative charge).

  Next, the control device 50 charges the flying capacitor 44 with a voltage equal to or higher than the effective value Vτ in the inter-terminal voltage Vd of the first cell group CG1, and completes the negative charge of the flying capacitor 44 in the first, The fourth input switches SW1 and SW4 are turned off.

Next, as shown in the fifth stage of FIG. 29, after the switches SW31 and 33 are turned on for a certain period, the switches SW31 and 33 are turned off, and the voltage V between terminals of the capacitor C32 after a certain period has elapsed (t40). _A is acquired from the second monitoring IC 30b. Actually, the disconnection determination of the electrical paths L5 and L6 is performed by using the voltage _VA between the terminals of the capacitor C32 at t40. However, the disconnection determination of the electrical paths L5 and L6 will be described later, and the description is given here. Omitted.

  Next, as shown in the second stage of FIG. 29, the control device 50 turns on the third and fourth input switches SW3 and SW4. The control device 50 keeps the third and fourth input switches SW3 and SW4 on until the voltage stored in the flying capacitor 44 is sufficiently discharged.

  Here, when an open abnormality has occurred in the inter-stack wire SP, as indicated by a broken line arrow in FIG. 24, the second input line Lβ → the sixth electric path L6 → the bypass path 70 → the fifth line from the flying capacitor 44. A discharge path (closed circuit) through which a current flows from the electrical path L5 to the first input line Lα is formed.

  The discharge current from the flying capacitor 44 flows from the sixth electric path L6 side having the same potential as the high potential side terminal in the inter-stack wire SP to the fifth electric path L5 having the same potential as the low potential side terminal. Therefore, the discharge current does not flow through the protection diode 32.

  Thereby, the voltage stored in the flying capacitor 44 is discharged (discharged) in the discharge path including the bypass path 70 described above.

  When no open abnormality has occurred in the inter-stack wire SP, the discharge (discharge) is performed in the discharge path including the inter-stack wire SP instead of the bypass path 70 described above.

  Next, after the voltage stored in the flying capacitor 44 is sufficiently discharged (discharged), the control device 50 turns off the switches SW3 and SW4, turns on the output switches SWa and SWb, and turns on the flying capacitor 44. A digital signal indicating the inter-terminal voltage Vc is acquired.

  Then, the control device 50 compares the magnitude relationship between the inter-terminal voltage Vc of the flying capacitor 44 and a preset determination threshold value Vth1, and determines whether there is an open abnormality of the inter-stack wire SP. Note that the determination of whether there is an open abnormality of the inter-stack wire SP can be performed in the same manner as in the first embodiment.

Further, after turning off the switches SW3 and SW4, the control device 50 turns on the switch SW32 for a certain period, as shown in the fourth row of FIG. Then, turning off the switch SW32, then it acquires from the second monitoring IC30b the terminal voltage _{V B} of the capacitor C32 after the elapse of a predetermined time period (t41).

  In addition, by turning on the switch SW32 for a certain period, the voltage of the capacitor C32 stored when the flying capacitor 44 is discharged is discharged. Thus, by turning on the switch SW32 for a certain period, the capacitor C32 is discharged (refreshed), and the voltage across the terminals of the capacitor C32 converges to 0V.

Thus, the control device 50 while refreshing the capacitor C32, and turns off the switch SW32, then it acquires from the second monitoring IC30b the terminal voltage _{V B} of the capacitor C32 after the elapse of a predetermined time period (t31). Therefore, the voltage V _B between the terminals of the capacitor C32 can be acquired from the second monitoring IC 30b without being affected by the current flowing through the discharge path indicated by the dotted line arrow in FIG.

  Next, the control device 50 turns on the first and fourth input switches SW1 and SW4. That is, the first and fourth terminals are charged so that the flying capacitor 44 is charged with the terminal voltage of the first cell group CG1 having the reverse polarity (the positive terminal A is “−” and the negative terminal B is “+”). The input switches SW1 and SW4 are turned on.

  As a result, the discharging current of the first cell group CG1 flows to the flying capacitor 44 from the negative terminal B side to the positive terminal A side, and the flying capacitor 44 is charged with a reverse polarity voltage (negative charge).

  Next, the control device 50 charges the flying capacitor 44 with a voltage equal to or higher than the effective value Vτ in the inter-terminal voltage Vd of the first cell group CG1, and completes the negative charge of the flying capacitor 44 in the first, The fourth input switches SW1 and SW4 are turned off.

Next, as shown in the fifth stage of FIG. 29, after the switches SW31 and 33 are turned on for a certain period, the switches SW31 and 33 are turned off, and the voltage V between terminals of the capacitor C32 after a certain period has elapsed (t42). _A is acquired from the second monitoring IC 30b.

Next, as shown in the sixth stage of FIG. 29, the control device 50 determines the magnitude of the difference between the terminal voltage V _A of the capacitor C32 at t41 and the terminal voltage V _B of the capacitor C32 at t42 and the predetermined value α. The relationship is compared and the presence or absence of disconnection of the electric paths L5 and L6 is determined.

Specifically, if the magnitude of the difference of the terminal voltage _{V B} of the capacitor C32 in the inter-terminal voltage _{V A} and t42 of the capacitor C32 is equal to or less than the predetermined value α at t41, the electric path L5, L6 are determined to be normal.

In addition, when the magnitude of the difference between the terminal voltage V _A of the capacitor C32 at t41 and the terminal voltage V _B of the capacitor C32 at t42 is larger than the predetermined value α, the electrical paths L5 and L6 are determined to be disconnection abnormalities.

  In this manner, the negative charge and discharge of the flying capacitor 44 are repeatedly performed to determine whether the inter-stack wire SP is open or not, and the electric path L5 between the negative charge period and the discharge period of the flying capacitor 44, L6 disconnection detection is repeated.

  As described above, the battery monitoring unit 20 includes the capacitor C32 provided between the pair of electrical paths L5 and L6 connected to both ends of the inter-stack wire SP among the plurality of electrical paths L1 to L10, and the plurality of electrical paths. Among the paths L1 to L10, a capacitor C31 provided between a pair of electrical paths L4 and L5 connected to both ends of the unit battery BC3 connected in series to the lower potential side than the inter-stack wire SP, and a plurality of electrical paths Among L1 to L10, a capacitor C33 provided between a pair of electric paths L6 and L7 connected to both ends of a unit battery BC4 connected in series to the higher potential side than the inter-stack wire SP is provided.

The battery monitoring unit 20 further discharges the first capacitor C32, then stops the discharge of the first capacitor C32, and detects the voltage V _A between the terminals of the capacitor C32 and the second and third capacitors C31. , First to third capacitors based on the magnitude of the voltage difference between the terminals of the first capacitor C32 detected after discharging the C33 and then stopping the discharge of the second and third capacitors C31, C33. The presence or absence of a disconnection of a plurality of electrical paths connected to is determined.

  In addition, the battery monitoring unit 20 has the first electric path L6 via either the inter-stack wire SP or the bypass path 70 in a state where the flying capacitor 44 is charged with a voltage equal to or higher than a predetermined reference voltage. A plurality of electrical paths connected to the first to third capacitors C31 to C33 after the input side switch group is operated so that the discharge current of the flying capacitor 44 flows from the side to the second electrical path L5 side Since the first capacitor C32 is discharged before the presence / absence of disconnection is determined, even if the first capacitor C32 is charged when the flying capacitor 44 is discharged, a plurality of electric paths are provided. It is possible to prevent erroneous determination of the presence or absence of disconnection. That is, the open abnormality of the inter-stack wire SP and the disconnection of the plurality of electrical paths L5 and L6 can be distinguished and detected.

(Other embodiments)
As mentioned above, although embodiment of this invention was described, this invention is not limited to the above-mentioned embodiment, In the range described in the claim, it can change suitably. For example, various modifications are possible as follows.

  (1) In each of the above-described embodiments, the example in which the pair of electrical paths L5 and L6 connected to both ends of the inter-stack wire SP are short-circuited by the bypass path 70 is described, but the present invention is not limited to this.

  The bypass path is a first electric path L6 to L10 that is equal to or higher than the high potential side terminal of the inter-stack wire SP, and a second electric path that is equal to or lower than the low potential side terminal of the inter-stack wire SP. The structure which short-circuits path | route L1-L5 may be sufficient.

  Hereinafter, in the bypass path 70 shown in the first embodiment, as shown in FIG. 30, the seventh electric path L7 and the fifth electric path L5 having a higher potential than the terminals on the high potential side of the inter-stack wires SP are short-circuited. An example in which the bypass path 71 is changed will be described.

  In this case, the fourth input switch SW4 of the first embodiment is changed to a tenth input switch SW31 whose one end is connected to the seventh electric path L7 via the resistor R31. The bypass path 71 is provided with third and fourth Zener diodes 71a and 71b corresponding to the first and second Zener diodes 70a and 70b of the first embodiment. As the third and fourth Zener diodes 71a and 71b, those whose breakdown voltage has a value (for example, 8.2V) greater than the voltage (for example, 3V) between the terminals of the fourth unit battery BC4 is used.

  In the abnormality determination process in the configuration illustrated in FIG. 30, first, the second and tenth input switches SW <b> 2 and SW <b> 31 are turned on to charge the flying capacitor 44 with a reverse polarity voltage. The flying capacitor 44 is charged with the voltages of the first cell group CG1 and the fourth unit battery BC4 in reverse polarity.

  After the flying capacitor 44 is charged with a reverse polarity voltage, the third and tenth input switches SW3 and SW31 are turned on. As a result, the discharge current of the flying capacitor 44 is connected to the low potential side from the seventh electrical path L7 connected to the high potential side of the interstack wire SP via either the interstack wire SP or the bypass path 71. In addition, a discharge path that flows to the fifth electric path L5 is formed.

  When the open abnormality of the inter-stack wire SP does not occur, the discharge current of the flying capacitor 44 becomes a discharge path through which the inter-stack wire SP flows, and the inter-terminal voltage Vc of the flying capacitor 44 changes with time of the fourth unit battery BC. It converges to the voltage between terminals.

  On the other hand, when an open abnormality of the inter-stack wire SP occurs, the discharge current of the flying capacitor 44 becomes a discharge path that flows toward the bypass path 71 as shown by the broken line arrow in FIG. In this case, the inter-terminal voltage Vc of the flying capacitor 44 converges to a value near the breakdown voltage Vz of the third Zener diode 71a (> the inter-terminal voltage of the fourth unit battery BC4) with time.

  As described above, in the configuration illustrated in FIG. 30, the voltage between the terminals of the flying capacitor 44 greatly deviates depending on the presence or absence of the open abnormality of the inter-stack wire SP. The presence or absence of SP open abnormality can be determined. In addition, what is necessary is just to set the determination threshold value at the time of determining open abnormality to the value which considered the voltage between terminals of 4th unit battery BC4 when setting it as the structure of FIG.

  Of course, the bypass path may be other than the configuration illustrated in FIG. For example, the bypass path 70 shown in the first embodiment is changed to a bypass path that short-circuits the sixth electrical path L6 and the fourth electrical path L4 having a lower potential than the low potential side terminal of the inter-stack wire SP. Also good. In this case, if the third input switch SW3 of the first embodiment is connected to the fourth electric path L4, the discharge current of the flying capacitor 44 is transferred between the stacks via either the inter-stack wire SP or the bypass path 71. A discharge path that flows from the sixth electric path L7 connected to the high potential side of the wire SP to the fourth electric path L4 connected to the low potential side can be formed.

  (2) In each of the above-described embodiments, the unit battery is not included in the discharge path through which the discharge current of the flying capacitor 44 flows. However, the present invention is not limited to this, and the discharge path through which the discharge current of the flying capacitor 44 flows. A unit battery may be included.

  Here, FIG. 31 shows a configuration in which the sixth input switch SW6 of the second embodiment is changed to an eleventh input switch SW41 whose one end is connected to the seventh electric path L7 via the resistor R41.

  In the configuration illustrated in FIG. 31, when the flying capacitor 44 is charged with a positive voltage and then the fifth and eleventh input switches SW11 and SW41 are turned on, the discharging current of the flying capacitor 44 causes the fourth unit battery BC4 to be turned on. A discharge path flowing therethrough is formed.

  When the open abnormality of the inter-stack wire SP does not occur, the discharge current of the flying capacitor 44 becomes a discharge path that flows to the fourth unit battery BC4 and the inter-stack wire SP. It converges to the voltage across the terminals of the 4-unit battery BC4.

  On the other hand, when the open abnormality of the inter-stack wire SP has occurred, the discharge current of the flying capacitor 44 flows to the fourth unit battery BC4 and the bypass path 70 as shown by the broken line arrows in FIG. Become. In this case, the inter-terminal voltage Vc of the flying capacitor 44 converges to a value obtained by adding the inter-terminal voltage of the fourth unit battery BC4 to the breakdown voltage Vz of the first Zener diode 70a over time.

  As described above, in the configuration illustrated in FIG. 31, the voltage between the terminals of the flying capacitor 44 greatly deviates depending on the presence or absence of the open abnormality of the inter-stack wire SP. The presence or absence of SP open abnormality can be determined. In the case of the configuration shown in FIG. 31, the determination threshold for determining an open abnormality may be set to a value that takes into account the voltage across the terminals of the fourth unit battery BC4.

  (3) FIG. 32 shows a configuration in which the fifth input switch SW5 of the second embodiment is changed to a twelfth input switch SW51 whose one end is connected to the seventh electric path L7 via the resistor R51. Yes.

  In the configuration illustrated in FIG. 32, after the positive voltage is charged in the flying capacitor 44, when the sixth and twelfth input switches SW16 and SW51 are turned on, the discharge current of the flying capacitor 44 causes the third unit battery BC3 to be turned on. A discharge path flowing therethrough is formed.

  When the open abnormality of the inter-stack wire SP has not occurred, the discharge current of the flying capacitor 44 becomes a discharge path through which the discharge current flows to the inter-stack wire SP and the third unit battery BC3. It converges to the voltage across the terminals of the three unit battery BC3.

  On the other hand, when an open abnormality of the inter-stack wire SP occurs, the discharge current of the flying capacitor 44 flows to the bypass path 70 and the third unit battery BC3 as shown by the broken line arrow in FIG. Become. In this case, the inter-terminal voltage Vc of the flying capacitor 44 converges to a value obtained by adding the inter-terminal voltage of the third unit battery BC3 to the breakdown voltage Vz of the first Zener diode 70a over time.

  In this way, in the configuration illustrated in FIG. 32, the voltage between the terminals of the flying capacitor 44 greatly deviates depending on whether or not the inter-stack wire SP is open. The presence or absence of SP open abnormality can be determined. In the case of the configuration of FIG. 32, the determination threshold for determining the open abnormality may be set to a value that takes into account the voltage across the terminals of the third unit battery BC3.

  (4) In each of the above-described embodiments, the example in which the pair of Zener diodes 70a and 70b are provided in the bypass path 70 has been described. However, only the first Zener diode 70a out of the pair of Zener diodes 70a and 70b is provided in the bypass path 70. It is good also as a structure to provide.

  (5) In the above-described eighth and ninth embodiments, the example in which the Zener diodes 70a and 70b of the battery monitoring unit 20 of the first and sixth embodiments are changed to the bypass capacitor 72 has been described, but the present invention is not limited to this. . For example, the Zener diodes 70a and 70b may be changed to the bypass capacitor 72 in the embodiments other than the first and sixth embodiments.

  (6) In each of the above-described embodiments, the example in which the inter-stack wire SP is used as the “conductive member” has been described. However, the “conductive member” is not limited to a wire, and may be configured by a bus bar or the like.

  (7) In each of the above-described embodiments, the assembled battery 10 including the two cell groups CG1 and CG2 has been illustrated, but at least a part of the adjacent cell groups is connected by the conductive member (inter-stack wire SP). Thus, the assembled battery 10 may be configured by three or more cell groups.

  (8) In the above-described embodiments, the example in which the battery voltages of the unit batteries BC1 to BC6 are monitored by the plurality of monitoring ICs 30a to 30c has been described. However, the unit batteries BC1 to BC6 are monitored by a single monitoring IC. It is good also as a structure.

  (9) In each of the above-described embodiments, the example in which the abnormality detection device according to the present invention is applied to the battery monitoring unit 20 that monitors the high-voltage battery that constitutes the power source of the motor generator as the in-vehicle main unit has been described. However, the present invention may be applied to other battery systems.

  (10) In each of the above-described embodiments, the elements constituting the embodiment are not necessarily essential unless explicitly stated as essential and clearly considered essential in principle. Needless to say.

  (11) In each of the above-described embodiments, when numerical values such as the number, numerical value, quantity, range, etc. of the constituent elements of the embodiment are mentioned, the specific number is clearly specified when clearly indicated as essential. It is not limited to the specific number except when limited to.

  (12) In each of the above-described embodiments, when referring to the shape, positional relationship, etc. of the component, etc., unless otherwise specified and in principle limited to a specific shape, positional relationship, etc. It is not limited to shape, positional relationship, and the like.

  (13) In the tenth embodiment described above, the first capacitor is charged via the inter-stack wire SP or the bypass path 70 while the flying capacitor 44 is charged with a voltage equal to or higher than a predetermined reference voltage. After the input-side switch group is operated so that the discharge current of the flying capacitor 44 flows from the electric path side to the second electric path side, and before the presence / absence of disconnection of the plurality of electric paths is determined, the first Although the switch SW32 provided in parallel with the capacitor is controlled to be turned on to discharge the capacitor C32, for example, even if the switch SW32 is not controlled to be turned on, for example, a predetermined reference for the flying capacitor 44 is used. You may make it charge (negative charge) by applying the voltage more than a voltage.

  (14) In the tenth embodiment described above, the configuration in which the Zener diodes 70a and 70b are provided in the bypass path 70 is shown in the same manner as in the first embodiment, but instead of the Zener diodes 70a and 70b, the second embodiment is provided. Similarly, the bypass path 70 may be provided with a bypass capacitor 72.

10 battery pack 32 protection diode (current protection element)
40 Voltage detection unit (capacitor voltage detection means)
50a Abnormality determining means 70 Bypass path 70a First Zener diode (Zener diode)
SP Inter-stack wire (conductive member)
BC1 to BC6 unit battery L1 to L10 Electrical path

Claims (9)

Applied to an assembled battery (10) formed by connecting a plurality of cell groups (CG1, CG2), which are series connection bodies in which a plurality of battery cells are connected in series, and provided between adjacent cell groups. An abnormality detection device for detecting an open abnormality of a member (SP),
A plurality of electric paths (L1) connected to both ends of each unit battery (BC1 to BC6) defined by either a single battery cell in the cell group or a predetermined number of battery cells connected in series To L10),
Among the plurality of electrical paths, the electrical path is provided between a pair of electrical paths (L5, L6) connected to both ends of the conductive member, and the high potential side from the low potential side electrical path (L5) in the pair of electrical paths. A current protection element (32) that allows only current flow to the electrical path (L6) of
Of the plurality of electrical paths, a first electrical path (L6) having a potential equal to or higher than the high potential side at both ends of the conductive member, and a second potential having a potential equal to or lower than the low potential side at both ends of the conductive member. A bypass path (70) for short-circuiting the electrical path (L5) of
A Zener diode (70a) provided in the bypass path, having a cathode connected to the first electrical path and an anode connected to the second electrical path;
A detection circuit (46, 48) for detecting a voltage between terminals of the flying capacitor (44), an input for charging the battery voltage of one or more unit cells to the flying capacitor via the plurality of electrical paths. Capacitor voltage detecting means (40) including a side switch group (42);
An abnormality determining means (50a) for determining the presence or absence of an open abnormality of the conductive member,
The abnormality determining means is configured to charge the flying capacitor with a voltage equal to or higher than a predetermined reference voltage from the first electric path side through either the conductive member or the bypass path. The conductive member based on a potential difference at both ends of the bypass path or a voltage between terminals of the flying capacitor when the input side switch group is operated so that a discharging current of the flying capacitor flows to the second electric path side An abnormality detection device for determining whether or not there is an open abnormality.   The abnormality detection device according to claim 1, wherein the reference voltage is a breakdown voltage of the Zener diode. Applied to an assembled battery (10) formed by connecting a plurality of cell groups (CG1, CG2), which are series connection bodies in which a plurality of battery cells are connected in series, and provided between adjacent cell groups. An abnormality detection device for detecting an open abnormality of a member (SP),
A plurality of electric paths (L1) connected to both ends of each unit battery (BC1 to BC6) defined by either a single battery cell in the cell group or a predetermined number of battery cells connected in series To L10),
Among the plurality of electrical paths, the electrical path is provided between a pair of electrical paths (L5, L6) connected to both ends of the conductive member, and the high potential side from the low potential side electrical path (L5) in the pair of electrical paths. A current protection element (32) that allows only current flow to the electrical path (L6) of
Of the plurality of electrical paths, a first electrical path (L6) having a potential equal to or higher than the high potential side at both ends of the conductive member, and a second potential having a potential equal to or lower than the low potential side at both ends of the conductive member. A bypass path (70) for short-circuiting the electrical path (L5) of
A bypass capacitor (72) provided in the bypass path and connected between the first electrical path and the second electrical path;
A detection circuit (46, 48) for detecting a voltage between terminals of the flying capacitor (44), an input for charging the battery voltage of one or more unit cells to the flying capacitor via the plurality of electrical paths. Capacitor voltage detecting means (40) including a side switch group (42);
An abnormality determining means (50a) for determining the presence or absence of an open abnormality of the conductive member,
The abnormality determining means is configured to charge the flying capacitor with a voltage equal to or higher than a predetermined reference voltage from the first electric path side through either the conductive member or the bypass path. The conductive member based on a potential difference at both ends of the bypass path or a voltage between terminals of the flying capacitor when the input side switch group is operated so that a discharging current of the flying capacitor flows to the second electric path side An abnormality detection device for determining whether or not there is an open abnormality. Discharge switching means (34) for switching between an on state for discharging the bypass capacitor and an off state for stopping discharge of the bypass capacitor;
The discharge switching unit switches the bypass capacitor to the on state when the flying capacitor is charged, and switches the bypass capacitor to the off state when the flying capacitor is discharged. The abnormality detection device according to claim 3.   The abnormality determination means operates after the input side switch group is operated so that the discharge current of the Fline capacitor flows from the first electric path side to the second electric path side, and then the discharge current of the Fline capacitor 5. The presence or absence of an open abnormality of the conductive member is determined based on a detection value of the capacitor voltage detection means when a time longer than a time constant of a flowing discharge path has elapsed. The abnormality detection apparatus according to one. Comprising a potential difference detection means (30b) configured to detect a potential difference at both ends of the bypass path;
The abnormality determination means is configured to determine a time constant of a discharge path through which a discharge current of the capacitor flows after the input side switch group is operated so that a current flows from the first electric path side to the second electric path side. 5. The presence or absence of an open abnormality of the conductive member is determined based on a detection value of the potential difference voltage detection means before a longer time elapses. Anomaly detection device. A first capacitor (C32) provided between a pair of electrical paths (L5, L6) connected to both ends of the conductive member among the plurality of electrical paths;
Of the plurality of electrical paths, a second capacitor provided between a pair of electrical paths (L4, L5) connected to both ends of the unit battery (BC3) connected in series to a lower potential side than the conductive member. (C31),
A third capacitor provided between a pair of electrical paths (L6, L7) connected to both ends of the unit battery (BC4) connected in series to the higher potential side than the conductive member among the plurality of electrical paths. (C33),
After discharging the first capacitor, after discharging the first capacitor, the voltage between the terminals of the first capacitor detected, and after discharging the second and third capacitors, 2. Disconnection of a plurality of electrical paths connected to the first to third capacitors based on the magnitude of the difference in the voltage across the terminals of the first capacitor detected after stopping the discharge of the third capacitor A disconnection determining means for determining presence or absence,
The disconnection determination means is in a state in which a voltage equal to or higher than a predetermined reference voltage is charged with respect to the flying capacitor, from the first electric path side through either the conductive member or the bypass path. After the input side switch group is operated so that the discharge current of the flying capacitor flows to the second electric path side, and before determining the presence or absence of disconnection of the plurality of electric paths by the disconnection determination means, The abnormality detection apparatus according to claim 1, further comprising a discharge unit that discharges the first capacitor.   The abnormality detection device according to claim 7, wherein the discharging unit discharges the first capacitor by turning on a switch (SW32) provided in parallel with the first capacitor.   The abnormality detection device according to claim 7, wherein the discharging unit discharges the first capacitor by applying a voltage equal to or higher than a predetermined reference voltage to the flying capacitor to charge the flying capacitor.

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