JP2015079936A - Low-temperature manufacturing method of polycrystalline silicon thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low-temperature manufacturing method of a polycrystalline silicon thin-film transistor.SOLUTION: A low-temperature manufacturing method of a polycrystalline silicon thin-film transistor comprises the steps of: forming a polycrystalline silicon layer on a substrate; forming, on the polycrystalline silicon layer, a gate insulator layer having laminate structure of silicon oxide and silicon nitride, and a gate layer in turn; forming a patterned photoresist on the gate layer; removing parts of the silicon nitride and the gate layer which are not covered with the photoresist by performing plasma etching and reactive ion etching on the substrate; forming a gate foot and a gate by partially removing the gate layer; and forming a source/drain and a low-doped drain by removing the photoresist and performing high-concentration doping while using, as a mask, the gate and the gate foot. According to the manufacturing method of the present invention, the loss of silicon nitride when etching a gate layer and SiNx can be reduced.

Description

  The present invention relates to a technique in the field of thin film transistors, and more particularly, to a method for manufacturing a low temperature polysilicon thin film transistor (LTPS TFT).

In the LTPS process, the presence of a lightly doped drain (LDD) is very important for suppressing leakage current (Ioff). As one of the LDD manufacturing methods, a gate insulating layer having a stacked structure of silicon oxide and silicon nitride (SiO _x / SiN _x ) is formed, a gate layer is formed on the gate insulating layer, and then gate etching is performed by dry etching. That is, a SiN _x foot is formed.

1 to 4 show a TFT structure of a prior art LTPS process.
As shown in FIG. 1, before dry etching, a gate insulating layer 14 in which SiO _x and SiN _x are laminated is formed above the polysilicon layer 13. Thereafter, as shown in FIG. 2, the SiN _x of the gate layer 15 and the gate insulating layer 14 not covered with the photoresist PR was removed by physical etching or chemical etching. Subsequently, as shown in FIG. 3, the gate layer 15 was further etched to form a SiN _x foot 14a. Thereafter, the photoresist was removed and an LDD structure was formed by doping.

The prior art LTPS process shown in FIGS. 1 to 3 has the following problems. In other words, in the process of etching the SiN _x of the gate layer 15 and the gate insulating layer 14, physical etching is excessively performed, causing a loss of SiO _x of the gate insulating layer 14 (FIG. 4). As a result, the threshold voltage is shifted, the leakage current path is shortened, and the leakage current may increase. Note that unevenness may occur due to non-uniformity of SiO _x loss.

In order to solve the problems of the prior art as described above, the present invention provides an LTPS TFT manufacturing method capable of avoiding loss of SiO _x .

The present invention includes forming a polysilicon layer on a substrate;
Forming a gate insulating layer having a laminated structure of silicon oxide and silicon nitride, and a gate layer in order on the polysilicon layer;
Forming a patterned photoresist on the gate layer;
Removing the silicon nitride and the gate layer not covered by the photoresist by performing plasma etching and reactive ion etching on the substrate;
Forming a gate foot and a gate by partially removing the gate layer;
And a step of forming a source / drain and a low-doped drain by performing high-concentration doping using the gate and the gate foot as a mask, and providing a method of manufacturing an LTPS TFT.

According to the LTPS TFT manufacturing method of the present invention, in the step of etching the gate layer and SiN _x , two types of etching, that is, plasma etching (Plasma Etching, PE) and reactive ion etching (Reactive Ion Etching, RIE) are performed. While doing so, the power of RIE can be reduced. That is, by reducing the ratio of RIE in the etching step, the influence of physical etching can be reduced, and loss of SiO _x when the gate layer and SiN _x are etched can be avoided. Accordingly, it is possible to avoid disadvantages such as a threshold shift due to SiO _x loss and an increase in leakage current.

It is a figure which shows typically the TFT structure in the LTPS process of a prior art. It is a figure which shows typically the TFT structure in the LTPS process of a prior art. It is a figure which shows typically the TFT structure in the LTPS process of a prior art. It is a figure which shows typically the TFT structure in the LTPS process of a prior art. The flowchart of the Example of the manufacturing method of LTPS TFT of this invention is shown typically. It is sectional drawing which shows typically the TFT manufactured by the Example of the manufacturing method of LTPS TFT of this invention. It is sectional drawing which shows typically the TFT manufactured by the Example of the manufacturing method of LTPS TFT of this invention. It is sectional drawing which shows typically the TFT manufactured by the Example of the manufacturing method of LTPS TFT of this invention. It is sectional drawing which shows typically the TFT manufactured by the Example of the manufacturing method of LTPS TFT of this invention. It is sectional drawing which shows typically the TFT manufactured by the Example of the manufacturing method of LTPS TFT of this invention. It is sectional drawing which shows typically the TFT manufactured by the Example of the manufacturing method of LTPS TFT of this invention. Is a graph showing the relationship between the percentage number relative etching ratio of O _2.

  FIG. 5 schematically shows a flowchart of an embodiment of a method for producing an LTPS TFT of the present invention. 6 to 10 are cross-sectional views schematically showing TFTs manufactured by the embodiment of the LTPS TFT manufacturing method of the present invention.

  In step S101, a polysilicon layer 23 is formed on the substrate 21 as shown in FIG. This substrate is a glass substrate or other substrate applicable to a display. The polysilicon layer may include a channel portion 23a, a lightly doped drain formation portion 23b, and a source / drain formation portion 23c. The present invention is not particularly limited to the method for forming the polysilicon layer 23. For example, as a method of forming the polysilicon layer 23, after an amorphous silicon layer is formed on the substrate 21, excimer laser annealing or heat treatment is performed on the amorphous silicon layer so that the amorphous silicon layer becomes a polysilicon layer. It may be.

A buffer layer 22 may also be formed between the substrate 21 and the polysilicon layer 23. The buffer layer 22 may have a stacked structure formed of SiO _x and SiN _x .

In step S102, a gate insulating layer 24 having a stacked structure of SiO _x and SiN _x and a gate layer 25 are sequentially formed on the polysilicon layer 23 as shown in FIG. The material of the gate layer 25 may be a metal such as molybdenum (Mo), for example. In this step, the formation method of the gate insulating layer 24 and the gate layer 25 is not particularly limited, and for example, a chemical vapor deposition method, a sputtering method, a vapor deposition method, or the like may be used.

  In step S103, a patterned photoresist PR is formed on the gate layer 25 as shown in FIG. Specifically, after forming a photoresist PR layer on the gate layer 25, using the patterned mask, the photoresist PR layer is subjected to processing such as exposure and development by a photolithography technique, Thereby, a patterned photoresist PR is formed. The pattern of the photoresist PR is determined by the size of the gate to be formed and the size of the gate foot.

In step S104, as shown in FIG. 9, plasma etching and reactive ion etching are performed on the substrate as shown in FIG. 8, thereby removing SiN _x and the gate layer 25 that are not covered with the photoresist PR. . For example, this step may be performed in an apparatus (eg, an inductively coupled plasma apparatus) that can perform plasma etching and reactive ion etching simultaneously. In this process, ion bombardment can be reduced by reducing the power of reactive ion etching. Since the ion bombardment is reduced, the etching of SiO _{x in} the etching can be reduced, and the loss of SiO _x is reduced.

In step S104, the reactive gas introduced may be a mixed gas of sulfur fluoride (SF ₆ ) and oxygen (O ₂ ). Here, the ratio of oxygen is determined by the etching ratio of the film and the yield of the thin film transistor. FIG. 12 is a graph showing the relationship between the percentage number of O ₂ and the relative etching ratio. As can be seen from the figure, when the proportion of O ₂ is about 25%, the etching ratio of SiO _x is the largest. If the TFT yield is also taken into consideration in this figure, the ratio of oxygen to the mixed gas of SF ₆ and O ₂ can be determined appropriately. In principle, the TFT yield cannot be ignored in order to pursue only a high etching ratio, and both the etching ratio and the TFT yield must be considered.

Of course, other reactive gases such as carbon fluoride (CF ₄ ) may be used.
In step S104, the temperature used during etching can be set based on uniformity (a key point related to TFT quality). For example, etching may be performed at a temperature of about 60 ° C. or lower, and it is preferable to perform etching at room temperature (about 25 ° C.). Moreover, the pressure used at the time of an etching can be set based on the quantity and temperature of reactive gas.

In step S105, as shown in FIG. 10, the gate layer 25 is partially removed to form a gate foot and a gate 25a. The gas used in this step may be a mixed gas of chlorine gas (Cl ₂ ) and O ₂ .

  In step S106, as shown in FIG. 11, after removing the photoresist PR, high concentration doping is performed using the gate 25a and the gate foot 24a as a mask, thereby forming a source / drain and a lightly doped drain. Specifically, the source / drain is formed by performing high concentration doping so that the source / drain formation portion 23c not covered with the gate foot 24a is highly doped. On the other hand, the LLD forming portion 23b becomes a low-concentration doping region by the shielding action of the gate foot 24a.

  After step S106, contact lines that contact the source / drain, an insulating layer, and the like may be further formed. However, since these can be formed by a well-known technique, they are not described in detail in the present invention.

  The manufacturing method of the LTPS TFT of the present invention further includes a step of analyzing the tilt angle of the gate foot of the formed silicon thin film transistor (for example, analyzing by an analysis method of a scanning electron microscope (SEM)), a gate foot A step of determining a reactive ion etching power and a plasma etching power corresponding to the inclination angle of the substrate (specifically, determining a reactive ion etching power and a plasma etching power corresponding to a preferable gate foot inclination angle) And reactive ion etching and plasma etching using reactive ion etching power and plasma etching power corresponding to the inclination angle of the gate foot.

  In a TFT having an LDD structure, the smaller the gate foot inclination angle, that is, the gentler the gate foot, the better the electrical performance of the LDD. Conversely, the greater the gate foot inclination angle, that is, the steeper the gate foot, the worse the electrical performance of the LDD.

  In forming the LDD TFT, it is difficult to monitor the tilt angle of the gate foot in real time. Therefore, after the TFT is formed, the tilt angle of the formed gate foot can be analyzed by the SEM method, and the reactive ion etching power and the plasma etching power corresponding to the preferable gate foot tilt angle can be determined.

  Specifically, when the power of RIE is large, that is, when RIE and PE are simultaneously biased to RIE, the inclination angle of the gate foot becomes relatively large, that is, the gate foot becomes relatively steep. On the contrary, when the PE power is large, that is, when the PE is biased in the step of simultaneously etching with RIE and PE, the inclination angle of the gate foot becomes relatively small and the gate foot becomes relatively gentle.

  Thus, if analyzed by SEM method and it is determined that the formed gate foot tilt angle is greater than the preferred gate foot tilt angle, in subsequent manufacturing, by increasing PE power and decreasing RIE power, The gate foot formed after that becomes loose.

According to the LTPS TFT manufacturing method of the present invention, in the step of etching the gate layer and SiN _x , two types of etching of PE and RIE (for example, in an apparatus capable of performing two types of etching of PE and RIE, Etching may be performed) and the RIE power may be reduced. That is, by reducing the ratio of RIE in the etching process, the influence of physical etching can be reduced, and loss of SiO _x when the gate layer and SiN _x are etched can be avoided. Therefore, it is possible to avoid defects such as a threshold shift due to SiO _x loss, a decrease in leakage current path, and an increase in leakage current, and the reliability of the LTPS element can be improved.

  Further, according to the LTPS TFT manufacturing method of the present invention, the power of PE and RIE is determined by analyzing the tilt angle of the formed gate foot by the SEM analysis method. And by increasing the power of PE, the inclination angle of the gate foot is decreased, that is, the gate foot becomes gentle and an LDD having excellent electrical performance can be produced.

As described above, according to the LTPS TFT manufacturing method of the present invention, it is possible to form a SiN _x foot that meets the requirements so that the LDD performance can be maximized, and to solve a series of problems due to SiO _x loss. SiO _x loss can be avoided to avoid.

  6 to 10 of the present invention have been described mainly using a P-channel TFT as an example, but the TFT may be an N-channel TFT. Since the specific manufacturing process in that case is almost the same as that of the P-channel TFT, the description thereof is omitted here.

  Although the invention has been illustrated and described in detail, the foregoing description is illustrative and not restrictive. Therefore, it can be said that many modifications and embodiments are possible without departing from the scope of the present invention.

  21 substrate, 23 polysilicon layer, 23a channel part, 23b lightly doped drain forming part, 23c source / drain forming part.

Claims (6)

Forming a polysilicon layer on the substrate;
Forming a gate insulating layer having a laminated structure of silicon oxide and silicon nitride, and a gate layer in order on the polysilicon layer;
Forming a patterned photoresist on the gate layer;
Removing the silicon nitride and the gate layer not covered by the photoresist by performing plasma etching and reactive ion etching on the substrate;
Forming a gate foot and a gate by partially removing the gate layer;
And a step of forming a source / drain and a low-doped drain by performing high-concentration doping using the gate and the gate foot as a mask while removing the photoresist.   2. The method of manufacturing a low-temperature polysilicon thin film transistor according to claim 1, wherein a mixed gas of sulfur fluoride and oxygen is used as a reactive gas in a process of performing plasma etching and reactive ion etching on the substrate.   3. The method of manufacturing a low-temperature polysilicon thin film transistor according to claim 2, wherein the ratio of sulfur fluoride and oxygen is determined by an etching ratio and a yield of the thin film transistor.   2. The method of manufacturing a low-temperature polysilicon thin film transistor according to claim 1, wherein the temperature used in the process of etching the substrate is lower than 60.degree.   5. The method of manufacturing a low-temperature polysilicon thin film transistor according to claim 4, wherein the temperature used in the process of etching the substrate is 25.degree. Analyzing the tilt angle of the gate foot of the formed silicon thin film transistor;
Determining the reactive ion etching power and the plasma etching power corresponding to the gate foot tilt angle;
2. The low-temperature polysilicon thin film transistor according to claim 1, further comprising: performing reactive ion etching and plasma etching with reactive ion etching power and plasma etching power corresponding to the inclination angle of the gate foot. Production method.