JP2015076524A - Semiconductor chips and semiconductor device formed by stacking them - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize a power-supply voltage supplied to each circuit of semiconductor chips, in a stacked-type semiconductor device.SOLUTION: A semiconductor device is formed by stacking a plurality of semiconductor chips. The semiconductor chips are connected to one another by a through electrode. In each semiconductor chip, a through electrode region is disposed in its center, a peripheral circuit region is disposed outside the through electrode region, and a memory cell region is disposed further outside the peripheral circuit region. A first annular power-supply line connected to the through electrode is formed around the through electrode region. Any of peripheral circuits disposed in the peripheral circuit region are indirectly connected to the through electrode via the first annular power-supply line.

Description

  The present invention relates to a stacked semiconductor device configured by electrically connecting a plurality of semiconductor chips by through electrodes and the semiconductor chip.

  The storage capacity required for semiconductor devices such as DRAM (Dynamic Random Access Memory) is increasing year by year. In recent years, in order to satisfy this requirement, a method has been proposed in which a plurality of semiconductor chips (memory chips) are stacked and these are electrically connected via through electrodes provided on a silicon substrate (see Patent Document 1). ).

JP 2012-119368 A

  In a general stacked semiconductor device, a lowermost semiconductor chip is connected to an external power supply, and a power supply voltage is also supplied to an upper semiconductor chip through a through electrode. A power supply line is connected to the through electrode, and the internal circuit is supplied with a power supply voltage from the power supply line.

  When the through electrode is arranged at the center of the semiconductor chip, the voltage on the power supply line becomes unstable as the periphery of the semiconductor chip, in other words, the farther from the through electrode. Therefore, a plurality of power supply lines are connected to a plurality of through electrodes, and these power supply lines are connected to each other to construct a power supply network, thereby stabilizing the power supply voltage at the peripheral portion.

  However, it is expected that it will be difficult to construct a power supply network that can stably supply a power supply voltage as the operating frequency of the DRAM increases and the storage capacity increases (chip size increases).

  The semiconductor device according to the present invention includes a plurality of semiconductor chips connected to each other by a plurality of through electrodes. In each of the plurality of semiconductor chips, a through electrode region where a plurality of through electrodes are formed, and a circuit region surrounding the through electrode region are formed. A first annular power supply line connected to the plurality of through electrodes is formed at the boundary between the through electrode region and the circuit region. Any circuit formed in the circuit region is indirectly connected to the through electrode via the first annular power supply line.

  In the semiconductor chip according to the present invention, a through electrode region in which a plurality of through electrodes are formed, and a circuit region surrounding the through electrode region are formed. A first annular power supply line connected to the plurality of through electrodes is formed at the boundary between the through electrode region and the circuit region. Any circuit formed in the circuit region is indirectly connected to the through electrode via the first annular power supply line.

  According to the present invention, power quality can be improved in a stacked semiconductor device.

It is a typical top view of a semiconductor chip. It is sectional drawing of the penetration electrode periphery part of a semiconductor device. It is an expanded sectional view of the penetration electrode peripheral part of a semiconductor chip. It is a top view which shows the power network generally assumed. It is a top view which shows the power network in this embodiment. It is a surrounding enlarged view of a penetration electrode area. It is a schematic diagram which shows the connection relation of a 1st cyclic | annular power supply line, a penetration electrode, a power supply line, and each circuit. It is a figure which shows another wiring method of a 1st cyclic | annular power supply line. It is a top view which shows the power supply network at the time of forming the 2nd annular power supply line and the 3rd annular power supply line in addition to the 1st annular power supply line. It is a top view which shows the structure of a 1st cyclic | annular power supply line when supplying three or more types of power supply voltages. It is a top view which shows the connection relation of an evaluation pad and a 1st annular power supply line.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic plan view of the semiconductor chip 100. The semiconductor chip 100 is a so-called wide IO SDRAM (Synchronous Dynamic Random Access Memory), and includes four channels CH-A to CH-D that can operate independently of each other. A plurality of semiconductor chips 100 are stacked to form a stacked semiconductor device 200 (see FIG. 2).

  Four through electrode regions 106 a to 106 d are provided in the center of one semiconductor chip 100. When these are collectively referred to or not particularly distinguished, they are referred to as through electrode regions 106. The same applies to a memory cell region 102, a peripheral circuit region 104, and the like which will be described later. Four peripheral circuit regions 104a to 104d are formed outside the four through electrode regions 106a to 106d. Further, four memory cell regions 102a to 102d are formed outside thereof. Thus, the memory cell region 102, the peripheral circuit region 104, and the through electrode region 106 are formed for each channel CH. A “circuit area” is formed by the memory cell area 102 and the peripheral circuit area 104.

  In the memory cell region 102, as is known, a memory cell to be accessed is designated by the row decoder XDEC and the column decoder YDEC. A plurality of through electrodes (Through Silicon Via or Through Substrate Via) are formed in the through electrode region 106. The plurality of semiconductor chips 100 are electrically connected by the through electrode. Some penetrating electrodes serve as signal lines, while others serve as power supply lines. In the following, a description will be given of a through electrode serving as a power line. The peripheral circuit region 104 is a region where various control circuits that operate based on the power supply voltage supplied from the through electrode region 106 are formed. Specifically, a data input / output circuit, a command decoder, an address decoder, a DLL (Delay Locked Loop) circuit, a timing generator, and the like.

  Further, an evaluation pad region 108 is formed along the X direction at the center of the semiconductor chip 100. In the evaluation pad area 108, a plurality of evaluation pads 110 (see FIG. 4) are arranged. The evaluation pad 110 is an electrode for contacting a tester probe when the semiconductor chip 100 is subjected to an operation test in a wafer state. In order to secure structural strength when the semiconductor device 200 is stacked, support bumps made of dummy through electrodes may be provided.

  FIG. 2 is a cross-sectional view of the periphery of the through electrode of the semiconductor device 200. In the semiconductor device 200 shown in FIG. 2, four semiconductor chips 100-1 to 100-4 are stacked. The through silicon vias TSV formed at the center of each semiconductor chip 100 are connected in the vertical direction. An external terminal 112 is connected to the lowermost semiconductor chip 100-1, and a power supply voltage is supplied from the external terminal 112 to each semiconductor chip 100 through a through electrode. Further, a power supply line 114 is connected to each through electrode TSV, and a power supply voltage is supplied to each internal circuit of the semiconductor chip 100 via the power supply line 114.

  FIG. 3 is an enlarged cross-sectional view of the periphery of the through electrode of the semiconductor chip 100. As shown in FIG. 3, the through electrode penetrates the silicon substrate 122 and the wiring layer 124. The back end 132 on the silicon substrate 122 side of the through electrode is covered with the back bump 128, and the front end 130 on the front side of the wiring layer 124 is covered with the surface bump 126. The back bump 128 is an electrode in contact with the front bump 126 of the underlying semiconductor chip 100. The front bump 126 is an electrode in contact with the rear bump 128 of the upper semiconductor chip 100.

  The wiring layer 124 includes a first wiring layer 140, a second wiring layer 138, a third wiring layer 136, and a fourth wiring layer 134. The first wiring layer 140 and the second wiring layer 138 are connected by the via conductor VIA3, the second wiring layer 138 and the third wiring layer 136 are connected by the via conductor VIA2, and the third wiring layer 136 and the fourth wiring layer 134 are Connected by via conductor VIA1. These wiring layers and via conductors are covered with an oxide film. The power supply voltage supplied to the through electrode is supplied to various circuits formed in the silicon substrate 122 and the wiring layer 124 via the wiring layer and via conductor.

  FIG. 4 is a plan view showing a generally assumed power supply network. Here, it is assumed that two types of power supply voltages, VDD and VSS, are supplied from the through electrode region 106. In the through electrode region 106, the power supply line 114D is connected to the through electrode that supplies the power supply voltage VDD, and the power supply line 114S is connected to the through electrode that supplies the power supply voltage VSS. The power supply lines 114D and 114S are both drawn out from the through electrode in the y direction.

  Various circuits in the peripheral circuit region 104 and the memory cell region 102 need to supply a desired power supply voltage regardless of the layout position. However, in the case of the circuit A and the circuit B formed in the peripheral circuit region 104a, the lengths of paths until the power supply voltage is supplied from the through electrode are different. Therefore, the circuit A is caused by the difference in the parasitic resistance component and the parasitic capacitance component. , B are slightly different in stability of the power supply voltages VDD, VSS. Therefore, the power supply lines 114D and 114S are connected in a mesh shape in the xy direction to strengthen the power supply and stabilize the power supply voltage. In this way, channel power supply networks 116a to 116d are configured corresponding to the channels CH-A to CH-D, respectively.

  In order to further stabilize the power supply voltage supply to each channel power supply network 116, it is desirable to connect the channel power supply networks 116a to 116d to each other. However, since the evaluation pads 110, circuits, signal lines, support bumps, and the like are formed in the boundary regions 120a to 120d between the channel power supply network 116 and the channel power supply network 116, the connectable places are limited. Further, when the channel power supply networks 116 are connected to each other while avoiding various circuit elements in the boundary region 120, the layout of the power supply lines 114 tends to be complicated.

  As the operating frequency of the DRAM increases in the future, noise superimposed on the power supply line 114 increases. Further, when the memory cell region 102 is enlarged as the storage capacity is increased, the channel power supply network 116 becomes larger, and there is a concern that it is difficult to suppress voltage fluctuation at a position far from the through electrode.

  FIG. 5 is a plan view showing a power supply network in the present embodiment. FIG. 6 is an enlarged view around the through electrode region 106. In the present embodiment, the first annular power supply lines 142D and 142S are formed so as to surround the through electrode region 106. These are collectively referred to as the first annular power supply line 142. The first annular power supply line 142 is formed at the boundary between the through electrode region 106 and the peripheral circuit region 104. The first annular power supply line 142 is a kind of power supply line to be supplied with a particularly stable power supply voltage from the through electrode.

  The four channel power supply networks 116a to 116d are all connected to the first annular power supply line 142 at a plurality of locations. The channel power supply networks 116 are connected to each other via a first annular power supply line 142. With such a connection method, fluctuations in the power supply voltage supplied to a circuit far from the through electrode region 106 are suppressed.

  In addition, since the channel power supply network 116 can be connected anywhere on the first annular power supply line 142, the connection between the channel power supply network 116 and the first annular power supply line 142 can be made strong and reliable. Of course, as shown in FIG. 5, the channel power supply networks 116 may or may not be connected in the boundary region 120. The first annular power supply line 142 may be formed in any one layer among the first wiring layer 140 to the fourth wiring layer 134, or may be formed in a plurality of layers. Further, a mesh-like power line 114 (first power line) may be formed inside the first annular power line 142. With such a mesh-like power supply line 114, the power supply voltage of the first annular power supply line 142 can be further stabilized.

  FIG. 7 is a schematic diagram showing the connection relationship between the first annular power supply line 142, the through electrode 144, the power supply line 114, and each circuit. As shown in FIGS. 5 and 6, the first annular power supply line 142 is formed around the through electrode regions 106 a to 106 d. The first annular power supply line 142 is formed at the boundary between the peripheral circuit region 104 and the through electrode region 106, all the through electrodes are inside the first annular power supply line 142, and all the peripheral circuits in the peripheral circuit region 104 are in the first annular shape. It is outside the power line 142.

  The power supply line 114-1 led out in the y direction from the through electrode 144 formed in the through electrode region 106 a is directly connected to the through electrode 144. Here, “direct connection” refers to connection to the target power supply line 114 without being connected to another power supply line 114 or a circuit after the power supply line 114 is drawn in a certain direction. “Indirect connection” means a connection method that is not a direct connection.

  The through electrode 144 is directly connected to the first annular power supply line 142 at the shortest distance. Further, the plurality of through electrodes 144 are connected at a plurality of locations of the first annular power supply line 142. For this reason, the power supply voltage supplied to the first annular power supply line 142 becomes stable. As shown in FIGS. 5 and 6, the first annular power supply line 142 is connected by a mesh-like power supply line 114 (first power supply line) on the inside thereof, so that the power supply of the first annular power supply line 142 is provided. The voltage is further stabilized. Substantially, a stable power supply voltage almost equivalent to the through electrode 144 is supplied to the first annular power supply line 142. Furthermore, in order to stabilize the power supply voltage of the first annular power supply line 142, it is desirable to make the cross-sectional area of the first annular power supply line 142 larger than the cross-sectional areas of the other power supply lines 114 to reduce the internal resistance.

  A plurality of power supply lines 114 (second power supply lines) extend in the y direction outside the first annular power supply line 142. In FIG. 7, the circuit C is directly connected to the first annular power supply line 142 and the power supply line 114-2. The circuit B is connected to the power supply line 114-3 (second power supply line) through the power supply line 114-5. The circuit A is connected to the power supply line 114-3 (second power supply line) via the power supply line 114-6. That is, the circuits A and B are indirectly connected to the first annular power supply line 142, and the circuit C is directly connected to the first annular power supply line 142, but both circuits are first connected to the through electrode 144. They are indirectly connected via an annular power line 142.

  In summary, the control circuit in the peripheral circuit region 104 may be directly connected to the first annular power supply line 142 or indirectly connected to the first annular power supply line 142, but all the circuits are the first through electrodes 144. They are indirectly connected via an annular power line 142. Each circuit in the memory cell region 102 is also indirectly connected to the through electrode 144 via the first annular power supply line 142. In the present embodiment, the supply of the power supply voltage to all the circuits of the semiconductor chip 100 is stabilized by stabilizing the power supply voltage of the first annular power supply line 142 that supplies the power supply voltage to all the circuits.

  FIG. 8 is a diagram illustrating another wiring method for the first annular power supply line 142. In FIG. 5, the four through electrode regions 106 are surrounded by one first annular power supply line 142, but the first annular power supply line 142 need not surround all the through electrode regions 106. For example, as shown in FIG. 8, the through electrode region 106 is formed like a first annular power supply line 142-1 surrounding the through electrode regions 106a and 106d and a first annular power supply line 142-2 surrounding the through electrode regions 106b and 106c. You can surround them two by two. Alternatively, the first annular power supply line 142-1 may surround the through electrode regions 106a and 106b, and the first annular power supply line 142-2 may surround the through electrode regions 106c and 106d.

  FIG. 9 is a plan view showing a power supply network when a second annular power supply line 146 and a third annular power supply line 148 are formed in addition to the first annular power supply line 142. In FIG. 9, the second annular power supply line 146a is formed around the memory cell region 102a and the peripheral circuit region 104a of the channel CH-A. Inside the second annular power supply line 146a, a power supply line 114 (third power supply line) is formed in a mesh shape, thereby forming a channel power supply network 116a. The same applies to the other channels CH-B to CH-D.

  Similarly to the first annular power supply line 142, the second annular power supply line 146 may be formed of a conductive wire thicker than the through electrode 144. The first annular power supply line 142 and the second annular power supply line 146 are directly connected at a plurality of locations. Therefore, the power supply voltage is supplied to the second annular power supply line 146 in a uniform and stable manner similarly to the first annular power supply line 142. The voltage of the second annular power supply line 146 is also stabilized in the mesh wiring (third power supply line) inside the second annular power supply line 146. Various circuits formed in the memory cell region 102 and the peripheral circuit region 104 are directly or indirectly connected to the second annular power supply line 146.

  Further, the third annular power supply lines 148a to 148d may be similarly formed in the boundary regions 120a to 120d. The second annular power supply line 146 is connected to the third annular power supply line 148 at one or more locations. The third annular power supply line 148 is preferably formed so as to avoid various circuit elements such as the evaluation pad 110 and the support bump. Further, it is preferable that the third annular power supply line 148 is also connected to the first annular power supply line 142. According to the configuration shown in FIG. 9, a stable power supply voltage can be supplied to the first annular power supply line 142, the second annular power supply line 146, and the third annular power supply line 148.

  FIG. 10 is a plan view showing the configuration of the first annular power supply line 142 when three or more types of power supply voltages are supplied. In FIG. 5, the first annular power supply line 142 is doubled corresponding to the power supply voltages VDD and VSS, but the concept when supplying three or more kinds of power supply voltages is the same. In FIG. 10, the power supply voltage VSSQ is supplied to the first annular power supply line 142SQ, the power supply voltage VDDQ is supplied to the first annular power supply line 142DQ, and the power supply voltage VSS for a specific application is supplied to the first annular power supply line 142SS. The power supply voltage VSS for a specific application is a power supply voltage that is supplied by branching from a through electrode of the normal power supply voltage VSS to another path as a noise countermeasure, and is used for, for example, a sense amplifier.

  FIG. 11 is a plan view showing the connection relationship between the evaluation pad 110 and the first annular power supply line 142. During the operation test of the semiconductor chip 100, a test power supply voltage is supplied from the evaluation pad 110. On the other hand, during normal operation, the power supply voltage is supplied from the through electrode 144. As described above, the evaluation pad 110 is an electrode for contacting a tester probe when the semiconductor chip 100 is subjected to an operation test in a wafer state. For this reason, the evaluation pad 110 is not used after the test is completed and shipped.

  In the case of the configuration shown in FIG. 4, the connection conditions are greatly different between when the power supply voltage is supplied from the evaluation pad 110 to the circuits A and B and when the power supply voltage is supplied from the through electrode 144. For example, since the circuit A is close to the evaluation pad 110 but far from the through electrode 144, the condition of the power supply voltage that is actually supplied may differ between the test and the normal operation.

  On the other hand, in FIG. 11, all the evaluation pads 110 are directly connected to the first annular power supply line 142. This is the same connection method as the through electrode 144. All the evaluation pads 110 may be formed inside the first annular power supply line 142. The circuits A and B are supplied with the power supply voltage from the first annular power supply line 142 in both the test and the normal operation. Since the voltage of the first annular power supply line 142 is stable, the conditions of the power supply voltage supplied to the circuit during the test and the normal operation can be matched.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 100 Semiconductor chip 102 Memory cell area 104 Peripheral circuit area 106 Through electrode area 108 Evaluation pad area 110 Evaluation pad 112 External terminal 114 Power supply line 116 Channel power supply network 118 Circuit 120 Boundary area 122 Silicon substrate 124 Wiring layer 126 Surface bump 128 Back surface bump 130 Front end 132 Back end 134 Fourth wiring layer 136 Third wiring layer 138 Second wiring layer 140 First wiring layer 142 First annular power supply line 144 Through electrode 146 Second annular power supply line 148 Third annular power supply line 200 Semiconductor apparatus

Claims (13)

A plurality of semiconductor chips connected to each other by a plurality of through electrodes,
In each of the plurality of semiconductor chips, a through electrode region in which the plurality of through electrodes are formed, and a circuit region surrounding the through electrode region are formed,
A first annular power line connected to the plurality of through electrodes is formed at a boundary between the through electrode region and the circuit region,
Any circuit formed in the circuit region is indirectly connected to the through electrode via the first annular power supply line.   2. The semiconductor device according to claim 1, wherein each of the plurality of through electrodes is directly connected to the first annular power supply line.   3. The semiconductor device according to claim 1, wherein a memory cell array and a control circuit for controlling the memory cell array are formed in the circuit area.   4. The semiconductor device according to claim 1, wherein the first power supply line is arranged in a mesh shape inside the first annular power supply line. 5. A plurality of power supply voltages are supplied to the plurality of through electrodes formed in the through electrode region,
5. The semiconductor device according to claim 1, wherein a plurality of the first annular power supply lines are formed around the through electrode region corresponding to the plurality of power supply voltages. 6. Outside the first annular power supply line, a second power supply line extends from the first annular power supply line,
6. The semiconductor device according to claim 1, wherein all or part of the circuit is indirectly connected to the first annular power supply line via the second power supply line. .   The semiconductor device according to claim 6, wherein a cross-sectional area of the first annular power supply line is larger than a cross-sectional area of the second power supply line. A plurality of through electrode regions are formed in the center of the semiconductor chip,
The semiconductor device according to claim 1, wherein the first annular power supply line is formed around two or more through electrode regions. In the center of the semiconductor chip, a plurality of through electrode regions corresponding to a plurality of channels, a plurality of the circuit regions are formed,
9. The semiconductor device according to claim 1, wherein a second annular power supply line is formed around the circuit region corresponding to the same channel. The second annular power line is connected to the first annular power line;
10. The semiconductor device according to claim 9, wherein any of the circuits is indirectly connected to the first annular power supply line via the second annular power supply line.   11. The semiconductor device according to claim 9, wherein a third power supply line is disposed in a mesh shape inside the second annular power supply line. 11. A plurality of evaluation pads are formed on the semiconductor chip,
12. The semiconductor device according to claim 1, wherein each of the plurality of evaluation pads is directly connected to the first power supply ring line. A through electrode region in which a plurality of through electrodes are formed, a circuit region surrounding the through electrode region is formed,
A first annular power line connected to the plurality of through electrodes is formed at a boundary between the through electrode region and the circuit region,
Any of the circuits formed in the circuit region is indirectly connected to the through electrode via the first annular power supply line.

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