JP2015051305A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of having a RAM clear function and an error cancel function while contributing to cost reduction.SOLUTION: An operation switch 860a has a RAM clear function of outputting a RAM clear signal for deleting information related to a game stored in a main control incorporation RAM to a main control board 4100 and outputting a RWMCLR signal to a put-out control MPU 4120a as a RAM clear signal for deleting information related to putting-out stored in a put-out control incorporation RAM, when the operation switch is operated within a predetermined period from power source supply; and also an error cancel function of outputting a RWMCLR signal to the put-out control MPU 4120a without outputting the signal to the main control board 4100 as an error cancel signal for canceling an error that has occurred concerning a prize ball device 740, when the operation switch is operated after a predetermined period elapses after power source supply.

Description

  The present invention relates to a gaming machine.

  Conventionally, a RAM clear switch for initializing information stored in the RAM of the game control device and the RAM of the payout control device is provided in the power supply device, and when an error occurs in the payout control device, the game store There has been proposed a gaming machine in which an error release switch for canceling an error state is input to a payout control device when a store clerk or the like eliminates the cause of the error that has occurred (for example, Patent Document 1). In the gaming machine described in Patent Document 1, the RAM or the like of the game control device is initialized by operating the RAM clear switch when the power is turned on, and an error occurs in the payout control device after the power is turned on. When the error is resolved, an error cancel switch is operated to cancel the error state.

JP 2012-210397 A (paragraphs [0090], [0091], and [0098] to [0100])

  By the way, in the gaming machine described in Patent Document 1, the operation time of the RAM clear switch is limited to when the power is turned on, whereas the operation time of the error release switch causes an error in the payout control device after the power is turned on. And when the cause was solved. Unlike the error release switch, it is difficult to contribute to cost reduction if a RAM clear switch is provided in the gaming machine that has a limited operation timing when the power is turned on. However, since the RAM clear function by operating the RAM clear switch and the error cancel function by operating the error cancel switch are important functions in the gaming machine, it is necessary to provide the RAM clear function and the error cancel function in the gaming machine.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a gaming machine capable of providing a RAM clear function and an error canceling function while contributing to cost reduction. .

  Effective solutions for achieving the above-described object will be described below. In addition, the effect | action etc. are demonstrated as needed. In addition, for easy understanding, the corresponding configuration in the embodiment of the invention is also shown as appropriate, but is not limited at all.

(Solution 1)
A game control microprocessor is mounted that controls the progress of the game based on the fact that the game ball launched by the ball striking device launches toward the game area defined on the game board and enters the start area provided in the game area. A game control board, and a payout control board on which a payout control microprocessor for controlling payout of a game ball by the payout device based on a payout command from the game control board is mounted. The control microprocessor includes a game control RAM capable of storing at least information relating to a game even after power-off, and the payout control microprocessor can store information relating to payout at least even after power-off. With a payout control RAM, if operated within a predetermined period from power-on, A RAM clear signal for erasing information related to the game stored in the game control RAM and information related to the payout stored in the payout control RAM is output to the game control microprocessor and the payout control microprocessor, respectively. When the RAM clear function is operated after a predetermined period of time has elapsed since the power is turned on, an error cancel signal for canceling an error generated with respect to the payout device is not output to the game control microprocessor. A gaming machine comprising an operation switch having an error canceling function for outputting to a payout control microprocessor.

  This gaming machine includes a game control board and a payout control board. The game control board is a game control micro that controls the progress of the game based on the fact that the game ball launched by the ball striking device is invaded into the start area provided in the game area toward the game area defined on the game board. A processor is implemented. The payout control board is mounted with a payout control microprocessor that controls payout of game balls by the payout device based on a payout command from the game control board.

  The game control microprocessor includes at least a game control RAM. The game control RAM can store information related to the game even after the power is turned off.

  The payout control microprocessor includes at least a payout control RAM. The payout control RAM can store information relating to payout even after the power is shut off.

  The gaming machine further includes an operation switch. When the operation switch is operated within a predetermined period from when the power is turned on, a RAM clear signal for erasing information relating to the game stored in the game control RAM and information relating to the payout stored in the payout control RAM RAM clear function for outputting to the game control microprocessor and the payout control microprocessor, and an error release signal for releasing an error that has occurred with respect to the payout device when operated after a predetermined period has elapsed since the power was turned on. And an error canceling function for outputting to the payout control microprocessor without outputting to the game control microprocessor.

  As described above, when the operation switch is operated within a predetermined period from when the power is turned on, the game-related information stored in the game control RAM and the payout information stored in the payout control RAM are erased. A RAM clear function for outputting the RAM clear signal to the game control microprocessor and the payout control microprocessor, and an error generated with respect to the payout device when it is operated after a predetermined period has elapsed since the power was turned on. The error clear function that outputs the error cancel signal to the payout control microprocessor without outputting it to the game control microprocessor is combined with the RAM clear function and the error cancel function by an operation with one operation switch. Two different functions can be provided in each gaming machine. Therefore, a RAM clear function and an error cancel function can be provided while contributing to cost reduction.

  In the present embodiment, for example, the game board 4 in FIG. 8 corresponds to the game board, the game area 1100 in FIG. 8 corresponds to the game area, the ball hitting device 650 in FIG. 5 corresponds to the ball hitting device, and FIG. The upper start port 2101 and the lower start port 2102 correspond to the start region, the main control MPU 4100a in FIG. 11 corresponds to the game control microprocessor, the main control board 4100 in FIG. 11 corresponds to the game control board, and FIG. The award ball commands in a) and (b) correspond to the payout command, the prize ball device 740 in FIG. 5 corresponds to the payout device, the payout control MPU 4120a in FIG. 12 corresponds to the payout control microprocessor, and the payout in FIG. The control board 4110 corresponds to the payout control board, the pachinko gaming machine 1 in FIG. 1 corresponds to the gaming machine, and the RAM (main control built-in RAM) built in the main control MPU 4100a in FIG. 12 corresponds to the RAM (payout control built-in RAM) incorporated in the payout control MPU 4120a in FIG. 12, and the determination process in step S16 in the main control side power-on process in FIG. 32 is performed from when the power is turned on. The period (or the period during which the determination process of step S512 in the payout control unit power-on process in FIG. 35 is performed from the time of power-on) corresponds to a predetermined period from the time of power-on, and is input to the main control MPU 4100a in FIG. 12 and the RWMCLR signal input to the payout control MPU 4120a in FIG. 24 correspond to the RAM clear signal, the RWMCLR signal input to the payout control MPU 4120a in FIG. The switch 860a corresponds to an operation switch.

  In the gaming machine of the present invention, a RAM clear function and an error cancel function can be provided while contributing to cost reduction.

It is a perspective view which shows the state which open | released the main body frame with respect to the outer frame of a pachinko gaming machine, and opened the door frame with respect to the main body frame. It is a front view of a pachinko gaming machine. It is a rear view of a pachinko gaming machine. It is a front perspective view of an outer frame. It is a front perspective view of a main body frame. It is a back surface perspective view of the board | substrate unit in a main body frame. It is a perspective view of a door frame. It is a front view of a game board. It is the disassembled perspective view which decomposed | disassembled the game board of FIG. 8 and was seen from the front. It is a front view which expands and shows the function display unit in a game board in the state where it attached to the pachinko game machine. It is a block diagram of a main control board, a payout control board, and a peripheral control board. FIG. 12 is a block diagram showing a continuation of FIG. 11. It is the schematic of the various detection signals input / output to lending device connection terminal boards, such as a game ball which relays the electrical connection of the payout control board which comprises a main board, CR unit, and a frequency display board. FIG. 12 is a block diagram showing a continuation of FIG. 11. It is a block diagram which shows the outline of peripheral control MPU. It is a block diagram around VDP with a built-in sound source in the liquid crystal and the sound control unit. It is a block diagram which shows the power supply system of a pachinko gaming machine. FIG. 18 is a block diagram illustrating the continuation of FIG. 17. It is a circuit diagram which shows the circuit of a main control board. It is a circuit diagram which shows a power failure monitoring circuit. It is a circuit diagram which shows the interface circuit for communication between the board | substrates of a main control board and a peripheral control board. It is a circuit diagram which shows the circuit etc. of a payout control part. It is a circuit diagram which shows the payout control input circuit. FIG. 24 is a circuit diagram illustrating a continuation of FIG. 23. It is a circuit diagram which shows a payout motor drive circuit. It is a circuit diagram which shows CR unit input / output circuit. It is an input / output diagram showing various input / output signals to / from the main control board and various output signals to the external terminal board. It is a table which shows an example of the various commands transmitted to the payout control board from the main control board. It is a table which shows an example of the various commands transmitted to a peripheral control board from a main control board. 30 is a table showing a continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 29. It is a table which shows an example of the various commands from the payout control board which a main control board receives. It is a flowchart which shows an example of the main control side power-on process. FIG. 33 is a flowchart showing a continuation of main-control-side power-on processing in FIG. 32. FIG. It is a flowchart which shows an example of the main control side timer interruption process. It is a flowchart which shows an example of the process at the time of power-on of a payout control part. FIG. 36 is a flowchart showing a continuation of the power-on process of the payout control unit in FIG. 35. FIG. 37 is a flowchart showing a continuation of the payout control unit power-on process following FIG. 36. It is a flowchart which shows an example of a payout control part timer interruption process. It is a flowchart which shows an example of a rotation angle switch log | history production process. It is a flowchart which shows an example of a sprocket fixed position determination skip process. It is a flowchart which shows an example of a spherical collision determination process. It is a flowchart which shows an example of the prize ball stock number addition process for prize balls. It is a flowchart which shows an example of the number-of-use prize ball stock number addition process. It is a flowchart which shows an example of a stock monitoring process. It is a flowchart which shows an example of a pay-out ball engagement operation determination setting process. It is a flowchart which shows an example of a payout setting process. It is a flowchart which shows an example of a sphere ball movement setting process. It is a flowchart which shows an example of a retry operation | movement monitoring process. It is a flowchart which shows an example of a mismatch counter reset determination process. It is a flowchart which shows an example of an error cancellation operation determination process. It is a timing chart which shows the signal process (a) at the time of paying-out operation by ball lending, and the input signal confirmation process (a) from CR unit. It is a flowchart which shows an example of a peripheral control part power-on process. It is a flowchart which shows an example of the peripheral control part V blank interruption process. It is a flowchart which shows an example of a peripheral control part 1ms timer interruption process. It is a flowchart which shows an example of a peripheral control part command reception interruption process. It is a flowchart which shows an example of a peripheral control part power failure warning signal interruption process.

[1. Overall configuration of pachinko machine]
Hereinafter, a pachinko gaming machine as a gaming machine of the present invention will be described with reference to the drawings. First, the entire pachinko gaming machine according to the embodiment will be described with reference to FIGS. FIG. 1 is a perspective view showing a state in which a main body frame is opened with respect to an outer frame of the pachinko gaming machine according to the embodiment and a door frame is opened with respect to the main body frame, and FIG. 2 is a front view of the pachinko gaming machine. FIG. 3 is a rear view of the pachinko gaming machine.

  As shown in FIG. 1 to FIG. 3, the pachinko gaming machine 1 includes an outer frame 2 installed in an island facility (not shown) of a game hall, and a box that is pivotally supported by the outer frame 2 so as to be opened and closed and opened on the front side. A game board 4 having a frame-shaped main body frame 3, a game area 1100 in which a game ball as a game medium is inserted and fixed to the main body frame 3 from the front side, and the front face of the main body frame 3 and the game board 4 are on the player side And a door frame 5 pivotally supported so as to be openable and closable with respect to the main body frame 3. The door frame 5 of the pachinko gaming machine 1 stores a gaming window 101 formed so that the gaming area 1100 of the gaming board 4 can be viewed from the player side, and a gaming ball disposed below the gaming window 101. A dish-shaped upper plate 301 and lower plate 302 (see FIG. 7), and a handle device 500 that a player operates to drive game balls stored in the upper plate 301 into the game area 1100 of the game board 4 It is equipped with.

  Also, in the pachinko gaming machine 1, the outer frame 2, the main body frame 3, and the door frame 5 are each formed in a vertically long rectangular shape extending in the vertical direction in the front view, and the horizontal widths in the horizontal directions are substantially the same. The size of the main body frame 3 and the door frame 5 is slightly shorter than that of the outer frame 2. A decorative cover 23 is attached to the front surface of the outer frame 2 at a position below the main body frame 3 and the door frame 5, and the front surface of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. The outer frame 2, the main body frame 3, and the door frame 5 are arranged so that their upper ends are substantially aligned, and the main body frame 3 and the door frame 5 can be rotated at a position on the left end front side of the outer frame 2. The right end of the main body frame 3 and the door frame 5 moves to the front side with respect to the outer frame 2 so as to be in an open state.

  Further, the pachinko gaming machine 1 has a game area 1100 into which a game ball is driven through a substantially circular game window 101 in front view, and projects forward to the lower side of the game window 101. In this way, two upper plates 301 and lower plates 302 are arranged vertically. In addition, a handle device 500 for the player to operate is disposed at the lower right corner of the front surface of the door frame 5, and the player holds the handle device 500 in a state where game balls are stored in the upper plate 301. When the rotation operation is performed, the game ball in the upper plate 301 is driven into the game area 1100 of the game board 4 with a hitting strength corresponding to the rotation angle, and a game can be played.

  The game window 101 of the door frame 5 is closed by a transparent glass unit 590 so that the player can visually recognize the inside of the game area 1100, but the player inserts a hand or the like into the game area 1100 to play the game. The game balls and obstacle nails in the area 1100, various winning holes and bonuses cannot be touched.

[2. Overall structure of outer frame]
Next, the outer frame 2 installed in the island facility of the game hall will be described with reference to FIG. FIG. 4 is a front perspective view of the outer frame. As shown in FIG. 4, the outer frame 2 includes upper and lower upper and lower frame plates 10 and 11 that extend in the horizontal direction, left and right side frame plates 12 and 13 that extend in the vertical (vertical) direction, and respective frame plates. And four connecting members 14 that connect the end portions of 10, 11, 12, and 13 and connecting the frame plates 10, 11, 12, and 13 with the connecting member 14 to form a vertically long rectangular shape ( (Square shape). The upper frame plate 10 and the lower frame plate 11 in the outer frame 2 are formed of a solid material (for example, wood, plywood, etc.) having a predetermined thickness. Note that an upper support fitting 20 described later is attached to the upper surface and the front surface of the left end portion of the upper frame plate 10.

  On the other hand, the side frame plates 12 and 13 are light metal molds (for example, aluminum alloys) having a constant cross-sectional shape. In addition, a plurality of grooves extending in the vertical direction are formed on the outer side surface and the inner side surface of the side frame plates 12 and 13, and work is performed when the pachinko gaming machine 1 is installed in the pachinko island facility of the game hall. The pachinko gaming machine 1 can be easily held by a person's finger and the design of the appearance can be enhanced.

  The outer frame 2 is arranged so as to face the upper support fitting 20 fixed to the upper surface of the left end of the upper frame plate 10 and the lower support plate 20 and is fixed to a predetermined position inside the lower portion of the left side frame plate 12. A support bracket 21, a reinforcement bracket 22 arranged to support the lower surface of the lower support bracket 21 and fixed to connect the left and right side frame plates 12 and 13, and a decorative cover fixed to the front surface of the reinforcement bracket 22 23. The upper support fitting 20 and the lower support fitting 21 are for pivotally supporting the main body frame 3 and the door frame 5 so as to be opened and closed. A shaft support pin 633 (see FIG. 5) of an upper shaft support bracket 630 in the main body frame 3 to be described later is detachably engaged with the support hole 20c in the upper support bracket 20. A main body frame shaft support formed on a main body frame shaft support bracket 644 of the main body frame 3, which will be described later, is inserted into the support protrusion 21d of the lower support bracket 21. After the main body frame 3 is inserted into the support hole of the main body frame shaft support bracket 644, the main body frame 3 can be simply mounted by locking the shaft support pin 633 of the upper shaft support bracket 630 of the main body frame 3 in the support hole 20c. It can be pivotally supported so that it can be opened and closed.

  Further, the outer frame 2 has two closing plates 24 and 25 (see FIG. 1) attached and fixed inside the right side frame plate 13 with a predetermined distance apart in the vertical direction. These closing plates 24 and 25 are formed in a substantially L shape in plan view. The closing plates 24 and 25 are hook portions 1054 and 1065 (see FIG. 1) of the lock device 1000 that are attached along the open side of the main body frame 3 when the main body frame 3 is closed with respect to the outer frame 2. As will be described in detail later, the hooks 1054 and 1065 are disengaged from the closing plates 24 and 25 by inserting a key into the cylinder lock 1010 of the locking device 1000 and turning it to one side. Thus, the main body frame 3 can be opened with respect to the outer frame 2.

[3. Overall structure of main frame]
Next, the main body frame 3 provided on the front side of the outer frame 2 so as to be freely opened and closed will be described with reference to FIGS. FIG. 5 is a front perspective view of the main body frame, and FIG. 6 is a rear perspective view of the substrate unit in the main body frame. As shown in FIG. 5, the main body frame 3 forms a skeleton of the main body frame 3 and penetrates in the front-rear direction and has a main body frame base 600 having a rectangular game board holding port 601 for holding the game board 4. An upper shaft support bracket 630 and a lower shaft support bracket 640 that are respectively attached to the upper and lower ends of the left end of the main body frame base 600 and are pivotally supported by the outer frame 2 and pivotally support the door frame 5; A ball hitting device 650 that is attached to the lower front surface of the main body frame base 600 and drives a game ball into the game area 1100 of the game board 4, and is attached to the rear side of the main body frame base 600 to the upper plate 301 of the dish unit 300. A prize ball unit 700 for paying out a ball, and when the door frame 5 is attached to the front surface of the main body frame base 600 and the door frame 5 is opened with respect to the main body frame 3, the prize ball unit 700 is moved to the dish unit 300 of the door frame 5. It includes a ball outlet opening and closing unit 790 to shut off the flow of skill sphere, the.

  The main body frame 3 is attached to the lower rear surface of the main body frame base 600, and includes various control boards and power supply boards 851 for controlling electrical components provided in the door frame 5 and the main body frame 3 except the game board 4. Are combined into a unit board unit 800, a back cover 900 that covers the rear opening of the game board holding port 601 in the main body frame base 600, and a side security plate 950 that covers the left end of the main body frame base 600 when viewed from the front. And a locking device 1000 that is attached to the right end portion of the main body frame base when viewed from the front and that locks the main body frame 3 with respect to the outer frame 2 and opens and closes the door frame 5 with respect to the main body frame 3.

[3-1. Body frame base]
Next, the main body frame base 600 will be described. The main body frame base 600 is integrally formed of a synthetic resin, and the outer shape in front view is a vertically long rectangular shape along the outer shape of the door frame 5 and is formed to have a predetermined amount of depth in the front-rear direction. Has been. The main body frame base 600 has a game board holding port 601 through which the inside of about 3/4 of the whole from the upper part to the lower part penetrates in a rectangular shape in the front-rear direction and can fit and hold the outer periphery of the game board 4, and the main body frame A U-shaped front end frame portion 602 that forms the outer periphery of the front end excluding the left side of the base 600 when viewed from the front, and is recessed backward from the front surface of the front end frame portion 602, and from the lower end of the door frame base body 110 in the door frame 5 to the rear. The protruding door frame protruding piece 110c (see FIG. 1), the upper bent protruding piece 167 (see FIG. 1) protruding to the rear of the upper reinforcing sheet metal 151 in the reinforcing unit 150 of the door frame 5, and the open side reinforcing sheet metal 153. And an engaging groove 603 into which an open-side outer bent projecting piece 164 (see FIG. 1) protruding rearward is inserted and engaged.

  Further, the main body frame base 600 extends from the lower side of the game board holding port 601 to the lower end of the main body frame base 600 and is recessed from the front end of the front end frame portion 602 to the rear side by a predetermined amount and spread in a plate shape in the left-right direction. 604 and a peripheral wall portion 605 that protrudes rearward inside the front end frame portion 602 and forms the inner peripheral wall of the game board holding port 601. The peripheral wall portion 605 connects the free end portions (upper and lower left end portions in front view) of the U-shaped front end frame portion 602 so that the outer shape of the main body frame base 600 has a frame shape. It has become.

  In addition, the main body frame base 600 forms a lower side of the game board holding port 601 at the upper end of the lower rear wall part 604, and a game board placement part 606 on which the game board 4 is placed, and the game board placement part 606. A positioning protrusion 607 that protrudes upward from substantially the center in the left-right direction and engages with the out-ball discharge groove of the game panel 1150 in the game board 4, and is formed at a predetermined position on the right inner wall when viewed from the front in the peripheral wall portion 605. A game board locking portion to which the tool 1120 is fastened, and a plurality of upper end restricting ribs 609 arranged in the left-right direction in a plate shape that hangs downward from the upper inner wall of the peripheral wall portion 605 and whose lower ends can contact the upper end of the game board 4 And. The positioning protrusion 607 of the main body frame base 600 can be engaged with the out-ball discharge groove of the game board 4 to restrict the lower end of the game board 4 from moving in the left-right direction and the rear direction. Yes. Further, the game board locking portion can restrict the right side of the game board 4 from moving in the front-rear direction when the game board stopper 1120 of the game board 4 is locked. . Although the details of the left side of the game board 4 when viewed from the front will be described later, the movement in the front-rear direction is restricted by the positioning member 956 of the side security plate 950.

  In addition, the main body frame base 600 is formed at a position where the lower rear wall portion 604 is recessed one step further to the rear side than the front surface of the front end frame portion 602. The ball striking device 650 is attached from the front side so that the firing solenoid 654 of 650 is housed in the solenoid housing recess. In a state in which the ball hitting device 650 is attached to the front surface of the lower rear wall portion 604, a foul space 626 that extends leftward and downward is formed on the left side of the front view of the ball hitting device 650 from the upper end of the shot rail 660. It is like that. In the present embodiment, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e (see FIG. 1) in the foul cover unit 540 is positioned below the foul space 626. The game ball descending the foul space 626 is received by the foul ball inlet 542e of the foul cover unit 540 and discharged to the lower plate 302 (see FIG. 7) in the plate unit 300.

  Further, the main body frame base 600 is formed in a plurality of openings in a rectangular shape in the front-rear direction on the left side of the left and right center of the lower rear wall 604 in the front view, and a plurality of openings on the upper side of the opening and the left and right sides in the front view. And a through hole 615 penetrating the through hole. The opening portion of the main body frame base 600 is closed from the front side by a relay terminal plate cover 692, and the board unit attached to the rear surface of the lower rear wall portion 604 through the opening 692 a of the relay terminal plate cover 692. The 800 main door relay terminal plate 880 and the peripheral door relay terminal plate 882 face the front side.

  Further, the main body frame base 600 detects the opening of the door frame 5 with respect to the main body frame 3 on the lower front surface of the substantially circular cylinder lock through hole 611 penetrating in the front-rear direction at the upper right end of the lower rear wall 604 in front view. A door frame opening switch 618 is attached, and when the door frame 5 is opened (opened) with respect to the main body frame 3, the pressing is released and the opening of the door frame 5 can be detected. It is like that. Further, the main body frame base 600 is provided with a main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 on the lower rear surface from the position where the door frame opening switch 618 is attached. When the main body frame 3 is opened (opened) with respect to the outer frame 2, the pressing is released and the opening of the main body frame 3 can be detected.

[3-2. Upper shaft support bracket and lower shaft support bracket]
Next, the upper shaft bracket 630 and the lower shaft bracket 640 will be described. The upper shaft bracket 630 and the lower shaft bracket 640 are respectively attached to the bracket mounting portions on the upper left and lower rear ends of the main body frame base 600 using a predetermined screw to attach the door frame 5 to the main body frame 3. The main frame 3 can be pivotally supported with respect to the outer frame 2 so as to be openable and closable.

  The upper shaft support bracket 630 is attached to the upper bracket attachment portion of the main body frame base 600 and has a plate-like attachment portion 631 extending in the vertical and horizontal directions, and a plate-like front extension extending forward from the upper end of the attachment portion 631. Portion 632, a shaft support pin 633 projecting upward from the vicinity of the front end of the front extension portion 632, and a shaft pin 155 of the door frame 5 disposed on the left side of the shaft support pin 633 in front view (FIG. 7). And the door frame shaft support hole 634 penetrating in the up-down direction, and the front end of the front extension 632 hangs downward from the front end and restricts the rotation end of the door frame 5 toward the open side. And a stopper. In the upper shaft support 630, the attachment portion 631, the front extension portion 632, and the stopper are integrally formed by bending a single metal plate.

  The lower shaft support bracket 640 is disposed below the door frame shaft support bracket 642 for supporting the door frame 5 and supports the main body frame 3 with respect to the outer frame 2. The main body frame shaft support bracket 644 is provided. The door frame shaft support bracket 642 in the lower shaft support bracket 640 is attached to the lower bracket mounting portion of the main body frame base 600 and extends forward from the lower end of the mounting portion. A plate-like front extension 642b, a door frame shaft support hole 642c through which a shaft pin 157 (see FIG. 7) of the door frame 5 is inserted in the vertical direction near the front end of the front extension 642b, and the front And a stopper 642d that is erected upward from the left end portion of the extension portion 642b when viewed from the front and restricts the rotation end of the door frame 5 toward the open side. The door frame shaft support 642 is integrally formed with a mounting portion, a front extension 642b, and a stopper 642d by bending a single metal plate.

  Further, the main body frame shaft support bracket 644 in the lower shaft support bracket 640 is attached to the lower bracket attachment portion of the main body frame base 600 and extends forward and downward from the lower end of the attachment portion. A front extending portion 644b that protrudes, and a main body frame shaft support hole that penetrates in the vertical direction near the front end of the front extending portion 644b are provided. The main body frame shaft support 644 is also integrally formed with an attachment portion and a front extension portion 644b by bending a single metal plate.

  The lower shaft bracket 640 is in a state where the mounting portion of the door frame shaft bracket 642 and the mounting portion of the main body frame shaft bracket 644 are overlapped (contacted) in the front-rear direction. The front extension part 642b and the front extension part 644b of the main body frame shaft support metal 644 are attached to the lower metal attachment part of the main body frame base 600 in a state of being separated by a predetermined distance in the vertical direction.

  The upper shaft support 630 and the lower shaft support 640 are attached to the main body frame base 600, and the shaft support pin 633 of the upper shaft support 630 and the main body frame shaft support hole of the lower shaft support 640 are coaxial. The body frame shaft support hole of the body frame shaft support bracket 644 in the lower shaft support bracket 640 is fitted to the support protrusion 21d (see FIG. 4) of the lower support bracket 21 in the outer frame 2. The front extension portion 644b of the main body frame shaft support bracket 644 is placed on the support protruding piece 21c (see FIG. 4) of the lower support bracket 21, so that the shaft of the upper shaft support bracket 630 is inserted. By inserting the support pin 633 into the support hole 20c (see FIG. 4) of the upper support fitting 20 in the outer frame 2, the main body frame 3 can be pivotally supported with respect to the outer frame 2 so as to be opened and closed. It is like that.

  Further, the upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the main body frame base 600, and the door frame shaft support hole 634 of the upper shaft support bracket 630 and the door frame shaft support hole of the lower shaft support bracket 640. 642c is positioned coaxially with the door frame so that the shaft pin 157 of the door frame 5 is inserted into the door frame shaft support hole 642c of the door frame shaft support bracket 642 in the lower shaft support bracket 640. 5 is mounted on the front extension 642b of the door frame shaft bracket 642, and the shaft pin 155 of the door frame 5 is placed on the door frame of the upper shaft bracket 630. The door frame 5 can be pivotally supported with respect to the main body frame 3 so as to be openable and closable by being inserted into the pivotal support hole 634. In the present embodiment, the shaft pin 155 on the upper side of the door frame 5 is slidable in the vertical direction. When the shaft pin 155 is inserted into the door frame shaft support hole 634 of the upper shaft support 630, the shaft pin 155 is inserted. Is once slid downward so that the upper shaft support portion 156 of the door frame 5 and the front extension portion 632 of the upper shaft support fitting 630 overlap vertically, and then the shaft pin 155 is slid upward. It can be inserted into the door frame shaft support hole 634.

[3-3. Hitting ball launcher]
Next, the hit ball launching device 650 will be described. The hitting ball launching device 650 is mounted so that the metal plate launch base 652 is mounted at a predetermined position on the front surface of the lower rear wall portion 604 in the main body frame base 600, and the rotary drive shaft 654a projects forward from the lower rear surface of the launch base 652. Firing solenoid 654, a hitting ball 656 fixed to the rotation drive shaft 654a of the firing solenoid 654 so as to be integrally rotatable, a tip 658 fixed to the tip of the hitting ball 656, and a predetermined movement path of the tip 658 A firing rail 660 extending diagonally to the upper left when viewed from the front and attached to the front surface of the firing base 652, and a tip 658 at the tip of the hitting ball 656 passes between the firing rail 660 and the top of the firing rail 660. A ball stopper that holds the game ball at the base end of the firing rail 660 while forming a gap through which the game ball cannot pass at the same time. 662 and a stopper for restricting the ball hitting ball 656 (tip 658) from rotating toward the shooting rail 660 from the hitting position where the game ball held at the base end of the shooting rail 660 by the ball stopper piece 662 can be hit. 664.

  The firing solenoid 654 of the ball striking device 650 is not shown in detail, but the rotational drive shaft 654a reciprocates with a strength (speed) corresponding to the rotational operation angle of the handle device 500. . Further, the hitting ball basket 656 of the hitting ball launching device 650 has a fixed portion 656a fixed to the rotation drive shaft 654a of the launch solenoid 654, and a gentle arc extending from the fixed portion 656a, and the tip is centered on the rotation drive shaft 654a. On the other hand, a hook portion 656b with the hook tip 658 fixed to the tip at a normal direction, a stopper portion 656c extending to the opposite side of the hook portion 656b with the fixing portion 656a interposed therebetween, and a stopper portion 656c capable of contacting the stopper 664 It has. When the stopper portion 656c of the hitting ball basket 656 is in contact with the stopper 664, the tip of the tip 658 is rotated to the firing rail 660 side from the hitting position (the rotation end in the counterclockwise direction when viewed from the front). Being regulated.

  When the hitting ball launcher 650 is attached to the lower rear wall portion 604 of the main body frame base 600, the upper end of the firing rail 660 is substantially the center in the left-right direction, that is, the upper end of the lower rear wall portion 604, that is, the game board mounting portion. 606 (the lower side of the game board holding port 601) is located below and has a predetermined width in the left-right direction between the lower end of the outer rail 1111 in the game board 4 held by the game board holding port 601. Thus, a foul space 626 extending downward is formed. The hit ball launching device 650 can hit the game ball into the game area 1100 of the game board 4 by firing the game ball so as to jump over the foul space 626 on the left side of the front view from the launch rail 660. It has become. In a state where the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e of the foul cover unit 540 attached to the door frame 5 is positioned below the foul space 626. A game ball that has become a foul ball without being driven into the area 1100 falls in the foul space 626, is received by the foul ball inlet 542 e, and is discharged to the lower plate 302.

[3-4. Prize ball unit]
Next, the prize ball unit 700 will be described. In the pachinko island facility in the hall where the pachinko gaming machine 1 is installed, the game balls supplied from the pachinko island facility side to the pachinko gaming machine 1 are stored, and the upper plate 301 of the pachinko gaming machine 1 is based on a predetermined payout instruction. To pay out. The prize ball unit 700 has a prize ball base 710 attached to the rear surface of the main body frame base 600 and a prize ball tank attached to the upper rear surface of the prize ball base 710 and receiving and storing game balls supplied from the Pachinko island equipment side. 720, a tank rail unit 730 arranged below the prize ball tank 720 and arranged to send the game balls stored in the prize ball tank 720 to the downstream side, and the game balls arranged by the tank rail unit 730 The prize ball device 740 to be paid out based on the payout instruction, and the game balls paid out by the prize ball device 740 can be guided to the upper plate 301 of the tray unit and are paid out when the upper plate 301 is full of game balls. And a full tank branching unit 770 capable of branching and guiding the game ball to the lower plate 302 side.

The prize ball unit 700 includes an external terminal board 784 attached to the rear surface of the prize ball base 710 and an external terminal board cover 786 that covers the rear side of the external terminal board 784.
[3-4-1. Prize ball tank]

  In the prize ball tank 720, the outer periphery of the bottom wall portion 721 is surrounded by an outer peripheral wall portion 722, and a predetermined amount of game balls can be stored on the bottom wall portion 721. The prize ball tank 720 is inclined so that the upper surface of the bottom wall portion 721 is lowered toward the discharge port 723 so that the game ball on the bottom wall portion 721 rolls toward the discharge port 723. It has become.

  The prize ball tank 720 includes two ball leveling members 727 that are pivotally supported by the shaft portion 725. One end side of the ball leveling member 727 is pivotally supported by the shaft portion 725 and holds a weight inside, and the other end side is suspended by its own weight. The ball leveling member 727 hangs down in a tank rail unit 730, which will be described later, so that game balls circulating in the tank rail unit 730 can be leveled and aligned.

[3-4-2. Tank rail unit]
The tank rail unit 730 includes a tank rail 731 disposed below the prize ball tank 720 and extending long in the left-right direction. The tank rail 731 has a bowl-like shape with a predetermined depth opened upward, and has a width (depth) in which the game balls can be aligned in two lines in the front-rear direction. The bottom is inclined so as to be low.

  The tank rail unit 730 is connected to the alignment gear 732 rotatably supported on the upper portion of the discharge port of the tank rail 731, the gear cover 733 covering the upper portion of the alignment gear 732, and the right end of the gear cover 733 as viewed from the front, A ball retainer plate 734 that closes the upper portion of the rail 731; a ball stop piece 735 that can move forward and backward in the tank rail 731 and stop the game ball in the tank rail 731 from rolling toward the outlet; It is equipped with. Two alignment gears 732 are provided side by side in the front-rear direction so as to correspond to the two flow paths of the game balls partitioned in two rows by the partition wall of the tank rail 731.

[3-4-3. Prize ball device]
The prize ball device 740 is for paying out the game balls discharged and supplied from the discharge port of the tank rail unit 730 to the upper plate 301 of the plate unit 300 based on a predetermined payout instruction. The prize ball device 740 has a predetermined width that communicates with a supply passage that opens to the upper end and extends to a position slightly lower than the center in the vertical direction with a width that is slightly wider than the outer shape of the game ball. A distribution space having a space, a prize ball passage that opens into the left side of the rear view when bent in a substantially square shape and communicates with the lower left side (open side) of the rear side of the distribution space, and the right side of the rear side of the distribution space (Axis support side) A ball passage that communicates with the lower end and extends downward and opens at the lower end. The supply passage, the distribution space, the prize ball passage, and the ball removal passage are formed in a state opened rearward.

  The prize ball device 740 is meshed with the first gear fixed to the rotating shaft of the payout motor 744 and disposed behind the motor support plate, the second gear meshing with the first gear, and the second gear. The third gear that rotates together with the third gear and is disposed in the distribution space, and the dispensing rotator is fixed to the opposite side so as to be integrally rotatable on the opposite side of the third gear. A rotation detecting board having a plurality of detection slits (three in the present embodiment) formed at intervals, a ball break switch 750 for detecting the presence or absence of a game ball in the supply passage, and a prize ball passage A counting switch 751 for detecting a game ball flowing down inside, a rotation angle switch 752 for detecting a detection slit formed in a rotation detection board that rotates integrally with the payout rotating body, and a rotation angle switch 752 are held. Rotation angle switch board 53, a payout motor 744, burn out switch 750, a counting switch 751, and the rotation angle prize balls casing substrate 754 that relays the connection between dispensing the below-described control board and the switch 752, the.

  The payout rotator includes three recesses each having a size capable of accommodating one game ball at equal intervals in the circumferential direction. When the payout rotator rotates, 1 game ball supplied from the supply passage is 1 Each ball is accommodated in the recess, and can be paid out to the prize ball passage or the ball removal passage side. Further, the three detection slits formed on the rotation detecting board that rotates integrally with the payout rotating body are equally formed (every 120 degrees) on the outer periphery of the rotation detecting board, and correspond to between the recesses of the payout rotating body. The rotation position of the payout rotating body can be detected by detecting the detection slit with the rotation angle switch 752. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (dispensing rotary body) is designed to correspond to the 18-step rotation of the dispensing motor 744.

  The award ball device 740 is configured such that when the payout rotating body is rotated counterclockwise by the payout motor 744, the game ball in the supply passage is paid out to the award ball passage. The game balls paid out to the prize ball passage by the rotation of the body are counted by the counting switch 751 one by one and then delivered to the prize ball passage. On the other hand, when the ball removal operation member is operated by a hall clerk or the like, the game balls in the supply passage are paid out to the ball removal passage. The pachinko gaming machine 1 can be discharged from the lower end of the passage to the rear outside of the pachinko gaming machine 1 through a full tank branching unit 770 described later.

[3-4-4. Full tank branch unit]
The full tank branching unit 770 is formed in a box shape that becomes lower as it goes from the rear end to the front end. The full branching unit 770 opens upward substantially at the center in the left-right direction at the upper end of the rear end, and the award of the prize ball device 740 is obtained. A prize ball receiving hole for a game ball flowing down the ball passage, a branching space that is arranged below the prize ball receiving hole and extends in the left-right direction, and a game from directly under the prize ball receiving hole in the branching space to the front side A normal path for guiding the ball, a normal ball outlet 774 that releases the game ball flowing through the normal path to the front and opened at the front right end of the front view, and the right side in the rear view rather than just below the prize ball receiving opening in the branch space A full tank passage that guides the game ball from the raised position to the front side, and a full ball exit 776 that discharges the game ball that has circulated through the full tank passage to the front and opens to the left in front of the normal ball outlet 774. ing.

  In addition, the full tank branching unit 770 includes a ball receiving port that receives a game ball that opens upward at the left end portion of the rear end upper portion when viewed from the front and flows down the ball passage of the prize ball device 740, and a ball receiving portion. A ball passage that guides the game ball received in the mouth to the front side, and a game ball that has circulated through the ball passage is released forward and at the left end of the front view at a position behind the normal ball outlet 774 and the full ball exit 776 And an open ball outlet.

  When the full tank branching unit 770 is in a state in which the door frame 5 is closed with respect to the main body frame 3, the normal ball outlet 774 and the full tank outlet 776 are respectively connected to the first ball inlet 542 a of the foul cover unit 540 in the door frame 5. And the second ball inlet 542c (see FIG. 1) and communicates with each other, and the game ball released from the normal ball outlet 774 passes through the first ball inlet 542a of the foul cover unit 540, The game balls supplied to the upper plate 301 of the unit 300 and released from the full ball outlet 776 are supplied to the lower plate 302 of the plate unit 300 through the second ball inlet 542c of the foul cover unit 540. ing. The ball outlet is formed so as to communicate with the upper right side upper end of the main body frame base ball passage in the main body frame base 600, and the game ball discharged from the ball outlet is the main body frame of the main body frame base 600. It is to be delivered to the base ball passage.

  When a game ball is further paid out from the prize ball unit 700 (prize ball device 740) in a state where the upper plate 301 of the dish unit 300 is full of game balls, the upper ball ball is raised from the first ball exit of the foul cover unit 540. The game balls that can no longer come out to the side of the tray 301 stagnate in the first ball passage of the foul cover unit 540, and eventually fill up the normal passage upstream through the normal ball outlet 774 in the full tank branching unit 770. In this state, the game ball that has entered the branch space from the prize ball receiving port cannot normally enter the passage, and starts moving in the lateral direction in the branch space, and the game ball that has moved in the horizontal direction is full. So as to enter the tongue passage and be supplied from the full bulb exit to the lower plate 302 of the dish unit 300 through the second bulb inlet 542c, the second bulb passage, and the second bulb outlet of the foul cover unit 540. It has become.

[3-5. Substrate unit]
Next, the substrate unit 800 will be described. As shown in FIG. 6, the substrate unit 800 includes a substrate unit base 810 attached to the rear surface of the lower rear wall portion of the main body frame base 600, a speaker box 820 attached to the rear left side of the substrate unit base 810, and a substrate. A power supply board box holder 840 attached to the rear face of the unit base 810, and a power supply board box attached to the rear face of the power supply board box holder 840 and having a rear end substantially flush with the rear end of the speaker box 820 850, a payout control board box 860 attached to the rear surfaces of the power supply board box 850 and the speaker box 820, and a terminal board box 870 attached to the rear face of the speaker box 820 so as to cover the left end of the payout control board box 860 when viewed from the front. And board unit base A main door relay terminal plate 880 and the peripheral door relay terminal plate 882 is attached to the front surface 10, and a.

  The power supply board box holder 840 has a discharge ball receiving portion 841 that receives a game ball that is opened upward and discharged from the out ball discharge portion of the game board 4 downward from the left and right front in front view, A discharge passage 842 that guides and discharges the game ball received by the discharge ball receiving portion 841 downward and the front of the discharge passage 842 and the side of the discharge ball receiving portion 841 (right side in front view) is opened forward and upward. A power supply board box holder 840 having a box housing portion that is formed so that the entire rear surface of the power board box holder 840 is recessed to the front side and can accommodate the front end of the power board board box 850.

  The power supply board box holder 840 is configured such that the open front end side of the discharge passage 842 is closed by the rear surface of the substrate unit base 810 and the opening of the substrate unit base 810 faces the discharge passage 842. The main body frame base 600 is circulated through the main body frame base ball passage formed on the rear surface of the lower rear wall portion of the main body frame base 600 and flows down to the rear side of the substrate unit base 810 through the opening of the substrate unit base 810. The game ball and the game ball discharged from the out ball discharge portion of the game board 4 and received by the discharge ball receiving portion 841 can be discharged to the lower rear side of the pachinko gaming machine 1 through the discharge passage 842. It has become.

  The power supply board box 850 is formed in a horizontally long box shape with the front open, and includes a power supply board 851 attached so as to close the front end opening. The power supply board box 850 accommodates various electronic components attached to the power supply board 851, and externally transfers heat from the electronic parts and the like through a plurality of slits 850a formed on the upper surface and the lower surface. Can be released. A power switch 852 attached to the power supply board 851 faces the rear surface of the power supply board box 850.

  The payout control board box 860 includes a thin box-shaped box base 861 that is horizontally long and opened rearward, a thin box-shaped cover 862 that is fitted into the box base 861 from the rear side and opened front, and a box base 861. And a payout control board 4110 attached to the rear surface and covered by the cover 862. Further, the payout control board box 860 includes a plurality of separation cutting portions 863 that protrude outward from the left end in the rear view and are formed on both the box base 861 and the cover 862, and are provided at one location of the plurality of separation cutting portions 863. The box base 861 and the cover 862 are fixed by caulking. Thus, in order to separate the box base 861 and the cover 862, the separation and cutting portion 863 must be cut so that the box base 861 and the cover 862 cannot be separated. When the dispensing control board box 860 is opened, the trace remains. . Therefore, it can be determined whether or not the dispensing control board box 860 has been opened and closed illegally. In the present embodiment, the payout control board box 860 can be opened and closed only once for inspection or the like.

  Further, the payout control board box 860 is configured such that the operation switch 860a attached to the payout control board 4110, the inspection output terminal 860c, and the like face rearward through the cover 862. The payout control board box 860 has various connection terminals for connecting to the main control board 4100 and the like facing rearward through the cover 862. The operation switch 860a is operated when clearing the RAM built in the microprocessor of the payout control board 4110 and the RAM built in the microprocessor of the main control board 4100 when the power is turned on, or after the power is turned on. When an error is reported, it is operated to cancel the error, and the RAM clearing function at power-on and the power-on (time period for functioning as RAM clearing have elapsed) And a function of canceling an error in (after). A detailed description of this point will be described later.

  The terminal board box 870 includes a board base 871 attached to the rear face of the speaker box 820, a frame peripheral relay terminal board 868 attached to the rear face of the board base 871 and fixed with a peripheral panel relay terminal 872 toward the rear, and a board base. A board for lending device connection terminal plate 869 such as a game ball attached to the rear surface of 871 and having CR unit relay terminal 873 fixed to the rear, so that peripheral panel relay terminal 872 and CR unit relay terminal 873 face the rear side. And a substrate cover 874 that covers the rear side of the base 871. The peripheral panel relay terminal 872 is for connecting to a frequency indicator for displaying the operating state of the pachinko gaming machine 1 provided on the pachinko island facility side where the pachinko gaming machine 1 is installed. The terminal 873 is for connection with a CR unit installed adjacent to the pachinko gaming machine 1.

  The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are provided in the door frame 5, the peripheral control board 4140 provided in the game board 4 attached to the main body frame 3, the payout control board 4110 of the board unit 800, and the like. This is for relaying the connection with the handle device 500, each decorative board, the operation unit 400 and the like. The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are attached to the board mounting portion formed on the front surface of the board unit base 810 so as to face the front side of the main body frame base 600, Wiring extending from the door frame 5 can be connected.

  The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are covered with a relay terminal plate cover 692 attached to the front surface of the main body frame base 600, and the front side of the relay terminal plate cover 692 is also covered. Only the connection terminal faces the front side through the opening 692a, so that the front surface of the main body frame 3 has a clean appearance.

  Further, the main door relay terminal plate 880 includes a ball rental button 361, a return button 362, a remaining rental display portion 363, a potentiometer 512 of the handle device 500, and a touch in the tray unit 300 arranged on the door frame 5 side. This is for relaying the connection between the switch 516, the firing stop switch 518, and the full tank switch 550 of the foul cover unit 540 and the payout control board 4110 disposed on the main body frame 3 side. It should be noted that the ball rental button 361, the return button 362, the remaining rental display unit 363, the potentiometer 512 of the handle device 500, the touch switch 516, the firing stop switch 518, and the full switch 550 of the foul cover unit 540 are provided. The description will be described later.

  In addition, the peripheral door relay terminal plate 882 is provided in each decorative unit 200, 240, 280 and the decorative unit provided in the plate unit 300 or the operation unit 400 and the operation unit 400 arranged on the door frame 5 side. The relay is used to relay the connection between the dial drive motor 414, various switches for detecting the operation of the dial operation unit 401 and the pressing operation unit 405, and the peripheral control board 4140 of the game board 4 arranged on the main body frame 3 side. is there. The decorative units 200, 240, and 280 arranged on the door frame 5 side, the decorative boards provided in the dish unit 300 and the operation unit 400, the dial drive motor 414 provided in the operation unit 400, the dial operation, and the like. A description will be given later of various switches that detect operations of the unit 401 and the pressing operation unit 405.

[4. Overall structure of door frame]
Next, the door frame 5 that can be freely opened and closed on the front side of the main body frame 3 will be described with reference to FIG. FIG. 7 is a perspective view of the door frame. As shown in FIG. 7, the door frame 5 includes a door frame base unit 100 having a gaming window 101 whose outer shape is formed in a vertically long rectangular shape and whose inner peripheral shape is a slightly vertically long circular shape (elliptical shape), A right side decoration unit 200 attached to the right outer periphery of the gaming window 101 on the front surface of the frame base unit 100, and a left side facing the right side decoration unit 200 and attached to the left outer periphery of the gaming window 101 on the front surface of the door frame base unit 100. The decoration unit 240, the upper decoration unit 280 attached to the upper outer periphery of the gaming window 101 in front of the door frame base unit 100, and the door frame base unit disposed below the lower ends of the right side decoration unit 200 and the left side decoration unit 240. And a pair of side speaker covers 290 attached to the front surface of 100.

  The door frame 5 is attached to the right side of the dish unit 300, the tray unit 300 attached to the lower part of the gaming window 101 on the front surface of the door frame base unit 100, the operation unit 400 attached to the upper center of the dish unit 300. A handle device 500 that is attached to the lower right corner portion of the door frame base unit 100 through the upper plate side liquid crystal display device 470 and the dish unit 300, and the door frame base unit 100 is sandwiched therebetween. A foul cover unit 540 disposed on the rear side of the dish unit 300 and attached to the rear surface of the door frame base unit 100; a ball feeding unit 580 attached to the rear surface of the door frame base unit 100 on the right side of the foul cover unit 540; Installed to close the game window 101 on the rear side of the base unit 100 The glass unit 590 is provided with a.

[4-1. Door frame base unit]
Next, the door frame base unit 100 will be described. The door frame base unit 100 has a door frame base main body 110 having a gaming window 101 having an outer shape formed in a vertically long rectangular shape and penetrating in the front-rear direction and having an inner periphery formed in a substantially elliptical shape. An upper bracket 120 that is attached to the upper center of the gaming window 101 on the front surface of the base body 110 and fixes the upper decorative unit, and a pair of sides that are attached to the lower left and right outer sides of the gaming window 101 on the front surface of the door frame base body 110. The speaker 130 and a handle bracket for supporting the handle device 500 attached to the lower right corner of the front view on the front surface of the door frame base main body 110 are provided.

  The door frame base unit 100 includes a metal frame-shaped reinforcing unit 150 (see FIG. 1) fixed to the rear side of the door frame base main body 110, and the gaming window 101 on the rear surface of the door frame base main body 110. A security cover 180 (see FIG. 1) attached so as to cover the lower part, and a glass unit locking member 190 (see FIG. 1) attached to a predetermined position on the outer periphery of the gaming window 101 on the rear surface of the door frame base body 110. 1), and a launch cover 191 (see FIG. 1) that is disposed on the left side (open side) from the center in the left-right direction in a rear view and is attached to the rear surface of the door frame base body 110 along the lower end of the game window 101. A main control board mounted on the rear surface of the door frame base body 110 below the launch cover 191 and provided in a potentiometer 512 of the handle device 500 described later and a game board 4 described later. A handle relay terminal plate 192 (see FIG. 1) that relays the connection to the 100, a handle relay terminal plate cover 193 (see FIG. 1) that covers the rear side of the handle relay terminal plate 192, and a center in the left-right direction. A frame decoration drive amplifier board 194 that is disposed on the opposite side to the launch cover 191 and the handle relay terminal plate 192 (on the right side (axial support side) from the center in the left-right direction in rear view) and attached to the rear surface of the door frame base body. (See FIG. 1) and a frame decoration drive amplifier board cover 195 (see FIG. 1) covering the rear side of the frame decoration drive amplifier board 194.

  The frame decoration drive amplifier board 194 is electrically connected to the side speakers 130 and the upper speakers of the left and right side decoration units 200 and 240, and is also electrically connected to a peripheral control board 4140 provided in the game board 4 described later. And an amplification circuit that amplifies the acoustic signal sent from the peripheral control board 4140 and outputs the amplified signal to each speaker 130. Although not specifically shown, in the present embodiment, the decorative units 200, 240, 280, the decorative boards provided in the dish unit 300 and the operation unit 400, and the dial drive motor provided in the operation unit 400. In addition, the wiring for electrically connecting the switch, the handle relay terminal plate 192, the ball rental unit 360 of the dish unit 300, etc., and the payout control board 4110, the peripheral control board 4140, etc. After being bundled together at the right side (axial support side) position, it extends rearward and is connected to the main door relay terminal plate 880 and the peripheral door relay terminal plate 882 of the main body frame 3.

[4-1-1. Door frame base body]
The door frame base body 110 is formed in a vertically long frame shape with a synthetic resin, and is formed in such a manner that the gaming window 101 having a vertically long and substantially elliptical shape penetrating in the front-rear direction is offset upward as a whole. Has been. The gaming window 101 is formed in a smooth curved shape in which the left and right side and upper inner peripheral edges are continuous, whereas the lower inner peripheral edge is formed in a straight line extending left and right. In addition, a rectangular notch that allows insertion of the first ball outlet of the foul cover unit 540 is formed on the shaft support side (left side in front view) on the inner peripheral edge of the lower side of the game window 101 in the door frame base body 110. A speaker mounting portion for mounting and fixing the side speaker 130 disposed on the left and right outer sides of the lower side of the gaming window 101, a right side (open side) end of the front surface disposed at the lower right corner portion in front view and bulging forward The handle mounting portion for tilting the handle bracket to tilt backward, the wiring passage opening through which the wiring from the handle device 500 can pass through at a predetermined position of the handle mounting portion, and the upper side of the handle mounting portion. Thus, a lock hole 116 is formed which is formed in a cylindrical shape extending short forward and into which a cylinder lock 1010 described later can be inserted. The door frame base body 110 has an upper side formed by the game window 101 and widths on the left and right sides of an upper reinforcing sheet metal 151, a pivot supporting side reinforcing sheet metal 152, and an open side reinforcing sheet metal 153 of a reinforcing unit 150 described later. The gaming window 101 is formed as large as possible with respect to the size of the door frame base body in a front view.

[4-1-2. Reinforcement unit]
The reinforcing unit 150 includes an upper reinforcing sheet metal 151 (see FIG. 1) attached along the back side of the upper side of the door frame base body 110 and a shaft support attached along the back side of the side of the shaft support side of the door frame base body 110. Side reinforcing sheet metal 152 (see FIG. 1), an open side reinforcing sheet metal 153 (see FIG. 1) attached along the back side of the open side of the door frame base body 110, and the gaming window 101 of the door frame base body 110 And a lower reinforcing metal plate 154 (see FIG. 1) attached along the back surface of the lower side, and they are fastened to each other with screws, rivets or the like to form a square shape.

  An upper shaft support portion 156 having a shaft pin 155 slidably provided on the upper surface of the upper and lower ends of the shaft support side reinforcing sheet metal 152 and a lower shaft support portion 158 having a shaft pin 157 on the lower surface thereof. Integrated. The upper and lower shaft pins 155 and 157 are pivotally supported by the upper shaft bracket 630 and the lower shaft bracket 640 formed on the upper and lower sides of the body frame 3, so that the door frame 5 is attached to the body frame 3. So that it can be freely opened and closed.

  In addition, a hook cover 165 that contacts the door frame hook portion 1041 of the locking device 1000 is provided at the lower rear side of the opening-side reinforcing sheet metal 153. The hook cover 165 is engaged with the door frame hook portion 1041 of the lock device 1000 attached along the open side of the main body frame 3 when the door frame 5 is closed with respect to the main body frame 3. By inserting a key into the cylinder lock 1010 of the locking device 1000 and rotating it in one direction (rotating in the direction opposite to the direction in which the main body frame 3 is opened with respect to the outer frame 2), the door frame hook portion 1041 and the hook cover The door frame 5 can be opened with respect to the main body frame 3 by disengaging from the 165.

[4-2. Dish unit]
Next, the dish unit 300 will be described. The tray unit 300 includes an upper plate 301 and a lower plate 302 for storing the game balls paid out from the prize ball device 740, and the game balls stored in the upper plate 301 are shot through the ball feeding unit. Can be supplied to the device 650.

  The shape of the upper dish upper panel 314 of the dish unit 300 is formed in a curved shape so as to protrude forward from the left to the center in a front view, and forward straightly from the center to the right. Protrusively formed. An operation unit attachment portion to which the operation unit 400 is attached is formed at the upper center of the plate unit 300, and a liquid crystal attachment portion 314d for attaching the upper plate side liquid crystal display device 470 is formed on the right side of the operation unit attachment portion. . The shape of the upper plate upper panel 314 on which the liquid crystal mounting portion 314d is formed is formed in a plate shape, and for example, when a player presses the portion downward with a hand, the upper plate 314d bends downward. When the pressing force exceeds a predetermined force, the upper plate upper panel 314 is broken. This is because the upper plate side liquid crystal display device 470 is expensive, and when the player presses the hand on the screen of the upper plate side liquid crystal display device 470, the force is received by the upper plate upper panel 314. The upper plate side liquid crystal display device 470 is prevented from being damaged by bending the upper plate upper panel 314. That is, a structure is adopted in which the upper plate upper panel 314 is damaged before the upper plate side liquid crystal display device 470 is damaged. In addition, when the upper plate upper panel 314 is damaged, the plate unit 300 is replaced. In this case, the upper plate side liquid crystal display device 470 is removed from the broken upper plate upper panel 314 and attached to the upper plate upper panel 314 of the plate unit 300 to be replaced for reuse.

  Further, the dish unit 300 includes an upper dish ball removal mechanism 340 for removing game balls stored in the upper dish 301 to the lower dish 302 in response to an operation of the upper dish ball removal button 341, and a lower dish ball removal button 354. The lower tray ball removing mechanism 350 for pulling down the game balls stored in the lower tray 302 in accordance with the operation of the lower tray ball through the lower tray ball removing hole 324b and the pachinko gaming machine 1 are not shown. A ball rental unit 360 for operating the CR unit.

[4-2-1. Operation unit]
The operation unit 400 includes a dial operation unit 401 that can be rotated by the player and a pressing operation unit 405 that can be pressed by the player. The player can accept the player's operation according to the game state, and the dial operation unit 401 can be moved. The player can participate not only in the game ball driving operation but also in the game. It is something that can be done. The rotation (rotation direction) of the dial operation unit 401 is detected by a rotation detection switch provided in the operation unit 400, and the operation of the pressing operation unit 405 is detected by a press detection switch provided in the operation unit 400.

  Further, the operation unit 400 can rotate the dial operation unit 401 in the clockwise direction or the counterclockwise direction by the driving force of the dial drive motor 414. Further, the operation unit 400 rotates the dial operation unit 401 step by step by the driving force of the dial drive motor 414 using a stepping motor, or when the player rotates the dial operation unit 401, Rotation can be assisted, it can be prevented from turning on purpose, or a click can be added to the rotation. Further, the operation unit 400 can vibrate the dial operation unit 401 by alternately repeating the rotation for rotating the dial drive motor 414 in small increments and the rotation for rotating in reverse.

[4-2-2. Rental unit]
The lending unit 360 includes a lending button 361 and a return button 362 that can be pressed backward, and a lending remaining display portion 363 between the lending button 361 and the return button 362. When the ball rental button 361 is operated, it is detected by the ball rental switch 365a, and when the return button 362 is operated, it is detected by the return switch 365b. The display content of the remaining frequency indicator 365c can be visually recognized through the rental remaining display portion 363. A CR unit lamp 365d is disposed adjacent to the remaining frequency indicator 365c so that the light emission mode of the CR unit lamp 365d can be visually recognized through the rental remaining display portion 363. The ball lending switch 365a, the return switch 365b, the remaining frequency indicator 365c, and the CR unit lamp 365d are mounted on the frequency display plate 365, and the frequency display plate 365 is attached to the inside of the ball rental unit 360. . When the ball rental unit 360 is pushed into the ball lending machine provided adjacent to the pachinko gaming machine 1 with a cash or prepaid card and the ball lending button 361 is pressed, a predetermined number of game balls are transferred to the dish unit. 300 can be lent out (paid out) into the top plate 301, and when the return button 362 is pressed, the balance of the loaned portion is drawn and the remaining cash or prepaid card is returned. ing. In addition, the remaining lending display section 363 displays the number of cash and prepaid cards remaining in the ball lending machine.

[4-3. Ball transport unit]
Next, the ball feeding unit 580 will be described. The ball feeding unit 580 can supply the game balls supplied from the upper plate 301 in the plate unit 300 one by one to the hitting ball launching device 650, and the game balls stored in the upper plate 301 are supplied to the upper plate ball. It can be pulled out to the lower pan 302 by operating the upper pan ball release button 341 of the pulling mechanism 340.

  The ball feeding unit 580 is an intrusion port in which game balls stored in the upper plate 301 of the plate unit 300 are supplied through the upper plate ball discharge port of the upper plate 301 and the ball opening of the door frame base body 110 and penetrate in the front-rear direction. And a box-shaped front cover that has a ball opening that opens below the intrusion opening and is open at the rear, and a box-like shape that closes the rear end of the front cover and opens the front, and penetrates in the front-rear direction The rear cover having a hitting ball supply port 582a for supplying the game ball that has entered from the intrusion port of the front cover to the hitting ball launcher 650, and the axis extending in the front-rear direction between the rear cover and the front cover. A ball removing member that is pivotally supported and has a partitioning portion for partitioning between the entrance and the ball outlet on the rear side of the front cover, and the game balls on the partitioning portion of the ball removing member are hit one by one on the rear cover. Up and down between the front cover and the rear cover before feeding to the supply port 582a And Tamaoku member rotatably supported around an axis extending to, and a Tamaoku solenoid 585 to rotate the Tamaoku member.

  When the ball feeding solenoid 585 is driven (ON state), the ball feeding member accepts one game ball, while when the ball feeding solenoid 585 is released (OFF state), the ball feeding member accepts it. The game ball is sent (supplied) to the hitting ball launching device 650 side.

[4-4. Handle device]
Next, the handle device 500 will be described. The handle device 500 is fixed to a handle bracket attached to the front surface of the door frame base main body 110, is cylindrical, and has a handle base whose front end bulges out in a direction perpendicular to the axis, and a handle base that is rotatable relative to the handle base. Arranged at the front of the front of the rotary handle main body 506, the front of the rotary handle main body 506, the front of the rotary handle main body 506 fixed to the front of the rear of the rotary handle main body and being rotatable integrally with the rear of the rotary handle main body. And a front end cover 508 that is fixed to the handle base and rotatably supports the front of the rotary handle main body 506 and the rear of the rotary handle main body in cooperation with the handle base.

  In addition, the handle device 500 is attached and fixed to the center of rotation in front of the rotary handle body so as to protrude from the front side to the rear side, and has a non-circular bearing portion at the rear end, and the shaft member bearing portion is fitted. A potentiometer 512 that has a detection shaft portion that can be rotated together and is non-rotatably fitted to the front surface of the handle base, and is fixed to the front surface of the handle base so that the potentiometer 512 is sandwiched between the handle base and A switch support member having a through-hole through which the shaft portion can pass, a touch switch 516 attached to the rear surface of the switch support member, and a firing stop switch 518 attached to the touch switch 516 at a different position on the rear surface of the switch support member; A single-shot button that is pivotally supported with respect to the switch support member and operates the firing stop switch 518. And a handle that is arranged so as to cover the outer periphery of the shaft member and urges the front of the rotary handle body 506 and the rear of the rotary handle body to return to the original rotation position (rotation end in the counterclockwise direction when viewed from the front). And a return spring. The potentiometer 512 is for electrically adjusting the strength of launching the game ball toward the game area 1100 according to the rotational position of the front 506 of the rotary handle. In addition, after the rotary handle main body 506 and after the rotary handle main body, it is rotated from the original rotational position to the limit rotational position (rotation end in the clockwise direction when viewed from the front) that is the maximum rotational position in the clockwise direction when viewed from the front. To do.

  Further, in the handle device 500, the potentiometer 512 is a variable resistor. When the front part 506 of the rotary handle and the rear part of the rotary handle body are rotated, the detection shaft portion of the potentiometer 512 is rotated via the shaft member. . Then, the internal resistance of the potentiometer 512 changes according to the rotational position (rotation angle) of the detection shaft portion, and the driving force of the firing solenoid 654 in the ball hitting device 650 changes according to the internal resistance of the potentiometer 512, so that the rotary handle A game ball is driven into the game area 1100 with a launch intensity corresponding to (a match with) the rotation angle of the front of the main body 506 and the rear of the rotary handle, that is, the rotation position of the front of the rotary handle main body 506 and the rear of the rotary handle. Yes.

[4-5. Foul cover unit]
Next, the foul cover unit 540 will be described. The foul cover unit 540 is attached to the rear surface below the game window 101 in the door frame base unit 100, and is a game area that is discharged from the prize ball unit 700 or a ball hitting device 650, although it is fired. A game ball (foul ball) that has not reached 1100 is guided to the upper plate 301 or the lower plate 302 of the plate unit 300. The foul cover unit 540 includes a cover base that is open on the front side and has a plurality of game ball passages therein, and a front cover that closes the front end of the cover base.

  The cover base of the foul cover unit 540 has a first sphere inlet 542a that is disposed in the upper right corner when viewed from the rear and penetrates in the front-rear direction, and a first base that communicates with the first sphere inlet and expands to the right in the front view toward the front end of the cover base 542. One ball passage, a second ball inlet 542c arranged outside the first ball inlet 542a (on the right side in the rear view) and having a larger opening than the first ball inlet 542a, and communicated with the second ball passage and inside the cover base And a second sphere inlet 542c that extends downward and is inclined toward the lower right corner when viewed from the front. The first ball inlet 542a and the second ball inlet 542c are the normal ball outlet 774 and the full ball outlet 776 of the full tank branching unit 770 in the prize ball unit 700 in a state where the door frame 5 is closed with respect to the main body frame 3. Are formed at positions facing each other. In the second ball passage in the cover base, the height of the portion extending in the left-right direction along the lower end is about three times as high as the outer diameter of the game ball. An accommodating space that can be accommodated is formed.

  Further, the cover base 542 is arranged at a substantially upper center in the left-right direction and has a foul ball inlet 542e that opens upward, and a foul that communicates with the foul ball inlet 542e and can guide the game ball to the upper portion near the downstream of the second ball passage. And a ball passage. In addition, the cover base includes an opening / closing operation piece for operating the opening / closing shutter 792 of the bulb outlet opening / closing unit 790 on the lower rear surface of the second bulb entrance. When the door frame 5 is closed with respect to the main body frame 3, the opening / closing operation piece contacts the spherical contact portion of the opening / closing crank in the ball outlet opening / closing unit 790, thereby rotating the opening / closing crank and opening / closing the shutter 792. It can be in an open state.

  The front cover of the foul cover unit 540 is formed in a substantially plate shape that closes the front surface of the cover base, and is disposed in the upper left corner of the front view and communicates with the first ball passage of the cover base and penetrates in the front-rear direction. An outlet, and a second ball outlet that is disposed in the lower right corner of the front view and communicates with the downstream end of the second ball passage of the cover base 542 and penetrates in the front-rear direction. A first ball outlet of the front cover is connected to an upper plate ball supply port of the plate unit 300 through a notch portion of the door frame base unit 100. Further, the rear end of the lower tray ball supply bowl in the tray unit 300 is connected to the second ball outlet through the ball passage opening of the door frame base main body 110.

  The foul cover unit 540 transfers the game balls supplied from the normal ball outlet 774 of the full tank branching unit 770 in the prize ball unit 700 to the first ball inlet 542a from the first ball outlet to the dish unit 300 through the first ball passage. It can supply to the upper plate 301 through the upper plate ball supply port. Further, the foul cover unit 540 passes the game ball supplied from the full tank outlet 776 of the full tank branch unit 770 in the prize ball unit 700 to the second ball inlet 542c from the second ball outlet through the second ball passage. The plate unit 300 can be supplied to the lower plate 302 via the lower plate ball supply basket and the lower plate ball supply port.

  Further, in the foul cover unit 540, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e is positioned below the foul space 626 of the main body frame 3, and the ball hitting device When the game ball launched by 650 does not reach the game area 1100 and becomes a foul ball and falls in the foul space 626, the game ball is received by the foul ball inlet 542e. The foul cover unit 540 can discharge (supply) the game balls received at the foul ball inlet 542e from the second ball outlet to the lower plate 302 of the dish unit 300 through the foul ball passage and the second ball passage. It can be done.

  Further, the foul cover unit 540 forms an upstream (left side in front view) side surface of the accommodation space in the second ball passage and is pivotally supported by the cover base so as to be swingable by a game ball stored in the accommodation space. A member, a full tank switch 550 that detects the swing of the swing member, and a spring that biases the swing member in a non-detection state by the full switch 550. The swinging member is pivotally supported at the lower end with respect to the cover base, and the upper end is rotated leftward when viewed from the front. It comes to form. Further, the swing member is biased to a position where the swing member is in a substantially vertical state by a spring. Further, the swinging member is formed with a detection piece projecting outward on the side surface opposite to the accommodation space side, and this detection piece is detected by the full switch 550. That is, based on the detection signal from the full tank switch 550, it can be determined whether or not the game ball in which the accommodation space is stored is full.

[5. Overall configuration of game board]
Next, the overall configuration of the game board 4 will be described with reference to FIGS. FIG. 8 is a front view of the game board, and FIG. 9 is an exploded perspective view of the game board of FIG. As shown in FIGS. 8 and 9, the game board 4 has an outer rail 1111 and an inner rail 1112, and a game area 1100 in which a game ball as a game medium is driven when the player operates the handle device 500. A frame-shaped front component member 1110 that defines an outer periphery, and a position that is visible from the game window 101 of the door frame 5 to the player side when attached to the pachinko gaming machine 1 at the lower right corner of the front component member 1110 when viewed from the front. And a plurality of openings 1158 penetrating in the front-rear direction in a predetermined shape at positions corresponding to the game area 1100 and attached to the rear side of the front component member 1110 so as to close the game area 1100. A plate-like gaming panel 1150, a front unit 2000 attached from the front side to the opening 1158 of the gaming panel 1150, and a gaming panel A back unit 3000 is attached to the rear surface 150, and a.

  Further, the game board 4 is disposed between the game panel 1150 and the back unit 3000, and is inserted from the rear side of the game panel 1150 into a plurality of light-emitting decorative holes that penetrate the game panel 1150. A panel lens member 2500, a liquid crystal display device that is detachably attached to the rear side of the back unit 3000 and that can display a predetermined effect image that is visible from the player side according to the gaming state, and a lower part of the back unit 3000 Is provided with a board holder 1160 attached to the lower part of the rear surface of the game panel 1150 and a main control board box 1170 attached to the rear surface of the board holder 1160.

[5-1. Previous component]
Next, the front component member 1110 will be described. The front component member 1110 has a substantially rectangular shape whose outer shape can be inserted into the game board holding port 601 of the main body frame 3, and has an inner shape that penetrates in a front-rear direction in a substantially circular shape. The outer periphery of the region 1100 is partitioned. The front component member 1110 has an outer rail 1111 that extends in an arc shape from the lower left end toward the left side from the center in the left-right direction in a front view and extends to the upper right side through the center upper end in the left-right direction in the front view. An inner rail 1112 that is arranged substantially inside the outer rail 1111 along the outer rail 1111 and extends in an arc shape from the center lower part in the left-right direction in front view to the upper left part in the front view so as to smoothly continue from the lower end of the inner rail 1112 An inner peripheral rail 1113 extending in an arc shape to a position below the end (upper end) of the outer rail 1111 along the counterclockwise circumferential direction when viewed from the front, and the end (upper end) of the inner peripheral rail 1113 and the outer rail 1111 , The inner rail 1112 and the inner peripheral rail 1113, which can be contacted with the game ball rolling along the outer rail 1111. Is located at the lowermost end of the game area 1100 at the boundary of the outer area, and is supported by the upper end of the inner rail 1112 so as to be rotatable, and closes between the outer rail 1111. In this way, it is possible to rotate only between a closed position that extends upward from the upper end of the inner rail 1112 and an open position that rotates clockwise from the front and opens the outer rail 1111. And a backflow preventing member 1116 biased by a spring so as to return to the closed position side.

  When the front component member 1110 is in a state where the game board 4 is attached to the main body frame 3, the lower end opening between the outer rail 1111 and the inner rail 1112 is a launch rail 660 in the hitting ball launcher 650 of the main body frame 3 (FIG. 1). )). Between the lower end of the outer rail 1111 and the upper end of the firing rail 660, a space extending in the left-right direction and downward is formed, and a game ball launched along the firing rail 660 of the hitting ball launcher 650 is Then, it jumps over the space and is driven between the outer rail 1111 and the inner rail 1112 from the lower end opening between the outer rail 1111 and the inner rail 1112. The game ball driven between the outer rail 1111 and the inner rail 1112 rolls upward along the outer rail 1111 according to the momentum, and the backflow prevention member 1116 pivotally supported on the upper end of the inner rail 1112 is moved. The player can enter the game area 1100 by rotating it toward the open position against the biasing force.

  In addition, when the game ball is strongly hit by the hit ball launching device 650, the game ball that rolls along the outer rail 1111 in the game area 1100 comes into contact with the stop portion 1114 provided at the end of the outer rail 1111. The rolling direction of the game ball can be forcibly changed by the game ball coming into contact with the stop 1114, and the game ball rolls continuously from the outer rail 1111 to the inner rail 1113. It can be prevented from moving. Note that even if a game ball that has entered (injected into) the game area 1100 attempts to return between the outer rail 1111 and the inner rail 1112, the backflow prevention member 1116 returns to the closed position by the biasing force before that. Thus, the backflow prevention member 1116 prevents the backflow of the game ball.

  In addition, if the game ball that has been driven into the game area 1100 is not received by the start opening 2101, 2102 or the winning opening 2103, 2104, 2201, etc. of the table unit 2000, it flows down to the lower end of the game area 1100, The out-port guide surface 1115 at the boundary between the inner rail 1112 and the inner peripheral rail 1113 is guided to the out-port 1151 of the game panel 1150 and discharged from the out-port 1151 downward to the rear side of the game board 4. .

  On the other hand, if the game ball launched from the hitting ball launcher 650 cannot enter the game area 1100 beyond the backflow prevention member 1116 at the tip of the inner rail 1112, the outer rail 1111 and the inner rail 1112 A foul space 626 formed between the upper end of the firing rail 660 and the lower end of the outer rail 1111 from the lower end opening between the outer rail 1111 and the inner rail 1112. 1 (see FIG. 1) is dropped and is received by the foul ball inlet 542e (see FIG. 1) of the foul cover unit 540 attached to the door frame 5 located below the foul space 626. It is discharged to the lower plate 302 (see FIG. 7).

  Note that the outer rail 1111 in the front component member 1110 has a metal plate attached to the surface thereof, so that the wear resistance due to rolling of the game ball is enhanced and the game ball rolls smoothly. ing. In addition, the stopper 1114 has an elastic body such as rubber or synthetic resin on the surface, and even if the game ball rolls vigorously along the outer rail 1111 and collides, the impact is reduced. The game ball can be repelled inward.

  In addition, the front component member 1110 is spaced apart in the vertical direction at the left end when viewed from the front, is recessed from the front to the rear and is opened at the left end, and is spaced apart from the right end when viewed from the front in the vertical direction. A pair of game board stoppers 1120 arranged, a fixed recess 1121 which is disposed on the left side of the front view of the outer rail 1111 and opened downward and opened downward, and has an arcuate upper side and recessed from the front side, and a lower end of the front view And a ball passage cutout 1122 that is cut out in a rectangular shape extending in the left-right direction upward from the lower end. The positioning concave portion 1119 of the front component member 1110 is fitted with a positioning member 956 (see FIG. 5) attached to the inside of the side crime prevention plate 950 in the main body frame 3, thereby allowing the game board holding port 601 (see FIG. 5). It is possible to restrict the left end of the game board 4 inserted in the front view from moving in the front-rear direction. The game board stopper 1120 can be detachably locked to the game board locking portion of the main body frame base 600 in the main body frame 3, and the game board stopper 1120 is connected to the game board. By locking to the stop portion, the right end of the game board 4 inserted into the game board holding port 601 of the main body frame 3 can be restricted from moving in the front-rear direction.

  Further, the fixing recess 1121 of the front component member 1110 has a game board fixture 690 (see FIG. 5) pivotally supported on the front surface of the main body frame 3 in a state where the game board 4 is inserted into the game board holding port 601 of the main body frame 3. (See FIG. 5) is inserted into the game board fixing tool 690, and the game board fixing tool 690 allows the game board 4 to be inserted. The lower end of the head is restricted from moving forward. Further, the ball passage cutout portion 1122 of the front component member 1110 is formed with the same ball passage cutout portion 1152 at the same position of the game panel 1150, and the game board 4 is connected to the game board holding port 601 of the main body frame 3. In the inserted state, the front end of the full tank branching unit 770 (see FIG. 5) is inserted into the notches 1122 and 1152 for the ball passage.

  A function display unit 1180, which will be described later, is arranged at the lower right of the front component member 1110 when viewed from the front.

[5-2. Table unit]
Next, the front unit 2000 of the game board 4 will be described. The front unit 200 includes an attacker unit 2100 that is disposed at a substantially lower center in the left-right direction in the gaming area 1100 and above the out port 1151 and is supported by the front surface of the gaming panel 1150. And a side prize opening member 2200 supported along the front surface of the gaming panel 1150 and a frame-shaped center accessory 2300 disposed approximately at the center of the gaming area 1100 and supported by the gaming panel 1150. Yes.

  The front unit 2000 is inserted from the front side into an opening 1158 formed at a position corresponding to the gaming area 1100 in the gaming panel 1150 and is attached to the front surface of the gaming panel 1150. A portion protruding forward from the game panel 1150 is positioned in the game area 1100. As a result, the front unit 2000 comes into contact with the game ball that has been driven into the game area 1100 at an appropriate position, and together with the obstacle nail implanted on the front surface of the game panel 1150, Can be changed. The table unit 2000 can decorate the game area 1100.

[5-2-1. Attacker unit]
Next, the attacker unit 2100 of the table unit 2000 will be described. The attacker unit 2100 has a plurality of entrances (winning entrances) through which game balls driven into the game area 1100 can be received. Specifically, the attacker unit 2100 is arranged at a substantially central position in the left-right direction. A start port 2101, a lower start port 2102 disposed below the upper start port 2101, and a rectangular disposed below the lower start port 2102 and extending more in the left-right direction than the upper start port 2101 and the lower start port 2102 A large winning opening 2103 having a shape, and a general winning opening 2104 arranged slightly on the left and right sides of the large winning opening 2103 are provided. The game balls received in the upper start opening 2101, the lower start opening 2102, the big winning opening 2103, and the general winning opening 2104 are guided from the front side of the game panel 1150 to the rear side.

  The upper start port 2101 of the attacker unit 2100 is open on the upper side, so that game balls can always be received (winning). On the other hand, a pair of movable pieces 2106 that can be expanded by a start port solenoid 2105 (see FIG. 99) is disposed between the lower start port 2102 arranged below the upper start port 2101 and the upper start port 2101. In the state where the pair of movable pieces 2106 rises substantially vertically, the upper starting port 2101 and the pair of movable pieces 2106 make it impossible to receive the game ball into the lower starting port 2102, whereas the pair of movable pieces 2106 In a state where the piece 2106 is expanded in the left-right direction, a game ball can be received in the lower start port 2102. That is, the lower start opening 2102 is a variable winning opening by the pair of movable pieces 2106. The pair of movable pieces 2106 are opened and closed by driving the start opening solenoid 2105 based on detection of the passage of the game ball by the gate switch 2352 of the gate portion 2350 in the center accessory 2300 described later.

  Further, the special winning opening 2103 of the attacker unit 2100 can be opened and closed by a horizontally long rectangular opening and closing member 2107 that can close the opening. The opening / closing member 2107 is pivotally supported at its lower side, and in a substantially vertical state, the big prize opening 2103 can be closed to make it impossible to receive a game ball, and the upper side can move forward. When it is rotated, the special winning opening 2103 is opened so that a game ball can be received. The opening / closing member 2107 is in a state in which the big prize opening 2103 is closed in a normal gaming state, and a special lottery is drawn when a game ball is received (starts winning) into the upper start opening 2101 or the lower start opening 2102. Depending on the lottery result (when the special lottery result is “big hit” or “small hit”), the attacker solenoid 2108 (see FIG. 99) is driven to open and close.

  Furthermore, the general winning opening 2104 of the attacker unit 2100 is opened upward so that game balls can be received (winned) at all times.

  Although not shown in detail, the attacker unit 2100 has a lower start port switch 2109 for detecting a game ball received in the lower start port 2102 and a count switch for detecting a game ball received in the big winning port 2103. The game ball detected by the lower start port switch 2109 and the count switch 2110 is discharged onto the bottom wall portion of the substrate holder 1160. The back unit 3000 includes an upper start port switch 3022 for detecting a game ball received in the upper start port 2101 and a general winning port switch 3020 for detecting a game ball received in the general winning port 2104. .

[5-2-2. Side prize opening member]
Next, the side prize opening member 2200 of the front unit 2000 will be described. The side winning opening member 2200 is inserted from the front side with respect to the opening 1158 formed on the left side of the opening 1158 in which the attacker unit 2100 is inserted and fixed at the lower left side from the center in the left-right direction of the game panel 1150. Above, two fixed to the front surface of the gaming panel 1150 and facing each other along the outer periphery of the gaming area 1100 so as to line up with the general winning port 2104 on the left side of the front view in the attacker unit 2100 A general winning opening 2201 is provided. These two general winning holes 2201 are opened upward so that game balls can be received (winning) at all times, and the game balls received in the general winning holes 2201 are guided from the front side of the game panel 1150 to the rear side. Then, it is detected by a general prize opening switch 3020 provided in the back unit 3000 described later.

  Further, the side prize opening member 2200 is arranged at a position where the left end is substantially in contact with the outer periphery of the game area 1100 at the upper left end of the side prize opening member 2200, and is inclined so as to become lower toward the right end. The shelf portion 2202 and the first shelf portion 2202 are arranged on the opposite side and the lower side with the two general winning holes 2201 sandwiched therebetween, and the center side in the left-right direction of the game area 1100 (the lower start opening 2102 and the big winning opening of the attacker unit 2100) A second shelf 2203 that becomes lower toward the game area 1100), and the first shelf 2202 can bring the game balls that have flowed down along the outer periphery of the game area 1100 toward the center of the game area 1100. It can be done.

  Note that the two general winning ports 2201 are arranged on the right side of the right end of the first shelf 2202, and even if the game balls are brought closer to the center of the game area 1100 by the first shelf 2202, There is a possibility of winning a prize in the general winning opening 2201. A third shelf 2204 that is inclined so as to become lower toward the center side of the game area 1100 is also provided on the upper side between the two general winning ports 2201.

  The side prize port member 2200 is formed so as to have a light-transmitting property as a whole, and although detailed illustration is omitted, a side prize port decoration board is provided on the rear side of the second shelf 2203. At the same time, a side lamp decorative board 3014 in a back unit 3000, which will be described later, is arranged on the rear side of the side prize opening member 2200. Can be decorated with light emission.

[5-2-3. Center character]
Next, the center accessory 2300 of the table unit 2000 will be described. The center accessory 2300 is inserted from the front side into an opening 1158 that is formed so as to penetrate substantially the center of the game panel 1150, and is fixed to the front surface of the game panel 1150. It is formed in a frame shape with a size that occupies most of the area 1100, and the outer peripheral surface on the right side when viewed from the front is in an arc shape so that a gap slightly larger than the outer diameter of the game ball is formed between the outer periphery of the game area 1100 The left outer peripheral surface is formed on a substantially straight line that hangs down so that a region having a predetermined width is formed between the outer peripheral surface of the game region 1100 and the outer periphery.

  The center accessory 2300 is an upper shelf portion 2301 that is inclined so as to become lower toward the left side from the position slightly on the right side in the center in the left-right direction on the outer peripheral surface on the upper side of the front wall portion located on the front surface of the game panel 1150. When a game ball driven into the upper part of the game area 1100 flows down to the upper shelf 2301, it flows down to the left of the center accessory 2300, and on the right side of the upper shelf 2301. The game balls that have flowed down (invaded) flow down to the lower part of the game area 1100 through the right side of the center bonus 2300. In other words, when a game ball is driven so that the game ball enters the right side of the upper shelf 2301 in the center accessory 2300, the chance of enjoying the flow of the game ball is reduced. It is possible to appropriately adjust the length, and to maintain a sense of tension and to suppress a loose game.

  Further, the center accessory 2300 has entered a warp inlet 2302 in which a game ball flowing down the game area 1100 can enter the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150 and the warp inlet 2302. A warp exit (not shown) that releases the game ball into the frame, and a game ball released from the warp exit rolls in the left-right direction, and then releases it into the game area 1100 above the attacker unit 2100. And a stage 2310 formed on the upper surface of the lower side in the frame in 2300.

  Although the detailed illustration of the stage 2310 in the center accessory 2300 is omitted, the game ball released from the warp outlet is supplied, and the game ball is placed on the front side of the first stage from the first stage. A second stage that is supplied and is capable of releasing a game ball into the game area 1100. This stage 2310 is formed in a curved surface shape such that the approximate center in the left-right direction is lowered. In addition, a chance entrance 2313 into which a game ball can enter is formed at the rear side of the center of the first stage in the left-right direction. The game is discharged from the exit 2314 into the game area 1100. The chance exit 2314 is arranged immediately above the upper start opening 2101 in the attacker unit 2100, and the game ball released from the chance exit 2314 is received (wins) with high probability by the upper start opening 2101. ing.

  The stage 2310 in the center accessory 2300 is formed of a transparent member, and through this stage 2310, the decorative body arranged below the stage 2310 in the back unit 3000 is visible from the player side. It has become.

  Further, the center accessory 2300 is a transparent member extending leftward so as to be substantially in contact with the inner rail 1112 above the warp entrance 2302 on the left outer peripheral surface of the front wall portion located on the front side of the game panel 1150. An arch portion 2315 is further provided. The arch portion 2315 extends in a thin plate shape from a substantially front end of the front wall portion, and forms a space through which a game ball can pass between the arch portion 2315 and the front surface of the game panel 1150. Thereby, the game ball that is driven into the upper part of the game area 1100 and guided to the left of the center accessory 2300 by the upper shelf 2301 flows down to the downstream side through the rear side of the arch part 2315. .

  Further, the center accessory 2300 includes a gate portion 2350 that detects the passage of a game ball in the vicinity of the arch portion 2315 on the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150. The gate portion 2350 detects a game entrance that is arranged on the left outer peripheral surface of the front wall portion above the arch portion 2315 and allows a game ball flowing down the game area 1100 to enter, and a game ball that has entered the gate entrance. A gate switch 2352 for discharging the game ball detected by the gate switch 2352 from the outer peripheral surface of the front wall portion to the game area 1100. In the present embodiment, although detailed illustration is omitted, the gate outlet of the gate portion 2350 is formed at the same height as the arch portion 2315, and the game ball detected by the gate switch 2352 is The portion 2315 can be seen as if diving.

[5-3. Panel lens member]
Next, the panel lens member 2500 of the game board 4 will be described. The panel lens member 2500 has a plurality of light emitting elements formed so as to penetrate in the front-rear direction in a circular or X shape at a position outside the opening 1158 in which the center accessory 2300 is inserted in the gaming area 1100 of the gaming panel 1150. The decorative hole is used for luminescent decoration. The panel lens member 2500 includes a transparent upper panel lens 2510 corresponding to a plurality of light emitting decoration holes formed on the upper left side of the outer periphery of the center accessory 2300, and a plurality of light emitting decoration holes disposed on the rear side of the upper panel lens 2510. An upper panel lens substrate on which the LED is mounted, a transparent lower panel lens 2520 corresponding to a plurality of light emitting decoration holes formed on the lower left side of the outer periphery of the center accessory 2300, and a rear side of the lower panel lens 2520. And a lower panel lens substrate on which a plurality of LEDs are mounted.

  The upper panel lens 2510 and the lower panel lens 2520 in the panel lens member 2500 protrude forward from the plate-like lens base portion, and have a plurality of rod-shaped insertion light guides that have substantially the same shape as the light emitting decoration hole to be inserted. Department. In a state where the insertion light guide portion is inserted into the light emitting decoration hole of the game panel 1150 from the rear side, the tip is formed so as to substantially coincide with the front surface of the game panel 1150, and the game flows down the front surface of the game panel 1150. The ball is not affected as much as possible.

  The panel lens member 2500 can illuminate and decorate the area where the game ball flows even if an opaque game panel 1150 such as a veneer plywood is used by appropriately emitting the LEDs of the upper panel lens substrate and the lower panel lens substrate. In addition to being able to show the player the decoration of the gaming panel 1150 that has never been seen before, the pachinko gaming machine 1 can be conspicuous and differentiated from other pachinko gaming machines.

[5-4. Back unit]
Next, the back unit 3000 of the game board 4 will be described. The back unit 3000 is attached and fixed to the rear surface of the game panel 1150, and a back box 3001 that supports the liquid crystal display device 1900 at a position away from the game panel 1150 by a predetermined distance, and a liquid crystal display in the back box 3001. The upper unit 3100 disposed on the upper side of the device 1900, the character unit 3400 disposed on the right side of the liquid crystal display device 1900 in the back box 3001, and the gear decoration disposed on the left side of the liquid crystal display device 1900 in the back box 3001. And a body unit 3500.

  Further, the back unit 3000 is disposed at a position corresponding to the side prize opening member 2200 in the front unit 2000 attached to the front surface of the game panel 1150 near the lower left front end of the back box 3001, and a plurality of LEDs are mounted on the surface. A side lamp decoration board 3014 and a game ball attached to the lower front end of the back box 3001 and received in the general winning port 2201 of the side winning port member 2200, and a game received in the left general winning port 2104 in the attacker unit 2100 A left guiding member 3016 for guiding the ball downward, and a right guiding the game ball disposed on the right side of the left guiding member 3016 and received in the upper start port 2101 and the right general winning port 2104 on the attacker unit 2100. The guide member 3018 is mainly provided.

  Further, although not shown in detail, the back unit 3000 is disposed in the lower rear portion of the back box 3001 and has a horizontally-long rectangular lamp drive board box 3423 that accommodates the lamp drive board 4170, and a lower part of the lamp drive board box 3423. The motor drive board box 3430 having a horizontally long rectangular shape that is disposed on the side and accommodates the motor drive board 4180 and the lamp drive board box 3423 and the motor drive board box 3430 fixed to the rear side of the back box 3001 are arranged on the left side when viewed from the rear. A panel relay terminal plate 4161, a horizontally-long rectangular upper resistance substrate disposed at the upper rear side of the back box 3001, and a lock member attached to the rear side of the back box 3001 for detachably holding the liquid crystal display device 1900. Are further provided.

  In this embodiment, the back unit 3000 can be viewed from the player side through the frame of the center accessory 2300 in the front unit 2000, and each unit 3100, 3400 shaped into a predetermined shape. , 3500, etc., the concept of the pachinko gaming machine 1 can be characterized. Further, the back unit 3000 is configured such that each unit 3100, 3400, 3500 can move independently or in conjunction with each other depending on the gaming state. It is possible to suggest the arrival of a game or a chance, and to entertain the player.

[5-4-1. Back box]
Next, the back box 3001 of the back unit 3000 will be described. The back box 3001 is formed in a box shape with the front side open, and is provided with a plurality of flange-shaped fixing portions 3001a projecting outward at the front end, and on the rear side of the game panel 1150 via the fixing portions 3001a. It is supposed to be fixed. Further, the back box 3001 is formed with a rectangular opening substantially at the center of the rear wall, and the liquid crystal display device 1900 supported on the rear side through this opening can be viewed from the player side. Further, the back box 3001 is provided with mounting portions at appropriate positions for mounting and fixing the units 3100, 3400, 3500, the substrates 3014, and the like.

  Although not shown, the back box 3001 inserts and locks one fixing piece 1902 that protrudes outward from the left and right sides of the liquid crystal display device 1900 to the right of the opening in the rear view (right side in the rear view). A liquid crystal support unit is provided, and a lock member is attached to the left side of the opening in the rear view. A display device 1900 is detachably attached to the rear side of the back box 3001.

[5-4-2. Guide member]
Next, the left guide member 3016 and the right guide member 3018 will be described. The left guiding member 3016 guides and discharges the game balls received in the general winning port 2201 of the side winning port member 2200 and the general winning port 2104 on the left side of the attacker unit 2100 downward through different flow paths. Each of the flow paths is provided with a general winning opening switch 3020 for detecting the passage of the game ball. On the other hand, the right guiding member 3018 guides and discharges the game balls received in the upper start opening 2101 and the right general winning opening 2104 on the attacker unit 2100 downward through different flow paths to the vicinity of the lower end. The upper start opening switch 3022 is provided in the flow path corresponding to the upper start opening 2101, and the general winning opening switch 3020 is provided in the flow path corresponding to the right general winning opening 2104. The right guide member 3018 is provided with a magnetic detection switch 3024 that can detect magnetism.

  The game balls guided downward by the left guide member 3016 and the right guide member 3018 are discharged onto the bottom wall portion of the substrate holder 1160, and are discharged downward from the game board 4 from the out ball discharge portion 1161 of the substrate holder 1160. It has become so.

[5-4-3. Upper unit]
Next, the upper unit 3100 will be described. The upper unit 3100 is formed to be horizontally long as a whole, and is attached and fixed to the upper side of the opening facing the liquid crystal display device 1900 in the back box 3001. The upper unit 3100 is disposed on the front surface at a substantially central position in the left-right direction and is circular in a front view, and a lifting mechanism that moves up and down the rotational decoration body unit 3200. 3250, a swing decorative body unit 3300 disposed substantially at the center in the left-right direction on the rear side of the lifting mechanism 3250, and a movable ceiling unit 3350 disposed on the left and right sides of the swing decorative body unit 3300. ing.

  The rotating ornament body unit 3200 can be moved up and down by an elevating mechanism 3250 between a raised position located above the liquid crystal display device 1900 and a lowered position located substantially in the center of the liquid crystal display device 1900. It has become. The rotating decorative body unit 3200 is configured such that a rotating decorative body formed in the shape of a shuriken arranged on the front surface is rotated, and the rotation radius of the rotating decorative body is increased by the centrifugal force by rotating. It is like that.

  In addition, the rotating ornament body unit 3200 not only rotates at the end but also protrudes outward in the radial direction, so that the rotation radius of the entire rotating ornament body expands and the appearance changes greatly. It is possible to make it possible to give a strong impact to the player, to entertain the player and to suppress a decrease in interest in the game, and to attract the player's interest strongly Therefore, the pachinko gaming machine 1 can be easily selected as a pachinko gaming machine that is greatly differentiated from other pachinko gaming machines.

  The swing ornament body unit 3300 includes swing ornament bodies disposed on the left and right sides of the swing ornament body unit 3200 so as to be adjacent to the rotary ornament body unit 3200 positioned at the ascending position. The body can be swung to the left and right at the same time.

  The movable ceiling unit 3350 includes plate-like ceiling decoration bodies that extend in the horizontal direction at the left and right ends of the upper unit 3100. This ceiling decoration body is formed so as to be rotatable around an axis extending in the left-right direction with the front end side as a center, so that the rear end side of the ceiling decoration body is lowered in a descending direction according to the gaming state. It has become.

[5-4-4. Character unit]
Next, the character unit 3400 of the back unit 3000 will be described. The character unit 3400 includes a character body that is shaped like a ninja and is three-dimensionally shaped, and the character body moves in the left-right direction from the right end position toward the center side according to the gaming state. Can be done. Further, when the character body of the character unit 3400 moves in the left-right direction, the character body 3400 is rotated by a predetermined angle around an axis extending in the up-down direction along with the movement.

  Further, the character body of the character unit 3400 can reciprocate around an axis in which the head extends in the left-right direction, and can reciprocate around the axis in which the right arm extends in the up-down direction. Can be done. Thus, by reciprocating the head, it is possible to perform an action as if the character is scolding. Further, by reciprocating the right arm in the horizontal direction, it is possible to perform an action as if the character is throwing a shuriken.

[5-4-5. Gear decoration body unit]
Next, the gear decoration body unit 3500 of the back unit 3000 will be described. The gear decoration body unit 3500 is provided with a gear-shaped gear decoration body that is rotatable around an axis extending in the left-right direction and is arranged in a plurality of vertical directions. It is designed to rotate.

[5-4-6. Liquid crystal display device]
Next, the liquid crystal display device 1900 of the game board 4 will be described. The liquid crystal display device 1900 is detachably attached to the rear surface of the back box 3001 of the back unit 3000, and can display a predetermined effect image according to the gaming state. The liquid crystal display device 1900 includes a fixed piece 1902 that protrudes outward from the left and right sides, and is attached to the back box 3001 via the fixed piece 1902.

  Although not shown in detail, the liquid crystal display device 1900 includes a peripheral board box 1905 that houses a peripheral control board 4140 on the rear side.

[6. Function display unit]
Next, the function display unit 1180 in the game board 4 will be described with reference to FIG. This function display unit 1180 is mounted and disposed at a predetermined position of the front component member 1110. FIG. 10 is an enlarged front view showing the function display unit in the game board in a state of being attached to the pachinko gaming machine.

  As shown in an enlarged view in FIG. 10, the function display unit 1180 is a game state display composed of one LED for displaying a game state that is changed by a game ball driven into the game area 1100 at the left end of the front view. An upper special symbol memory display 1184 for displaying the number of holdings relating to the reception of the game ball to the upper start port 2101, which consists of two LEDs arranged vertically on the right side of the game machine 1183 and the game status indicator 1183, Upper special symbol comprising one 7-segment LED for displaying the first special lottery result arranged as the first special symbol, which is arranged on the right side of the special symbol memory display 1184 and is drawn by receiving the game ball into the upper start port 2101 Display 1185 and the second special symbol placed on the upper right of the upper special symbol display 1185 and drawn by receiving a game ball into the lower start port 2102 A lower special indicator 1186 composed of one 7-segment LED for displaying a separate lottery result as a second special symbol, and a lower start port comprising two LEDs arranged in the vertical direction on the right side of the lower special symbol indicator 1186 And a lower special symbol memory display 1187 for displaying the number of holdings relating to the reception of the game ball in 2102.

  The display unit 1181 of the function display unit 1180 displays the number of suspensions related to the passage of the gate unit 2350 by the game balls that are arranged in a circular arc substantially along the inner peripheral rail 1113 from directly above the lower special symbol display 1186. The normal symbol memory display 1188 composed of the four LEDs and the normal lottery result which is placed under the normal symbol memory display and the game ball passes through the gate portion 2350 is displayed as a normal symbol. The normal symbol display 1189 made of one LED and the normal symbol memory display 1188 are arranged side by side diagonally to the upper right, and the first prize lottery result or the second special lottery result is “big hit”, and the opening / closing of the big prize opening 2103 A round indicator 1190 composed of two LEDs for displaying the number of repetitions of the pattern (number of rounds).

  The gaming status indicator 1183 is a full-color LED that can change the emission color of red, green, and orange, and various gaming statuses (in combination with lighting / flashing) For example, a probability variation state, a time shortening state, a probability variation short state, a big hit game state, a small hit game state, etc.) can be displayed.

  When the upper special symbol display 1184 cannot display the first special symbol in the upper special symbol display 1185 in a variable manner, if the game ball is received in the upper start port 2101, the start of the variable display is suspended ( The number of stored first special symbols (stored) is displayed. In addition, the special symbol memory display 1184 has a first special symbol memory lamp 1184a and a first special symbol memory lamp 1184b made of predetermined LEDs. The first special symbol memory lamps 1184a and 1184b are turned on / off. The number of holds can be displayed by the blinking pattern. Specifically, for example, the first special symbol memory lamp 1184a is turned on and the first special symbol memory lamp 1184b is turned off when the number of holdings is one, and the first special symbol memory lamps 1184a and 1184b when the number of holdings is two. When the number of holds is 3, the first special symbol memory lamp 1184a blinks and the first special symbol memory lamp 1184b is lit. When the number of held is 4, the first special symbol memory lamps 1184a and 1184b are both It is blinking. In the present embodiment, up to four are reserved.

  When the lower special symbol display 1187 cannot display the second special symbol in the lower special symbol display 1186 variably, if the game ball is received in the lower start port 2102, the start of the variable display is suspended ( The number of stored second special symbols (stored) is displayed. The lower special symbol memory indicator 1187 has a second special symbol memory lamp 1187a and a second special symbol memory lamp 1187b made of predetermined LEDs. The second special symbol memory lamps 1187a and 1187b are turned on / off. The number of holds can be displayed by the blinking pattern. Specifically, for example, the second special symbol memory lamp 1187a is turned on and the second special symbol memory lamp 1187b is turned off when the number of reserved is 1, and the second special symbol memory display lamp 1187a, When the number of holdings is three, the second special symbol memory lamp 1187a blinks and the second special symbol memory lamp 1187b is lit. When the number of holdings is four, the second special symbol memory lamps 1187a and 1187b are turned on. Both are blinking. In the present embodiment, up to four are reserved.

  The upper special symbol display 1185 and the lower special symbol display 1186 display the first special lottery result and the second special lottery result which are drawn by receiving the game balls to the upper start port 2101 and the lower start port 2102. The 7-segment LED stops after it fluctuates for a predetermined time according to the special lottery result, and the first special lottery result and the second special lottery result are played according to the light emission pattern (special symbol) of the stopped 7-segment LED. It can be made to recognize the person side.

  The normal symbol display 1189 is a full-color LED that can change the emission color of red, green, and orange, and the gate portion 2350 can be played by a combination of the emission color and lighting / flashing. A normal lottery result drawn by passing a ball can be displayed. In addition, the display of the normal symbol by the normal symbol display 1189 is also stopped and displayed with the light emission pattern corresponding to the normal lottery result after being displayed for a predetermined period of time, like the special symbol.

  The normal symbol memory display 1188 is a normal symbol whose start of variable display is suspended (stored) when a game ball passes through the gate part 2350 when the normal symbol display 1189 cannot display the normal symbol in a variable manner. The number of hold (number of storage) is displayed. The normal symbol memory display 1188 includes four normal symbol memory lamps 1188a to 1188d arranged side by side from below, each of which is a predetermined LED, and the normal symbol memory lamp 1188a from the bottom according to the number of holds. By sequentially lighting up to 1188d, it is possible to display the number of reserved normal symbols. In the present embodiment, up to four normal symbol fluctuation displays are held (stored).

  The round indicator 1190 includes a two-round display lamp 1190a made of predetermined LEDs and a 15-round display lamp 1190b, and can display the number of rounds in a “hit” game by lighting each lamp. It is like that.

  Further, as shown in FIG. 10, the function display unit 1180 can be viewed from the player side through the game window 101 of the door frame 5 with the game board 4 attached to the pachinko gaming machine 1. Yes. Game status indicator 1183, upper special symbol memory display 1184, upper special symbol indicator 1185, lower special symbol indicator 1186, lower special symbol memory indicator 1187, normal symbol memory indicator 1188, normal symbol indicator 1189, and The round indicator 1190 is attached to the front surface of the function display board 1191. Note that a connection terminal for connecting the function display board 1191 and the main control board 4100 is attached to the rear end of the rearward projecting portion of the function display unit 1180.

  In this embodiment, since the function display unit 1180 is provided in the front component member 1110 of the game board 4, as compared with the case where it is provided in the front unit 2000 and the back unit 3000 attached to the game panel 1150, The function display unit 1180 can be used as the basic configuration of the game board 4, the configuration related to the pachinko gaming machine 1 can be simplified to prevent an increase in cost, and the model of the pachinko gaming machine 1 (table The position of the function display unit 1180 does not change even if the detailed configuration of the game board 4 that is embodied by the unit 2000 or the back unit 3000 and can characterize the model of the pachinko gaming machine 1 is different. Let the hall clerk recognize the position of the function display unit 1180 without confusion. So that the can.

[7. Main control board, payout control board and peripheral control board]
Next, a control board for performing various controls of the pachinko gaming machine 1 will be described with reference to FIGS. 11 is a block diagram of the main control board, the payout control board, and the peripheral control board, FIG. 12 is a block diagram showing a continuation of FIG. 11, and FIG. 13 is a payout control board, CR unit and frequency constituting the main board. FIG. 14 is a schematic diagram of various detection signals input / output to / from a lending device connection terminal board such as a game ball that relays an electrical connection with the display board, FIG. 14 is a block diagram showing a continuation of FIG. 11, and FIG. FIG. 16 is a block diagram showing an outline of the peripheral control MPU, and FIG. 16 is a block diagram around the sound source built-in VDP in the liquid crystal and sound control unit.

  As shown in FIG. 11, the control configuration of the pachinko gaming machine 1 is mainly configured by a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and various controls are shared. First, the main control board will be described, and then the payout control board, the power supply board, and the peripheral control board will be described.

[7-1. Main control board]
As shown in FIG. 11, the main control board 4100 for controlling the progress of the game is a main control MPU 4100a which is a microprocessor in which a ROM for storing various control programs and various commands, a RAM for temporarily storing data, and the like are incorporated. A main control input circuit 4100b to which detection signals from various detection switches are input, a main control output circuit 4100c for outputting various signals to an external substrate, etc., and a main control solenoid drive for driving various solenoids The circuit mainly includes a circuit 4100d and a power failure monitoring circuit 4100e that monitors a sign of a power failure or instantaneous power failure at a predetermined voltage.

  The main control MPU 4100a includes a built-in RAM (hereinafter referred to as “main control built-in RAM”) and a built-in ROM (hereinafter referred to as “main control built-in ROM”). In addition, a watchdog timer for monitoring the operation (system), a function for preventing fraud, and the like are also incorporated.

  The main control MPU 4100a has a built-in nonvolatile RAM. In this non-volatile RAM, a unique ID code with a unique code (a code that exists only in the world) for identifying an individual by the manufacturer that manufactured the main control MPU 4100a is stored in advance. Since the ID code once attached is stored in the nonvolatile RAM, it cannot be rewritten using an external device. The main control MPU 4100a can take out the ID code from the nonvolatile RAM and refer to it.

  The main control input circuit 4100b is not provided with a reset terminal for forcibly resetting information whose detection signals from various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the main control input circuit 4100b is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control input circuit 4100b does not reset the information based on the detection signals from the various detection switches input to the various input terminals by a main control system reset to be described later. The circuit is configured to be output from the output terminal.

  The main control output circuit 4100c is configured as an open collector output type in which an emitter terminal is grounded with a ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. Main control output circuit 4100ca with a reset function having a reset function in which a reset terminal for forcibly resetting the received information is provided, and a main control output circuit 4100cb without reset function without a reset function in which no reset terminal is provided. And is composed of. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is input. That is, the main control output circuit 4100ca with a reset function is reset when information for outputting various signals input to the various input terminals to an external board or the like is reset by a main control system reset described later. Is configured as a circuit that does not output any signal from the various output terminals. On the other hand, the main control output circuit 4100cb without a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control output circuit 4100cb having no reset function does not reset the information for outputting various signals input to the various input terminals to an external board or the like by a main control system reset described later. The signal based on this is comprised as a circuit from which the various output terminals are output.

  As shown in FIG. 8, the upper start port switch 3022 for detecting the game ball that has entered the upper start port 2101, the lower start port switch 2109 for detecting the game ball that has entered the lower start port 2102, and the general winning port 2104 A detection signal from the general winning opening switch 3020 for detecting a game ball that has entered and a signal from the power failure monitoring circuit 4100e are input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. Yes. In addition, as shown in FIG. 8, the gate switch 2352 that detects the game ball that has passed through the gate portion 2350, the general winning port switch 3020 that detects the gaming ball that has entered the general winning port 2201, and the big winning port 2103 are entered. A detection signal from a count switch 2110 that detects a game ball and a magnetic detection switch 3024 that is attached to the back unit 3000 shown in FIG. The signal is inputted to the input terminal of a predetermined input port of the main control MPU 4100a through the terminal board 4161 and the main control input circuit 4100b.

  The main control MPU 4100a outputs a drive signal from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function based on the detection signals from these switches, so that the main control output circuit with reset function is output. 4100ca outputs a control signal to the main control solenoid drive circuit 4100d, and outputs a drive signal from the main control solenoid drive circuit 4100d to the start port solenoid 2105 and the attacker solenoid 2108 via the panel relay terminal plate 4161, or a predetermined output thereof. By outputting a drive signal from the output terminal of the port to the main control output circuit 4100ca with reset function, the upper special symbol display from the main control output circuit 4100ca with reset function via the panel relay terminal board 4161 and the function display board 1191 1185, Drive signals to the special symbol display 1186, the upper special symbol storage display 1184, the lower special symbol storage display 1187, the normal symbol display 1189, the normal symbol storage display 1188, the game state display 1183, and the round display 1190 Or output.

  Further, the main control MPU 4100a outputs various information (game information) relating to the game from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function, so that payout control is performed from the main control output circuit 4100ca with reset function. Main control output with reset function by outputting various information (game information) to the substrate 4110 or by outputting a signal (power failure clear signal) from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function A signal (power failure clear signal) is output from the circuit 4100ca to the power failure monitoring circuit 4100e.

  In this embodiment, the upper start port switch 3022, the lower start port switch 2109, the gate switch 2352, and the count switch 2110 use non-contact type electromagnetic proximity switches, whereas Contact type ON / OFF operation type mechanical switches are used for the prize opening switches 3020 and 3020. This is because game balls frequently enter the upper start opening 2101 and the lower start opening 2102 and frequently pass through the gate portion 2350, so the upper start opening switch 3022, the lower start opening switch 2109, and the gate switch 2352 Detection of game balls also occurs frequently. Therefore, long-life proximity switches are used as the upper start port 3022, the lower start port switch 2109, and the gate switch 2352. In addition, when a big hit gaming state that is advantageous to the player occurs, the game winning balls 2103 are opened and game balls are frequently entered, so that the game balls are frequently detected by the count switch 2110. For this reason, a proximity switch having a long life is also used as the count switch 2110. On the other hand, detection by the general winning opening switches 3020 and 3020 does not occur frequently in the general winning opening 2104 and 2201 where game balls do not enter frequently. For this reason, mechanical switches having a shorter lifetime than the proximity switches are used as the general winning award opening switches 3020 and 3020.

  Also, the main control MPU 4100a transmits various commands relating to payout as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100cb without reset function, thereby controlling payout from the main control output circuit 4100cb without reset function. Various commands are transmitted to the substrate 4110 as serial data. When the payout control board 4110 completes normal reception of various commands from the main control board 4100 as serial data, the payout control board 4110 outputs a signal to that effect (payer ACK signal) to the main control board 4100. This signal (payer ACK signal) is input to an input terminal of a predetermined input port of the main control MPU 4100a through the main control input circuit 4100b.

  Also, the main control MPU 4100a receives various commands related to the state of the pachinko gaming machine 1 from the payout control board 4110 as serial data by the main control input circuit 4100b, so that the main control input circuit 4100b receives the predetermined serial input port. Receives various commands as serial data at the input terminal. When the main control MPU 4100a completes normal reception of various commands from the payout control board 4110 as serial data, a main control output with a reset function is sent from the output terminal of the predetermined output port to that effect (main payout ACK signal). The signal is output to the circuit 4100ca, and a signal (main payment ACK signal) is output from the main control output circuit 4100ca with reset function to the payout control board 4110.

  Further, the main control MPU 4100a transmits, as serial data, various commands relating to control of game effects and various commands relating to the state of the pachinko gaming machine 1 from the output terminal of the predetermined serial output port to the main control output circuit 4100cb having no reset function. Thus, various commands are transmitted as serial data from the main control output circuit 4100cb having no reset function to the peripheral control board 4140.

  Here, a main peripheral serial transmission port for transmitting various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is configured with a main control CPU core 4100aa as the center. In addition to the main control built-in RAM, a main peripheral serial transmission port 4100ae, which is one of various main control serial I / O ports, is connected to the bus 4100ah. Circuit connection (see FIG. 21). The main peripheral serial transmission port 4100ae transmits various commands as main peripheral serial data to the peripheral control board 4140, and mainly includes a transmission shift register 4100aea, a transmission buffer register 4100aeb, a serial management unit 4100aec, and the like (FIG. 21). When the main control CPU core 4100aa sets a command in the transmission buffer register 4100aeb and outputs a transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec sends the command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb. The data is transferred to the transmission shift register 4100aea, and transmission to the peripheral control board 4140 is started as main peripheral serial data. In the present embodiment, the transmission buffer register 4100aeb has a storage capacity of 32 bytes. The main control CPU core 4100aa continuously sends a plurality of commands to the peripheral control board 4140 by setting a plurality of commands in the transmission buffer register 4100aeb and then outputting a transmission start signal to the serial management unit 4100aec.

  The power supply board 851 for supplying various voltages to the main control board 4100 is an electric double layer capacitor (hereinafter simply referred to as “capacitor”) as a backup power supply for supplying power to the main control board 4100 for a predetermined time even when the power is shut off. BC0 (see FIG. 17). The capacitor BC0 allows the main control MPU 4100a to store various types of information in the main control built-in RAM even when the power is turned off. Various kinds of information stored in the main control built-in RAM are stored in the operation signal (RAM clear signal) from the operation switch 860a when an operation switch 860a of a payout control board 4110 (to be described later) is operated within a predetermined period from when the power is turned on. Is output from the payout control board 4110 and input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b, and triggered by this, the main control MPU 4100a completely erases it from the main control built-in RAM. (Clear).

[7-2. Dispensing control board]
As shown in FIG. 12, the payout control board 4110 for controlling the payout of game balls, etc., has a payout control unit 4120 for performing various controls related to payout, an operation switch 860a that also serves various functions, and the state of the pachinko gaming machine 1. And an error LED indicator 860b for displaying.

[7-2-1. Dispensing control unit]
As shown in FIG. 12, a payout control unit 4120 that performs various controls relating to payouts is a payout control MPU 4120a that is a microprocessor that includes a ROM that stores various control programs and various commands, a RAM that temporarily stores data, and the like. , A payout control input circuit 4120b to which detection signals from various detection switches relating to payout are input, a payout control output circuit 4120c for outputting various signals to an external substrate or the like, and the prize ball device 740 shown in FIG. A payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744, and a CR unit input / output circuit 4120e for exchanging various signals with the CR unit 6. The payout control MPU 4120a includes a built-in RAM (hereinafter referred to as “payout control built-in RAM”) and a built-in ROM (hereinafter referred to as “payout control built-in ROM”). In addition, a watchdog timer for monitoring the operation (system), a function for preventing fraud, and the like are also incorporated.

  The payout control input circuit 4120b is not provided with a reset terminal for forcibly resetting information whose detection signals from the various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the payout control input circuit 4120b is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. In other words, the payout control input circuit 4120b does not reset the information based on the detection signals from the various detection switches inputted to the various input terminals by a payout control system reset to be described later. The circuit is configured to be output from the output terminal.

  The payout control output circuit 4120c is configured as an open collector output type in which the emitter terminal is grounded with the ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. Payout control output circuit 4120ca with a reset function having a reset function in which a reset terminal for forcibly resetting the received information is provided, and a payout control output circuit 4120cb without reset function having no reset function in which no reset terminal is provided And is composed of. The payout control output circuit 4120ca with a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is input. That is, the payout control output circuit 4120ca with a reset function resets the information for outputting various signals input to the various input terminals to an external substrate or the like by a payout control system reset described later, and the information Is configured as a circuit that does not output any signal from the various output terminals. In contrast, the payout control output circuit 4120cb without a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. In other words, the payout control output circuit 4120cb without the reset function does not reset the information for outputting the various signals input to the various input terminals to an external substrate or the like by the payout control system reset described later. The signal based on this is comprised as a circuit from which the various output terminals are output.

  A detection signal from a ball break switch 750 that detects the presence or absence of a game ball in the supply passage of the prize ball device 740 and a count switch 751 that detects a game ball flowing down in the prize ball device 740 is first a prize. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a through the prize ball case substrate 754 of the ball device 740 and the payout control input circuit 4120b. The detection signals from the rotation angle switch 752 for detecting the detection slit formed on the rotation detection board of the prize ball device 740 are first a rotation angle switch board 753 of the prize ball device 740, a prize ball case inner board 754, and It is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  The detection signals from the door frame opening switch 618 for detecting the opening of the door frame 5 with respect to the main body frame 3 and the main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 are sent to the payout control input circuit 4120b. To the input terminal of a predetermined input port of the payout control MPU 4120a.

  Further, the detection signal from the full switch 550 for detecting whether or not the storage space of the foul cover unit 540 shown in FIG. 851 and the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  The payout control MPU 4120a receives various commands relating to payout from the main control board 4100 at the input terminal of the serial input port via the payout control input circuit 4120b. When the payout control MPU 4120a completes the normal reception of various commands from the main control board 4100 as serial data, a payout control output with a reset function is sent from the output terminal of the predetermined output port. By outputting to the circuit 4120ca, a signal (payer ACK signal) is output from the payout control output circuit with reset function 4120ca to the main control board 4100.

  Also, the payout control MPU 4120a sends out various commands for indicating the state of the pachinko gaming machine 1 from the output terminal of the serial output port as serial data to the payout control output circuit 4120cb without the reset function, thereby giving out the payout without the reset function. Various commands are transmitted as serial data from the control output circuit 4120cb to the main control board 4100. When the main control board 4100 completes normal reception of various commands from the payout control board 4110 as serial data, the main control board 4100 outputs a signal (main payment ACK signal) to that effect to the payout control board 4110. This signal (main payment ACK signal) is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  Also, the payout control MPU 4120a outputs a drive signal for driving the payout motor 744 from the output terminal of the predetermined output port to the payout control output circuit 4120ca with reset function, so that the payout control output circuit 4120ca with reset function is output. Is output to the payout motor drive circuit 4120d, and the drive signal is output from the payout motor drive circuit 4120d to the payout motor 744 via the prize ball case substrate 754, or from the output terminal of the predetermined output port. By outputting a drive signal for displaying the state of the gaming machine 1 on the error LED indicator 860b to the payout control output circuit 4120ca with reset function, the drive signal is output from the error LED indicator 860b with the reset function payout control output circuit 4120ca. Or output to

  The error LED display 860b is a segment display, and displays the state of the pachinko gaming machine 1 by displaying alphanumeric characters and figures. The contents displayed and notified by the error LED indicator 860b include the following. For example, when the figure “-” is displayed, it is notified that it is “normal”, and when the numeral “0” is displayed, it indicates that it is “connection abnormality” (specifically, with the main control board 4100). The fact that there is an abnormality in electrical connection between the board and the payout control board 4110) is notified, and when the number “1” is displayed, it is “out of ball” (specifically, out of ball) Based on the detection signal from the switch 750, it is notified that there is no game ball in the supply passage of the prize ball device 740, and when the number “2” is displayed, it means that “the ball is clear” (specifically, Is based on the detection signal from the rotation angle switch 752, and the payout rotator and the game ball are meshed in the vicinity of the entrance at the entrance of the distribution space communicating with the supply passage of the prize ball device 740, and the payout rotator is difficult to rotate. Number) When “3” is displayed, the fact that it is a “counter switch error” (specifically, that a malfunction has occurred in the count switch 751 based on a detection signal from the count switch 751) is notified, and the number “ When “5” is displayed, it is informed that it is a “retry error” (specifically, that the number of retries of the payout operation has reached a preset upper limit value), and the number “6” is displayed. When it is, it is informed that it is “full” (specifically, based on the detection signal from the full tank switch 550, the game ball in which the accommodation space of the foul cover unit 540 is stored is full) When the number “7” is displayed, it is reported that “CR is not connected” (electrical connection is cut off from either the payout control board 4110 to the CR unit 6). However, when the number “9” is displayed, the fact that it is “in stock” (specifically, the number of game balls that have not been paid out has reached a predetermined number of balls) is notified. Yes.

  Also, the payout control MPU 4120a outputs the number of game balls actually paid out from the output terminal of the predetermined output port to the payout control output circuit 4120ca with reset function, thereby outputting the payout control output circuit 4120ca with reset function. The number of game balls actually paid out is output to the external terminal board 784 through a resistor (not shown).

  Also, the payout control board 4110 outputs various information (game information) related to the game from the main control board 4100 to the external terminal board 784 via a resistor (not shown). The external terminal board 784 is provided with a plurality of photocouplers (not shown) (infrared LEDs and photo ICs are built in), and a game hall (hole) is provided via the plurality of photocouplers. ), The number of game balls and various information (game information) are transmitted to the hall computer. The external terminal board 784 and the hall computer are electrically insulated by a plurality of photocouplers, and an abnormal voltage is applied to the hall computer via the external terminal board 784 of the pachinko gaming machine 1. The hall computer does not malfunction or break down, and the main control board 4100 that advances the game from the hall computer via the external terminal board 784 of the pachinko gaming machine 1 and the payout control board that controls the payout etc. An abnormal voltage is applied to 4110 to prevent malfunction or failure. The hall computer monitors the player's game by grasping the number of game balls paid out by the pachinko gaming machine 1 and the game information of the pachinko gaming machine 1.

  The ball lending request signal for the game ball from the ball lending switch 365a of the ball lending unit 360 shown in FIG. 2 and the return request signal for the prepaid card from the return switch 365b are first the frequency display board 365 and the main door relay terminal board 880. And, it is input to the CR unit 6 through a lending device connection terminal board 869 such as a game ball. The CR unit 6 transmits a signal designating the number of game balls to be lent according to the ball lending request signal to the payout control board 4110 via the gaming ball lending device connection terminal board 869 in a serial manner, and this signal is transmitted to the CR unit. It is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the input / output circuit 4120e. In addition, the CR unit 6 updates the remaining degree of the prepaid card inserted according to the number of rented game balls, and displays a signal for displaying the remaining degree on the remaining number display 365c, such as a game sphere. The signal is output to the lending device connection terminal plate 869, the main door relay terminal plate 880, and the frequency display plate 365, and this signal is input to the remaining frequency display 365c. In addition, the CR unit lamp 365d adjacent to the remaining frequency indicator 365c is supplied with the supply voltage from the CR unit 6 via the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. Yes.

  The power supply board 851 for supplying various voltages to the payout control board 4110 includes a capacitor BC1 (see FIG. 17) as a backup power supply for supplying power to the payout control board 4110 for a predetermined time even when the power is shut off. Yes. With the capacitor BC1, the payout control MPU 4120a can store various types of information in the payout control built-in RAM even when the power is turned off. Various types of information stored in the payout control built-in RAM are stored in the payout control MPU 4120a via the payout control input circuit 4120b when the operation switch 860a is operated within a predetermined period from when the power is turned on. The payout control MPU 4120a input to the input terminal of the input port determines as a RAM clear signal for completely erasing the information stored in the payout control built-in RAM, and triggered by this from the payout control built-in RAM by the payout control MPU 4120a. It is completely erased (cleared). This operation signal (RAM clear signal) is output to the payout control output circuit 4120cb without reset function, and is output to the main control board 4100 from the payout control output circuit 4120cb without reset function.

[7-2-2. Exchange of various signals with game ball rental device connection terminal board]
Here, the exchange of various signals between the payout control unit 4120 and the CR unit 6 and the exchange of various signals between the CR unit 6 and the frequency display board 365 will be described with reference to FIG. As shown in FIG. 13, the game ball lending device connection terminal board 869 relays the electrical connection between the CR unit 6 and the payout control board 4110 as well as the CR unit 6 and the frequency display board 365. (To be precise, the game ball rental device connection terminal plate 869 is electrically connected to the frequency display plate 365 via the main door relay terminal plate 880. The CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected, the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880 are electrically connected, and the main door relay Terminal board 880 and frequency display board 365 are electrically connected). Between the board of CR unit 6 and gaming ball lending device connection terminal plate 869, between the gaming ball lending device connection terminal plate 869 and payout control board 4110, gaming ball lending device connection terminal plate 869 and main door relay. The board between the terminal board 880 and the board between the game ball lending device connection terminal board 869 and the frequency display board 365 are electrically connected by wiring (harness), respectively. In addition, AC24V, which will be described later, from the power supply board 851 is supplied to the CR unit 6 via a gaming ball rental device connecting terminal plate 869. The CR unit 6 generates a predetermined voltage VL (in this embodiment, DC +12 V (DC +12 V, hereinafter referred to as “+12 V”)) from the supplied AC 24 V by a built-in voltage generation circuit (not shown) together with the ground LG. The game ball lending device connection terminal plate 869 is supplied to the payout control board 4110, while the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880 are supplied to the frequency display plate 365. .

  The frequency display board 365 has a ball lending switch 365a, which is a push button switch, mounted on the component surface at a position corresponding to the lending button 361 of the lending unit 360 shown in FIG. A return switch 365b, which is a push button switch, is mounted at a position corresponding to the button 362, and a remaining frequency display 365c, which is a segment display, is mounted at a position corresponding to the remaining lending display section 363 of the rental unit 360.

  The ball rental switch 365a and the return switch 365b are electrically connected to the ground LG from the CR unit 6 via a game ball rental device connection terminal plate 869 and a main door relay terminal plate 880. When the ball lending button 361 is pressed, the ball lending switch 365a is turned on (the ball lending switch 365a is turned on), and the ball lending operation signal TDS from the ball lending switch 365a is transmitted to the main door relay terminal plate 880 and the game. It is inputted to the CR unit 6 through a ball lending device connection terminal board 869. When the return button 365b is pressed, the return switch 365b is turned on (turned on), and the return operation signal RES from the return switch 365b is connected to the main door relay terminal plate 880 and a rental device such as a game ball. The signal is input to the CR unit 6 through the terminal board 869.

  The remaining frequency indicator 365c is composed of three segment indicators arranged in a line. Of these three digit segment indicators, one digit segment indicator is sequentially driven, so-called dynamic lighting system is used for three digits. The segment display is controlled to be lit. By such lighting control, the remaining frequency indicator 365c displays the remaining amount of the prepaid card inserted into the CR unit 6 or displays an error of the CR unit 6. The remaining frequency indicator 365c includes digit signals DG0 to DG2 (three signals in total) for designating one-digit segment indicator among the three-digit segment indicator, and the designated one-digit segment indicator. Segment drive signals SEG-A to SEG-G (a total of 7 signals) for designating the contents to be lit and displayed are connected from the CR unit 6 to the lending device connection terminal board 869 such as a game ball and the main door relay terminal board When input via the 880, a one-digit segment indicator is sequentially emitted according to the input digit signals DG0 to DG2 and segment drive signals SEG-A to SEG-G, and these three-digit segment indicators The contents due to the light emission can be visually recognized through the lending remaining display portion 363.

  A CR unit lamp 365d is mounted on the frequency display board 365 adjacent to the remaining frequency display 365c. The CR unit lamp 365d is supplied with a predetermined voltage VL from the CR unit 6 via a game ball lending device connection terminal plate 869 and a main door relay terminal plate 880. The predetermined voltage VL is input to the CR unit 6 as a ball lending available signal TDL through a current limiting resistor mounted on the gaming ball lending device connection terminal plate 869 via the CR unit lamp 365d. The CR unit 6 creates a predetermined voltage VL from the AC 24 V supplied from the power supply board 851 by the built-in voltage creation circuit, and the ball rental switch 365a and the return switch 365b are in a valid ball rental state. Controls the logic of the ball lending available signal TDL to cause the CR unit lamp 365d to emit light, and this light emission can be visually recognized through the lending remaining display portion 363. Further, the segment drive signals SEG-A to SEG-G are input to the remaining frequency indicator 365c through a current limiting resistor mounted on the gaming ball lending device connection terminal board 869.

  In the CR unit 6, the ball lending button 361 is pressed, and the ball lending operation signal TDS from the ball lending switch 365a is transmitted from the frequency display plate 365 via the main door relay terminal plate 880 and the game ball lending device connection terminal plate 869. When inputted, the ball rental request signal BRDY is output to the payout control board 4110 (payout control MPU 4120a) via the game ball lending device connecting terminal board 869. The CR unit 6 performs a single payout operation start request signal for paying out a predetermined number of rented balls (in this embodiment, 25 balls, corresponding to 100 yen as an amount) in one payout operation. Is output to the payout control board 4110 (the payout control MPU 4120a) via the gaming ball rental device connecting terminal board 869. The payout control board 4110 (payout control MPU 4120a) to which BRDY and BRQ are input, sends EXS, which is a signal for notifying that the one payout operation has been started or ended, to the lending device connection terminal board 869 such as a game ball. A ball terminal for connecting a device such as a game ball to output a PRDY signal indicating that the payout operation for outputting the ball or paying out the ball is possible or impossible. 869 to output to the CR unit 6. In addition, for example, when a hall clerk or the like is preset in the CR unit 6 so that a game ball of 200 yen is paid out when the ball rental button 361 is pressed, one payout operation is performed. Is performed twice in succession, and when 25 balls for 100 yen are paid out, 25 balls for 100 yen are paid out, and 50 balls for a total of 200 yen are paid out. Become.

  In the CR unit 6, the return button 362 is pressed, and a return operation signal RES from the return switch 365 b is input from the frequency display board 365 via the main door relay terminal board 880 and the game ball lending device connection terminal board 869. The prepaid card is discharged from an insertion slot (not shown) and returned. The returned prepaid card stores a remaining amount obtained by subtracting an amount corresponding to the number of game balls paid out as a result of the ball rental button 361 being pressed.

[7-3. Power supply board]
Next, the power supply board 851 will be briefly described. The power supply board 851 is supplied from the Pachinko Island facility, and can be electrically connected to or disconnected from AC 24 volts (AC24V), and a power supply control unit 855 that generates various power supplies. And a launch control unit 857 that performs launch control by the launch solenoid 654 of the hit ball launcher 650 shown in FIG. 5 and ball feed control by the ball feed solenoid 585 of the ball feed unit 580 shown in FIG.

[7-3-1. Power control unit]
The power control unit 855 operates the power switch 852 to improve the power factor of the power rectified by the synchronous rectifier circuit 855a that rectifies the AC 24 volts (AC 24V) supplied from the pachinko island facility and the synchronous rectifier circuit 855a. Power factor correction circuit 855b, smoothing circuit 855c for smoothing the power whose power factor has been improved by power factor improvement circuit 855b, and various direct currents for supplying power smoothed by smoothing circuit 855c to various substrates A power generation circuit 855d for generating a power supply.
[7-3-2. Launch control unit]
A launch control unit 857 that performs launch control by the launch solenoid 654 and ball feed control by the ball feed solenoid 585 mainly includes a launch control circuit 857a. The launch control circuit 857a includes an operation signal from a potentiometer 512 that electrically adjusts the strength (launch strength) of launching a game ball toward the game area 1100 in accordance with the rotational position of the front 506 of the rotary handle body shown in FIG. , A detection signal from the touch switch 516 for detecting whether or not a palm or a finger is touching the front 506 of the rotating handle body, and whether or not to forcibly stop the launch (launch) of the game ball according to the player's will A detection signal from the firing stop switch 518 to be detected is input via the handle relay terminal plate 192. In addition, when the CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected to each other, the launch control circuit 857a receives a CR connection signal to that effect via the payout control board 4110. .

  The firing control circuit 857a is based on the operation signal from the potentiometer 512 that electrically adjusts the launch strength (launch strength) corresponding to the rotational position of the front of the rotary handle body 506 based on the operation signal from the potentiometer 512, and the rotary handle. While controlling the drive current for launching (launching) the game ball toward the game area 1100 and outputting it to the launch solenoid 654, a constant current is supplied to the ball feed solenoid 585 via the handle relay terminal plate 192. , The ball feeding member of the ball feeding unit 580 accepts one game ball stored in the upper plate 301 of the dish unit 300 shown in FIG. 7, and the game ball received by the ball feeding member is a ball hitting device 650. Control to send to the side.

[7-4. Peripheral control board]
As shown in FIG. 14, the peripheral control board 4140 includes a peripheral control unit 4150 that performs effect control based on various commands from the main control board 4100, a game board side liquid crystal display device 1900, and an upper plate side liquid crystal display device 470. A liquid crystal and sound control unit 4160 that performs drawing control and sound control such as music and sound effects flowing from the speaker housed in the speaker box 820 shown in FIG. 5 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. A real-time clock (hereinafter referred to as “RTC”) control unit 4165 that holds calendar information for specifying the date and time and time information for specifying the hour, minute, and second, and a speaker box 820 provided in the main body frame 3 Sound that adjusts the volume of music, sound effects, etc. flowing from the speaker housed in the speaker and the speaker 130 provided on the door frame 5 by rotating the knob. It comprises an adjusting volumes 4140A, a.

[7-4-1. Peripheral control unit]
As shown in FIG. 14, the peripheral control unit 4150 for effect control includes a peripheral control MPU 4150a as a microprocessor, a peripheral control ROM 4150b for storing various control programs, various data, various control data, and various schedule data, and will be described later. Various information (for example, drawing on the game board side liquid crystal display device 1900) that is continued across the peripheral control unit steady process that is executed each time the V blank signal from the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 is input. Peripheral control RAM 4150c for storing schedule data for defining screens, information for managing schedule data for defining light emission modes such as various LEDs, and the like, and various types of information (for example, big hit gaming state) continued across days Information and specials for managing the history of occurrence Peripheral control SRAM 4150d for storing information for managing production flags and the like, and peripheral control external watchdog timer 4150e (hereinafter referred to as "peripheral control external WDT 4150e" for monitoring whether or not peripheral control MPU 4150a is operating normally. ").).

  Peripheral control RAM 4150c can retain the stored content only for the time when power is restored immediately after an instantaneous power failure, and power is cut off for a long time (when a long-time power interruption occurs) ), The peripheral control SRAM 4150d is supplied with backup power by a large-capacity electrolytic capacitor (not shown) provided on the power supply board 851 (hereinafter referred to as “electrolytic capacitor for SRAM”). Thus, the stored contents can be held for about 50 hours. By providing the electrolytic capacitor for SRAM on the power supply board 851, when the game board 4 is detached from the pachinko gaming machine 1, backup power is not supplied to the peripheral control SRAM 4150d. Therefore, the peripheral control SRAM 4150d stores the stored contents. Loses its contents because it can no longer hold.

  The peripheral control external WDT 4150e is a timer for monitoring whether or not the system of the peripheral control MPU 4150a is running out of control. When this timer expires, a hardware reset is performed. That is, the peripheral control MPU 4150a is reset when a clear signal for clearing the timer of the peripheral control external WDT 4150e is not output to the peripheral control external WDT 4150e within a certain period (until the timer expires). When the peripheral control MPU 4150a outputs a clear signal to the peripheral control external WDT 4150e within a certain period, the peripheral control external WDT 4150e can restart the timer count of the peripheral control external WDT 4150e, and therefore no reset is applied.

  The peripheral control MPU 4150a incorporates a plurality of parallel I / O ports, serial I / O ports, and the like, and upon receiving various commands from the main control board 4100, each decorative board of the game board 4 is received based on these various commands. The game board side light emission data for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs etc. provided in the lamp is outputted from the serial I / O port for lamp driving board via a peripheral control output circuit (not shown). The game board side motor drive data for transmitting a drive signal to an electric drive source such as a motor or a solenoid for transmitting various kinds of movable bodies provided in the game board 4 to the drive board 4170 is serialized for the motor drive board. Transmission from the I / O port to the motor drive board 4180 via the peripheral control output circuit, or the power of the dial drive motor 414 provided on the door frame 5 or the like. Door side motor drive data for outputting a drive signal to the general drive source from the frame decoration drive amplifier board motor serial I / O port to the peripheral control output circuit, frame peripheral relay terminal plate 868, and peripheral door relay terminal plate 882 The door-side light emission data for transmitting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs provided on each decoration board of the door frame 5 is transmitted to the frame decoration drive amplifier board 194 via The frame decoration drive amplifier board LED serial I / O port transmits the frame decoration drive amplifier board 194 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882.

  Various commands from the main control board 4100 are input to the serial I / O port for main control board of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). In addition, a detection signal from a rotation detection switch for detecting the rotation (rotation direction) of the dial operation unit 401 and a pressure detection switch for detecting the operation of the pressing operation unit 405 provided in the operation unit 400. The detection signal is serialized by a door-side serial transmission circuit (not shown) provided on the frame decoration drive amplifier board 194, and the serialized operation unit detection data is transmitted from the door-side serial transmission circuit to the peripheral door relay terminal plate 882, the frame. The signal is input to the operation unit detection serial I / O port of the peripheral control MPU 4150a via the peripheral relay terminal plate 868 and the peripheral control input circuit.

  Detection signals from various detection switches (for example, photosensors) for detecting the original positions and movable positions of various movable bodies provided on the game board 4 are on the game board side (not shown) provided on the motor drive board 4180. Serialized by the serial transmission circuit, and this serialized movable body detection data is input to the serial I / O port for the motor drive board of the peripheral control MPU 4150a from the serial transmission circuit on the game board via the peripheral control input circuit. Yes. The peripheral control MPU 4150a exchanges various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input / output of the serial I / O port for the motor drive board.

  Peripheral control MPU 4150a has a built-in watchdog timer (hereinafter referred to as “peripheral control built-in WDT”). It is diagnosed whether or not.

[7-4-1a. Peripheral control MPU]
Next, the peripheral control MPU 4150a which is a microcomputer will be described. As shown in FIG. 15, the peripheral control MPU 4150a has a peripheral control built-in RAM 4150ab, a peripheral control DMA (Direct Memory Access) controller 4150ac, a peripheral control bus controller 4150ad, a peripheral control various serial I, and the peripheral control CPU core 4150aa. / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, peripheral control analog / digital converter (hereinafter referred to as peripheral control A / D converter) 4150ak, and the like.

  Peripheral control CPU core 4150aa reads / writes various data to / from peripheral control built-in RAM 4150ab and peripheral control DMA controller 4150ac via internal bus 4150ah, while peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, Various data are read from and written to the various peripheral control parallel I / O ports 4150ag and the peripheral control A / D converter 4150ak via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai.

  The peripheral control CPU core 4150aa reads various data from the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while reading from the peripheral control RAM 4150c and the peripheral control SRAM 4150d. Various data are read and written via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h.

  The peripheral control DMA controller 4150ac includes storage devices such as a peripheral control built-in RAM 4150ab, a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag and a dedicated controller that performs data transfer independently between devices such as the peripheral control A / D converter 4150ak and the peripheral control CPU core 4150aa without using the DMA0 ~ It has four channels called DMA3.

  Specifically, the peripheral control DMA controller 4150ac includes a storage device of a peripheral control built-in RAM 4150ab incorporated in the peripheral control MPU 4150a, various peripheral control serial I / O ports 4150ae and peripheral control built-in WDT 4150af incorporated in the peripheral control MPU 4150a. In order to transfer data independently between the peripheral control various parallel I / O ports 4150ag and the input / output devices such as the peripheral control A / D converter 4150ak without the peripheral control CPU core 4150aa. The peripheral control built-in RAM 4150ab reads / writes data from / to the storage device via the internal bus 4150ah, while the peripheral control serial I / O port 4150ae, the peripheral control built-in WDT 4150af, and the peripheral control various parallel I / O port 4150. g, and the peripheral control A / D converter input and output devices such as 4150Ak, via the peripheral control bus controller 4150ad and peripheral bus 4150Ai, reading and writing.

  The peripheral control DMA controller 4150ac is a storage device such as a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, and various peripheral control serial I / Os built in the peripheral control MPU 4150a. Without the peripheral control CPU core 4150aa between the input / output devices such as the O port 4150ae, the peripheral control built-in WDT 4150af, the peripheral control various parallel I / O ports 4150ag, and the peripheral control A / D converter 4150ak. In order to perform data transfer independently, peripheral control bus controller 4150ad and external bus 4150h are connected to storage devices such as peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d. The peripheral control I / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag, peripheral control A / D converter 4150ak, etc. Reading and writing are performed via the control bus controller 4150ad and the peripheral bus 4150ai.

  The peripheral control bus controller 4150ad controls the internal bus 4150ah, peripheral bus 4150ai, and external bus 4150h to control the central processing unit of the peripheral control MPU core 4150aa, peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control Various devices such as storage devices such as SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, and peripheral control A / D converter 4150ak It is a dedicated controller that exchanges various data between them.

  Peripheral control various serial I / O ports 4150ae are: lamp drive board serial I / O port, motor drive board serial I / O port, frame decoration drive amplifier board motor serial I / O port, frame decoration drive amplifier board LED Serial I / O port, frame decoration drive amplifier board motor serial I / O port, main control board serial I / O port, and operation unit information acquisition serial I / O port.

  Peripheral control built-in watchdog timer (peripheral control built-in WDT) 4150af is a timer for monitoring whether the system of the peripheral control MPU 4150a is running out of control, and when this timer is up, the hardware reset is performed. It has become. In other words, when the watchdog timer is started, the peripheral control CPU core 4150aa resets when the clear signal for clearing the timer is not output to the peripheral control built-in WDT 4150af within a certain period (until the timer is up). Will take. When the peripheral CPU core 4150aa starts the watchdog timer and outputs a clear signal to the peripheral control built-in WDT 4150af within a certain period, the peripheral count CPU core 4150aa can restart the timer count and is not reset.

  The peripheral control various parallel I / O port 4150ag outputs various latch signals such as a game board side motor drive latch signal and a door side motor drive light emission latch signal, and also outputs a clear signal to the peripheral control external WDT 4150e, The detection signals from various detection switches for detecting the original position and the movable position of various movable bodies provided on the board 4 are serialized by a game board side serial transmission circuit (not shown) provided on the motor drive board 4180, and this serial A movable body information acquisition latch signal for receiving the converted movable body detection data from the serial transmission circuit on the game board side by the serial I / O port for the motor drive board of the peripheral control MPU 4150a, or an upper decoration in the door frame 5 The lighting signal of the LED mounted on the upper decorative board of the unit 280 is output. This LED is a high-intensity white LED and serves as a confirmation notification lamp for informing that the occurrence of the big hit gaming state has been confirmed. In the present embodiment, by adopting a configuration in which the LED and the peripheral control various parallel I / O port 4150ag are electrically connected directly, the path between the LED and the peripheral control various parallel I / O port 4150ag is shortened. Therefore, it is possible to take noise countermeasures for lighting control of the LED having a significant meaning in games. The LED lighting control is executed in a peripheral control unit 1 ms timer interrupt process described later, and other LEDs and the like other than this LED are executed in a peripheral control unit steady process described later. It has become.

  The peripheral control A / D converter 4150ak is electrically connected to the volume adjustment volume 4140a, and the resistance value is changed by rotating the knob portion of the volume adjustment volume 4140a, and the resistance at the rotation position of the knob portion is changed. The voltage divided by the value is converted from an analog value to a digital value, and converted to a value in 1024 steps from 0 to 1023. In the present embodiment, the values of 1024 levels are divided into seven and managed as substrate volumes 0-6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The liquid crystal and sound control unit 4160 (a sound source built-in VDP 4160a to be described later) is controlled so that the volume is set to the substrate volume 0 to 6 and the speaker and door frame 5 housed in the speaker box 820 provided in the main body frame 3 Music and sound effects flow from the provided speaker 130. In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by volume adjustment based on the turning operation of the knob portion. .

  In the present embodiment, in addition to music and sound effects, notification sounds for notifying a hall clerk or the like of the occurrence of a malfunction of the pachinko gaming machine 1 or fraudulent acts on the pachinko gaming machine 1, contents relating to game effects, etc. (For example, the screen spread on the game board side liquid crystal display device 1900 is rendered more powerful, or the game state is likely to shift to a game state advantageous to the player). ) Also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are adjusted in volume based on the turning operation of the knob portion. The sound volume flows from the mute to the maximum volume by a liquid crystal and sound control unit 4160 (a sound source built-in VDP 416 described later). So that the it can be adjusted by controlling the a). The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. Thus, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speakers and doors housed in the speaker box 820 provided in the main body frame 3 Although the production sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, the sound volume is increased when a malfunction occurs in the pachinko gaming machine 1 or when the player is cheating. In the embodiment, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, there is a possibility that the screen unfolded on the game board side liquid crystal display device 1900 will be rendered more powerful, or the game state may be shifted to an advantageous game state. You can also announce that it is expensive.

[7-4-1b. Peripheral control ROM]
The peripheral control ROM 4150b stores in advance various control programs, various data, various control data, and various schedule data for controlling the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the RTC control unit 4165, and the like. The various schedule data includes screen generation schedule data for generating a screen to be drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, light emission mode generation schedule data for generating light emission modes of various LEDs, music And sound generation schedule data for generating sound effects and the like, and electric drive source schedule data for generating drive modes of electric drive sources such as motors and solenoids. The screen generation schedule data is configured by arranging time-series screen data for defining the screen configuration, and the order of screens to be drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is defined. Has been. The light emission mode generation schedule data is configured by arranging light emission data defining the light emission modes of various LEDs in time series. The sound generation schedule data is configured by arranging sound command data in time series, and defines the order in which music and sound effects flow. The sound command data includes an output channel number for instructing which output channel to use among a plurality of output channels in a built-in sound source of the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 described later, and a sound source built-in VDP 4160a. A track number for instructing which track to incorporate sound data such as music and sound effects out of a plurality of tracks in the built-in sound source is defined. The electrical drive source schedule data is configured by arranging drive data of electrical drive sources such as motors and solenoids in time series, and defines the operation of electrical drive sources such as motors and solenoids.

  Various control programs stored in the peripheral control ROM 4150b may be read out and executed directly from the peripheral control ROM 4150b, or copied to various control program copy areas of the peripheral control RAM 4150c described later when the power is turned on. Some are read and executed. In addition, various data, various control data, and various schedule data stored in the peripheral control ROM 4150b may be directly read from the peripheral control ROM 4150b, or when various power control data copy areas of the peripheral control RAM 4150c described later are turned on. Some of which are copied in the above are read out.

  Further, the peripheral control ROM 4150b is one of various control programs for controlling the RTC control unit 4165 to correct the luminance of the game board side liquid crystal display device 1900 according to the usage time of the game board side liquid crystal display device 1900. A brightness correction program is included. This brightness correction program corrects a decrease in brightness due to aging of the game board side liquid crystal display device 1900 when the backlight of the game board side liquid crystal display device 1900 is mounted with an LED type. The date and time when the game board side liquid crystal display device 1900 is first turned on, the current date and time, the luminance setting information, and the like are acquired from the built-in RAM of the RTC control unit 4165 described later, and the acquired luminance setting information is based on the correction information. To correct. This correction information is stored in advance in the peripheral control ROM 4150b. As will be described later, the brightness setting information includes brightness adjustment information for adjusting the range of the brightness of the LED, which is the backlight of the game board side liquid crystal display device 1900, from 100% to 70% in increments of 5%, The brightness of the LED that is the backlight of the game board side liquid crystal display device 1900 that is set is included. For example, the date and time when the game board side liquid crystal display device 1900 was first turned on and the current date and time From the date when the game board side liquid crystal display device 1900 is first powered on, when six months have already passed, the corresponding correction information (for example, 5%) is obtained from the peripheral control ROM 4150b, and the brightness When the brightness of the LED included in the setting information is 75% and the backlight of the game board side liquid crystal display device 1900 is turned on, the correction information acquired for this 75% is used. On the game board side, the brightness of the backlight of the game board side liquid crystal display device 1900 is adjusted based on the brightness adjustment information included in the brightness setting information so that the brightness is further increased by 5%. If December has already passed since the date when the liquid crystal display device 1900 was first turned on, the corresponding correction information (for example, 10%) is acquired from the peripheral control ROM 4150b, and the LED included in the luminance setting information When the backlight of the game board side liquid crystal display device 1900 is turned on with the brightness of 75%, the brightness setting is set so that the brightness is further increased by 10%, which is the correction information acquired with respect to 75%, to 85%. Based on the luminance adjustment information included in the information, the luminance of the backlight of the game board side liquid crystal display device 1900 is adjusted to light up.

[7-4-1c. Peripheral control RAM]
As shown in FIG. 15, the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a is a backup that exclusively stores information to be backed up among various information updated by executing various control programs. A management target work area 4150ca, a backup first area 4150cb and a backup second area 4150cc for storing a copy of various information stored in the backup management target work area 4150ca, and a peripheral control ROM 4150b. Various control program copy area 4150cd for storing a copy of the various control programs exclusively, and various data, various control data, various schedule data, etc. stored in peripheral control ROM 4150b, etc. Various control data copy area 4150ce for storing the copied data exclusively, and backup non-management target for storing the information not updated for backup among the various information updated by executing various control programs And a work area 4150cf.

  When the pachinko gaming machine 1 is turned on (including when power is restored due to a momentary power failure or a power failure), the value 0 is forcibly written to the backup unmanaged work area 4150cf and cleared to zero. For the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc, when the power of the pachinko gaming machine 1 is turned on, the power-on command from the main control board 4100 (see FIG. 29) starts the RAM clear effect. And instructing the start of each state effect (for example, instructing the start of the effect when the operation switch 860a shown in FIG. 11 is operated within a predetermined period from when the power is turned on. ) Is cleared to zero.

  The backup management target work area 4150ca is effect information (various information updated in the peripheral control unit steady process executed each time a V blank signal from the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160 described later is input) Bank 0 (1fr) for storing 1fr) exclusively as a backup target, and production information (1ms) which is various information updated in the peripheral control unit 1ms timer interrupt process executed every time a 1ms timer interrupt described later occurs. Bank 0 (1 ms) that is stored exclusively as a backup target. Here, the names of Bank0 (1fr) and Bank0 (1 ms) will be briefly described. “Bank” is a minimum management unit representing the size of a storage area for storing various information. The subsequent “0” means that the storage area is normally used for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. In addition, “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150cb to a backup second area 4150cc, which will be described later, are stored in the same storage area as “Bank0”. It means having a size. As will be described later, “(1fr)” indicates that when the built-in sound source VDP 4160a outputs drawing data for one screen (one frame) to the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, the peripheral control MPU 4150a Since the V blank signal indicating that the screen data from the camera can be received is output to the peripheral control MPU 4150a, every time the V blank signal is input, in other words, one frame (1 frame) Since the peripheral control unit steady process is executed every time, “Bank 0”, “Bank 1”, “Bank 2”, “Bank 3”, and “Bank 4” are appended respectively (effect information (1fr) and effects described later) The backup information (1fr) is also used in the same meaning.) “(1 ms)” will be described later. As described above, each time the 1 ms timer interrupt is generated, the peripheral control unit 1 ms timer interrupt process is executed, so that “Bank 0”, “Bank 1”, “Bank 2”, “Bank 3”, and “Bank 4” are added respectively. (Effect information (1 ms) and later-described effect backup information (1 ms) are also used in the same meaning).

  Bank0 (1fr) includes a lamp drive board side transmission data storage area 4150caa, a frame decoration drive amplifier board side LED transmission data storage area 4150cab, a reception command storage area 4150cac, an RTC information acquisition storage area 4150cad, and a schedule data storage area 4150cae. Etc. are provided. In the lamp drive board side transmission data storage area 4150caa, the game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal or a gradation lighting signal to a plurality of LEDs provided on each decoration board of the game board 4 is provided. Is stored in the frame decoration drive amplifier board side LED transmission data storage area 4150cab in the lighting data, flashing signal, or gradation lighting to a plurality of LEDs provided on each decoration board of the door frame 5. This is a storage area in which door side light emission data STL-DAT for outputting a signal is set. In the reception command storage area 4150cac, various commands transmitted from the main control board 4100 are received and the received various commands are stored. The RTC information acquisition storage area 4150cad has an RTC control unit 4165 (RTC 41654a described later). Various information acquired from the RTC built-in RAM 4165aa) is set in a storage area, and the schedule data storage area 4150cae corresponds to the received command based on the command received from the main control board 4100 (main control MPU 4100a). This is a storage area in which various schedule data are set. In the schedule data storage area 4150cae, some schedule data copied from the peripheral control ROM 4150b to the various control data copy areas 4150ce are read and set, and various schedule data are directly read from the peripheral control ROM 4150b. Some are set.

  Bank 0 (1 ms) is provided with a frame decoration drive amplifier board side motor transmission data storage area 4150caf, a motor drive board side transmission data storage area 4150cag, a movable body information acquisition storage area 4150cah, an operation unit information acquisition storage area 4150cai, and the like. It has been. In the frame decoration drive amplifier board side motor transmission data storage area 4150caf, door side motor drive data STM-DAT for outputting a drive signal to an electric drive source such as a dial drive motor 414 provided in the door frame 5 is stored. This is a storage area to be set, and a motor drive board side transmission data storage area 4150cag is used to output a drive signal to an electric drive source such as a motor or solenoid for operating various movable bodies provided in the game board 4. This is a storage area where the game board side motor drive data SM-DAT is set. The movable body information acquisition storage area 4150cah is provided in the game board 4 based on detection signals from various detection switches provided in the game board 4. This is a storage area in which various information obtained by acquiring the original position and the movable position of various movable bodies is set, and an operation unit information acquisition storage area 4150ca. Includes various information (for example, in the operation unit 400) obtained from the rotation (rotation direction) of the dial operation unit 401 and the operation of the pressing operation unit 405 based on detection signals from various detection switches provided in the operation unit 400. The rotation (rotation direction) history information of the dial operation unit 401, the operation history information of the pressing operation unit 405, and the like created based on detection signals from the various detection switches provided.

  The bank 0 (1fr) lamp drive board side transmission data storage area 4150caa and the frame decoration drive amplifier board side LED transmission data storage area 4150cab, and the Bank 0 (1 ms) frame decoration drive amplifier board side motor transmission data storage area 4150caf. The motor drive board side transmission data storage area 4150cag is divided into two areas, a first area and a second area, respectively.

  In the lamp drive board side transmission data storage area 4150caa, when the peripheral control unit steady process described later is executed, the game board side light emission data SL-DAT is set in the first area of the lamp drive board side transmission data storage area 4150caa. When the next peripheral control unit steady process is executed, the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa. Each time the process is executed, the game board side light emission data SL-DAT are alternately set in the first area and the second area of the lamp drive board side transmission data storage area 4150caa. For example, when the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa in the current peripheral control part steady process, When the control unit steady process is executed, the process proceeds based on the game board side light emission data SL-DAT set in the first area of the lamp drive board side transmission data storage area 4150caa.

  When the peripheral control unit steady process is executed, the frame decoration drive amplifier board side LED transmission data storage area 4150cab has the door side light emission data STL in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. -DAT is set, and when the next peripheral control unit steady process is executed, the door side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. Each time the peripheral control unit steady process is executed, the door side light emission data STL-DAT is alternately set in the first area and the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. The For example, when the door side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab in the current peripheral control part steady process, When the previous peripheral control unit steady process is executed, the process proceeds based on the door side light emission data STL-DAT set in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. It has become.

  The frame decoration drive amplifier board side motor transmission data storage area 4150caf has a door in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when a later-described peripheral control unit 1 ms timer interrupt process is executed. When the side motor drive data STM-DAT is set and the next peripheral control unit 1 ms timer interrupt process is executed, the door side motor drive data STM is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. -DAT is set, and each time the peripheral control unit 1 ms timer interrupt process is executed, the door side is connected to the first area and the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. Motor drive data STM-DAT is set alternately. The peripheral control unit 1 ms timer interrupt process is executed. For example, in this peripheral control unit 1 ms timer interrupt process, the door side motor drive data STM-DAT is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. When set, the door side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when the previous peripheral control unit 1 ms timer interrupt process was executed. The process is based on this.

  When the peripheral control unit 1 ms timer interrupt process is executed, the motor drive board side transmission data storage area 4150cag is set with the game board side motor drive data SM-DAT in the first area of the motor drive board side transmission data storage area 4150cag. When the next peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag, Each time the peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT are alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150cag. The peripheral control unit 1 ms timer interrupt process is executed. For example, in the current peripheral control unit 1 ms timer interrupt process, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag. Sometimes, when the previous peripheral control unit 1 ms timer interrupt process is executed, the process proceeds based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150cag. It is like that.

  Next, the backup first area 4150cb and backup second area 4150cc that store specially copied production information, which is various information stored in the backup management target work area 4150ca, will be described. In the backup first area 4150cb and the backup second area 4150cc, two pairs each having two banks as one pair are managed as one page. Production information (1fr), which is the content stored in Bank0 (1fr), which is a storage area that is normally used, is produced as production backup information (1fr) every time the peripheral control unit steady process is executed for each frame (1frame). In addition, the production information (1 ms) which is the content stored in Bank0 (1 ms), which is a storage area normally used, is copied to the backup first area 4150 cb and the backup second area 4150 cc at high speed by the peripheral control DMA controller 4150ac. As the production backup information (1 ms), the peripheral control DMA controller 41 is assigned to the backup first area 4150 cb and the backup second area 4150 cc each time the peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to the high speed by 0ac. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, the backup first area 4150cb is managed as a pair of Bank1 (1fr) and Bank2 (1fr) as one pair, and Bank1 (1ms) and Bank2 (1ms) as one pair. ing. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank1 (1fr) and Bank2 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. The peripheral control DMA controller 4150ac copies the data to Bank1 (1ms) and Bank2 (1ms) at high speed. The consistency of this page is determined by whether or not the contents of Bank1 (1fr) and Bank2 (1fr) match. Bank1 (1ms) and Bank2 ( It carried out by whether or not the contents of the ms) are the same.

  The backup second area 4150cc is managed as one page with a total of two pairs, with Bank3 (1fr) and Bank4 (1fr) as one pair and Bank3 (1ms) and Bank4 (1ms) as one pair. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank3 (1fr) and Bank4 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to Bank 3 (1 ms) and Bank 4 (1 ms) at high speed by the peripheral control DMA controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank 3 (1 fr) and Bank 4 (1 fr) match. Bank3 (1 ms) and Bank4 ( It carried out by whether or not the contents of the ms) are the same.

  As described above, in this embodiment, the backup first area 4150cb has one pair of Bank1 (1fr) and Bank2 (1fr), and one pair of Bank1 (1ms) and Bank2 (1ms). It is an area to manage as a page, and the backup second area 4150 cc has a total of 2 pairs, with Bank 3 (1 fr) and Bank 4 (1 fr) as one pair, Bank 3 (1 ms) and Bank 4 (1 ms) as one pair This is an area for management as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150cb and backup second area 4150cc.

  In the present embodiment, the production information (1fr) that is the content stored in Bank0 (1fr) that is a storage area that is normally used is the production control information (1fr), and the peripheral control unit for each frame (1frame). Every time the steady process is executed, the contents are copied to the backup first area 4150cb and the backup second area 4150cc at high speed by the peripheral control DMA controller 4150ac and stored in Bank0 (1 ms) which is a storage area used normally. The production information (1 ms) is, as production backup information (1 ms), every time the 1 ms timer interrupt is generated, the backup first area 4150 cb and the backup second area 4150 cc are executed each time the peripheral control unit 1 ms timer interruption process is executed. Peripheral control Although designed to be copied at a high speed by the MA controller 4150Ac, a program for executing a fast copy from these peripheral control DMA controller 4150Ac are common. That is, in this embodiment, the production information (1fr) and the production information (1 ms) are managed by a common management method (execution of a common program).

[7-4-1d. Peripheral control SRAM]
A peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a includes a backup management target work area 4150da that exclusively stores information to be backed up among various information updated by executing various control programs. A backup first area 4150db and a backup second area 4150dc are provided for storing a copy of various information stored in the backup management target work area 4150da. The content stored in the peripheral control SRAM 4150d is a power-on command (see FIG. 29) from the main control board 4100 when the pachinko gaming machine 1 is powered on (including when power is restored due to an instantaneous power failure or a power failure). Instructs the start of the RAM clear effect and the start of each state effect (for example, instructs the start of the effect when the operation switch 860a shown in FIG. 11 is operated within a predetermined period from when the power is turned on. It is not cleared to zero. This is completely different from the point that the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc of the peripheral control RAM 4150c described above are cleared to zero. Further, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the game board side liquid crystal display device 1900. It has come to be. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, each content (item) stored in the peripheral control SRAM 4150d (for example, a history of occurrence of a big hit gaming state, etc.) On the other hand, the contents (items) stored in the peripheral control RAM 4150c are not displayed at all and cannot be cleared in the setting mode. This point is also completely different between the peripheral control RAM 4150c and the peripheral control SRAM 4150d.

  The backup management target work area 4150da is production information (SRAM) which is various information continued across days (for example, information for managing the history of occurrence of the big hit gaming state and special production flag management) Information) and the like are stored in a dedicated manner as a backup target. Here, the name of Bank0 (SRAM) will be briefly described. As described above, “Bank” is a minimum management unit that represents the size of a storage area for storing various types of information. The subsequent “0” means a storage area that is normally used for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150db to a backup second area 4150dc, which will be described later, are in the same storage area as “Bank0”. It means having a size. Since “(SRAM)” is a backup target of various information stored in the peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, “Bank0”, “Bank1”, “Bank2”, “Bank3” , And “Bank4”, respectively (effect information (SRAM) and effect backup information (SRAM) to be described later are also used in the same meaning).

  Next, the backup first area 4150db and backup second area 4150dc that store specially copied production information (SRAM), which is various information stored in the backup management target work area 4150da, will be described. The backup first area 4150db and the backup second area 4150dc are managed with one pair of two banks, and one pair as one page. Production information (SRAM), which is the content stored in Bank0 (SRAM), which is a storage area used normally, is production backup information (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). The peripheral control DMA controller 4150ac copies the backup first area 4150db and the backup second area 4150dc at high speed. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, in the backup first area 4150db, Bank1 (SRAM) and Bank2 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank1 (SRAM) and Bank2 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (SRAM) and Bank2 (SRAM) match.

  In the backup second area 4150dc, Bank3 (SRAM) and Bank4 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank3 (SRAM) and Bank4 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (SRAM) and Bank4 (SRAM) match.

  As described above, in this embodiment, the backup first area 4150db is an area for managing Bank 1 (SRAM) and Bank 2 (SRAM) as one pair, and managing this one pair as one page. Reference numeral 4150 dc is an area for managing Bank 1 (SRAM) and Bank 4 (SRAM) as one pair, and managing this one pair as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150db and backup second area 4150dc.

[7-4-2. Liquid crystal and sound control unit]
The drawing control of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, the speakers housed in the speaker box 820 provided in the main body frame 3, the music flowing from the speakers 130 provided in the door frame 5, sound effects, etc. As shown in FIG. 14, the liquid crystal and sound control unit 4160 that performs sound control has a built-in sound source for sound control such as music and sound effects (hereinafter referred to as “built-in sound source”). A sound source built-in VDP (Video Display Processor) 4160a for performing drawing control of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, and display on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 A liquid crystal and sound control ROM 4160b for storing various sound data such as music and sound effects in addition to various character data of the screen to be displayed; It includes the audio data transmission IC4160c to be transmitted towards the frame decoration drive amplifier board 194 Al of music and sound effects and the like as audio data.

  The peripheral control MPU 4150a of the peripheral control unit 4150 extracts the screen generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. Set to 4150cae in the schedule data storage area of the peripheral control RAM 4150c, and the top screen data of the screen generation schedule data set in the schedule data storage area 4150cae is stored in the peripheral control ROM 4150b or the peripheral control RAM 4150c of the peripheral control unit 4150. After being extracted from the control data copy area 4150ce and output to the sound source built-in VDP 4160a, the schedule data is triggered by the input of a V blank signal described later. The next screen data following the first screen data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c in accordance with the screen generation schedule data set in the storage area 4150cae, and the sound source is built-in. Output to the VDP 4160a. As described above, the peripheral control MPU 4150a converts the screen data arranged in time series into the screen generation schedule data according to the screen generation schedule data set in the schedule data storage area 4150cae every time the V blank signal is input. In addition, the first screen data is output to the built-in sound source VDP 4160a one by one.

  Also, the peripheral control MPU 4150a receives the sound command data at the head of the sound generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. Extracted and set to 4150cae in the schedule data storage area of the peripheral control RAM 4150c, and the head sound command data of the sound generation schedule data set in the schedule data storage area 4150cae is the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral After extracting from the various control data copy area 4150ce of the control RAM 4150c and outputting it to the sound source built-in VDP 4160a, the schedule data recording is triggered by the input of the V blank signal. In accordance with the sound generation schedule data set in the area 4150cae, the next sound command data following the head sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the sound source Output to built-in VDP 4160a. As described above, the peripheral control MPU 4150a receives the sound command data arranged in time series in the sound generation schedule data according to the sound generation schedule data set in the schedule data storage area 4150cae, and the V blank signal is input. Each time, the head sound command data is output to the built-in sound source VDP 4160a one by one.

[7-4-2a. Sound source built-in VDP]
When the screen data is input from the peripheral control MPU 4150a in addition to the above-described built-in sound source, the sound source built-in VDP 4160a receives a game board from the liquid crystal and sound control ROM 4160b as shown in FIG. 16 based on the input screen data. The drawing data for one screen (one frame) to be displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is generated by extracting the side character data and the upper plate side character data and generating sprite data. VRAM for this purpose is also built-in (hereinafter referred to as “built-in VRAM”). The sound source built-in VDP 4160a outputs image data for the game board side liquid crystal display device 1900 out of the drawing data generated on the built-in VRAM to the game board side liquid crystal display device 1900 from the channel CH1 and also for the upper plate side liquid crystal display device 470. By outputting the image data from the channel CH2 to the upper plate side liquid crystal display device 470, the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 are synchronized. Thus, when the peripheral control MPU 4150a outputs the screen data for one screen (one frame) displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 to the sound source built-in VDP 4160a, Based on the input screen data, character data is extracted from the liquid crystal and sound control ROM 4160b to create sprite data and displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 (1 Frame data) is generated on the built-in VRAM, and among the generated drawing data, image data for the game board side liquid crystal display device 1900 is output from the channel CH1 to the game board side liquid crystal display device 1900, and the upper plate side The image data for the liquid crystal display device 470 is transferred from the channel CH2. And outputs to the side the liquid crystal display device 470. That is, “screen data for one screen (for one frame)” means drawing data for one screen (for one frame) displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. This is the data to generate above.

  The sound source built-in VDP 4160a outputs drawing data for one screen (one frame) from the channel CH1 to the game board side liquid crystal display device 1900, and also outputs image data for the upper plate side liquid crystal display device 470 from the channel CH2. When output to the dish-side liquid crystal display device 470, a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is output to the peripheral control MPU 4150a. In this embodiment, since the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is set to approximately 30 fps per second, a V blank signal is output. The interval is about 33.3 ms (= 1000 ms ÷ 30 fps). The peripheral control MPU 4150a executes a peripheral control unit V blank signal interrupt process to be described later when this V blank signal is input. Here, the interval at which the V blank signal is output varies somewhat depending on the liquid crystal sizes of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. In addition, even in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the built-in sound source VDP 4160a are mounted, the interval at which the V blank signal is output may change somewhat.

  The sound source built-in VDP 4160a employs a frame buffer method. In this “frame buffer system”, drawing data for one screen (one frame) to be drawn on the screens of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is held in a frame buffer (built-in VRAM). The drawing data for one screen (one frame) held in the frame buffer (built-in VRAM) is output to the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470.

  When the sound command data described above is input from the peripheral control MPU 4150a based on the command from the main control board 4100, the built-in sound source VDP 4160a, as shown in FIG. 16, stores the music stored in the liquid crystal and sound control ROM 4160b. By extracting sound data such as sound and sound effects and controlling the built-in sound source, sound data such as music and sound effects are incorporated into the track according to the track number specified in the sound command data and used according to the output channel number The output channel is set and the music accommodated in the speaker box 820 provided in the main body frame 3 and the speaker, the sound effect, etc. flowing from the speaker 130 provided in the door frame 5 are serialized and output as audio data to the audio data transmission IC 4160c. .

  Note that the sound command data also includes a sub-volume value for adjusting the volume of the track in which the sound data is incorporated, and a plurality of tracks in the built-in sound source of the sound source built-in VDP 4160a include effect sounds such as music and sound effects. In addition to the sound data and the sub-volume value for adjusting the sound volume, the sound data of the notification sound and the sound volume for notifying the clerk of the hall of the occurrence of the malfunction of the pachinko gaming machine 1 and the illegal act on the pachinko gaming machine 1 Incorporates a sub-volume value that adjusts. Specifically, for the production sound, the substrate volume adjusted by rotating the knob portion of the volume adjustment volume 4140a described above is set as the sub volume value, and for the notification sound, the volume adjustment is performed. The maximum volume is set as the sub-volume value without depending on the volume adjustment based on the turning operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound can be adjusted by shifting to a setting mode to be described later by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400.

  The sound designation data also includes a master volume value for adjusting the volume of the output channel. A plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a include a plurality of sound channels in the built-in sound source of the sound source built-in VDP 4160a. Of the tracks, the sound data of the production sound built into the track to be used is combined with the sub-volume value that adjusts the volume of the production sound built into the track to be used. Actually, it amplifies the master volume value that is the volume that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and serializes the amplified effect sound as audio data. The data is output to the audio data transmission IC 4160c.

  In the present embodiment, the master volume value is set to a constant value, and when the volume of the synthesized effect sound is the maximum volume, the master volume value is amplified to the speaker box 820 provided in the main body frame 3. The volume that flows from the speaker housed in the speaker and the speaker 130 provided on the door frame 5 is set to an allowable maximum volume. Specifically, for the production sound, among the multiple tracks, the sound data of the production sound incorporated in the track to be used and the sub-volume value that adjusts the volume of the production sound incorporated in the track to be used The volume of the set sound adjustment volume 4140a is synthesized with the substrate volume adjusted by rotating the knob, and the volume of the synthesized performance sound is actually applied to the speaker box 820 provided in the main body frame 3. It amplifies up to the master volume value that is the volume that flows from the speaker to be accommodated and the speaker 130 provided on the door frame 5, serializes the amplified effect sound, and outputs it as audio data to the audio data transmission IC 4160c. Indicates the sound data of the notification sound incorporated in the track used and the sound of the notification sound incorporated in the track used. Is combined with the maximum volume without depending on the volume adjustment based on the turning operation of the knob portion of the volume adjustment volume 4140a set as the sub volume value for adjusting the volume, and the volume of the synthesized notification sound is actually Amplification is performed up to a master volume value which is a volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and the amplified notification sound is serialized to be audio data as audio data. The data is output to the transmission IC 4160c.

  Here, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the occurrence of the malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 To briefly explain the control of playing a notification sound in order to notify the store clerk etc. of fraudulent behavior, the sub-volume value of the track in which the production sound is incorporated is forcibly set to mute, and this production sound is incorporated. The track sound data, the sub-volume value set for the mute, the sound data of the track in which the notification sound is incorporated, and the sub-volume value where the notification sound volume is set to the maximum volume are synthesized. The volume of the produced effect sound and the volume of the notification sound are actually set to the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. Amplified to a master volume value as the volume flowing from 130, and outputs the amplified effect sound and alarm sound as an audio data to the audio data transmission IC4160c Serialize.

  In other words, the sound that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is only the notification sound of the maximum volume. At this time, since the production sound is muted, the production sound does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the production sound is used for the sound generation described above. Progressing according to schedule data. In the present embodiment, the notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 for a predetermined period (for example, 90 seconds). When the period of time elapses, the volume of the effect sound that has progressed in accordance with the sound generation schedule data that has been forcibly set to mute so far has been adjusted by rotating the knob portion of the volume adjustment volume 4140a. It is set again as the volume value (at this time, when the adjustment is made by moving to the setting mode by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, the adjusted effect sound is sub- Set to the volume value), the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. So that the flow from mosquitoes 130.

  Thus, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the occurrence of a malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 When a notification sound flows in order to notify a store clerk or the like of a fraudulent act to the hall, the volume of the effect sound is muted and the notification sound is provided in the speaker and door frame 5 housed in the speaker box 820 provided in the main body frame 3. Although the silenced effect sound flows from the speaker 130 and proceeds in accordance with the sound generation schedule data, the speaker is accommodated in the speaker box 820 provided in the main body frame 3 after a predetermined period of time. When the speaker 130 provided on the door frame 5 stops flowing, the production sound does not start to flow again from where the notification sound starts to flow. So that the start flowing again from where the notification sound is beginning to flow to proceed according to the schedule data for generating sound until after the lapse of a predetermined period of time.

[7-4-2b. Liquid crystal and sound control ROM]
As shown in FIG. 16, the liquid crystal and sound control ROM 4160b is used to draw the game board side character data for drawing in the display area of the game board side liquid crystal display device 1900 and the display area of the upper plate side liquid crystal display device 470. The upper plate side character data is stored in advance, and various sound data such as music, sound effects, notification sounds, and notification sounds are also stored in advance.

[7-4-2c. Audio data transmission IC]
When the audio data transmission IC 4160c receives the serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c transmits the right audio data to the frame decoration drive amplifier substrate 194 as differential serial data using a plus signal and a minus signal. At the same time, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as differential serial data using a plus signal and a minus signal. Thereby, music, sound effects, etc. adapted to various effects are reproduced in stereo from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5.

  Note that the audio data transmission IC 4160c outputs audio data between the boards extending from the peripheral control board 4140 to the frame decoration drive amplifier board 194 as differential serial data on the left and right sides, for example, a positive signal of the left audio data, Even when the negative signal is affected by noise, the frame decoration drive amplifier board 194 combines the noise component riding on the plus signal and the noise component riding on the minus signal into one left audio data. Since noise components are canceled by canceling each other, noise countermeasures can be taken.

[7-4-3. RTC control unit]
As shown in FIG. 14, the RTC control unit 4165 that holds calendar information for specifying the date and time and time information for specifying the hour, minute, and second is configured with the RTC 4165a as the center. The RTC 4165a has a built-in RAM 4165aa that holds calendar information and time information (hereinafter referred to as “RTC built-in RAM 4165aa”). The RTC 4165a is supplied with power from a battery 4165b (in this embodiment, a button battery is used) as a driving power source and a backup power source for the RTC built-in RAM 4165aa. That is, the RTC 4165a is not supplied with any power from the peripheral control board 4140 (pachinko gaming machine 1), but is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1). Thereby, even if the power of the pachinko gaming machine 1 is cut off, the RTC 4165a can update and hold calendar information and time information by supplying power from the battery 4165b.

  The peripheral control MPU 4150a of the peripheral control unit 4150 acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a, sets the information in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c, and stores the acquired calendar information and time information. The production based on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 can be unfolded. As such effects, for example, on December 25th, a Christmas tree or reindeer screen is unfolded on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. The screen to be executed may be unfolded on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. Calendar information and time information are set at the time of factory shipment.

  In addition to calendar information and time information, the RTC built-in RAM 4165aa stores and holds LED brightness setting information when an LED type backlight is attached to the game board side liquid crystal display device 1900. Yes. The peripheral control MPU 4150a obtains luminance setting information from the RTC built-in RAM 4165aa and adjusts the luminance of the backlight by PWM control when the backlight of the game board side liquid crystal display device 1900 is mounted with an LED type. . The luminance setting information includes luminance adjustment information for adjusting the range of the luminance of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, from 100% to 70% in increments of 5%, and the currently set game. The brightness of the LED which is the backlight of the panel side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is included.

  In addition to the calendar information, time information, and luminance setting information, the RTC built-in RAM 4165aa stores the calendar information, time information, and luminance setting information as date / time and hour / minute / second information that was first stored in the RTC built-in RAM 4165aa. Input date information is also stored.

  When the backlights of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 are mounted with a cold cathode tube type, the peripheral control MPU 4150a is configured to turn the backlight ON / OFF control or only ON. It is supposed to be.

  Various information stored in the RTC built-in RAM 4165aa, such as calendar information, time information, luminance setting information, and input date / time information, is set in the production line of the gaming machine manufacturer. In the production line, for example, in order to perform various tests such as a display test of the game board side liquid crystal display device 1900, the year when the input date information is entered on the production line as the date when the game board side liquid crystal display device 1900 was first turned on. Set to the date and time of manufacture, which is the date and time.

  Thus, in addition to the calendar information and time information, the RTC built-in RAM 4165aa has brightness setting information and input date / time information when the backlight of the game board side liquid crystal display device 1900 is of the LED type. In addition, it is possible to store and hold information that needs to be maintained independently of the model information of the pachinko gaming machine 1 (for example, the probability of occurrence of a big hit gaming state with a low probability or a high probability).

  Also, the brightness setting information and the like stored and held in the RTC built-in RAM 4165aa is too bright for the backlight brightness of the game board side liquid crystal display device 1900 set to the date of manufacture depending on the environment of the hall where the pachinko gaming machine 1 is installed. Or it may be too dark. Therefore, by operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400, the mode can be shifted to the setting mode, and the luminance of the backlight can be adjusted to a predetermined luminance. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the pachinko gaming machine 1 is turned on, a screen for performing a setting mode is displayed on the game board side liquid crystal display device 1900. In addition, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period when the game board side liquid crystal display device 1900 is in the waiting state and the demonstration is performed, the setting mode is performed. The screen is displayed on the game board side liquid crystal display device 1900. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, the calendar information and time information can be reset, and the backlight brightness of the game board side liquid crystal display device 1900 can be set to a desired value. It can be adjusted to brightness. The adjusted desired brightness of the backlight of the game board side liquid crystal display device 1900 is overwritten (updated) as the brightness of the LED stored in the brightness setting information.

  In the setting mode, the peripheral control MPU 4150a executes the above-described brightness correction program, and when the backlight of the game board side liquid crystal display device 1900 is an LED type, the game board side liquid crystal is installed. The luminance reduction accompanying the secular change of the display device 1900 is corrected. The peripheral control MPU 4150a acquires input date / time information from the RTC built-in RAM 4165aa of the RTC control unit 4165, specifies the date and time when the game board side liquid crystal display device 1900 is first turned on, and specifies calendar information and time for specifying the date. Time information that specifies minutes and seconds is acquired to specify the current date and time, and the brightness range of the LED, which is the backlight of the game board side liquid crystal display device 1900, is adjusted in increments of 5%. Brightness setting information including brightness adjustment information for performing and the brightness of the LED that is the backlight of the game board-side liquid crystal display device 1900 that is currently set. The acquired brightness setting information is corrected based on correction information stored in advance in the peripheral control ROM 4150b.

  For example, from the date and time when the game board side liquid crystal display device 1900 was first turned on and the current date and time, when six months have already passed since the date and time when the game board side liquid crystal display device 1900 was first turned on, When the corresponding correction information (for example, 5%) is obtained from the peripheral control ROM 4150b and the backlight of the game board side liquid crystal display device 1900 is turned on when the brightness of the LED included in the brightness setting information is 75%, the 75% The luminance of the backlight of the game board side liquid crystal display device 1900 is adjusted based on the luminance adjustment information included in the luminance setting information so that the luminance is further increased by 5% which is the correction information acquired with respect to the luminance setting information. And when the game board side liquid crystal display device 1900 has been powered on for the first time, December has already passed. When the corresponding correction information (for example, 10%) is acquired from 0b and the backlight of the game board side liquid crystal display device 1900 is turned on when the luminance of the LED included in the luminance setting information is 75%, The luminance of the backlight of the game board side liquid crystal display device 1900 is adjusted based on the luminance adjustment information included in the luminance setting information so that the luminance is further increased by 10% which is the correction information acquired in this way. Light.

  The current date and time may be specified by acquiring calendar information for specifying the date and time and time information for specifying the hour, minute, and second directly from the RTC built-in RAM 4165aa of the RTC control unit 4165, or a peripheral described later. Current calendar information that is set in the calendar information storage unit and updated by the system of the peripheral control board 4140 in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c in the current time information acquisition process of step S1002 in the control unit power-on process And the current time information set in the time information storage unit and updated by the system of the peripheral control board 4140 may be acquired to identify the current date and time.

[7-4-4. Volume adjustment volume]
As described above, the volume adjustment volume 4140a is used to rotate the knob portion to adjust the volume of music, sound effects and the like flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. It can be adjusted by doing. As described above, the volume adjustment volume 4140a is configured such that the resistance value can be changed by rotating the knob portion, and the electrically connected peripheral control A / D converter 4150ak is connected to the knob portion. The voltage divided by the resistance value at the rotational position is converted from an analog value to a digital value, and converted into a value in 1024 steps from 0 to 1023. In the present embodiment, as described above, the values of the 1024 steps are divided into seven and managed as the substrate volumes 0 to 6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The liquid crystal and sound control unit 4160 (VDP 4160a with built-in sound source) is controlled so that the volume is set to the substrate volume 0 to 6, and the speaker and door frame 5 provided in the speaker box 820 provided in the main body frame 3 are provided. Music and sound effects flow from the speaker 130.

  In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by volume adjustment based on the turning operation of the knob portion. . Further, in the present embodiment, as described above, in addition to music and sound effects, a notification sound for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko gaming machine 1 or an illegal act against the pachinko gaming machine 1, Announce contents related to game effects (for example, an announcement that the screen developed on the game board side liquid crystal display device 1900 is more powerful, or that there is a high possibility of shifting to a game state advantageous to the player) The notification sound for the flow of sound from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is also operated. It is a mechanism that flows without depending on the volume adjustment based on the sound volume, and the volume from the mute to the maximum volume is programmed by the liquid crystal and sound control unit 4160 (VDP4 with built-in sound source) So that the it can be adjusted by controlling the 60a).

  The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. Thus, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speakers and doors housed in the speaker box 820 provided in the main body frame 3 Although the production sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, the sound volume is increased when a malfunction occurs in the pachinko gaming machine 1 or when the player is cheating. In the embodiment, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound.

  Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, the screen unfolded on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 can be rendered more powerful or advantageous to the player. It is also possible to notify that there is a high possibility that the game state will be entered.

  In the present embodiment, in addition to adjusting the volume of music and sound effects by turning the knob of the volume adjustment volume 4140a, the dial operation unit 401 and the press of the operation unit 400 are adjusted. By operating the operation unit 405, it is possible to shift to the setting mode and adjust the volume of music and sound effects. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the pachinko gaming machine 1 is turned on, a screen for performing a setting mode is displayed on the game board side liquid crystal display device 1900. In addition, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period when the game board side liquid crystal display device 1900 is in the waiting state and the demonstration is performed, the setting mode is performed. The screen is displayed on the game board side liquid crystal display device 1900. By operating the dial operation unit 401 and the press operation unit 405 of the operation unit 400 in accordance with the setting mode screen, the volume of music and sound effects can be adjusted to a desired volume. Specifically, the peripheral control A / D converter 4150ak converts the voltage divided by the resistance value at the rotational position of the knob portion of the volume adjustment volume 4140a from an analog value to a digital value. Thus, the value of the substrate volume can be increased or decreased by adding or subtracting a predetermined value according to the operation of the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400. . This adjusted volume is set and updated as a sub-volume value for a track in which sound data of effect sound such as music or sound effect is incorporated among a plurality of tracks in the sound source of the sound source with built-in sound source VDP 4160a. However, it is not reflected in the adjustment of the volume of the notification sound or notification sound described above.

  As described above, in the present embodiment, the volume of the music or the sound effect is adjusted by directly rotating the knob of the volume adjustment volume 4140a, and the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is adjusted. There are two methods: adding or subtracting a predetermined value according to the operation to adjust the volume of music or sound effects by increasing or decreasing the value of the substrate volume. Since the volume adjustment volume 4140a is mounted on the peripheral control board 4140, the main body frame 3 must be opened from the outer frame 2 without fail. Then, the hall clerk can turn the knob of the volume adjustment volume 4140a. However, at the volume adjusted by the hall clerk, it may be difficult for the player to hear the music or sound effect, or may be loud for the player to feel the music or sound effect. Therefore, within a predetermined time after the power of the pachinko gaming machine 1 is turned on, the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated, or a demonstration is performed by the game board side liquid crystal display device 1900 in a waiting state. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period being performed, a screen for performing the setting mode is displayed on the game board side liquid crystal display device 1900. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, the volume of music and sound effects can be adjusted to a desired volume. Thus, the player can adjust the volume of the music and sound effects to a desired volume. Therefore, when the volume of the hall clerk feels low and it is difficult to hear the music and sound effects, the operation unit 400 The dial operation unit 401 and the pressing operation unit 405 can be operated to increase the volume to a desired level. If the volume of the hall clerk feels loud and the music and sound effects are noisy, the operation unit 400 The dial operation unit 401 and the pressing operation unit 405 can be operated to reduce the volume to a desired level.

  Further, in the present embodiment, a state in which no game is played in the pachinko gaming machine 1 is continued for a predetermined period of time, and when the game board side liquid crystal display device 1900 is repeatedly demonstrated (for example, 10 times). ) The volume adjusted by the player who was sitting on the front of the pachinko gaming machine 1 and playing the game last time is canceled and the volume is initialized. In the initialization of the volume, the volume adjusted by the hall clerk, that is, the volume adjusted by the hall clerk by directly rotating the knob portion of the volume adjustment volume 4140a is adjusted. As a result, if it is difficult to hear the music or sound effect by feeling the volume adjusted by the player who was sitting on the front of the pachinko gaming machine 1 last time and adjusting the volume, A player who sits down and plays a game can increase the sound volume to a desired level by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, or sits in front of the pachinko gaming machine 1 and plays a game. When the player who has played the game feels loud and adjusts the volume, the player who sits on the front surface of the pachinko gaming machine 1 and plays the game this time The volume can be reduced to a desired level by operating 401 or the pressing operation unit 405.

[8. Power system]
Next, a power supply system of the pachinko gaming machine 1 will be described with reference to FIGS. 17 and 18. FIG. 17 is a block diagram showing a power supply system of a pachinko gaming machine, and FIG. 18 is a block diagram showing a continuation of FIG. First, the power supply board will be described, and then the power supplied to each control board will be described. Note that the grounds (GND) of the various substrates and the grounds (GND) of the various terminal boards are electrically connected to the ground (GND) of the power supply substrate 851 and are the same ground (GND).

[8-1. Power supply board]
The power supply board 851 is electrically connected to the power cord, and the plug of the power cord is inserted into the power outlet of the pachinko island facility. When the power switch 852 shown in FIG. 3 is operated, the power supplied from the pachinko island facility is supplied to the power supply board 851, and the pachinko gaming machine 1 can be turned on.

  As shown in FIG. 17, the power supply board 851 includes a power supply control unit 855 and a launch control unit 857. The power supply control unit 855 is a circuit that creates various DC voltages from AC 24 volts (AC24V) supplied from the Pachinko Island facility, and supplies backup power to the main control board 4100 and the payout control board 4110. The unit 857 is a circuit that drives and controls the firing solenoid 654 of the ball striking device 650 shown in FIG. 5 and the ball feeding solenoid 585 of the ball feeding unit 580 shown in FIG.

  The power supply control unit 855 includes a synchronous rectification circuit 851a, a power factor correction circuit 851b, a smoothing circuit 851c, a power supply generation circuit 855d, and capacitors BC0 and BC1. The AC 24V supplied from the pachinko island facility is supplied to the game ball lending device connection terminal plate 869 via the power supply board 851 and also to the synchronous rectifier circuit 851a. This synchronous rectification circuit 851a is supplied from the Pachinko Island facility and rectifies 24 volt (AC24V) and supplies it to the power factor correction circuit 851b. This power factor improvement circuit 851b improves the power factor of the rectified power to generate DC + 37V (DC + 37V, hereinafter referred to as “+ 37V”) and supplies it to the smoothing circuit 851c. The smoothing circuit 851c removes the supplied + 37V ripple, smoothes + 37V, and supplies the smoothed voltage to the launch control circuit 857a and the power generation circuit 855d of the launch control unit 857, respectively.

  The capacitor BC0 supplies backup power to a RAM (main control built-in RAM) built in the main control MPU 4100a of the main control board 4100, and the capacitor BC1 is built in the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110. A backup power source is supplied to the RAM (payout control built-in RAM).

  The launch control circuit 857a of the launch control unit 857 uses the + 37V supplied from the smoothing circuit 851c as a drive power supply, and plays the game ball with a launch strength (launch strength) corresponding to the rotational position of the front 506 of the rotary handle shown in FIG. The driving current for launching (launching) toward the game area 1100 shown in FIG. 1 is adjusted and output to the firing solenoid 654, while a constant current is output to the ball feeding solenoid 585 of the ball feeding unit 580. Thus, the ball feeding member of the ball feeding unit 580 receives one game ball stored in the upper plate 301 of the dish unit 300 shown in FIG. 7, and sends the game ball received by the ball feeding member to the hitting ball launching device 650 side. Take control.

  The power supply generation circuit 855d is supplied from the smoothing circuit 851c with + 37V to DC + 5V (DC + 5V, hereinafter referred to as “+ 5V”), DC + 12V (DC + 12V, hereinafter referred to as “+ 12V”), and DC. + 24V (DC + 24V, hereinafter referred to as “+ 24V”) is created and supplied to the payout control board 4110 and the frame peripheral relay terminal board 868, respectively. The power supply system supplied with + 5V is the + 5V power supply line, the power supply system supplied with + 12V is supplied with the + 12V power supply line, and the power supply system supplied with + 24V is supplied with the + 24V power supply line.

  + 5V created by the power generation circuit 855d is supplied to the payout control board 4110 as will be described later. + 5V supplied to the payout control board 4110 is applied to the power supply terminal of the payout control MPU 4120a via the payout control filter circuit 4110a, and to the power supply terminal of the payout control built-in RAM via the diode PD0. ing. + 12V created by the power supply creation circuit 855d is supplied to the + 5V creation circuit 4100g of the main control board 4100 via the payout control board 4110. The + 5V creation circuit 4100g creates + 5V that is the control reference voltage of the main control MPU 4100a from + 12V from the payout control board 4110. The + 5V generated by the + 5V generating circuit 4100g is supplied to the power supply terminal of the main control MPU 4100a via the main control filter circuit 4100h and is also supplied to the power supply terminal of the main control built-in RAM via the diode MD0. ing.

  The negative terminal of the capacitor BC1 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC1 is electrically connected to the power supply terminal of the payout control built-in RAM of the payout control board 4110, and is paid out. The cathode terminal of the diode PD0 of the control board 4110 is also electrically connected. That is, + 5V created by the power supply creation circuit 855d of the power supply board 851 flows toward the power supply terminal of the payout control MPU 4120a, and the power supply terminal of the payout control built-in RAM, which is forward by the diode PD0, and the capacitor BC1 Current flows to the positive terminal. In this way, the capacitor BC1 is + 5V by an electrical connection method in which + 5V generated by the power supply generation circuit 855d of the power supply board 851 returns to the payout control board 4110 and again from the payout control board 4110 to the power supply board 851. Is supplied and can be charged. As a result, when +5 V generated by the power generation circuit 855d is not supplied to the payout control board 4110, the charge charged in the capacitor BC1 is supplied to the payout control board 4110 as pay VBB. Therefore, although the current is blocked by the diode PD0 and does not flow to the power supply terminal of the payout control MPU 4120a, the payout control MPU4120a does not operate, but the stored contents are held by supplying the payout VBB to the power supply terminal of the payout control built-in RAM. It has become so.

  The negative terminal of the capacitor BC0 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC0 is electrically connected to the power supply terminal of the main control built-in RAM of the main control board 4100 via the payout control board 4110. And is also electrically connected to the cathode terminal of the diode MD0 of the main control board 4100. In other words, + 5V created by the + 5V creating circuit 4100g is such that current flows toward the power supply terminal of the main control MPU 4100a, and the power supply terminal of the main control built-in RAM, which is forward by the diode MD0, and the positive terminal of the capacitor BC0, An electric current flows toward. In this way, the capacitor BC0 is charged with + 5V supplied by the electrical connection method in which + 5V generated by the + 5V generating circuit 4100g is supplied from the main control board 4100 and the payout control board 4110 to the power supply board 851. Can be done. As a result, + 12V created by the power supply creation circuit 855d of the power supply board 851 is not supplied to the + 5V creation circuit 4100g of the main control board 4100 via the payout control board 4110, and the + 5V creation circuit 4100g can create + 5V. When the charge is lost, the electric charge charged in the capacitor BC0 is supplied as the main VBB to the main control board 4100 via the payout control board 4110. Therefore, a diode is connected to the power supply terminal of the main control MPU 4100a. Although the main control MPU 4100a does not operate because the current is blocked by MD0 and the main control MPU 4100a does not operate, the main VBB is supplied to the power supply terminal of the main control built-in RAM so that the stored contents are held.

[8-2. Voltage supplied to each control board]
Next, an outline of the voltage supplied to each control board and the like will be described, and subsequently, the voltage supplied mainly to the payout control board and the voltage supplied to the main control board will be described.

  As shown in FIG. 17, three types of voltages, + 5V, + 12V, and + 24V, generated by the power generation circuit 855d of the power supply board 851 are supplied to the payout control board 4110. Among these three types of voltages, + 12V and Two types of voltages of + 24V are supplied to the main control board 4100 via the payout control board 4110. The three types of voltages + 5V, + 12V, and + 24V created by the power generation circuit 855d of the power supply board 851 are supplied to the frame peripheral relay terminal plate 868, and through the frame peripheral relay terminal plate 868, the peripheral voltage is supplied. It is supplied to the control board 4140 and the peripheral door relay terminal plate 882, respectively.

  Three types of voltages, + 5V, + 12V, and + 24V, supplied to the peripheral control board 4140 are used as shown in FIG. 18A. 4180a, respectively. The lamp driving circuit 4170a of the lamp driving board 4170 outputs various signals such as a lighting signal, a blinking signal and a gradation lighting signal to various decorative boards of the game board 4, and the driving source driving circuit 4180a of the motor driving board 4180 is a game. A drive signal is output to an electric drive source such as a motor or solenoid of the panel 4.

  The peripheral control board 4140 includes a + 3.3V generation circuit 4140b that generates 3.3V DC (DC + 3.3V, hereinafter referred to as “+ 3.3V”) from + 5V supplied from the frame peripheral relay terminal plate 868. ing. + 3.3V created by the + 3.3V creation circuit 4140b is supplied to the liquid crystal module 1900a of the game board side liquid crystal display device 1900 and the liquid crystal module 470a of the upper plate side liquid crystal display device 470, respectively. Further, + 12V supplied to the peripheral control board 4140 is supplied to the backlight power source 1900b of the game board side liquid crystal display device 1900 and the backlight power source 470b of the upper plate side liquid crystal display device 470, respectively.

  On the other hand, three types of voltages, + 5V, + 12V, and + 24V, supplied to the peripheral door relay terminal board 882 are supplied to the frame decoration drive amplifier board 194 as shown in FIG. The frame decoration drive amplifier board 194 includes a + 9V creation circuit 194a that creates DC + 9V (DC + 9V, hereinafter referred to as “+ 9V”) from + 12V supplied from the peripheral door relay terminal board 882. Along with + 9V created by the + 9V creation circuit 194a, four types of voltages, + 5V, + 12V, and + 24V, supplied from the peripheral door relay terminal board 882, are supplied to various decorative boards and the like of the door frame 5.

[8-2-1. Voltage supplied to dispensing control board]
As shown in FIG. 17, the payout control board 4110 includes a payout control filter circuit 4110a in addition to the payout control MPU 4120a. The payout control filter circuit 4110a is supplied with + 5V from the power supply board 851, and removes noise from the + 5V. In addition to being supplied to the capacitor BC1 of the power supply board 851 through the diode PD0, this + 5V is supplied to, for example, the payout control MPU 4120a of the payout control unit 4120. For example, + 12V from the power supply board 851 is supplied to the payout control input circuit 4120b of the payout control unit 4120 and the like, and is also supplied to the external communication circuit 784a of the external terminal board 784 via the payout control board 4110. The external communication circuit 784a of the external terminal board 784 outputs a signal that conveys the number of game balls paid out by the pachinko gaming machine 1 and game information of the pachinko gaming machine 1 to a hall computer installed in the game hall (hall). Circuit. The hall computer monitors the player's game by grasping the number of game balls paid out by the pachinko gaming machine 1 and the game information of the pachinko gaming machine 1 from the signal output from the external communication circuit 784a. . Note that +24 from the power supply board 851 is supplied to the main control board 4100 via the payout control board 4110 without being used in the payout control board 4110 at all.

[8-2-2. Voltage supplied to main control board]
As shown in FIG. 17, the main control board 4100 includes, in addition to the main control MPU 4100a and the like, a + 5V creation circuit 4100g, a main control filter circuit 4100h, a power failure monitoring circuit 4100e, and the like. The + 5V creation circuit 4100g is supplied with + 12V from the power supply board 851 via the payout control board 4110, and creates + 5V which is the control reference voltage of the main control MPU 4100a from this + 12V. In the main control board 4100, a power supply system supplied with + 5V generated by the + 5V generating circuit 4100g is a + 5V power supply line. In this embodiment, the + 5V power supply line created by the power supply creation circuit 855d of the power supply board 851 and the + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 are not electrically connected. Thus, the + 5V power supply line created by the power supply creation circuit 855d of the power supply board 851 is not electrically connected to various electronic components of the main control board 4100, and the + 5V of the main control board 4100 is not connected. The + 5V power supply line created by the creation circuit 4100g is not electrically connected to various electronic components such as other boards other than the main control board 4100.

  The main control filter circuit 4100h is supplied with + 5V created by the + 5V creation circuit 4100g, and removes noise from this + 5V. In addition to being supplied to the capacitor BC0 of the power supply substrate 851 through the diode MD0, this + 5V is supplied to, for example, the main control MPU 4100a. For example, + 12V from the payout control board 4110 is supplied to the main control input circuit 4100b and the like, and + 24V from the payout control board 4110 is supplied to the main control solenoid drive circuit 4100d and the like, for example.

  The power failure monitoring circuit 4100e is supplied with + 12V and + 24V from the power supply board 851 via the payout control board 4110, and monitors these + 12V and + 24V signs of power failure or instantaneous power failure. When the power failure monitoring circuit 4100e detects signs of + 12V and + 24V power failure or instantaneous power failure, the power failure monitoring circuit 4100e outputs a power failure warning signal to the main control MPU 4100a as a power failure warning. The power failure notice signal is input to the payout control MPU 4120a via the main control board 4100 and the payout control input circuit 4120b of the payout control board 4110. The power failure notice signal is input to the peripheral control board 4140 via the main control board 4100. The power failure warning signal is input to the frame decoration drive amplifier board 194 through the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882 as shown in FIG. At the same time, the frame decoration driving amplifier board 194 is inputted to the decoration board or the like of the door frame.

  In the present embodiment, the power failure monitoring circuit 4100e is applied to one of the + 12V power line and the + 24V power line by monitoring the voltages applied to the two power lines, the + 12V power line and the + 24V power line, respectively. Compared with the case where the voltage to be monitored is monitored, it is possible to more accurately grasp the sign of power interruption such as a power failure or a momentary power failure.

[9. Main control board circuit]
Next, the circuit and the like of the main control board 4100 shown in FIG. 11 will be described with reference to FIGS. 19 is a circuit diagram showing a circuit of the main control board, FIG. 20 is a circuit diagram showing a power failure monitoring circuit, and FIG. 21 is a circuit showing an interface circuit for communication between the main control board and the peripheral control board. FIG. First, the main control filter circuit 4100h shown in FIG. 17 will be described, followed by the power source, main control system reset, main control crystal oscillator, main control input circuit, power failure monitoring circuit, main control MPU created by the main control board 4100. Various input / output signals to and from the main control board 4100 and the peripheral control board 4140 will be described.

  The main control board 4100 includes a main control MPU 4100a, a main control input circuit 4100b, a main control output circuit 4100c, a main control solenoid drive circuit 4100d, a power failure monitoring circuit 4100e, a + 5V generation circuit 4100g, and In addition to the control filter circuit 4100h, as a peripheral circuit, as shown in FIG. 19, a main control system reset MIC1 that outputs a reset signal, a main control crystal oscillator MX0 that outputs a clock signal (in this embodiment, 24 megahertz (MHz) )) Mainly.

[9-1. Main control filter circuit]
As shown in FIG. 19, the main control filter circuit 4100h mainly includes a main control three-terminal filter MIC0. This main control three-terminal filter MIC0 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite. In the main control three-terminal filter MIC0, + 5V generated by the + 5V generating circuit 4100g is applied to the first terminal, the second terminal is grounded to the ground (GND), and the noise component is removed from the third terminal. + 5V is output. + 5V applied to the first terminal is electrically connected to the other end of the capacitor MC0 whose one end is connected to the ground (GND), so that the ripple (AC component superimposed on the voltage) is first removed. Smoothed.

  + 5V output from the third terminal is electrically connected to the other end of the capacitor MC1 and the electrolytic capacitor MC2 (capacitance: 470 microfarad (μF) in this embodiment), one end of which is grounded with the ground (GND). By connecting to, ripples are further removed and smoothed. The smoothed + 5V is applied to the power supply terminal of the main control system reset MIC1, the VDD terminal that is the power supply terminal of the main control crystal oscillator MX0, the VDD terminal that is the power supply terminal of the main control MPU 4100a, and the like.

  One end of the VDD terminal of the main control MPU 4100a is electrically connected to the other end of the capacitor MC3 that is grounded to the ground (GND), and + 5V applied to the VDD terminal is further smoothed by removing ripples. The VSS terminal, which is the ground terminal of the main control MPU 4100a, is grounded to the ground (GND).

  In addition, the VDD terminal of the main control MPU 4100a is electrically connected to the anode terminal of the diode MD0 in addition to being electrically connected to the capacitor MC3. The cathode terminal of the diode MD0 is electrically connected to the VBB terminal, which is a power supply terminal of a RAM (main control built-in RAM) built in the main control MPU 4100a, and one end of the capacitor MC4 is grounded to the ground (GND). Is electrically connected to the other end. In addition to being electrically connected to the cathode terminal of the diode MD0 and the other end of the capacitor MC4, the VBB terminal of the main control built-in RAM is connected to the plus of the capacitor BC0 of the power supply board 851 shown in FIG. It is electrically connected to the terminal. That is, +5 V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal of the main control MPU 4100a, and via the diode MD0, the VBB terminal of the main control built-in RAM and the capacitor BC0. Are applied to the positive terminal. Accordingly, as described above, + 12V generated by the power generation circuit 855d of the power supply board 851 shown in FIG. 17 is not supplied to the + 5V generation circuit 4100g of the main control board 4100 via the payout control board 4110, and + 5V is generated. When the circuit 4100g cannot create + 5V, the electric charge charged in the capacitor BC0 is supplied to the main control board 4100 as the main VBB, so that the VDD terminal of the main control MPU 4100a has Although the current is blocked by the diode MD0 and does not flow and the main control MPU 4100a does not operate, the stored contents are held by applying the main VBB to the VBB terminal of the main control built-in RAM.

[9-2. Main control system reset]
As shown in FIG. 19, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the power supply terminal of the main control system reset MIC1. The main control system reset MIC1 resets the main control MPU 4100a and the main control output circuit 4100ca with a reset function, and has a built-in delay circuit. One end of the delay capacitor terminal of the main control system reset MIC1 is electrically connected to the other end of the capacitor MC5 grounded to the ground (GND), and the delay time by the delay circuit is set by the capacitance of the capacitor MC5. Be able to. Specifically, when + 5V input to the power supply terminal reaches a threshold value (for example, 4.25V), main control system reset MIC1 outputs a system reset signal from the output terminal after the delay time has elapsed.

  The output terminal of the main control system reset MIC1 is electrically connected to the SRST terminal which is a reset terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor MR1 that is electrically connected to the + 5V power line, and the other end is a capacitor that is grounded to the ground (GND). It is electrically connected to the other end of MC6. Ripple is removed and smoothed by the capacitor MC6. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to + 5V side by the pull-up resistor MR1, and the logic becomes HI. This logic is the SRST terminal of the main control MPU 4100a and the main control output with reset function. When the voltage input to the reset terminal of the circuit 4100ca is lower than the threshold value, the logic is LOW. This logic is the SRST terminal of the main control MPU 4100a and the main control output circuit 4100ca with reset function. Each is input to the reset terminal. Since the SRST terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with reset function are negative logic inputs, respectively, when the voltage input to the power supply terminal is smaller than the threshold value, the main control MPU 4100a and the reset function The attached main control output circuit 4100ca is reset. The power supply terminal is electrically connected to the other end of the capacitor MC7 whose one end is grounded (GND), and + 5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded with a grant (GND), and the NC terminal is not electrically connected to the outside.

[9-3. Main control crystal oscillator]
As shown in FIG. 19, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0. The VDD terminal is electrically connected to the other end of the capacitor MC8 whose one end is grounded (GND), and + 5V input to the VDD terminal is smoothed by further removing ripples. In addition to the VDD terminal, the smoothed + 5V is also applied to the A terminal, B terminal, C terminal, and ST terminal, which are output frequency selection terminals. The main control crystal oscillator MX0 outputs a clock signal of 24 MHz from the F terminal which is an output terminal by applying + 5V to these A terminal, B terminal, C terminal and ST terminal.

  The F terminal of the main control crystal oscillator MX0 is electrically connected to the CLK terminal which is the clock terminal of the main control MPU 4100a, and a clock signal of 24 MHz is input. Note that the GND terminal, which is the ground terminal of the main control crystal oscillator MX0, is grounded to the ground (GND), and the D terminal that outputs the divided frequency of the F terminal of the main control crystal oscillator MX0 is not electrically connected to the outside. It is in a state.

[9-4. Main control input circuit]
The main control input circuit 4100b receives the detection signals from the general prize opening switches 3020 and 3020, the upper start opening switch 3022, the lower start opening switch 2109, the magnetic detection switch 304, the count switch 2110, and the gate switch 2352 shown in FIG. In addition, this is a circuit to which an operation signal (RAM clear signal) or the like is input from an operation switch 860a provided in the payout control board 4110 shown in FIG. Since the circuit configuration to which the detection signal from each switch is input is the same, here, a circuit to which the operation signal (RAM clear signal) from the operation switch 860a is input will be described.

[9-4-1. A circuit to which an operation signal (RAM clear signal) is input from the operation switch]
First, as described above, the operation switch 860a includes the RAM (payout control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 and the main control of the main control board 4100 within a predetermined period from when the power is turned on. It is operated when clearing the RAM (main control built-in RAM) built in the MPU 4100a, or when an error is notified after the power is turned on, it is operated to cancel the error. Function to clear RAM within a predetermined period from power-on, and error cancellation after power-on (after a period during which the function is performed as RAM clear, that is, after a predetermined period elapses from power-on) And a function of performing Since the main control board 4100 does not have the error canceling function of the payout control board 4110, if an operation signal is input from the operation switch 860a within a predetermined period from when the power is turned on, the main control board 4100 receives the main control board 4100. A process of clearing the main control built-in RAM is performed as a RAM clear signal for clearing the built-in RAM.

  The main control board 4100 receives an operation signal whose logic is LOW from the payout control board 4110 when the operation switch 860a is not operated, while the logic from the payout control board 4110 when the operation switch 860a is operated. The operation signal in which HI becomes HI is input from the payout control board 4110 (detailed explanation of this point will be described later).

  As shown in FIG. 19, the transmission line for transmitting the operation signal from the operation switch 860a provided in the payout control board 4110 within a predetermined period from the time of power-on is a pull-up in which one end is electrically connected to the + 12V power line. It is electrically connected to the other end of the resistor MR2 and electrically connected to the base terminal of the transistor MTR0 via the resistor MR3. In addition to being electrically connected to the resistor MR3, the base terminal of the transistor MTR0 is also electrically connected to the other end of the resistor MR4 that is grounded to the ground (GND). The emitter terminal of the transistor MTR0 is grounded to the ground (GND), and the collector terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR5, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC 10 (non-inverted buffer ICMIC 10 includes eight non-inverted buffer circuits, and the signal waveform input to one of them (MIC 10A) is shaped and output without being inverted). The MPU 4100a is electrically connected to the input terminal PA0 of the input port PA.

  The circuit that outputs the operation signal from the operation switch 860a in the payout control board 4110 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and transmits the operation signal from the operation switch 860a. The line is pulled up to the + 12V side by the pull-up resistor MR2. In the main control board 4100, when the operation switch 860a is not operated, the operation signal from the payout control board 4110 is pulled down to the ground (GND) side and the logic is input as LOW, while the operation switch 860a is operated. The operation signal from the payout control board 4110 is pulled up to the + 12V side by the pull-up resistor MR2 and the logic becomes HI.

  A circuit including the resistors MR3 and MR4 and the transistor MTR0 is a switch circuit that is turned on / off by an operation signal from the operation switch 860a.

  When the operation switch 860a is not operated, an operation signal whose logic is LOW is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned OFF and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5 and the operation signal from the operation switch 860a whose logic becomes HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Is done. When the logic of the operation signal from the operation switch 860a input to the input terminal PA0 is HI, the main control MPU 4100a determines that the main control MPU 4100a does not instruct to perform RAM clear to erase information stored in the main control built-in RAM. To do.

  On the other hand, when the operation switch 860a is operated, an operation signal that is pulled up to + 12V by the pull-up resistor MR2 and has a logic level HI is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned on. The circuit is also turned on. As a result, the operation signal from the operation switch 860a in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Is done. The main control MPU 4100a instructs to clear the RAM for erasing the information stored in the main control built-in RAM when the logic of the operation signal from the operation switch 860a input to the input terminal PA0 is LOW. to decide.

  The operation signal from the operation switch 860a is pulled up to the + 12V side by the pull-up resistor MR2. This is because an operation signal from the operation switch 860 a is input via the payout control board 4110. That is, between the boards of the main control board 4100 and the payout control board 4110, it is higher than the control reference voltage +5 V in order to suppress the influence of noise entering the wiring (harness) that electrically connects the boards. The reliability of the signal is enhanced by using + 12V which is a voltage. Therefore, in the present embodiment, detection signals from the general winning opening switch 3020, the upper start opening switch 3022, and the lower start opening switch 2109 that are directly input to the main control board 4100 are pulled up to the + 5V side by the pull-up resistor. On the other hand, detection signals from the magnetic detection switch 3024, the count switch 2110, the general prize opening switch 3020, and the gate switch 2352, which are input via the panel relay terminal plate 4161 shown in FIG. Since it is not input, it is pulled up to the + 12V side by a pull-up resistor in the same manner as the operation signal from the operation switch 860a.

[9-5. Power failure monitoring circuit]
As shown in FIG. 17, the main control board 4100 is supplied with two types of voltages of + 12V and + 24V from the power supply board 851 via the payout control board 4110, and + 12V and + 24V are input to the power failure monitoring circuit 4100e. ing. The power failure monitoring circuit 4100e monitors the signs of + 12V and + 24V power failures or momentary power outages, and detects a power outage notice signal as a power outage notice in addition to the main control MPU 4100a when a sign of power outages or momentary power outages is detected. 4110 is output to the payout control MPU 4120a and the peripheral control board 4140. Here, the configuration of the power failure monitoring circuit will be described first, followed by the monitoring of the + 24V power failure or instantaneous power failure, the + 12V power failure or instantaneous power failure, and the output of the power failure warning signal.

[9-5-1. Configuration of power failure monitoring circuit]
As shown in FIG. 20, the power failure monitoring circuit 4100e mainly includes a shunt-type stabilized power supply circuit MIC20, an open collector output type comparator MIC21, a D-type flip-flop MIC22, and transistors MTR20 to MTR23.

  The reference voltage input terminal REF terminal and the cathode terminal K terminal of the shunt-type stabilized power supply circuit MIC20 are electrically connected to the other end of the resistor MR20, one end of which is electrically connected to the + 5V power supply line. + 5V is applied, and the current input to the REF terminal is limited by the resistor MR20. The K terminal outputs a reference voltage Vref that is a comparison reference voltage of the comparator MIC21 (in this embodiment, 2.495 V is set). The K terminal is electrically connected to the other end of the capacitor MC20 whose one end is grounded to the ground (GND). The reference voltage Vref output from the K terminal is rippled (convolved with the voltage by the capacitor MC20). AC component) is removed and smoothed. The A terminal, which is the anode terminal of the shunt-type stabilized power supply circuit MIC20, is grounded to the ground (GND).

  The comparator MIC21 includes two voltage comparison circuits, one of which (MIC21A) is used for comparing the monitor voltage V1 of + 24V and the reference voltage Vref, and the other one (MIC21B). , + 12V monitor voltage V2 and reference voltage Vref are used for comparison. The monitoring voltage V1 of + 24V is applied to the third terminal, which is the positive terminal of the MIC 21A, and the reference voltage Vref is applied to the second terminal, which is the negative terminal of the MIC 21A. The monitoring voltage V2 of + 12V is applied to the 5th terminal which is the plus terminal of the MIC 21B, and the reference voltage Vref is applied to the 6th terminal which is the minus terminal of the MIC 21B. These comparison results are input to the D-type flip-flop MIC22. The D-type flip-flop MIC22 includes two D-type flip-flop circuits, one of which (MIC22A) is used in the present embodiment. The Vcc terminal which is a power supply terminal of the comparator MIC21 is electrically connected to the other end of the capacitor MC21 whose one end is grounded (GND), and + 5V applied to the Vcc terminal which is the power supply terminal of the comparator MIC21 is The ripple is removed and smoothed by the capacitor MC21, and the GND terminal which is the ground terminal of the comparator MIC21 is grounded to the ground (GND).

[9-5-2. Monitoring of + 24V power outage or instantaneous power failure]
As described above, the + 24V power failure or instantaneous power failure is monitored by the MIC 21A of the comparator MIC21 comparing the + 24V monitoring voltage V1 with the reference voltage Vref. As shown in FIG. 20, the third terminal, which is the positive terminal of the MIC 21A of the comparator MIC 21 to which the + 24V monitoring voltage V1 is applied, has one end connected to the + 24V power line and the other end of the resistor MR21. Is connected to the ground (GND), the other end of the resistor MR22 is electrically connected and the other ends of the resistors MR21 and MR22, and the other end of the capacitor MC23 is grounded to the ground (GND). Are electrically connected. The + 24V monitoring voltage V1 applied to the third terminal, which is the positive terminal of the MIC21A of the comparator MIC21, is divided by + 24V by the resistance ratio of the resistors MR21 and MR22, and the ripple is removed by the capacitor MC23 and is smoothed. . The values of the resistors MR21 and MR22 are preset to the power failure detection voltage V1pf (in the present embodiment, set to 21.40V) when + 24V has a power failure or a momentary power failure, and the voltage starts dropping from + 24V. The monitoring voltage V1 of + 24V is set to be the same value as the reference voltage Vref.

  The first terminal that is the output terminal of the MIC 21A of the comparator MIC 21 is an open collector output, and one end is electrically connected to the other end of the pull-up resistor MR23 that is electrically connected to the + 5V power supply line. One end is electrically connected to the other end of the capacitor MC24, which is grounded with the ground (GND), and is electrically connected to a PR terminal which is a preset terminal of the D-type flip-flop MIC22. The capacitor MC24 plays a role as a low-pass filter.

  When the + 24V voltage is higher than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes higher than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC21A of the comparator MIC21 is + 5V by the pull-up resistor MR23. A signal whose logic is HI is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  On the other hand, when the + 24V voltage is smaller than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes smaller than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC 21A of the comparator MIC21 is the ground (GND). The signal with the logic level LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-3. Monitoring of + 12V power failure or instantaneous power failure]
As described above, the + 12V power failure or instantaneous power failure is monitored by the MIC 21B of the comparator MIC21 comparing the + 12V monitor voltage V2 with the reference voltage Vref. As shown in FIG. 20, the fifth terminal, which is the plus terminal of the MIC 21B of the comparator MIC 21 to which the monitoring voltage V2 of + 12V is applied, has one end connected to the + 12V power line and the other end of the resistor MR24. Are connected to the other end of the resistor MR25, and the other ends of the resistors MR24 and MR25, and the other end of the capacitor MC25 is connected to the ground (GND). Are electrically connected. The + 12V monitoring voltage V2 applied to the fifth terminal, which is the positive terminal of the MIC21B of the comparator MIC21, is divided by + 12V by the resistance ratio of the resistors MR24 and MR25, and the ripple is removed by the capacitor MC25 and is smoothed. . The values of the resistors MR24 and MR25 are preset to the power failure detection voltage V2pf (in this embodiment, set to 10.47V) when + 12V has a power failure or a momentary power failure and the voltage starts to drop from + 12V. The monitoring voltage V2 of + 12V is set to be the same value as the reference voltage Vref.

  The 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21, is an open collector output and is electrically connected to the 1st terminal, which is the output terminal of the MIC21A, so that one end is electrically connected to the + 5V power line. The D-type flip-flop MIC22 is preset by being electrically connected to the other end of the pull-up resistor MR23 that is electrically connected, and one end being electrically connected to the other end of the capacitor MC24 that is grounded to the ground (GND). The terminal is electrically connected to the PR terminal. As described above, the capacitor MC24 plays a role as a low-pass filter.

  When the voltage of + 12V is higher than the power failure detection voltage V2pf, the monitoring voltage V2 of + 12V becomes higher than the reference voltage Vref, and the voltage applied to the seventh terminal which is the output terminal of the MIC21B of the comparator MIC21 is + 5V by the pull-up resistor MR23. A signal whose logic is HI is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  On the other hand, when the voltage of + 12V is smaller than the power failure detection voltage V2pf, the monitoring voltage V2 of + 12V becomes smaller than the reference voltage Vref, and the voltage applied to the seventh terminal which is the output terminal of the MIC21B of the comparator MIC21 is the ground (GND). The signal with the logic level LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-4. Output of power failure warning signal]
The D type flip-flop MIC22 stores the value (logic) of the signal input to the 1D terminal, which is the D input terminal, according to the change in the edge of the clock signal input to the 1CK terminal, which is the clock input terminal. (Logic) is output from the 1Q terminal that is the output terminal, and a value obtained by inverting the stored value (logic) is output from the negative logic 1Q terminal that is the output terminal. In addition, when a signal whose logic is LOW is input to the CLR terminal which is the clear terminal, the D-type flip-flop MIC22 releases the latch state and changes the logic of the signal input to the PR terminal which is the preset terminal. The inverted signal is output from the 1Q terminal that is the output terminal (at this time, the same logic as that of the signal that is inverted from the logic of the signal output from 1Q, that is, the signal that is input to the PR terminal that is the preset terminal) On the other hand, when a signal whose logic is HI is input to the CLR terminal which is the clear terminal, the latch state is set. The D-type flip-flop MIC22 has a logic LOW at the preset terminal PR when a signal whose logic is HI is input to the CLR terminal which is a clear terminal and the latch state is set. When the signal is input, the state that the signal whose logic is HI is output from the 1Q terminal which is the output terminal is maintained (the signal obtained by inverting the logic of the signal output from 1Q is negative logic) The state of outputting from the 1Q terminal is maintained).

  In the D-type flip-flop MIC22, in this embodiment, the 1D terminal that is the D input terminal and the 1CK terminal that is the clock input terminal are grounded to the ground (GND). The circuit configuration is such that there is no change in the edge of the input clock signal, and the value (logic) of the signal input to the 1D terminal which is the D input terminal is stored and is not output from the 1Q terminal which is the output terminal. ing. As described above, the D-type flip-flop MIC22 has a signal from the first terminal that is the output terminal of the MIC21A of the comparator MIC21 that monitors the + 24V power failure or the instantaneous power failure, and the + 12V power failure. Alternatively, a signal from the 7th terminal that is the output terminal of the MIC 21B of the comparator MIC 21 that monitors the instantaneous power failure is input, and a signal is output from the 1Q terminal that is the output terminal based on these signals. The Vcc terminal, which is a power supply terminal, is electrically connected to the other end of the capacitor MC22 whose one end is grounded (GND), and is applied to the Vcc terminal, which is the power supply terminal of the D-type flip-flop MIC22. + 5V is smoothed by removing the ripple by the capacitor MC22, the GND terminal as the ground terminal is grounded to the ground (GND), and the negative logic 1Q terminal that inverts the logic of the 1Q terminal as the output terminal is electrically connected to the outside. In an unconnected state.

  In the present embodiment, in the D-type flip-flop MIC22, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal which is a clear terminal via the main control output circuit 4100ca with a reset function. This power failure clear signal is output after a predetermined time has elapsed after the start of output in the main control-side power-on process described later performed by the main control MPU 4100a. Since the CLR terminal is a negative logic input, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal with the logic being LOW via the main control output circuit 4100ca with a reset function. When the power failure clear signal is input to the CLR terminal, the D-type flip-flop MIC22 cancels the latch state. At this time, the logic input to the PR terminal which is a preset terminal is inverted and the output terminal Is output from the 1Q terminal.

  On the other hand, when the output of the power failure clear signal from the main control MPU 4100a is stopped, the logic becomes HI via the main control output circuit 4100ca with reset function and is input to the CLR terminal. When the power failure clear signal is not input to the CLR terminal, the D-type flip-flop MIC22 sets the latch state, and latches the state where the logic is LOW at the PR terminal.

  The 1Q terminal that is the output terminal of the D-type flip-flop MIC22 is electrically connected to the input terminal PA1 of the input port PA of the main control MPU 4100a via the main control input circuit 4100b, and is the output terminal of the D-type flip-flop MIC22. A signal output from the 1Q terminal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a as a power failure warning signal. The 1Q terminal that is the output terminal of the D-type flip-flop MIC22 is electrically connected to the main control output circuit 4100cb having no reset function, and resets the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22. The functionless main control output circuit 4100cb outputs a payout blackout notice signal to the payout control board 4110 and also outputs to the peripheral control board 4140 as a peripheral blackout notice signal.

  The main control input circuit 4100b that electrically connects the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, and the input terminal PA1 of the input port PA of the main control MPU 4100a has a D-type flip-flop as shown in FIG. The 1Q terminal, which is the output terminal of the MIC 22, is electrically connected to the other end of the resistor MR26, one end of which is electrically connected to the + 5V power supply line, and electrically connected to the base terminal of the transistor MTR20 via the resistor MR27. It is connected. In addition to being electrically connected to the resistor MR27, one end of the transistor MTR20 is electrically connected to the other end of the resistor MR28 that is grounded to the ground (GND). The emitter terminal of the transistor MTR20 is grounded to the ground (GND), and the collector terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC 23 (non-inverted buffer ICMIC 23 includes eight non-inverted buffer circuits, and the signal waveform input to one (MIC 23A) is shaped and output without being inverted). The MPU 4100a is electrically connected to the input terminal PA1 of the input port PA.

  The circuit composed of the resistors MR27 and MR28 and the transistor MTR20 is a switch circuit that is turned ON / OFF by a signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR20 is pulled down to the ground (GND) side, and the transistor MTR20 is turned OFF. The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR20 is raised to the + 5V side, turning on the transistor MTR20, The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Since the signal is output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, the logic becomes LOW and is input to the base terminal of the transistor MTR20. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled up to + 5V by the resistor MR29, and the power failure warning signal whose logic becomes HI via the non-inverting buffer ICMIC23 is input to the input port PA of the input port PA of the main control MPU4100a. Input to PA1.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 becomes the logic HI and is input to the base terminal of the transistor MTR20. As a result, the transistor MTR20 is turned ON. Thereby, the voltage applied to the collector terminal of the transistor MTR20 is pulled down to the ground (GND) side, and the power failure warning signal whose logic becomes LOW via the non-inverting buffer ICMIC23 becomes the input terminal of the input port PA of the main control MPU 4100a. Input to PA1.

  Further, as shown in FIG. 20, the main control output circuit 4100cb without reset function that outputs a signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, to the payout control board 4110 as a payout blackout signal is opened. The circuit is configured as a collector output type, and the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the transistor MTR21 of the previous stage is connected via the resistor MR30. It is electrically connected to the base terminal. In addition to being electrically connected to the resistor MR30, one end of the base terminal of the transistor MTR21 at the previous stage is electrically connected to the other end of the resistor MR31 that is grounded to the ground (GND). The emitter terminal of the front-stage transistor MTR21 is grounded to the ground (GND), and the collector terminal of the front-stage transistor MTR21 is electrically connected to the other end of the resistor MR32 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the subsequent transistor MTR22 via the resistor MR33. In addition to being electrically connected to the resistor MR33, one end of the base terminal of the transistor MTR22 at the subsequent stage is electrically connected to the other end of the resistor MR34 that is grounded to the ground (GND). The emitter terminal of the rear-stage transistor MTR22 is grounded to the ground (GND), and the collector terminal of the rear-stage transistor MTR22 is electrically connected to the other end of the capacitor MC26 whose one end is grounded to the ground (GND). It is electrically connected to the payout control board 4110 via (harness). When the collector terminal of the latter-stage transistor MTR22 is electrically connected to the payout control board 4110 via a wiring (harness), the payout control input of the payout control unit 4120 shown in FIG. In the circuit 4120b, one end of the circuit 4120b is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power line, and is electrically connected to an input terminal of a predetermined input port of the payout control MPU 4120a shown in FIG. Connected.

  A circuit composed of the resistors MR30 and MR31 and the preceding transistor MTR21 is a preceding switch circuit, and a circuit composed of the resistors MR33 and MR34 and the succeeding transistor MTR22 is a succeeding switch circuit, and is a D-type flip-flop. It is turned ON / OFF by a signal output from the 1Q terminal which is an output terminal of the MIC 22.

  When the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the previous transistor MTR21 is pulled down to the ground (GND) side, and the previous transistor The MTR 21 is turned OFF and the preceding switch circuit is also turned OFF, and the voltage applied to the collector terminal of the preceding transistor MTR 21, which is the voltage applied to the base terminal of the succeeding transistor MTR 22, is raised to the + 5V side by the resistor MR 32. As a result, the rear-stage transistor MTR22 is turned on, and the rear-stage switch circuit is also turned on. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR21 is raised to the + 5V side and the transistor MTR21 is turned ON. The front-stage switch circuit is also turned on, and the voltage applied to the collector terminal of the front-stage transistor MTR21, which is the voltage applied to the base terminal of the rear-stage transistor MTR22, is lowered to the ground (GND) side, thereby The transistor MTR22 is turned off, and the subsequent switch circuit is also turned off.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Because the signal is input to the PR terminal, which is the terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, becomes logic LOW and is input to the base terminal of the transistor MTR21 in the previous stage. The transistor MTR21 is turned off. As a result, the voltage applied to the collector terminal of the former-stage transistor MTR21 is pulled up to the + 5V side by the resistor MR32 and applied to the base terminal of the latter-stage transistor MTR22, thereby turning on the latter-stage transistor MTR22. As a result, the voltage applied to the collector terminal of the subsequent transistor MTR22 is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness), so that the payout power failure warning signal whose logic is LOW is issued. Input to the control board 4110.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, becomes logic HI and becomes the base terminal of the transistor MTR21 in the previous stage. As a result of the input, the previous-stage transistor MTR21 is turned ON. As a result, the voltage applied to the collector terminal of the preceding transistor MTR21 is pulled down to the ground (GND) and applied to the base terminal of the succeeding transistor MTR22, thereby turning off the succeeding transistor MTR22. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to + 12V side by the pull-up resistor in the payout control input circuit 4120b of the payout control unit 4120 in the payout control board 4110 via the wiring (harness). A payout power failure notice signal whose logic is HI is input to the payout control board 4110.

  Further, as shown in FIG. 20, the main control output circuit 4100cb having no reset function for outputting a signal output from the 1Q terminal which is an output terminal of the D type flip-flop MIC22 to the peripheral control board 4140 as a peripheral power failure warning signal is The circuit is configured as a collector output type, and the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the base terminal of the transistor MTR23 via the resistor MR35. And are electrically connected. In addition to being electrically connected to the resistor MR35, one end of the transistor MTR23 is electrically connected to the other end of the resistor MR36 that is grounded to the ground (GND). The emitter terminal of the transistor MTR23 is grounded to the ground (GND), and the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness). When the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness), a payout control input circuit (not shown) of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. In FIG. 14, one end is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power line, and is electrically connected to an input terminal of a predetermined input port of the peripheral control MPU 4150a shown in FIG. Connected.

  The circuit composed of the resistors MR35 and MR36 and the transistor MTR23 is a switch circuit that is turned ON / OFF by a signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR23 is pulled down to the ground (GND) side, and the transistor MTR23 is turned OFF. The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR23 is raised to the + 5V side, and the transistor MTR23 is turned on. The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Since the signal is output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, the logic becomes LOW and is input to the base terminal of the transistor MTR23. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR23 is pulled up to + 12V by the pull-up resistor in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via the wiring (harness), so that the logic becomes HI. The peripheral power failure warning signal is input to the peripheral control board 4140.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal that is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 becomes the logic HI and is input to the base terminal of the transistor MTR23. As a result, the transistor MTR23 is turned ON. As a result, the peripheral power failure notice signal whose logic is LOW is generated when the voltage applied to the collector terminal of the transistor MTR23 is pulled down to the ground (GND) side in the peripheral control board 4140 via the wiring (harness). 4140 is input.

  As described above, the main control input circuit 4100b that transmits the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 to the main control MPU 4100a as a power failure warning signal, and the 1Q terminal that is the output terminal of the D-type flip-flop MIC22. The main control output circuit 4100cb without reset function for outputting the signal output from the peripheral control board 4140 to the peripheral control board 4140 has one transistor, and the power failure warning signal input to the main control MPU 4100a and the peripheral While the logic of the peripheral power failure warning signal input to the control board 4140 is the same logic, the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is sent out to the payout control board 4110 No reset function to output as a power failure warning signal The control circuit 4100cb has two transistors, a front stage and a rear stage, and the logic of the payout power failure warning signal is the logic of the power failure warning signal input to the main control MPU 4100a and the peripheral power failure warning signal input to the peripheral control board 4140. The logic of the signal is inverted and is different from the logic of the power failure warning signal and the logic of the peripheral power failure warning signal.

  The collector terminal of the transistor MTR20 of the main control input circuit 4100b is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and the main control MPU 4100a via the non-inverting buffer ICMIC23. The collector terminal of the transistor MTR22 at the subsequent stage of the main control output circuit 4100cb without reset function is electrically connected to the input terminal PA1 of the input port PA of the payout control board via the wiring (harness). In the payout control input circuit 4120b of the payout control unit 4120 in 4110, one end is electrically connected to the other end of the pull-up resistor electrically connected to the + 12V power supply line, and the main control output circuit 4100cb without reset function is connected. The collector terminal of the transistor MTR23 is Wiring through a (harness), the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140, which is a pull-up resistor electrically connected to one end of which is connected + 12V power supply line and electrically. This is because the transistor MTR20 and the main control MPU 4100a of the main control input circuit 4100b are connected to the main control board between the collector terminal of the transistor MTR20 of the main control input circuit 4100b and the input terminal PA1 of the input port PA of the main control MPU 4100a. 4100, the main control board 4100 and the payout control board are used to perform the power outage notice by the logic (ON / OFF signal) of the power outage notice signal using + 5V which is the control reference voltage of the main control MPU 4100a. In order to suppress the influence of noise entering the wiring (harness) electrically connecting between the boards, the main control MPU 4100a, between the boards with 4110 and between the boards with the main control board 4100 and the peripheral control board 4140, Dispensing control MPU 4120a and peripheral control MPU 4150a Is performed blackout notice by the logic of a control reference voltage + 5V is at a higher voltage than the + with 12V power failure warning signal (ON / OFF signal).

[9-6. Various input / output signals to main control MPU]
Next, various input / output signals to the main control MPU 4100a will be described with reference to FIG. The RXA terminal which is the serial data input terminal of the serial input port of the main control MPU 4100a receives serial data from the payout control board 4110 shown in FIG. 11 as a payer serial data reception signal via the main control input circuit 4100b. . On the other hand, the TXA terminal and the TXB terminal, which are serial data output terminals of the serial output port of the main control MPU 4100a, receive the serial data transmitted from the TXA terminal to the payout control board 4110 as a main payout serial data transmission signal and do not have a reset function. A main payment serial data transmission signal is transmitted to the payout control board 4110 from the main control output circuit 4100cb without reset function to the circuit 4100cb, and the serial data to be sent to the peripheral control board 4140 shown in FIG. The peripheral serial data transmission signal is transmitted to the main control output circuit 4100cb without reset function, and the main peripheral serial data transmission signal is transmitted from the main control output circuit 4100cb without reset function to the peripheral control board 4140.

  In addition to the above-described operation signal (RAM clear signal) being input to each input terminal of a predetermined input port of the main control MPU 4100a, for example, a payout for notifying the completion of normal reception of the above-described main payment serial data reception signal A payer ACK signal from the control board 4110 is input via the main control input circuit 4100b, and detection signals from various switches such as the upper start port switch 3022 shown in FIG. 11 are input via the main control input circuit 4100b. It is input.

  On the other hand, from each output terminal of a predetermined output port of the main control MPU 4100a, for example, a main payment ACK signal that indicates the completion of normal reception of the above-described payment serial data reception signal is output to the main control output circuit 4100ca with reset function. Then, a main payout ACK signal is output from the main control output circuit 4100ca with reset function to the payout control board 4110, or a drive signal is sent to the main control output circuit 4100ca with reset function for the start port solenoid 2105 shown in FIG. To output a drive signal from the main control output circuit 4100ca with reset function to the start port solenoid 2105 via the main control solenoid drive circuit 4100d, or various displays such as the upper special symbol display 1185 shown in FIG. Drive signal to the main control output circuit 4100ca with reset function. Output to the equally and outputs a drive signal respectively to various indicator from resetting function main control output circuit 4100Ca.

[9-7. Interface circuit for communication between main control board and peripheral control board]
Next, a communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described with reference to FIG. The main control board 4100 is supplied with + 12V from the power supply board 851 shown in FIG. 17 via the payout control board 4110, and the + 5V creation circuit 4100g creates + 5V that is the control reference voltage of the main control MPU 4100a from this + 12V. ing. The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is affected by noise entering the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140. Therefore, the reliability is enhanced by using + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU 4100a.

  Specifically, the main control board 4100 causes the main control output circuit 4100cb without a reset function to function as a communication interface circuit, and the communication interface circuit mainly includes a resistor MR50, resistors MR51 and MR52, and a transistor MTR50. Has been. On the other hand, the peripheral control board 4140 includes a diode AD10, an electrolytic capacitor AC10 (capacitance: 47 μF in this embodiment), and a photocoupler AIC10 (infrared LED and photo IC) as a communication interface circuit. It is mainly configured).

  + 12V supplied from the power supply board 851 is applied to the anode terminal of the diode MD50 of the main control board 4100 through the payout control board 4110, and the minus terminal is grounded to the ground (GND) to the cathode terminal of the diode MD50. The electrolytic capacitor MC50 (capacitance: 220 microfarad (μF) in this embodiment) is electrically connected to the plus terminal. The cathode terminal of the diode MD50 is electrically connected to the positive terminal of the electrolytic capacitor MC50, and is electrically connected to the anode terminal (first terminal) of the photocoupler AIC10 of the peripheral control board 4140 via a wiring (harness). It is connected to the. Thereby, for example, when power from the power supply board 851 is not supplied to the main control board 4100 via the payout control board 4110 due to a power failure or a momentary power failure, the charge charged in the electrolytic capacitor MC50 is reduced. + 12V can be continuously applied from the main control board 4100 to the anode terminal of the photocoupler AIC 10 of the peripheral control board 4140.

  As described above, the power supply terminal VDD of the main control MPU 4100a is charged to the electrolytic capacitor MC2 shown in FIG. 19 (capacitance: 470 μF in this embodiment) when a power failure or a momentary power failure occurs. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a serially manages at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb. The unit 4100aec can transfer the data to the transmission shift register 41aea and complete the transmission from the transmission shift register 4100aea as main peripheral serial data.

  The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is connected to the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140 as described above. In order to suppress the influence of intruding noise, the reliability is enhanced by transmitting + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU 4100a.

  Therefore, in the present embodiment, when a power failure or a momentary power failure occurs, the charge charged in the electrolytic capacitor MC50 is applied as +12 V to the anode terminal of the photocoupler AIC10 of the peripheral control board 4140 from the main control board 4100. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a transfers the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb to the transmission shift register 41aea by the serial management unit 4100aec and transmits it. When transmission is performed from the shift register 4100aea as main circumference serial data, a main circumference serial data transmission signal having a logic level of HI can be transmitted from the collector terminal of the transistor MTR50 by + 12V.

  In this embodiment, the storage capacity of the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a has 32 bytes, and one packet is composed of 3 bytes of data. Therefore, data for 10 packets at the maximum is stored in the transmission buffer register 4100aeb. In this embodiment, the transfer bit rate of the main peripheral serial data transmitted from the main control MPU 4100a is set to 19200 bps.

  The cathode terminal (third terminal) of the photocoupler AIC10 is electrically connected to the collector terminal of the transistor MTR50 of the main control board 4100 via the resistor AR10 and its wiring (harness). The resistor AR10 of the peripheral control board 4140 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler AIC10.

  The TXB terminal that outputs the main serial data transmission signal from the main control MPU 4100a shown in FIG. 19 is electrically connected to the other end of the resistor MR50 that is electrically connected to the + 5V power supply line, and has the resistor MR51. And is electrically connected to the base terminal of the transistor MTR50. In addition to being electrically connected to the resistor MR51, one end of the transistor MTR50 is electrically connected to the other end of the resistor MR52 that is grounded to the ground (GND). The emitter terminal of the transistor MTR50 is grounded with the ground (GND).

  The circuit composed of the resistors MR51 and MR52 and the transistor MTR50 is a switch circuit. When the logic of the main serial data transmission signal is HI, the voltage applied to the base terminal of the transistor MTR50 is on the ground (GND) side. As a result, the transistor MTR50 is turned off, and the switch circuit is also turned off. As a result, the forward current does not flow through the built-in infrared LED of the photocoupler AIC10 on the peripheral control board 4140, so the photocoupler AIC10 is turned off. On the other hand, when the logic of the main serial data transmission signal is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to + 5V by the resistor MR50, turning on the transistor MTR50 and turning on the switch circuit. . As a result, a forward current flows through the built-in infrared LED of the photocoupler AIC10 on the peripheral control board 4140, so that the photocoupler AIC10 is turned on.

  + 5V supplied from the power supply board 851 is applied to the anode terminal of the diode AD10 of the peripheral control board 4140 via the frame peripheral relay terminal board 868, and the cathode terminal of the diode AD10 is connected to the ground (GND). It is electrically connected to the plus terminal of the electrolytic capacitor AC10 to be grounded. In addition to being electrically connected to the positive terminal of the electrolytic capacitor AC10, the cathode terminal of the diode AD10 is also electrically connected to the Vcc terminal (No. 6 terminal) that is the power supply terminal of the photocoupler AIC10. The emitter terminal (No. 4 terminal) of the photocoupler AIC10 is grounded to the ground (GND), and the collector terminal (No.5 terminal) of the photocoupler AIC10 is a pull-up resistor electrically connected to the plus terminal of the electrolytic capacitor AC10. It is pulled up to + 5V by AR11 and is electrically connected to the input terminal of the serial I / O port for the main control board of the peripheral control MPU 4150a. When the photocoupler AIC10 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler AIC10 changes, and the signal is used as the main peripheral serial data transmission signal as the serial I / O port for the main control board of the peripheral control MPU4150a. Is input to the input terminal.

  Thereby, as described above, for example, when a power failure or a momentary power failure occurs, +5 V supplied from the power supply board 851 is not supplied to the peripheral control board 4140 via the frame peripheral relay terminal board 868. The electric charge charged in the electrolytic capacitor AC10 can be continuously applied to the Vcc terminal of the photocoupler AIC10 as + 5V. When electric power or a momentary power failure occurs, + 5V from the electrolytic capacitor AC10 is applied, so that the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is sent to the main control MPU 4100a. The data set in the transmission buffer register 4100aeb of the built-in main circumference serial transmission port 4100ae can be completed, and the main circumference serial data transmission signal in the middle of transmission, that is, the main circumference serial data is cut off. The peripheral control board 4140 reliably receives the signal without being lost or missing.

  When the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is HI, the voltage applied to the base terminal of the transistor MTR50 is pulled down to the ground (GND) side and the transistor Since the photocoupler AIC10 is turned off when the MTR50 is turned off, the voltage applied to the collector terminal of the photocoupler AIC10 is pulled up to the + 5V side by the pull-up resistor AR11, and the logic becomes HI. While the serial data transmission signal is input to the input terminal of the serial I / O port for the main control board of the peripheral control MPU 4150a, the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 When is LOW Is applied to the collector terminal of the photocoupler AIC10 because the voltage applied to the base terminal of the transistor MTR50 is pulled up to + 5V by the resistor MR50 and the transistor MTR50 is turned on so that the photocoupler AIC10 is turned on. The main peripheral serial data transmission signal whose logic is LOW by the pulled voltage being pulled down to the ground (GND) side is input to the input terminal of the main control board serial I / O port of the peripheral control MPU 4150a. Thus, the logic of the main circumference serial data transmission signal output from the collector terminal of the photocoupler AIC10 is the same as the logic of the main circumference serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140. It is the logic of

  As described above, in this embodiment, the + 5V power supply line to which + 5V that is the control reference voltage of the main control MPU 4100a is applied, and the + 12V power supply line to which + 12V that is the communication voltage applied via the diode MD50 is applied. Measures are taken when a power failure or a momentary power failure occurs and the control reference voltage and the communication voltage drop. That is, for the main peripheral serial transmission port 4100ae built in the main control MPU 4100a, a + 5V power supply line, a positive terminal of the electrolytic capacitor MC2 using the electrolytic capacitor MC2 of the main control filter circuit 4100h as a first auxiliary power supply, Are electrically connected in parallel, so that even if a power failure or a momentary power failure occurs and the control reference voltage applied from the + 5V power supply line decreases, the electrolytic capacitor of the main control filter circuit 4100h as the first auxiliary power supply By applying the control reference voltage from the plus terminal of MC2, the state in which the control reference voltage is applied can be maintained, and the resistor MR50, the resistors MR51 and MR52, and the transistor MTR50 are configured. Main function without reset function to function as a communication interface circuit For the output circuit 4100cb, + 12V applied to the + 12V power supply line is applied as a communication voltage to the anode terminal of the diode MD50, and the positive terminal of the cathode terminal of the diode MD50 and the electrolytic capacitor MC50 as the second auxiliary power supply. Even if a power failure or a momentary power failure occurs and the communication voltage applied from the + 12V power supply line via the diode MD50 is reduced by the terminals being electrically connected in parallel, the second auxiliary power supply is provided. By applying the communication voltage from the positive terminal of the electrolytic capacitor MC50, the state where the communication voltage is applied can be maintained. As a result, it is possible to prevent the command being transmitted from the main control board 4100 to the peripheral control board 4140 from being broken, and to prevent omission of the command, so that the peripheral control board 4140 reliably receives the command being transmitted. can do. Therefore, it is possible to eliminate the missed command immediately after the occurrence of a power failure or during a momentary power failure.

  A plurality of commands set in the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a are all composed of a resistor MR50, resistors MR51 and MR52, and a transistor MTR50 as main peripheral serial data. 470 μF is set as the capacitance of the electrolytic capacitor MC2 of the main control filter circuit 4100h so that the transmission to the peripheral control board 4140 can be completed via the main control output circuit 4100cb having no reset function that functions as a communication interface circuit. 220 μF is set as the capacitance of the electrolytic capacitor MC50. As a result, even if a power failure or a momentary power failure occurs during transmission from the main control board 4100 to the peripheral control board 4140, a reset that causes all of the commands set in the transmission buffer register 4100aeb to function as an interface circuit as main peripheral serial data Since the transmission to the peripheral control board 4140 can be completed via the non-functional main control output circuit 4100cb, the peripheral control board 4140 can omit a plurality of commands set in the transmission buffer register 4100aeb without missing them. And can be received reliably.

[10. Dispensing control board circuit]
Next, the circuit and the like of the payout control board 4110 shown in FIG. 12 will be described with reference to FIGS. 22 is a circuit diagram showing a circuit and the like of the payout control unit, FIG. 23 is a circuit diagram showing a payout control input circuit, FIG. 24 is a circuit diagram showing a continuation of FIG. 23, and FIG. 26 is a circuit diagram showing a CR unit input / output circuit. FIG. 27 is an input / output diagram showing various input / output signals to / from the main control board and various output signals to the external terminal board. It is. First, the payout control filter circuit will be described, and then the payout control circuit, various input / output signals with the main control board, and various output signals to the external terminal board will be described.

[10-1. Dispensing control filter circuit]
As shown in FIG. 22, the payout control filter circuit 4110a mainly includes a payout control three-terminal filter PIC0. This payout control three-terminal filter PIC0 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite. The first terminal of the payout control three-terminal filter PIC0 is applied with + 5V from the power supply board 851 shown in FIG. 17, and is electrically connected to the other end of the capacitor PC0 whose one end is grounded to the ground (GND). Then, + 5V from the power supply board 851 is first smoothed by removing the ripple (the AC component superimposed on the voltage) by the capacitor PC0. The second terminal of the payout control 3-terminal filter PIC0 is grounded to the ground (GND), and the third terminal of the payout control 3-terminal filter PIC0 outputs +5 V from which noise components have been removed.

  The third terminal of the payout control three-terminal filter PIC0 has one end connected to the ground (GND) and the other end of the capacitor PC1 and the electrolytic capacitor PC2 (capacitance: 180 microfarad (μF) in this embodiment). By being electrically connected to each other, the ripple is further removed from the +5 V output from the third terminal of the payout control three-terminal filter PIC0 and smoothed. The smoothed + 5V is applied to a power supply terminal of the payout control system reset PIC1, a VCC terminal that is a power supply terminal of the payout control crystal oscillator PX0, a VDD terminal that is a power supply terminal of the payout control MPU 4120a, and the like. .

  The VDD terminal of the payout control MPU 4120a is electrically connected to the other end of the capacitor PC3 whose one end is grounded (GND), and + 5V applied to the VDD terminal is smoothed by further removing ripples by the capacitor PC3. ing. The VSS terminal, which is the ground terminal of the payout control MPU 4120a, is grounded to the ground (GND).

  Further, the VDD terminal of the payout control MPU 4120a is electrically connected to the anode terminal of the diode PD0 in addition to being electrically connected to the capacitor PC3. The cathode terminal of the diode PD0 is electrically connected to a VBB terminal that is a power supply terminal of a RAM (payout control built-in RAM) built in the payout control MPU 4120a, and one end of the capacitor PC4 is grounded to the ground (GND). Is electrically connected to the other end. In addition to being electrically connected to the cathode terminal of the diode PD0 and the other end of the capacitor PC4, the VBB terminal of this payout control built-in RAM is connected to the plus of the capacitor BC1 of the power supply board 851 shown in FIG. It is electrically connected to the terminal. That is, +5 V smoothed by removing noise components by the payout control filter circuit 4110a is applied to the VDD terminal of the payout control MPU 4120a, and via the diode PD0, the VBB terminal of the payout control built-in RAM and the capacitor BC1. Are applied to the positive terminal. Accordingly, as described above, when + 5V generated by the power generation circuit 855d of the power supply board 851 shown in FIG. 17 is not supplied to the payout control board 4110, the charge charged in the capacitor BC1 is discharged. Since the current is blocked by the diode PD0 and does not flow to the VDD terminal of the payout control MPU 4120a, the payout control MPU 4120a does not operate, but the VBB terminal of the payout control built-in RAM does not flow. The stored contents are held by applying the payment VBB.

[10-2. Circuit of payout control unit]
As shown in FIG. 22, the payout control unit 4120 includes a payout control MPU 4120a, a payout control input circuit 4120b, a payout control output circuit 4120c, a payout motor drive circuit 4120d, and a CR unit input / output circuit 4120e as peripheral circuits. The payout control system reset PIC1 that outputs a signal and the payout control crystal oscillator PX0 that outputs a clock signal (in this embodiment, 8 megahertz (MHz)) are mainly configured. Here, the payout control system reset will be described first, followed by the payout control crystal oscillator, the payout control input circuit, the payout motor drive circuit, the CR unit input / output circuit, and various input / output signals to the payout control MPU.

[10-2-1. Payment control system reset]
As shown in FIG. 22, + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is applied to the power supply terminal of the payout control system reset PIC1. The payout control system reset PIC1 resets the payout control MPU 4120a and the payout control output circuit 4120ca with reset function, and has a built-in delay circuit. One end of the delay control terminal of the payout control system reset PIC1 is electrically connected to the other end of the capacitor PC5 grounded to the ground (GND), and the delay time by the delay circuit is set by the capacitance of the capacitor PC5. Be able to. Specifically, the payout control system reset PIC1 outputs a system reset signal from the output terminal after the delay time elapses when + 5V input to the power supply terminal reaches a threshold value (for example, 4.25V).

  The output terminal of the payout control system reset PIC1 is electrically connected to the SRT0 terminal, which is a reset terminal of the payout control MPU 4120a, and the reset terminal of the payout control output circuit 4120ca with reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor PR1, which is electrically connected to the + 5V power supply line, and one end of which is grounded to the ground (GND). The other end of the PC 6 is electrically connected. The capacitor PC6 plays a role as a low-pass filter. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to + 5V side by the pull-up resistor PR1, and the logic becomes HI. This logic is the SRT0 terminal of the payout control MPU 4120a and the payout control output with reset function. When the voltage inputted to the reset terminal of the circuit 4120ca is smaller than the threshold value, the logic becomes LOW when the voltage inputted to the power supply terminal is smaller than the threshold value. This logic is the SRT0 terminal of the payout control MPU 4120a and Each is input to the reset terminal. Since the SRT0 terminal of the payout control MPU 4120a and the reset terminal of the payout control output circuit 4120ca with reset function are negative logic inputs, respectively, the payout control MPU 4120a and the reset function when the voltage input to the power supply terminal is smaller than the threshold value. The attached payout control output circuit 4120ca is reset. The power supply terminal is electrically connected to the other end of the capacitor PC7 whose one end is grounded (GND), and + 5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded with a grant (GND), and the NC terminal is not electrically connected to the outside.

[10-2-2. Dispensing control crystal oscillator]
As shown in FIG. 22, + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is input to the VCC terminal which is the power supply terminal of the payout control crystal oscillator PX0. The VCC terminal is electrically connected to the other end of the capacitor PC8, one end of which is grounded (GND), and + 5V input to the VCC terminal is further smoothed by removing ripples. In addition to the VCC terminal, the smoothed + 5V is also applied to an OE terminal that is an output enable terminal of the payout control crystal oscillator PX0. The payout control crystal oscillator PX0 outputs an 8 MHz clock signal from the OUT terminal, which is an output terminal, by applying +5 V to its OE terminal.

  The OUT terminal of the payout control crystal oscillator PX0 is electrically connected to the MCLK terminal which is the clock terminal of the payout control MPU 4120a, and an 8 MHz clock signal is input to the payout control MPU 4120a. Note that the GND terminal, which is the ground terminal of the payout control crystal oscillator PX0, is grounded to the grant (GND).

[10-2-3. Dispensing control input circuit]
The payout control input circuit 4120b receives the payout blackout notice signal from the door frame open switch 618, the main body frame open switch 619 shown in FIG. 12, and the blackout monitor circuit 4100e provided in the main control board 4100 shown in FIG. These circuits include a circuit, a handle relay terminal plate 192 shown in FIG. 12, a circuit to which a detection signal from the full switch 550 is input via the power supply board 851, a circuit to which an operation signal from the operation switch 860a is input, and the like. First, the circuit to which the detection signal from the door frame opening switch is input will be described, then the circuit to which the detection signal from the main body frame opening switch will be input, the circuit to which the payout power failure warning signal from the power failure monitoring circuit will be input, A circuit to which a detection signal from the full switch is input and a circuit to which an operation signal from the operation switch is input will be described. Note that the full switch 550 and various detection switches such as the ball break switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 12 have an output terminal of an open collector output type. Since the circuit configuration to which the detection signal is input is substantially the same, here, a circuit to which the detection signal from the full switch is input will be described.

[10-2-3 (a). Circuit where detection signal from door frame opening switch is input]
The door frame opening switch 618 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducted) with the door frame 5 opened from the main body frame 3 shown in FIG. The switch is turned off (cut) while 5 is closed to the main body frame 3. The second terminal of the door frame opening switch 618 is grounded to the ground (GND), while the first terminal of the door frame opening switch 618 is a pull-up resistor PR20 whose one end is electrically connected to the + 5V power line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21. The base terminal of the transistor PTR20 is electrically connected to the resistor PR21, and one end thereof is electrically connected to the other end of the resistor PR22 that is grounded to the ground (GND). Further, the first terminal of the door frame opening switch 618 is electrically connected to the pull-up resistor PR20, and is also electrically connected to the other end of the capacitor PC20 that is grounded to the ground (GND). . The emitter terminal of the transistor PTR20 is grounded to the ground (GND), and the collector terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR23, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Dispensing control via ICPIC 20 (non-inverted buffer ICPIC 20 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC20A) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA0 of the input port PA. When the transistor PTR20 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR20 changes, and the signal is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a as a door opening signal.

  The first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and the + 5V side by the pull-up resistor PR20. And is electrically connected to the base terminal of the transistor PTR21 via the resistor PR24. In addition to being electrically connected to the resistor PR24, one end of the transistor PTR21 is electrically connected to the other end of the resistor PR25 that is grounded to the ground (GND). The emitter terminal of the transistor PTR21 is grounded to the ground (GND), and the collector terminal of the transistor PTR21 is electrically connected to the external terminal plate 784 via a wiring (harness). Note that when the collector terminal of the transistor PTR21 is electrically connected to the external terminal plate 784 via a wiring (harness), one end of the external terminal plate 784 is electrically connected to the + 12V power line. It is electrically connected to the other end of the up resistor. When the transistor PTR21 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR21 changes, and the signal is input to the external terminal plate 784 as the outer end frame door opening information output signal.

  Further, the first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and at the + 5V side by the pull-up resistor PR20. To the base terminal of the transistor PTR21 via the resistor PR24, and to the + 5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR22 via the resistor PR26. ing. The base terminal of the transistor PTR22 is electrically connected to the resistor PR26, and one end is electrically connected to the other end of the resistor PR27 that is grounded to the ground (GND). The emitter terminal of the transistor PTR22 is grounded to the ground (GND), and the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 shown in FIG. 11 via a wiring (harness). When the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 via wiring (harness), one end of the collector terminal of the main control input circuit 4100b of the main control board 4100 shown in FIG. The other end of a pull-up resistor (not shown) that is electrically connected to the line is electrically connected. When the transistor PTR22 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR22 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

  The circuit composed of the pull-up resistor PR20 and the capacitor PC20 is a switch signal generation circuit. When the door frame 5 is opened from the main body frame 3, or when the door frame 5 is closed by the main body frame 3, It is configured as a circuit that also has a function of absorbing voltage fluctuations from the door frame opening switch 618 due to a fluttering phenomenon in which the contacts constituting the door frame opening switch 618 are repeatedly turned on and off for a short time.

  The circuit composed of the resistors PR21 and PR22 and the transistor PTR20, the circuit composed of the resistors PR24 and PR25 and the transistor PTR21, and the circuit composed of the resistors PR26 and PR27 and the transistor PTR22 are a door frame opening switch. A switch circuit that is turned ON / OFF by a detection signal from 618.

  In the state where the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR20 is pulled down to the ground (GND) side, whereby the transistor PTR20 is The switch circuit is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR23, and the door frame opening signal whose logic becomes HI is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. The Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR21 is pulled down to the ground (GND) side, so that the transistor The PTR 21 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled up to + 12V side by the pull-up resistor of the external terminal board 784 via the wiring (harness), and the outer end frame door opening information output signal whose logic becomes HI. Is input to the external terminal board 784. Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR22 is lowered to the ground (GND) side, thereby causing the transistor The PTR 22 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR22 is pulled up to the + 12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door opening signal is input to the main control board 4100.

  On the other hand, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR20. Thus, the transistor PTR20 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled down to the ground (GND) side and the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a. In addition, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR21 is pulled up to the + 5V side, thereby turning on the transistor PTR21. The switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled down to the ground (GND) side, and the outer end frame door opening information output signal whose logic is LOW is input to the external terminal plate 784. In addition, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR22 is raised to the + 5V side so that the transistor PTR22 is turned ON. The switch circuit is also turned on. As a result, the main frame door opening signal in which the voltage applied to the collector terminal of the transistor PTR22 is pulled down to the ground (GND) side and the logic becomes LOW is input to the main control board 4100.

  As described above, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is turned ON, so that the door frame opening signal whose logic is HI is input to the input terminal PA of the input port PA of the dispensing control MPU 4120a. While the outer frame door opening information output signal that is input to PA0 and whose logic is HI is input to the external terminal board 784, the main frame door opening signal that is logic is HI is input to the main control board 4100, When the door frame 5 is closed by the main body frame 3, the door frame opening switch 618 is turned OFF, so that the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the dispensing control MPU 4120a. The outer frame door opening information output signal whose logic is LOW is input to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

[10-2-3 (b). A circuit to which the detection signal from the body frame opening switch is input]
The body frame opening switch 619 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducted) with the body frame 3 opened from the outer frame 2 shown in FIG. The switch is turned off (cut) while 3 is closed by the outer frame 2. The second terminal of the body frame opening switch 619 is grounded to the ground (GND), while the first terminal of the body frame opening switch 619 is connected to the other end of the pull-up resistor PR28 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR23 via the resistor PR29. In addition to being electrically connected to the resistor PR29, one end of the transistor PTR23 is electrically connected to the other end of the resistor PR30 that is grounded to the ground (GND). In addition to being electrically connected to the pull-up resistor PR28, the first terminal of the body frame opening switch 619 is also electrically connected to the other end of the capacitor PC21 that is grounded to the ground (GND). . The emitter terminal of the transistor PTR23 is grounded to the ground (GND), the collector terminal of the transistor PTR23 is electrically connected to the collector terminal of the transistor PTR21 described above, and is connected to the external terminal plate 784 via a wiring (harness). Electrically connected. Note that when the collector terminal of the transistor PTR23 is electrically connected to the external terminal plate 784 via a wiring (harness), one end of the external terminal plate 784 is electrically connected to the + 12V power line. It is electrically connected to the other end of the up resistor. When the transistor PTR23 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR23 changes, and the signal is input to the external terminal plate 784 as the outer end frame door opening information output signal.

  Further, the first terminal of the body frame opening switch 619 is pulled up to the + 5V side by the pull-up resistor PR28 and is electrically connected to the base terminal of the transistor PTR23 through the resistor PR29, and the + 5V side by the pull-up resistor PR28. And is electrically connected to the base terminal of the transistor PTR24 via the resistor PR31. In addition to being electrically connected to the resistor PR31, one end of the transistor PTR24 is electrically connected to the other end of the resistor PR32 that is grounded to the ground (GND). The emitter terminal of the transistor PTR24 is grounded to the ground (GND), and the collector terminal of the transistor PTR24 is electrically connected to the collector terminal of the transistor PTR22 described above and shown in FIG. 11 via a wiring (harness). The main control board 4100 is electrically connected. Note that when the collector terminal of the transistor PTR24 is electrically connected to the main control board 4100 via wiring (harness), one end of the collector terminal of the main control input circuit 4100b of the main control board 4100 shown in FIG. The other end of a pull-up resistor (not shown) that is electrically connected to the line is electrically connected. When the transistor PTR24 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR24 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

  The circuit composed of the pull-up resistor PR28 and the capacitor PC21 is a switch signal generation circuit, and when the main body frame 3 is opened from the outer frame 2 or when the main body frame 3 is closed by the outer frame 2, The contacts constituting the body frame opening switch 619 are configured as a circuit that also has a function of absorbing fluctuations in voltage from the body frame opening switch 619 due to a fluttering phenomenon in which the contacts that repeatedly turn ON / OFF repeatedly.

  A circuit composed of the resistors PR29 and PR30 and the transistor PTR23 and a circuit composed of the resistors PR31 and PR32 and the transistor PTR24 are switch circuits that are turned on / off by a detection signal from the body frame opening switch 619.

  In the state where the main body frame 3 is opened from the outer frame 2, the main body frame opening switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR23 is pulled down to the ground (GND) side, whereby the transistor PTR23 is turned on. The switch circuit is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784 via the wiring (harness), and the outer end frame door opening information output signal whose logic becomes HI. Is input to the external terminal board 784. In the state where the main body frame 3 is opened from the outer frame 2, the main body frame opening switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR 24 is lowered to the ground (GND) side, so that the transistor The PTR 24 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR24 is pulled up to the + 12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door opening signal is input to the main control board 4100.

  On the other hand, when the main body frame 3 is closed by the outer frame 2, the main body frame opening switch 619 is OFF, so that the voltage applied to the base terminal of the transistor PTR23 is pulled up to the + 5V side by the pull-up resistor PR28. Thus, the transistor PTR23 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled down to the ground (GND) side in the external terminal board 784 via the wiring (harness), and the outer frame door opening information output signal whose logic becomes LOW is output. Input to the external terminal board 784. In the state where the main body frame 3 is closed by the outer frame 2, the main body frame opening switch 619 is OFF, so that the voltage applied to the base terminal of the transistor PTR24 is pulled up to the + 5V side by the pull-up resistor PR28. As a result, the transistor PTR24 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 24 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness), and the main frame door open signal whose logic is LOW is generated in the main control board. 4100 is input.

  As described above, when the main body frame 3 is released from the outer frame 2, the main body frame opening switch 619 is turned on so that the outer end frame door opening information output signal whose logic is HI is input to the external terminal plate 784. When the main frame door opening signal whose logic is HI is input to the main control board 4100, while the main body frame 3 is closed to the outer frame 2, the main body frame opening switch 619 is turned OFF, Is output to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

  In the present embodiment, as described above, one or both of the state in which the door frame 5 is closed by the main body frame 3 and the state in which the main body frame 3 is opened from the outer frame 2 are used. Even in this case, since the main frame door opening signal is input to the main control board 4100, the main control MPU 4100a of the main control board 4100 shown in FIG. Although it is not possible to determine whether the door frame 5 is opened from the main body frame 3 or the main body frame 3 is opened from the outer frame 2, the door frame 5 and / or It can be determined that a state in which the player has opened the main body frame 3 does not occur during a normal game, and an outer end frame door opening information output signal is output to the external terminal board 784. This outer edge because it is designed to be entered The door opening information output signal is transmitted to the hall computer via the external terminal board 784, and the hall computer is in a state where the door frame 5 is opened from the main body frame 3 based on the outer frame door opening information output signal. Although it cannot be determined whether or not the main body frame 3 is opened from the outer frame 2, there is a state in which the player does not occur during normal games that the door frame 5 and / or the main body frame 3 are opened. It can be determined that it has occurred.

  In the present embodiment, as described above, the door frame opening switch 618 and the main body frame opening switch 619 are normally closed, so that the door frame opening switch 618 is short-circuited for some reason and the switch is turned on ( Even if the door frame 5 is opened from the main body frame 3 even if it is in a conductive state, the main body frame opening switch 619 is short-circuited for some reason and the switch is turned on (conductive). 3 is released from the outer frame 2. Thus, by adopting a normally closed switch for the door frame opening switch 618 and the main body frame opening switch 619, a main frame door opening signal can be output to the main control board 4100 even in the event of a short circuit, and the outer end The frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

  When the door frame opening switch 618 and the body frame opening switch 619 are changed from a normally closed switch to a normally open type (normally open (NO)) switch (door frame opening switch 618 ′ and body frame opening switch 619 ′). The door frame opening switch 618 ′ is turned on (conductive) when the door frame 5 is closed from the main body frame 3, and is turned off (cut) when the door frame 5 is opened to the main body frame 3. . The body frame opening switch 619 ′ is turned on (conductive) when the body frame 3 is closed from the outer frame 2, and turned off (disconnected) when the body frame 3 is opened to the outer frame 2. Then, even if the door frame opening switch 618 ′ is disconnected due to some cause and the switch is turned off (cut), the door frame 5 is opened from the main body frame 3, and the main body is not used for some reason. Even when the frame opening switch 619 ′ is disconnected and the switch is turned off (cut), the main body frame 3 is released from the outer frame 2. As described above, the door frame opening switch 618 ′ and the body frame opening switch 619 ′ can output a main frame door opening signal to the main control board 4100 even when a normally open switch is used or a disconnection occurs. An outer end frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

[10-2-3 (c). A circuit that receives a power outage warning signal from the power outage monitoring circuit]
A transmission line for transmitting a payout power failure notice signal from the power failure monitoring circuit 4100e provided on the main control board 4100 is electrically connected to the other end of the pull-up resistor PR40, one end of which is electrically connected to the + 12V power supply line, and a resistor. It is electrically connected to the base terminal of the transistor PTR40 via PR41. In addition to being electrically connected to the resistor PR41, one end of the transistor PTR40 is electrically connected to the other end of the resistor PR42 that is grounded to the ground (GND). The emitter terminal of the transistor PTR40 is grounded to the ground (GND), and the collector terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR43, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Dispensing control via ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC 40A) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA1 of the input port PA. When the transistor PTR40 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR40 changes, and the signal is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a as a payout power failure notice signal.

  A circuit composed of the resistors PR41 and PR42 and the transistor PTR40 is a switch circuit that is turned ON / OFF by a payout power failure notice signal from a power failure monitoring circuit 4100e provided in the main control board 4100.

  As described above, the power failure monitoring circuit 4100e monitors the signs of power failure or instantaneous power failure of two types of voltages, + 12V and + 24V, from the power supply board 851, and if a power failure or power failure sign is detected, there is no reset function. A payout blackout notice signal is output to the payout control board 4110 as a blackout notice via the main control output circuit 4100cb. The power failure monitoring circuit 4100e monitors the signs of a power failure or instantaneous power failure at + 12V and + 24V. As described above, the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf, and the voltage of + 12V is higher than the power failure detection voltage V2pf. When both conditions are satisfied, the voltage applied to the collector terminal of the subsequent transistor MTR22 is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness), and the logic becomes LOW. One of a condition that the + 24V voltage is smaller than the power failure detection voltage V1pf and a condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is input to the dispensing control board 4110. When the condition is satisfied, the subsequent transistor MTR22 Payout power failure warning signal of the voltage applied to the collector terminal wiring logic by via (harness) is pulled up to + 12V side by the pull-up resistor PR40 described above it becomes HI is input to the payout control board 4110.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, that is, there is no sign of power failure or instantaneous interruption of the voltages of + 12V and + 24V. In some cases, a payout power failure warning signal whose logic is LOW is input to the payout control board 4110, so that the voltage applied to the base terminal of the transistor PTR40 is pulled down to the ground (GND) side to turn off the transistor PTR40. The voltage applied to the collector terminal of the transistor PTR40 is pulled up to the + 5V side by the resistor PR43. As a result, a payout power failure warning signal whose logic is HI is input from the collector terminal of the transistor PTR40 to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, that is, the voltage of + 12V and / or + 24V When there is an indication of a power outage or a momentary power failure, a payout power outage warning signal whose logic is HI is input to the payout control board 4110 and is applied to the base terminal of the transistor PTR 40 by a payout power outage notice signal from the power outage monitoring circuit 4100e. Is pulled up to + 12V by the pull-up resistor PR40, the transistor PTR40 is turned on, and the voltage applied to the collector terminal of the transistor PTR40 is pulled down to the ground (GND) side. As a result, a payout power failure warning signal whose logic at the collector terminal of the transistor PTR40 is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  Thus, when there is an indication of a power failure or instantaneous power failure at a voltage of +12 V and / or +24 V, a payout power failure notice signal whose logic is HI is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a, When there is no sign of a power failure or a momentary power failure at voltages of +12 V and +24 V, a payout power failure notice signal whose logic is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a. This is because, as described above, when there is an indication of a power failure or a momentary power failure at a voltage of + 12V and / or + 24V, a power failure warning signal whose logic is HI is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. On the other hand, when there is no sign of + 12V and + 24V power failure or instantaneous power failure, a power failure warning signal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. The logic of the payout blackout signal input to the payout control MPU 4120a and the logic of the blackout notice signal input to the main control MPU4100a are the same logic.

[10-2-3 (d). Circuit that receives detection signal from full switch]
A detection signal from the full switch 550 provided in the foul cover unit 540 shown in FIG. 1 is sent to the payout control board 4110 via the handle relay terminal plate 192 shown in FIG. 1 and the power supply board 851 shown in FIG. Have been entered. The output terminal of the full switch 550 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and one end of the payout control board 4110 is electrically connected to the + 12V power supply line. The pull-up resistor PR44a is electrically connected to the other end of the pull-up resistor PR44a and electrically connected to the first terminal of the full-switch three-terminal filter PIC50. This full-tank switch three-terminal filter PIC50 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite.

  The second terminal of the full tank switch three-terminal filter PIC50 is grounded to the ground (GND), and the third terminal of the full tank switch three-terminal filter PIC50 is connected to the full tank switch three-terminal filter PIC50 via the resistor PR44b. Is electrically connected to the base terminal of the transistor PTR41 via the resistor PR45. Thereby, the detection signal of the full tank switch 550 is input to the base terminal of the transistor PTR 41 after the noise component is removed in the full terminal switch three-terminal filter PIC50. In addition to the resistor PR45 being electrically connected, the base terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR46 that is grounded to the ground (GND), and has one end connected to the ground (GND). The other end of the electrically connected capacitor PC40 is electrically connected. The capacitor PC40 plays a role as a low-pass filter. The emitter terminal of the transistor PTR41 is grounded to the ground (GND), and the collector terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR47, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Payout control via ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC 40B) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA2 of the input port PA. When the transistor PTR41 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR41 changes, and the signal is input as a full signal to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  A circuit composed of the resistors PR45 and PR46 and the transistor PTR41 is a switch circuit that is turned on / off in response to a detection signal from the full switch 550.

  As described above, the full tank switch 550 detects whether or not the storage space in the second ball passage of the foul cover unit 540 is full with the stored game balls. In this embodiment, when the storage space is not full with the stored game balls, the voltage applied to the output terminal of the full switch 550 is paid out via the handle relay terminal plate 192 and the power supply board 851. When the control board 4110 is pulled up to the + 12V side by the pull-up resistor 44a and the logic becomes HI, the signal is input to the payout control board 4110, while the game ball in which the accommodation space is stored is full. The voltage applied to the output terminal of the full switch 550 is pulled down to the ground (GND) side in the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851, and a signal whose logic is LOW is sent out. Input to the control board 4110.

  When the storage space is not full with the stored game balls, the voltage applied to the output terminal of the full tank switch 550 is pulled on the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal that has been pulled up to + 12V by the up resistor 44a and whose logic has become HI is input to the base terminal of the transistor PTR41 described above, the transistor PTR41 is turned ON and the switch circuit is also turned ON. As a result, a full signal in which the voltage applied to the collector terminal of the transistor PTR41 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  On the other hand, when the game ball in which the accommodation space is stored is full, the voltage applied to the output terminal of the full tank switch 550 is supplied to the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal that is pulled down to the ground (GND) side and becomes logic LOW is input to the base terminal of the transistor PTR41 described above, the transistor PTR41 is turned OFF and the switch circuit is also turned OFF. As a result, a full-tank signal whose voltage applied to the collector terminal of the transistor PTR41 is pulled up to the + 5V side by the resistor PR47 and becomes logic HI is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  In the present embodiment, the detection signal from the full switch 550 is input to a switch circuit constituted by the resistor PR45, the resistor PR46, and the transistor PTR41 via the full switch three-terminal filter PIC50. However, the detection signals from various detection switches such as the ball break switch 750, counting switch 751, and rotation angle switch 752 shown in FIG. It is a circuit configuration that is directly input to each switch circuit without going through. Since the full tank switch 550 is provided in the foul cover unit 540 attached to the door frame 5, the ball break switch 750, the counting switch 751, and the rotation angle switch 752 provided in the prize ball device 740 attached to the main body frame 3. Compared to the above, the path for transmitting the detection signal is extremely long, and it is very susceptible to noise.

  The full tank switch 550 detects whether or not the storage space in the second ball passage of the foul cover unit 540 is full with the stored game balls. The payout control MPU 4120a If it is determined that the game space in which the accommodation space is stored is full, the drive control of the payout motor 744 is forcibly stopped and the payout of the game ball by the payout rotating body is stopped. To do. In other words, when noise enters a transmission path (transmission line) that transmits a detection signal from the full tank switch 550, the payout control MPU 4120a drives the payout motor 744 even though the game ball in which the accommodation space is stored is not full. In some cases, the control is forcibly stopped and the payout of the game ball by the payout rotating body is stopped, or the payout motor 744 is driven and controlled even though the storage space is full with the stored game balls. If the game ball is filled up to the upstream side of the above-mentioned prize ball passage by rotating the payout rotator and continuing to pay out the game ball, the payout rotator itself can no longer rotate and the payout motor 744 The load is abnormal, the payout motor 744 is overloaded, abnormally generates heat and breaks down, or the rotary shaft of the payout motor 744 is transmitted to the rotary motion of the payout rotating body. Sometimes referred to 構等 is or failure. Therefore, in this embodiment, in order to prevent such a problem from occurring, the circuit configuration is adopted so that the noise component is first removed from the detection signal from the full tank switch 550 in the full terminal switch three-terminal filter PIC50. .

[10-2-3 (e). Circuit that receives operation signal from operation switch]
The output terminals 1 and 2 of the operation switch 860a are connected to the ground (GND), and the output terminals 3 and 4 of the operation switch 860a are connected to the + 5V side by the pull-up resistor PR48. It is pulled up and electrically connected to the base terminal of the previous-stage transistor PTR42 via the resistor PR49. In addition to being electrically connected to the resistor PR49, one end of the base terminal of the transistor PTR42 in the previous stage is electrically connected to the other end of the resistor PR50 that is grounded to the ground (GND). The fourth terminal, which is the output terminal of the operation switch 860a, is electrically connected to the pull-up resistor PR48, and is also electrically connected to the other end of the capacitor PC41 whose one end is grounded to the ground (GND). ing. The emitter terminal of the front-stage transistor PTR42 is grounded to the ground (GND), and the collector terminal of the front-stage transistor PTR42 is electrically connected to the other end of the resistor PR51 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the subsequent transistor PTR43 via the resistor PR52. In addition to being electrically connected to the resistor PR52, one end of the base terminal of the transistor PTR43 at the subsequent stage is electrically connected to the other end of the resistor PR53 that is grounded to the ground (GND). The emitter terminal of the rear-stage transistor PTR43 is grounded to the ground (GND), and the collector terminal of the rear-stage transistor PTR43 is electrically connected to the other end of the resistor PR54 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 40 (the non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 40C) without inversion). Via the input terminal PA2 of the input port PA of the payout control MPU 4120a. The logic of the signal output from the collector terminal of the downstream transistor PTR43 is changed by turning ON / OFF the upstream and downstream transistors PTR42 and PTR43. Is input.

  The third and fourth terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48 and are electrically connected to the base terminal of the previous transistor PTR42 via the resistor PR49. The voltage is pulled up to + 5V by the pull-up resistor PR48 and is electrically connected to the base terminal of the transistor PTR44 via the resistor PR55. In addition to being electrically connected to the resistor PR55, one end of the transistor PTR44 is electrically connected to the other end of the resistor PR56 that is grounded to the ground (GND). The emitter terminal of the transistor PTR44 is grounded to the ground (GND), and the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via a wiring (harness). Note that when the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via a wiring (harness), one end of the collector terminal of the main control input circuit 4100b of the main control board 4100 shown in FIG. It is electrically connected to the other end of pull-up resistor MR2 that is electrically connected to the power supply line. When the transistor PTR44 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR44 changes, and the signal is input as the RAM clear signal to the input terminal PA0 of the input port PA of the main control MPU 4100a.

  The circuit composed of the pull-up resistor PR48 and the capacitor PC41 is a switch signal generation circuit, and when the operation switch 860a is pressed, the contact that constitutes the operation switch 860a repeatedly turns on and off for a short time. Is configured as a circuit that also has a function of absorbing fluctuations in voltage from the operation switch 860a.

  A circuit composed of the resistors PR49 and PR50 and the transistor PTR42 is a previous-stage switch circuit, and a circuit composed of the resistors PR52 and PR53 and the transistor PTR43 is a subsequent-stage switch circuit, and the resistors PR55 and PR56 and the transistor PTR44. Is a switch circuit that is turned ON / OFF by an operation signal from the operation switch 860a.

  As described above, the operation switch 860a is connected to the RAM (payout control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 and the main control MPU 4100a of the main control board 4100 within a predetermined period from when the power is turned on. It is operated when clearing the built-in RAM (main control built-in RAM), or when an error is reported after the power is turned on, it is operated to cancel the error. A function for clearing RAM within a predetermined period from the time and canceling an error after the power is turned on (after a period during which the function is performed as a RAM clear has elapsed, that is, after a predetermined period has elapsed since the power was turned on) And has a function. The operation signal from the operation switch 860a becomes a RAM clear signal in the function of performing a RAM clear within a predetermined period from the time of turning on the power, and after the power is turned on (after a predetermined period has elapsed since the time of turning on the power). In the function for performing error cancellation in (), an error cancellation signal is generated.

  When the operation switch 860a is not operated, the operation signal whose logic becomes HI by pulling up the third terminal and the fourth terminal, which are the output terminals of the operation switch 860a, to the + 5V side by the pull-up resistor PR48 is transmitted to the previous stage transistor. When input to the base terminal of the PTR 42, the previous stage transistor PTR 42 is turned ON, and the previous stage switch circuit is also turned ON, and is applied to the collector terminal of the previous stage transistor PTR 43, which is a voltage applied to the base of the subsequent stage transistor PTR 43. As a result, the rear-stage transistor PTR43 is turned OFF, and the rear-stage switch circuit is also turned OFF. Thereby, the voltage applied to the collector terminal of the transistor PTR43 at the subsequent stage is pulled up to the + 5V side by the resistor PR54, and the RWMCLR signal whose logic becomes HI is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs a RAM clear for erasing information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is HI within a predetermined period from the time when the power is turned on. If the logic of the RWMCLR signal input to the input terminal PA3 is HI after the power is turned on (after a predetermined period has elapsed since the power was turned on), the error is canceled. Judge that it is not an instruction.

  When the operation switch 860a is not operated, the operation signal in which the output terminal of the operation switch 860a is the third terminal and the fourth terminal are pulled up to the + 5V side by the pull-up resistor PR48 and the logic becomes HI is output from the transistor PTR44. The transistor PTR44 is turned on and the switch circuit is also turned on. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor PTR44 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness) and the logic becomes LOW is sent to the main control board 4100. Entered. When the RAM clear signal whose logic is LOW is input within a predetermined period from when the power is turned on, the main control MPU 4100a of the main control board 4100, as described above, the logic shown in FIG. Is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned OFF and the switch circuit is also turned OFF. Thereby, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5 and the logic clear signal HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. The main control MPU 4100a determines that the RAM clear signal for erasing the information stored in the main control built-in RAM is not instructed when the logic of the RAM clear signal input to the input terminal PA0 is HI.

  On the other hand, when the operation switch 860a is operated, the operation signal whose logic is LOW by pulling down the third terminal and the fourth terminal, which are output terminals of the operation switch 860a, to the ground (GND) side is the transistor in the previous stage. When input to the base terminal of the PTR 42, the previous stage transistor PTR 42 is turned OFF and the previous stage switch circuit is also turned OFF, and the voltage applied to the base of the rear stage transistor PTR 43 is applied to the collector terminal of the previous stage transistor PTR 42. As a result, the subsequent transistor PTR43 is turned on and the subsequent switch circuit is also turned on. Thereby, the voltage applied to the collector terminal of the transistor PTR43 at the subsequent stage is pulled down to the ground (GND) side, and the RWMCLR signal whose logic is LOW is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs a RAM clear for erasing information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is LOW within a predetermined period from when the power is turned on. If the logic of the RWMCLR signal input to the input terminal PA3 is LOW after the power is turned on (after a predetermined period has elapsed since the power was turned on), the error is canceled. Judge that it is an instruction.

  In addition, when the operation switch 860a is being operated, an operation in which the logic becomes LOW because the third and fourth terminals, which are output terminals of the operation switch 860a, are pulled down to the ground (GND) side by the pull-up resistor PR48. A signal is input to the base terminal of the transistor PTR44, the transistor PTR44 is turned OFF, and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor PTR44 is pulled up to the + 12V side by the pull-up resistor MR2 of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A clear signal is input to the main control board 4100. When the RAM clear signal whose logic is HI is input within a predetermined period from when the power is turned on, the main control MPU 4100a of the main control board 4100 has the logic shown in FIG. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned on and the switch circuit is also turned on. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. When the logic of the RAM clear signal input to the input terminal PA0 is LOW, the main control MPU 4100a determines that the instruction is to instruct RAM clear to erase information stored in the main control built-in RAM.

[10-2-4. Dispensing motor drive circuit]
Next, a payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5 will be described. As shown in FIG. 25, the payout motor drive circuit 4120d mainly includes a voltage switching circuit 4120da and a drive ICPIC 60. The power input terminals 1 and 2 of the voltage switching circuit 4120da are electrically connected to the + 12V power supply line and the + 5V power supply line, respectively, and +12 and + 5V are applied thereto, respectively. The ground terminal of the voltage switching circuit 4120da is the ground (GND). Grounded. A voltage switching signal is input to the power source switching input terminal of the voltage switching circuit 4120da. This voltage switching signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and is output from the payout control output circuit 4120ca with reset function to the power supply switching input terminal of the voltage switch circuit 4120da. It has come to be. The power output terminal of the voltage switching circuit 4120da is electrically connected to the third terminal and the tenth terminal, which are the cathode terminals of the drive ICPIC 60, via the Zener diode PZD60, and electrically connected to the power supply terminal of the payout motor 744. Based on the voltage switching signal input to the voltage switching input terminal of the voltage switching circuit 4120da, + 12V or + 5V is used as the motor driving voltage, and the third terminal which is the cathode terminal of the drive ICPIC60 through the Zener diode PZD60 The power is supplied to the terminal and the 10th terminal, and supplied to the dispensing motor 744.

  The drive ICPIC 60 includes four Darlington power transistors. In the present embodiment, the sixth terminal and the seventh terminal, which are the emitter terminals of the drive ICPIC 60, are grounded to the ground (GND), respectively, and are the base terminals of the drive ICPIC 60. The payout motor drive signal is input to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal through the resistors PR60 to PR63, respectively. The second terminal, the fourth terminal, the ninth terminal, and the eleventh terminal that are the collector terminals of the drive ICPIC 60 are the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal that are the base terminals of the drive ICPIC 60, respectively. If the payout motor drive signal is input to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal of the drive ICPIC 60 through the resistors PR60 to PR63, respectively, A certain drive pulse is output to each phase (/ B phase, B phase, A phase, / A phase) corresponding to the dispensing motor 744. This payout motor drive signal is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and from the payout control output circuit 4120ca with reset function via the resistors PR60 to PR63, the drive ICPIC60. The signal is output to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal, which are base terminals. These drive pulses are generated by switching excitation currents that flow through the phases (/ B phase, B phase, A phase, / A phase) of the dispensing motor 744, and rotate the dispensing motor 744. Note that a back electromotive force is generated when the drive pulse (excitation signal) of each phase (/ B phase, B phase, A phase, / A phase) is cut off by this switching. When this back electromotive force exceeds the withstand voltage of the drive ICPIC 60, the drive ICPIC 60 is damaged. As a protection, the above-described Zener diode PZD0 is electrically connected to the third terminal and the tenth terminal before the drive ICPIC 60. The circuit configuration is adopted.

[10-2-5. CR unit input / output circuit]
Next, a CR unit input / output circuit 4120e for inputting / outputting various signals to / from the CR unit 6 shown in FIG. 13 will be described. As described above, the payout control board 4110 receives the ball rental request signal BRDY and one payout operation start request signal BRQ from the CR unit 6 via the game ball rental device connection terminal plate 869. , And a predetermined voltage VL (+12 V) and a ground LG created from the AC24V supplied from the power supply board 851 shown in FIG. 13 are supplied, while the payout control board 4110 is connected to a rental device such as a game ball. Via the terminal board 869, an EXS signal that indicates that one payout operation has been started or ended, and a PRDY signal that indicates that a payout operation for paying out a rental ball is possible or impossible. And are output. As shown in FIG. 26, the input / output circuit for inputting / outputting these various signals mainly includes photocouplers PIC70 to PIC74 (infrared LEDs and phototransistors are incorporated).

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70 via the resistor PR70. The cathode terminal of the photocoupler PIC 70 is electrically connected to the ground LG from the CR unit 6. The resistor PR60 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC70. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, while the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70. In some cases, the photocoupler PIC 70 is turned off. The emitter terminal of the photocoupler PIC70 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC70 is electrically connected to the base terminal of the transistor PTR70 via the resistor PR71, and the transistor via the resistor PR72. It is electrically connected to the base terminal of the PTR 71. In addition to being electrically connected to the resistor PR71, the collector terminal of the photocoupler PIC70 is electrically connected to the other end of the pull-up resistor PR73 that is electrically connected to the + 5V power supply line.

  In addition to being electrically connected to the resistor PR71, the base terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR74 that is grounded to the ground (GND). The emitter terminal of the transistor PTR70 is grounded to the ground (GND), and the collector terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR75, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. 22 through ICPIC 80 (non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC 80A) is shaped and output without being inverted). Are electrically connected to an input terminal of a predetermined input port of the payout control MPU 4120a shown in FIG. When the transistor PTR70 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR70 changes, and the signal is input as the CR connection signal 1 to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, the base terminal of the transistor PTR71 is electrically connected to the resistor PR72 and one end is electrically connected to the other end of the resistor PR76 that is grounded to the ground (GND). The emitter terminal of the transistor PTR71 is grounded to the ground (GND), and the collector terminal of the transistor PTR71 is electrically connected to the power supply substrate 851 via a wiring (harness). Note that when the collector terminal of the transistor PTR71 is electrically connected to the power supply substrate 851 via a wiring (harness), one end of the collector terminal of the power supply substrate 851 is electrically connected to the + 12V power supply line (not shown). Is electrically connected to the other end. When the transistor PTR71 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR71 changes, and the signal is input to the power supply board 851 as a CR connection signal.

  A circuit composed of the resistors PR71 and PR74 and the transistor PTR70 is a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR70 is turned on by being pulled up to the + 5V side by the pull-up resistor PR73. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 70 is pulled down to the ground (GND) side, and the CR connection signal 1 whose logic becomes LOW is input to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, and the voltage applied to the base terminal of the transistor PTR70 is pulled down to the ground (GND) side. As a result, the transistor PTR 70 is turned OFF, and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor PTR70 is pulled up to the + 5V side by the pull-up resistor PTR75, and the CR connection signal 1 whose logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. The

  The circuit composed of the resistors PR72 and PR76 and the transistor PTR71 is also a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off and pulled up to the + 5V side by the pull-up resistor PR73, thereby turning on the transistor PTR71 and the switch circuit also It will be turned on. As a result, the CR connection signal in which the voltage applied to the collector terminal of the transistor PTR71 is pulled down to the ground (GND) side in the power supply board 851 via the wiring (harness) and the logic becomes LOW is input to the power supply board 851. The

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, and the voltage applied to the base terminal of the transistor PTR71 is pulled down to the ground (GND) side. As a result, the transistor PTR 71 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled up to + 12V side by the pull-up resistor of the power supply board 851 via the wiring (harness), and the CR connection signal whose logic becomes HI is input to the power supply board 851. Is done.

  The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 but also to the anode terminal of the photocoupler PIC71 via the resistor PR77. The BRDY from the CR unit 6 is input to the cathode terminal of the photocoupler PIC71. The resistor PR77 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC71. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is LOW, the photocoupler PIC71 is turned on, while the photocoupler PIC71 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC71 and the BRDY logic from the CR unit 6 is HI, the photocoupler PIC71 is turned off. Yes. The emitter terminal of the photocoupler PIC71 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC71 is electrically connected to the other end of the pull-up resistor PR78 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 80B) without inverting it). To the input terminal of a predetermined input port of the payout control MPU 4120a. When the photocoupler PIC71 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC71 changes, and the signal is input as a BRDY signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

  When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is LOW, the photocoupler PIC71 is turned on. The BRDY signal whose logic is set to LOW when the voltage applied to the collector terminal of the coupler PIC71 is pulled down to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is HI, the photocoupler PIC71 is turned off. Then, the BRDY signal whose logic applied to HI is pulled up to the + 5V side by the pull-up resistor PR78 and the voltage applied to the collector terminal of the photocoupler PIC71 is input to the input terminal of the predetermined input port of the payout control MPU 4120a. Thus, the logic of the BRDY signal output from the collector terminal of the photocoupler PIC 71 is the same as the logic of BRDY from the CR unit 6.

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 via the resistor PR79 in addition to the anode terminal of the photocoupler PIC70 and the anode terminal of the photocoupler PIC71. The BRQ from the CR unit 6 is input to the cathode terminal of the photocoupler PIC72. The resistor PR79 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC72. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the BRQ logic from the CR unit 6 is LOW, the photocoupler PIC72 is turned on, while the photocoupler PIC72 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC 72 and the BRQ logic from the CR unit 6 is HI, the photo coupler PIC 72 is turned off. Yes. The emitter terminal of the photocoupler PIC72 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC72 is electrically connected to the other end of the pull-up resistor PR80 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 80C) without inverting it). To the input terminal of a predetermined input port of the payout control MPU 4120a. When the photocoupler PIC72 is turned on / off, the logic of the signal output from the collector terminal of the photocoupler PIC72 changes, and the signal is input as a BRQ signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

  When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and when the BRQ logic from the CR unit 6 is LOW, the photocoupler PIC72 is turned on. A BRQ signal whose logic is LOW when the voltage applied to the collector terminal of the coupler PIC 72 is pulled down to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the BRQ logic from the CR unit 6 is HI, the photocoupler PIC72 is turned off. The voltage applied to the collector terminal of the photocoupler PIC72 is pulled up to the + 5V side by the pull-up resistor PR80, and the BRQ signal whose logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. Thus, the logic of the BRQ signal output from the collector terminal of the photocoupler PIC 72 is the same as the logic of the BRQ from the CR unit 6.

  An EXS signal indicating that one payout operation has started or ended from the output terminal of the predetermined output port of the payout control MPU 4120a is output to the payout control output circuit 4120cb without reset function, and the payout control output circuit without reset function. 4120cb is input to the cathode terminal of the photocoupler PIC73 via the resistor PR81. One end of the anode terminal of the photocoupler PIC73 is electrically connected to the other end of the resistor PR82 that is electrically connected to the + 12V power supply line. The resistor PR82 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC73. EXS output when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82 and output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the signal is LOW, the photocoupler PIC73 is turned on, while + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, and a predetermined output port of the payout control MPU 4120a. The photocoupler PIC 73 is turned OFF when the logic of the EXS signal output from the output terminal via the non-reset payout control output circuit 4120cb is HI. The emitter terminal of the photocoupler PIC73 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC73 is connected to the inside of the CR unit 6 via the pull-up resistor PR83 via the game ball lending device connection terminal plate 869. The voltage is raised to a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC73 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC73 changes, and the signal is input as EXS to the built-in control device of the CR unit 6.

  EXS output when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82 and output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the signal is LOW, the photocoupler PIC73 is turned ON, so that the voltage applied to the collector terminal of the photocoupler PIC73 is pulled down to the ground (GND) side, and EXS in which the logic becomes LOW is the CR unit. 6 built-in control device. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the output is output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the EXS signal is HI, the photocoupler PIC73 is turned OFF, so that the voltage applied to the collector terminal of the photocoupler PIC73 is pulled up to the predetermined voltage VL by the pull-up resistor PR83, and the logic becomes HI. EXS is input to the built-in control device of the CR unit 6. Thus, the logic of the EXS output from the collector terminal of the photocoupler PIC 73 is the logic of the EXS signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without a reset function. It has the same logic.

  The PRDY signal that indicates that the payout operation for paying out the rented ball from the output terminal of the predetermined output port of the payout control MPU 4120a is possible or impossible is a cathode terminal of the photocoupler PIC74 via the resistor PR84. Has been entered. One end of the anode terminal of the photocoupler PIC74 is electrically connected to the other end of the resistor PR85 that is electrically connected to the + 12V power supply line. The resistor PR85 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC74. PRDY output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85. When the logic of the signal is LOW, the photocoupler PIC74 is turned on, and when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the predetermined output port of the payout control MPU4120a When the logic of the PRDY signal output from the output terminal via the payout control output circuit 4120cb without reset function is HI, the photocoupler PIC74 is turned OFF. The emitter terminal of the photocoupler PIC74 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC74 is connected to the inside of the CR unit 6 by a pull-up resistor PR86 via a game ball lending device connection terminal plate 869. The voltage is raised to a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC74 is turned on / off, the logic of the signal output from the collector terminal of the photocoupler PIC74 changes, and the signal is input as PRDY to the built-in control device of the CR unit 6.

  PRDY output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85. When the signal logic is LOW, the photocoupler PIC74 is turned on. Therefore, the voltage applied to the collector terminal of the photocoupler PIC74 is pulled down to the ground (GND) side, and the PRDY whose logic is LOW is the CR unit. 6 built-in control device. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, it is output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the PRDY signal is HI, the photocoupler PIC74 is turned OFF, so that the voltage applied to the collector terminal of the photocoupler PIC74 is pulled up to the predetermined voltage VL by the pull-up resistor PR86, and the logic becomes HI. The PRDY is input to the built-in control device of the CR unit 6. Thus, the logic of PRDY output from the collector terminal of the photocoupler PIC74 is the logic of the PRDY signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. It has the same logic.

[10-2-6. Various input / output signals to payout control MPU]
Next, various input / output signals input / output from the input / output terminals of the various input / output ports of the payout control MPU 4120a will be described.

  The RXD terminal, which is the serial data input terminal of the serial input port of the payout control MPU 4120a, receives serial data from the main control board 4100 as a main pay serial data reception signal via the payout control input circuit 4120b as shown in FIG. Is done. On the other hand, from the TXD terminal which is the serial data output terminal of the serial output port of the payout control MPU 4120a, serial data to be sent to the main control board 4100 is sent as a payer serial data transmission signal to the payout control output circuit 4120cb without reset function. A payer serial data transmission signal is transmitted from the payout control output circuit 4120cb having no reset function to the main control board 4100.

  Each input terminal of the predetermined input port of the payout control MPU 4120a has the above-described RWMCLR signal, payout power failure warning signal, door open signal, full tank signal, various signals from the CR unit 6 (BRQ signal, BRDY signal, CR connection) For example, a main pay ACK signal from the main control board 4100 that informs the completion of normal reception of the payer serial data reception signal is sent via the payout control input circuit 4120b. The detection signals from the ball break switch 750, the count switch 751, the rotation angle switch 752, and the like shown in FIG. 12 are respectively input via the payout control input circuit 4120b.

  On the other hand, the EXS signal and the PRDY signal described above are output from the output terminals of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120cb without reset function, respectively, and the EXS signal from the payout control output circuit 4120cb without reset function and The PRDY signal is output to the CR unit input / output circuit 4120e, or the voltage switching signal described above is output to the payout control output circuit 4120ca with reset function, and the voltage switching signal is output from the payout control output circuit 4120ca with reset function to the voltage switching circuit 4120da. Or outputs a payout motor drive signal to the payout control output circuit 4120ca with reset function, and outputs a payout motor drive signal from the payout control output circuit 4120ca with reset function to the payout motor 744 via the payout motor drive circuit 4120d. In addition, for example, a payer ACK signal for notifying completion of normal reception of the main payment serial data reception signal described above is output to the payout control output circuit 4120ca with reset function, and the payout control output circuit 4120ca with reset function pays off. The main ACK signal is output to the main control board 4100, or the drive signal of the error LED display 860b shown in FIG. 12 is output to the payout control output circuit 4120ca with reset function to drive the drive signal from the payout control output circuit 4120ca with reset function. Is output to the error LED display 860b.

[10-3. Various input / output signals with the main control board and various output signals to the external terminal board]
Next, various input / output signals between the payout control board 4110 and the main control board 4100 and various output signals from the payout control board 4110 to the external terminal board 784 will be described with reference to FIG.

[10-3-1. Various input / output signals with the main control board]
The payout control board 4110 exchanges various input / output signals with the main control board 4100. Specifically, as shown in FIG. 27A, the payout control board 4110 has the above-described payer serial data transmission signal, payer ACK signal, operation signal (RAM clear signal), main frame door open signal, and the like. Is output to the main control board 4100. These output signals are pulled up to + 12V by the pull-up resistor of the main control input circuit 4100b of the main control board 4100.

  On the other hand, in addition to the main payment serial data reception signal, the main payment ACK signal, and the operation signal (RAM clear signal), the payout control board 4110 has a 15 round big hit information output signal, a two round big hit information output signal, etc. Jackpot information output signal, probabilistic fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, short and middle information output signal, start opening prize information output signal, etc. A signal or the like is input from the main control board 4100. These input signals are pulled up to the + 12V side by the pull-up resistor of the payout control input circuit 4120b of the payout control unit 4120 of the payout control board 4110.

[10-3-2. Various output signals to external terminal board]
The payout control board 4110 outputs various signals to the external terminal board 784. Specifically, as shown in FIG. 27 (b), in addition to the outer frame door opening information output signal described above, an award ball number information output signal indicating the number of game balls actually paid out by the payout motor 744. In addition to the jackpot information output signal such as the 15 round jackpot information output signal and the 2 round jackpot information output signal via the payout control board 4110 from the main control board 4100, the probability changing information output signal and the special symbol display information output A game information signal such as a signal, a normal symbol display information output signal, an hour / medium information output signal, and a start opening prize information output signal is output to the external terminal board 784. These output signals are pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

  A signal output from the external terminal board 784 is transmitted to a hall computer installed in a game hall (hall) (not shown), and the hall computer monitors a player's game and the like. When the 15 round jackpot information output signal or the 2 round jackpot information output signal is output to the hall computer as one jackpot information output signal, the hall computer counts the number of jackpots (two round jackpots). And the number of jackpots with 15 rounds (number of jackpots for 15 rounds) is the sum of the number of jackpots of the pachinko gaming machine 1. For this reason, since the hall computer cannot grasp the number of occurrences of 2 rounds of big hits and the number of occurrences of 15 land big hits from the total number of big hits, the number of big hits actually generated in the pachinko gaming machine 1 is large. However, it is not possible to grasp whether it is a big hit of 2 rounds or a big hit of 15 rounds. In addition, a data counter (not shown) is arranged above the pachinko gaming machine 1, and a player determines whether or not to play a game with reference to the number of occurrences of the big hit gaming state displayed on the data counter. Some people choose.

  However, the number of occurrences of the jackpot gaming state displayed in the data counter may actually be biased to the number of occurrences of two rounds of big hits. For example, a big hit of 15 rounds may not occur easily. As described above, the number of occurrences of the jackpot gaming state displayed on the data counter can give the player a sense of expectation, but may cause the player to be more eager than necessary.

  Therefore, in the present embodiment, as the jackpot information output signal, the 15 round jackpot information output signal and the two round jackpot information output signal are separately output to the hall computer, so that the hall computer can generate the number of occurrences of the two round jackpot, The number of occurrences of 15 round big hits can be accurately grasped. Therefore, the hall computer can grasp whether the number of big hits actually generated in the pachinko gaming machine 1 is a big hit of two rounds or a big hit of 15 rounds. Since the number of occurrences of big hits for rounds and the number of occurrences of big hits for two rounds can be displayed separately or only the number of occurrences of big hits for 15 rounds can be displayed as the number of occurrences of big hit gaming status, Nor.

  In the present embodiment, the 2-round jackpot information output signal is output to the hall computer in the period from when the 2-round jackpot is generated until it is finished, and the 15-round jackpot information output signal is also a 15-round jackpot. It is in a state of being output to the hall computer during the period from occurrence to termination. In addition to the method of outputting the 2-round jackpot information output signal and the 15-round jackpot information output signal to the hall computer as in the present embodiment, for example, when a 2-round jackpot occurs, the 2-round jackpot information output signal is output only for a predetermined period. When the 15 round jackpot is generated and the 15 round jackpot information output signal is output to the hall computer for a predetermined period when the 15 round jackpot occurs, such a 2 round jackpot information output signal and 15 round jackpot information are output. A method of outputting the output signal to the hall computer for the same predetermined period can also be mentioned.

[11. Various commands related to transmission / reception of main control board]
Next, various commands transmitted from the main control board 4100 to the payout control board 4110 and various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS. FIG. 28 is a table showing an example of various commands transmitted from the main control board to the payout control board, and FIG. 29 is a table showing an example of various commands sent from the main control board to the peripheral control board. FIG. 29 is a table showing a continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 29, and FIG. 31 is a table showing an example of various commands from the payout control board received by the main control board. First, a prize ball command that is a command related to payout transmitted from the main control board to the payout control board will be described, and then various commands transmitted from the main control board to the peripheral control board will be described and received by the main control board. Various commands from the payout control board will be described.

[11-1. Various commands sent from the main control board to the payout control board]
The main control MPU 4100a of the main control board 4100 receives detection signals from various winning switches such as the general winning opening switches 3020 and 3020, the upper starting opening switch 3022, the lower starting opening switch 2109, and the count switch 2110 shown in FIG. When inputted, based on these detection signals, a prize ball command for paying out a predetermined number of game balls as prize balls is transmitted to the payout control board. This prize ball command is a command having a storage capacity of 1 byte (8 bits). In this embodiment, the pachinko gaming machine 1 and the CR unit 6 (communicating with the pachinko gaming machine 1 and driving the payout motor 744 of the pachinko gaming machine 1 (prize ball device 740) to store the upper plate 301 or When the lower plate 302 is electrically connected to a device for paying out a game ball as a rental ball (such a pachinko game machine is referred to as a “CR machine”), as shown in FIG. In addition, commands 10H to 1EH (“H” represents a hexadecimal number) are prepared as prize ball commands transmitted from the main control board 4100 to the payout control board 4110. In the command 10H, one prize ball is designated. In the command 11H, two prize balls are designated, and in the command 1EH, 15 prize balls are designated. The payout control board 4110 controls to pay out the game balls by driving the payout motor 744 for the designated number of prize balls.

  Also, a pachinko gaming machine 1 and a ball lending machine (a device that pays out game balls directly to the upper plate 301 and the lower plate 302 as balls for lending) are installed adjacent to the game hall (hall). When the gaming machine 1 and the ball lending machine are electrically connected (such a pachinko gaming machine is referred to as a “general machine”), as shown in FIG. Command 20H to command 2EH are prepared as prize ball commands to be transmitted to the control board 4110, one prize ball is designated by the command 20H, two prize balls are designated by the command 21H,... In 2EH, 15 prize balls are designated. The payout control board 4110 controls to pay out the game balls by driving the payout motor 744 for the designated number of prize balls.

  As a command common to the CR machine and the general machine, a command 30H is prepared as shown in FIG. 28C, and the self-check is designated in the command 30H. By transmitting a command 30H and checking whether or not an ACK signal is input when the transmitting side does not input an ACK signal output as a command reception confirmation from the receiving side for a predetermined period after the command is transmitted. Check the connection status. In the case of the CR machine in the present embodiment, the payout control board 4110 confirms the connection state with the CR unit 6.

[11-2. Various commands sent from the main control board to the peripheral control board]
Next, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described. The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. These various commands are commands having a storage capacity of 2 bytes (16 bits). As shown in FIGS. 29 and 30, a status indicating the type of command having a storage capacity of 1 byte (8 bits), and And a mode showing variations of performance having a storage capacity of 1 byte (8 bits).

  As shown in FIG. 29 and FIG. 30, the various commands are related to special figure 1 production effects, special figure 2 production effects, jackpot relations, power-on, ordinary figure production effects, ordinary electric role effects, notification display, status Classified into display and other.

[11-2-1. Special Figure 1 Entrainment Production Related]
The special figure 1 tuning effect is based on the detection signal from the upper start-up switch 3022 shown in FIG. 11, and, as shown in FIG. 29, the function display board 1191 shown in FIG. Concerning the upper special symbol display 1185, it is composed of commands with names of special figure 1 synchronization effect start, special symbol 1 designation, special figure 1 synchronization production end, and change state designation. These various commands are assigned “A * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 1 synchronized production start command instructs the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 1 designated command designates the off, specific big hit, and non-specific big hit. The special figure 1 tuning effect end command is for instructing the end of the special figure 1 tuning effect, and the variable state designation command is for instructing the probability and the short time state.

  As the transmission timing of these various commands, the special symbol 1 tuning effect start command is transmitted at the start of the special symbol 1 fluctuation start, and the special symbol 1 designation command is transmitted immediately after the special symbol 1 tuning effect is started. The effect end command is transmitted when the special symbol 1 variation time has elapsed (when the special symbol 1 is determined), and the variation state designation command is transmitted immediately after the special symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process described later.

[11-2-2. Special figure 2 synchronized production]
The special figure 2 tune production effect is based on the detection signal from the lower start port switch 2109 shown in FIG. 11, and as shown in FIG. 29, the function display board 1191 shown in FIG. Concerning the lower special symbol display 1186, it is composed of commands named special figure 2 synchronization effect start, special symbol 2 designation, and special figure 2 synchronization effect end. These various commands are assigned “B * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 2 synchronized production start command instructs the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 2 designated command designates the off, specific big hit, and non-specific big hit. The end of the special figure 2 synchronization effect instructs the end of the special figure 2 synchronization effect.

  As the transmission timing of these various commands, the special symbol 2 tuning effect start command is transmitted at the start of the special symbol 2 fluctuation start, and the special symbol 2 designation command is transmitted immediately after the start of the special symbol 2 tuning effect. The effect end command is transmitted when the special symbol 2 variation time has elapsed (when the special symbol 2 is confirmed). These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[11-2-3. Jackpot related]
As shown in FIG. 29, the jackpot-related category includes a jackpot opening, a grand prize opening 1 open Nth display, a big prize opening 1 closed display, a big prize opening 1 count display, a jackpot ending, a jackpot symbol display, a small hit opening , A small hit opening display, a small hit count display, and a command with the names of small hit ending. These commands are assigned “C * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The jackpot opening command is for instructing the start of the jackpot opening, and the Nth display command for the winning prize opening 1 is started during the opening of the winning prize opening 1 for the 1st to 16th rounds (the attack unit 2100 shown in FIG. 8). The command indicating that the Nth round of the grand prize opening 2103 is being opened or the opening is started, and the grand prize opening 1 closing display command starts the closing of the grand prize opening 1 between rounds (the grand prize opening of the attacker unit 2100) 2103 during the closing of the round or the start of closing), the winning prize 1 count display command has been detected by the count switch 2110 shown in FIG. The number of game balls that have entered the big prize opening 2103), and the jackpot ending command is the jackpot ending Is intended to instruct the start, big hit symbol display command is for instructing the big hit symbol information display.

  The small hit opening command is for instructing the start of the small hit opening, and the small hit opening display command is for starting the small hit opening (during opening or opening of the big winning opening 2103 of the attacker unit 2100 at the time of the small hit). The small hit count display command is used when the count switch 2110 detects a game ball that has entered the big winning opening 2103 during the small hit. The small hit ending command is an instruction to start the small hit ending.

  As the transmission timing of these various commands, the big hit opening command is sent at the start of the big hit opening, and the big winning opening 1 opening N-th display command is when the big winning opening 1 is opened in the 1st to 16th rounds (the large amount of the attacker unit 2100). The winning prize opening 1 closing display command is transmitted when the winning prize opening 1 is closed (the closing of the winning prize opening 2103 of the attacker unit 2100) and is sent to the winning prize. The mouth 1 count display command is used when the winning prize opening 1 is opened and when the count changes to the winning prize opening 1 (when the winning prize opening 2103 of the attacker unit 2100 is opened and when the game ball that has entered the winning prize opening 2103 is counted. The jackpot ending command is sent at the start of the jackpot ending. Transmitted, big hit symbol display command is sent during the special winning opening open (when opening the special winning opening 2103 attacker unit 2100).

  The small hit opening command is transmitted at the start of the small hit opening, and the small hit release display command is transmitted when the small hit is released (when the big winning opening 2103 of the attacker unit 2100 is opened at the small hit). The hit count display command is transmitted at the time of winning a small hit medium / large winning opening (when a game ball that has entered the large winning opening 2103 is detected by the count switch 2110 during the small hit), and the small hit ending command is Sent when a small hit ending starts. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[11-2-4. Power on]
As shown in FIG. 29, the power-on category includes various commands named power-on. This power-on command is assigned “D * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The power-on command instructs the start of the RAM clear effect and the start of each state effect (for example, the start of the effect when the operation switch 860a of the payout control board 4110 is operated at the time of power-on shown in FIG. 12). Or give instructions).

  As the transmission timing of the power-on command, it is transmitted when the main control board power is turned on when the RAM is not cleared and when the RAM is not cleared. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the operation switch 860a of the payout control board 4110 is operated when the power is restored from a power failure or a momentary power interruption, the main control side power-on process described later Is executed, and a power-on command is transmitted in the peripheral control board command transmission process of step S92 in the main control timer interrupt process.

[11-2-5. General drawing related production]
The general-synchronization effect is based on the detection signal from the gate switch 2352 shown in FIG. 11, and is divided into the normal symbol display of the function display board 1191 shown in FIG. The command 1189 is composed of commands with the names of general drawing synchronization production start, universal symbol designation, universal drawing synchronization production end, and variable state designation. These various commands are assigned “E * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specifications of the pachinko gaming machine 1).

  The general pattern synchronization production start command is for instructing the general pattern synchronization production start with the production pattern specified in the mode, and the general pattern designation command is for specifying off, specific big hit, non-specific big hit, The figure synchronization effect end command is for instructing the end of the common figure synchronization effect, and the change state designation command is for instructing the probability and the short time state.

  As the transmission timings of these various commands, the general symbol synchronization effect start command is transmitted at the time of the normal symbol 1 fluctuation start, the general symbol designation command is transmitted immediately after the general symbol synchronization effect start, and the general symbol synchronization effect end command is When the normal symbol variation time has elapsed (when the normal symbol is determined), the variation state designation command is transmitted immediately after the ordinary symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[11-2-6. Ordinary electric role production related]
The ordinary electric role effect is related to the pair of movable pieces 2106 shown in FIG. 8 that are opened and closed by driving the start opening solenoid 2105 shown in FIG. It consists of commands named “Opening per figure”, “Opening of public power”, and “Ending per common figure”. These various commands are assigned “F * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The opening command per base map is an instruction to start the opening per base map, and the open command display command is a normal power open start (a pair of movable pieces 2106 are expanded in the horizontal direction by driving the start opening solenoid 2105). The ending command per universal map indicates the start of ending per universal map.

  As the transmission timing of these various commands, the opening command per base map is transmitted at the start of the opening per base map, and the general power open display command is displayed when the general power is open (the pair of movable pieces 2106 are driven by the start opening solenoid 2105). The ending command per universal map is transmitted at the start of ending per universal map. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[11-2-7. Notification display]
As shown in FIG. 30, the notification display section includes commands having names such as winning abnormality display, connection abnormality display, disconnection / short circuit abnormality display, magnetic detection switch abnormality display, door opening, and door closing. These various commands are assigned “6 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The winning anomaly display command is used when a winning ball is won other than during a big hit (while the condition device is operating) (a game ball enters the big winning port 2103 of the attacker unit 2100 even though it is not a big hit) (When the count switch 2110 detects), an instruction to start winning abnormality notification is instructed, and the connection abnormality display command is, for example, an electrical connection in a path between the main control board 4100 and the payout control board 4110. When there is an abnormality, an instruction to start connection abnormality notification is given, and the disconnection / short circuit abnormality display command includes, for example, the main control board 4100, the upper start port switch 3022, the lower start port switch 2109, the count switch 2110, and the like. Instructs the start of the disconnection / short circuit abnormality display when a disconnection / short circuit of the electrical connection occurs. Display command is for instructing the start of magnetic detection switch abnormality notification when an abnormality occurs in the magnetic detection switch 3024 shown in FIG. 11.

  Further, the door opening command is sent from the door frame 5 to the main body frame 3 based on a detection signal (open signal) from the door frame opening switch 618 input via the payout control board 4110 shown in FIG. When the door is opened, the door opening notification is instructed, and the door closing command indicates that the door frame 5 is closed with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618. If the door is in the closed state, the end of door opening notification is instructed.

  As the transmission timing of these various commands, the winning abnormality display command is transmitted when winning a big winning opening other than during the big hit (the condition device is operating), and the connection abnormality displaying command is sent from the main control board 4100 to the payout control board 4110. The command is sent when there is no ACK reply (ACK signal) from the payout control board 4110 at the time of command transmission to the command, and the disconnection / short circuit abnormality display command is one of the upper start port switch 3022, the lower start port switch 2109, the count switch 2110, etc. , Which is sent when any one of them is broken or short-circuited, the magnetic detection switch abnormality display command is transmitted when abnormality is detected in the magnetic detection switch 3024, and the door opening command is detected when door opening is detected (door frame opening). Based on the detection signal from the switch 618, the door frame 5 is opened with respect to the main body frame 3. The door closing command is a state in which the door frame 5 is closed with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618. If sent). These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[11-2-8. Status display]
As shown in FIG. 30, the status display category includes commands having names of frame state 1, error release navigation, and frame state 2. These various commands are assigned a status of “7 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The frame status 1 command, the error cancellation navigation command, and the frame status 2 command are commands having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, and detailed description thereof will be described later. When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, as shown in FIG. 30, “7 * H” is displayed. While setting as a status, the received command is set as a mode as it is. That is, when the main control MPU 4100a receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, it adds “7 * H” as additional information to these received commands. Thus, the command is shaped into a command having a storage capacity of 2 bytes (16 bits).

  The shaped frame status 1 command is transmitted when the power is restored, when the status of the frame is changed, and when the error cancellation navigation is performed. The error cancellation navigation command is transmitted when the error cancellation navigation is performed. And when the frame state changes. Note that the shaped frame state 1 command, error release navigation command, and frame state 2 command are actually transmitted in the peripheral control board command transmission process of step S92 in the main control timer interrupt process.

[11-2-9. Test related]
As shown in FIG. 30, the test-related category includes various commands named test. This test command is assigned “8 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). And is predetermined according to the specification content of the pachinko gaming machine 1).

  The test command instructs various inspections of the peripheral control board 4140 (for example, the sound source IC 4150c of the peripheral control unit 4150, the liquid crystal control unit 4160, the lamp driving board 4170, the motor driving board 4180, and the like shown in FIG. 14). Inspecting various substrates such as the frame decoration drive amplifier substrate 194).

  As a test command transmission timing, it is transmitted when the main control board power is turned on when the RAM is not cleared and when the RAM is not cleared. Specifically, when the operation of the operation switch 860a of the payout control board 4110 is operated when the power of the pachinko gaming machine 1 is turned on, or when the operation switch 860a of the payout control board 4110 is operated, And the test command is transmitted in the peripheral control board command transmission process in step S92 in the main control timer interruption process.

[11-2-10. Others]
As shown in FIG. 30, the other categories include start opening prize, change shortening operation end designation, high probability end designation, special symbol 1 memory, special symbol 2 memory, normal symbol memory, special symbol 1 memory pre-reading effect, and It consists of a command with the name of special symbol 2 storage pre-reading effect. These various commands are assigned a status of “9 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The start opening prize command is an instruction to start the start opening winning effect. When the game ball enters the upper start opening 2101 based on the detection signal from the upper start opening switch 3022, Based on the detection signal from the start port switch 2109, it instructs to start the production when a game ball enters the lower start port 2102. The command for instructing state transition to the fluctuation shortening non-operation state is instructed. The high probability end designation command is for instructing state transition from the high probability state to the low probability state, and the special symbol 1 storage command is a special symbol. 1 hold 0-4 pieces (a game ball enters the upper start port 2101 shown in FIG. 8 and the special symbol display 1185 on the function display board 1191 still displays the variation of the special symbol. The special symbol 2 memory command is used to transmit 0 to 4 special symbol 2 hold commands (the game ball enters the lower start port 2102 shown in FIG. 8). The special symbol display 1186 under the function display board 1191 conveys the number of balls that have not been used yet for the special symbol variation display (the number of holdings), and the normal symbol storage command is 0 to 4 normal symbol 1 holds. (A game ball passes through the gate part 2350 shown in FIG. 8, and the normal symbol display 1189 of the function display board 1191 conveys the number of balls (the number of holdings that are not yet used for the normal symbol variation display). The special symbol 1 storage pre-reading effect command is pre-read based on the special symbol 1 hold before the special symbol 1 hold is used for the variable symbol display on the special display 1118 on the function display board 1191. special The special symbol 2 storage prefetching effect command is used to instruct the start of the pre-reading effect to notify the advance notice of the display result by the design indicator 1185. Is used for pre-reading and instructing the start of a pre-reading effect to notify the advance notice of the display result by the lower special symbol display 1186 based on the special symbol 2 hold.

  As the transmission timing of these various commands, the start opening prize command is the start opening prize (when a game ball enters the upper start opening 2101 based on the detection signal from the upper start opening switch 3022 or the lower start opening switch 2109 (when a game ball enters the lower start port 2102 based on the detection signal from 2109), the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the door frame shown in FIG. 5 is transmitted mainly from the speaker 130 provided in order to notify the fact by voice, and the change shortening operation end designation command is sent at the end of the stop period after the end of the change after confirming the change of the specified number of changes (the elapse of the stoppage period) The high-probability end designation command is sent at the end of the stop period after the change is confirmed (after the lapse of the stoppage period). The special symbol 1 storage command is used when the special symbol 1 operation holding ball number changes (the game ball enters the upper start port 2101 and is still used for the special symbol change display on the special display 1118 on the function display board 1191. In the state where there is an unreserved number, when a game ball enters the upper start port 2101 and the retained number increases, the upper special symbol display 1185 is used to display the variation of the special symbol from the retained number. The special symbol 2 memory command is sent when the number of special symbol 2 actuated balls is changed (a game ball enters the lower start port 2102 and the lower special symbol of the function display board 1191). In the state where there is a number of holdings that are not yet used for the change display of the special symbol on the display unit 1186, when the number of holdings increases when the game ball enters the lower start port 2102 or when the number of holdings increases, the lower special symbol table The normal symbol storage command is sent when the number of reserved symbols of the normal symbol 1 is changed (when the game ball passes through the gate portion 2350). In the state where there is a reserve number that is not yet used for the normal symbol variation display on the normal symbol display 1189 of the function display board 1191, when the game ball passes through the gate part 2350 and the reserve number increases, or the reserve Is sent to the normal symbol display 1189 when the number of reserved symbols decreases and the number of reserved symbols decreases. Is sent when the game ball enters the mouth 2101 and the number of held balls increases, and the special symbol 2 memory pre-reading effect command is sent when the number of the special symbol 2 action held balls increases (the game ball enters the lower start port 2102) Sent when the number of balls on hold increases. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

  By the way, as described above, the start opening prize command is received at the start opening winning (when a game ball enters the upper start opening 2101 based on the detection signal from the upper start opening switch 3022 or from the lower start opening switch 2109. (When a game ball enters the lower start port 2102 based on the detection signal), the speaker is housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 mainly by voice. Although it is transmitted to notify the effect, how the peripheral control board 4140 shown in FIG. 14 uses the start opening winning command may differ depending on the specifications of the pachinko gaming machine. For example, in the pachinko gaming machine 1 in the present embodiment, in addition to notifying by voice from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the presence or absence of fraudulent activity is monitored. It is the specification of using for the purpose. On the other hand, in other pachinko machines, the peripheral control board 4140 simply receives the start opening prize command, and the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5 Some specifications do not notify by voice from 130.

[11-3. Various commands from the payout control board received by the main control board]
Next, various commands from the payout control board 4110 received by the main control board 4100 will be described.

  As shown in FIG. 31, each command from the payout control board 4110 is composed of commands named frame state 1, error release navigation, and frame state 2, and includes frame state 1, error release navigation, and Priorities are set in the order of frame state 2.

  In the frame state 1 command, a ball breakage, a full tank, a connection abnormality and a CR non-connection are prepared in 50 or more stocks, and in a ball breakage, bit 0 (B0, “B” represents a bit). Value 1 is set, bit 1 (B1) is set to 1 when full, bit 1 (B2) is set to 1 when there are 50 or more stocks, and bit 3 (B3) is set when connection is abnormal 1 is set, and the value 1 is set in bit 4 (B4) when the CR is not connected. In bit 5 (B5) to bit 7 (B7) of the frame state 1 command, a value 1 is set in B5, a value 0 is set in B6, and a value 0 is set in B7.

  In the error canceling navigation command, there are provided a sphere, a count switch error, and a retry error. In the sphere, a value 1 is set in bit 2 (B2), and in a count switch error, a value is set in bit 3 (B3). 1 is set, and a value 1 is set to bit 4 (B4) in the case of a retry error. Here, the “counting switch error” indicates whether or not the malfunction of the counting switch 751 shown in FIG. 12 has occurred. The “retry error” indicates that a game ball that is not consistent with the retry operation has been repeatedly paid out. Bit (B0), bit (B1), and bit 5 (B5) to bit 7 (B7) of the error cancellation navigation command have a value 0 for B0, a value 0 for B1, a value 0 for B5, a value 1 for B6, The value 0 is set in B7.

  The frame state 2 command is prepared for ball removal, and a value 1 is set to bit 0 (B0) during ball removal. Bit 1 (B1) to Bit 7 (B7) of the frame status 2 command include a value 0 for B1, a value 0 for B2, a value 0 for B3, a value 0 for B4, a value 1 for B5, a value 1 for B6, and The value 0 is set in B7.

  As the transmission timing of these various commands, the frame status 1 command is transmitted when the power is restored, when the frame status is changed, and during error cancellation navigation, and the error cancellation navigation command is transmitted during error cancellation navigation. Is transmitted when the power is restored and when the frame state changes. Note that these various commands are actually transmitted in the command transmission process in step S556 in the payout control unit main process of the payout control part power-on process described later.

[12. Various control processes of main control board]
Next, various control processes performed by the main control board 4100 shown in FIG. 11 according to the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 32 is a flowchart showing an example of main control-side power-on processing, FIG. 33 is a flowchart showing continuation of main-control-side power-on processing in FIG. 32, and FIG. 34 is an example of main control-side timer interrupt processing. It is a flowchart which shows. First, various random numbers used for game control will be described, and then the operation of the initial value update type counter, main control side power-on processing, and main control side timer interrupt processing will be described.

[12-1. Various random numbers]
As the various random numbers used for game control, a big hit determination random number for use in determining whether or not to generate a big hit gaming state, and an initial value for determining the big hit for use in determining the initial value of this big hit determination random number Random number for use in determining whether or not to generate a reach (reach out of reach) when the big hit gaming state is not generated, the upper special symbol display 1185 and the lower special symbol shown in FIG. The random display pattern random number for use in determining the variation display pattern of the special symbol variably displayed on the symbol display 1186 and the upper special symbol display 1185 and the lower special symbol display 1186 when generating the big hit gaming state The jackpot symbol for use in determining the jackpot symbol to be derived and displayed, and the jackpot symbol for use in determining the initial value of this jackpot symbol A random number for determining an initial value, a random number for a small hit symbol for use in determining a small hit symbol that is derived and displayed on the upper special symbol display 1185 and the lower special symbol display 1186 when the small hit gaming state is generated, A random number for determining an initial value for a small hit symbol for use in determining an initial value of a random number for a winning symbol is prepared. Further, in addition to these random numbers, a determination random number for normal symbols for use in determining whether or not to move the movable piece 2106 shown in FIG. 8 and an initial value of the random numbers for determination per normal symbol are determined. Random numbers for determining initial values for normal symbols to be used, random numbers for normal symbol variation display patterns to be used for determining the variation display pattern of ordinary symbols that are variably displayed on the ordinary symbol display 1189 shown in FIG. Is prepared.

  For example, the counter for updating the jackpot determination random number is updated within a predetermined fixed numerical range ranging from the minimum value to the maximum value (in this embodiment, the value 0 to the maximum value 32767 as the minimum value). The range from the minimum value to the maximum value is counted up by incrementing by 1 each time a main control timer interrupt process described later is performed. The counter counts up from the big hit determination initial value determination random number toward the maximum value, and then counts up from the minimum value toward the big hit determination initial value determination random number. When the counter finishes counting up the range from the minimum value to the maximum value of the jackpot determination random number, the initial value determination random number for jackpot determination is updated. Such a counter updating method is referred to as an “initial value updating type counter”. The big hit determination initial value determination random number can be obtained by executing an initial value lottery process for drawing one value from a fixed numerical range of a counter for updating the big hit determination random number. Further, the above-described random number for determining per ordinary symbol and the random number for determining initial value for determining per normal symbol are the same as the method for updating the random number for determining big hit.

  In the present embodiment, as described above, when the counter for updating the jackpot determination random number finishes counting up the range from the minimum value to the maximum value of the jackpot determination random number, as described above, for determining the initial value for the jackpot determination The random number is updated by executing the initial value lottery process. However, when the operation switch 860a of the payout control board 4110 shown in FIG. The check sum value (sum value) obtained by regarding the game information stored in the main control built-in RAM of the main control MPU 4100a shown in FIG. When clearing the entire area of the main control built-in RAM, such as when the checksum value (sum value) stored in the power-off process (power-off) does not match The main hit MPD 4100a shown in FIG. 11 takes out the ID code from the built-in non-volatile RAM and updates the big hit determination random number based on the extracted ID code. An initial value deriving process for always deriving the same fixed value from the fixed numerical value range is executed, and the derived fixed value is set. In other words, the initial value determination random number for jackpot determination is always overwritten and updated with the same fixed value derived based on the ID code by executing the initial value derivation process. As described above, the value set as the initial value for determining the initial value for jackpot determination is derived using the ID code, and the ID that is stored in the nonvolatile RAM built in the main control MPU 4100a by the manufacturer of the main control MPU 4100a. Based on the ID code by executing the initial value derivation process when clearing the entire area of the main control built-in RAM and the first security measure that the ID code is not rewritten even if an external device is used when the code is stored Thus, the second security measure of deriving the same fixed value and the two steps of security measures are taken to prevent analysis.

  Here, an advantage will be described in which an ID code is extracted from a nonvolatile RAM incorporated in the main control MPU 4100a and the extracted ID code is used as a random number for determining an initial value for determining a big hit. For example, a person who illegally acquires a game ball to be paid out as a prize ball obtains the game board 4 by some method and disassembles it, and uses an ID code stored in advance in a nonvolatile RAM built in the main control MPU 4100a. Even if it is possible to grasp the timing when the value of the counter for updating the jackpot determination random number and the jackpot determination value coincide with each other, the ID code is assigned a unique code for identifying the individual. Therefore, the ID code is completely different from the ID code stored in advance in the nonvolatile RAM built in the main control MPU 4100a ′ provided in the other game board 4 ′. That is, in the other game boards 4 ′, the timing at which the counter value for updating the jackpot determination random number matches the jackpot determination value is also completely different from that of the acquired game board 4. In other words, the ID code obtained by disassembling and analyzing the obtained game board 4 is not useful at all on the other game board 4 ', that is, the other pachinko gaming machine 1', so it is disassembled and analyzed. Even if aiming at a starting prize for causing a game ball to enter the upper start opening 2101 and the lower start opening 2102 shown in FIG. A gaming state cannot be generated.

[12-2. Operation of counter with initial value update type]
In the initial value update type counter, when the entire area of the main control built-in RAM is cleared (when the RAM is cleared), the main control MPU 4100a takes out the ID code from the built-in nonvolatile RAM, and based on the taken out ID code. An initial value deriving process for always deriving the same fixed value from the fixed numerical range of the counter for updating the big hit determination random number is executed, and this derived fixed value is set. The initial value update type counter counts up from this fixed value toward the maximum value and then counts up from the minimum value toward the fixed value as the first cycle. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit determination random number, one value is randomly selected from the fixed numerical range of the counter that updates the big hit determination random number as the initial value determination random number for the big hit determination The initial value lottery process is executed, and the value obtained by this lottery is set. In the second cycle, the initial value update type counter counts up from the value obtained by the lottery toward the maximum value, and then counts up from the minimum value to the value obtained by the lottery. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit determination random number, the initial value lottery process is executed again, the value obtained by this lottery is set, and the initial value update type counter As the third cycle, the value obtained by the lottery is counted up toward the maximum value. In the present embodiment, the value 32668 to the value 32767 are set for the low probability as the range of the big hit determination value (the jackpot determination range), which is read from the normal determination table, whereas the value 31768 to the value for the high probability. 32767 is set and is read from the probability variation determination table. In the present embodiment, the counter for updating the big hit determination random number updates a predetermined fixed numerical range ranging from a value 0 as a minimum value to a value 32767 as a maximum value. In other words, the range of the jackpot determination value (the jackpot determination range) is a range closer to the maximum value from the intermediate value (value 16384) between the minimum value and the maximum value in either of the low probability and the high probability. Is set.

  Here, as a big hit determination value range (big hit determination range), a value 10 to value 209 is set for a low probability and a value 10 to a value 339 is set for a high probability. The value range (big hit determination range) is set to a range closer to the minimum value side from the intermediate value (value 16384) between the minimum value and the maximum value in both the low probability and the high probability. . In such a case, the period from the timing when the value of the initial value update type counter becomes 0 to the time when it becomes the first value 10 in the range of the big hit determination value (big hit determination range), and this value 10 When the period from the next value 11 to the maximum value (value 32767) is compared, the probability of the former period being drawn by the above-described initial value lottery process is much lower than that of the latter period. In other words, the range from the timing when the value of the initial value update type counter becomes 0 to the last value (value 209 for low probability, value 339 for high probability) in the range of jackpot determination value (big hit determination range). And the range from the value after this last value (value 210 for low probability, value 340 for high probability) to the maximum value (value 32767), the former range is the latter Compared with the range, the probability of being drawn by the initial value lottery process is extremely low. Then, for example, the timing at which the value of the initial value update type counter becomes 0 is obtained by some method, and the game ball is started upward by irradiating the upper start opening 2101 and the lower start opening 2102 with radio waves. If a fraudulent act is performed as if entering the mouth 2101 or the lower start opening 2102, the value of the initial value update type counter becomes one of the values of the jackpot determination value range (the jackpot determination range). It can be said that the probability is high.

  On the other hand, as in the present embodiment, the range of the jackpot determination value (the jackpot determination range) is from an intermediate value (value 16384) between the minimum value and the maximum value in either the low probability or the high probability. If it is set to the range close to the maximum value side, the initial value update type counter value immediately before the value that becomes the first value in the range of the big hit judgment value (big hit judgment range) from the timing when the value becomes zero. A period extending to the time when the value (value 32667 for low probability, value 31767 for high probability) and a period extending from the first value (value 32668 for low probability, value 31768 for high probability) to the maximum value (value 32767) And the former period is much more likely to be drawn by the above-described initial value lottery process than the latter period. In other words, the value before the first value in the range of the big hit determination value (big hit determination range) from the timing when the value of the initial value update type counter becomes 0 (value 32667 for low probability, value 31767 for high probability). And the range from the first value (value 32668 for low probability, value 31768 for high probability) to the maximum value (value 32767), the former range is compared to the latter range The probability of being drawn by the initial value lottery process is extremely high. Then, the initial value update type counter has a range from the value 0 to the value before the first value (value 32667 for low probability, value 31767 for high probability) in the range of jackpot determination value (big hit determination range). Of these values, one of the values becomes a value drawn by the initial value lottery process, and is set in the above-described big hit determination initial value determination random number. Counting up, and then counting up from the minimum value to the value obtained by lottery. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit determination random number, the initial value lottery process is executed again, the value obtained by this lottery is set, and the initial value update type counter Then, the value obtained by the lottery is counted up toward the maximum value.

  That is, as in the present embodiment, the range of the big hit determination value (big hit determination range) is either the low probability or the high probability, and the maximum value side from the intermediate value (value 16384) between the minimum value and the maximum value. Is set to a range close to the initial value update type counter value from the timing when the value becomes 0, the first value in the range of the big hit determination value (big hit determination range) (low value) The period extending to the time when the probability becomes 32667 and the value 31767) with high probability is irregular and rich in randomness. As a result, for example, the timing at which the value of the initial value update type counter becomes 0 is illegally acquired by some method, and the game ball is raised by irradiating the upper start port 2101 or the lower start port 2102 with radio waves. Even if an illegal act pretending to have entered the starting port 2101 or the lower starting port 2102 is performed, the value of the initial value update type counter is one of the jackpot determination value ranges (the jackpot determination range). It can be said that the probability of becoming a value is low.

  The initial value update type counter is repeatedly updated in the range from the minimum value to the maximum value. Until the counter reaches the minimum value (first value) in the range of the big hit judgment value (big hit judgment range) in the second cycle from the minimum value (first value) of the range from the initial value to the big hit judgment value (big hit judgment range) The time required is time T0. The time required for the counter to reach the minimum value (first value) of the big hit determination value range (big hit determination range) in the third cycle from time T0 is time T1, and time T1 is shorter than time T0. . The time required for the counter to reach the minimum value (first value) of the big hit determination value range (big hit determination range) in the fourth cycle from time T1 is time T2, and time T2 is shorter than time T1. . In this way, in the initial value update type counter, fluctuation is given to the time when the counter to be updated becomes the minimum value (first value) of the range of the big hit determination value (big hit determination range) (periodicity) The player is not perceived by the player).

[12-3. Main control side power-on processing]
When the pachinko gaming machine 1 is turned on, the main control MPU 4100a of the main control board 4100 performs main control side power-on processing as shown in FIGS. When the main control side power-on processing is started, the main control MPU 4100a sets the stack pointer (step S10). The stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) in use, or temporarily returns the return address of this routine when returning to this routine after completing the subroutine. It indicates the address that is stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S10, an initial address is set in the stack pointer, and the contents of the register, the return address, etc. are stacked on the stack from this initial address. Then, the stack pointer returns to the initial address by sequentially reading from the last stacked stack to the first stacked stack.

  Subsequent to step S10, output of a power failure clear signal is started to the power failure monitoring circuit 4100e shown in FIG. 20 (step S11). The power failure monitoring circuit 4100e includes a comparator MIC21 that is a voltage comparison circuit and a D-type flip-flop MIC22. The comparator MIC21, which is a voltage comparison circuit, compares the voltage between + 24V and the reference voltage, or compares the voltage between + 12V and the reference voltage, and outputs the comparison result. This comparison result shows that when no power failure or instantaneous power failure occurs, the logic becomes HI and is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22, while when a power failure or instantaneous power failure occurs. The logic becomes LOW and is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22. In step S11, a power failure clear signal is output to the CLR terminal, which is the clear terminal of the D-type flip-flop MIC22. This power failure clear signal is input from the output terminal of the predetermined output port of the main control MPU 4100a to the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with a reset function by setting the logic to LOW. Is done. As a result, the main control MPU 4100a can release the latch state of the D-type flip-flop MIC22. It can be inverted and output from the 1Q terminal, which is the output terminal, and the signal from the 1Q terminal can be monitored.

  Subsequent to step S12, wait timer processing 1 is performed (step S12), and it is determined whether or not a power failure warning signal is input (step S14). The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when there is a power failure or a momentary power failure (a phenomenon in which the supply of power is temporarily stopped), when the voltage drops and becomes lower than the power failure warning voltage, a power failure warning signal is input as a power failure warning from the power failure monitoring circuit 4100e. Similarly, if the voltage becomes lower than the power failure warning voltage from when the power is turned on until it reaches the predetermined voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e. Therefore, the wait timer process 1 in step S12 is a process for waiting after the power is turned on until the voltage becomes larger than the power failure warning voltage and stabilizes. ms) is set. In step S14, it is determined whether or not the power failure notice signal is input. This determination is performed based on the signal output from the 1Q terminal, which is the output terminal of the above-described D-type flip-flop MIC22, as the power failure warning signal.

  If no power failure warning signal is input after the power is turned on in step S14 until the voltage becomes higher than the power failure warning voltage and stabilizes, the power failure clear signal is output to the CLR terminal which is the clear terminal of the D-type flip-flop MIC22. Stop (step S15). Here, the power failure clear signal is output from the output terminal of a predetermined output port of the main control MPU 4100a, the logic is HI, and the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with reset function. Is input. As a result, the main control MPU 4100a can set the D-type flip-flop MIC22 to the latched state. When the D-type flip-flop MIC22 latches the state that the logic is LOW and is input to the PR terminal that is the preset terminal, the D-type flip-flop MIC22 outputs a power failure warning signal from the 1Q terminal that is the output terminal.

  Following step S15, it is determined whether or not the operation switch 860a of the payout control board 4110 shown in FIG. 12 is operated (step S16). This determination is based on the logic of the operation signal from the operation switch 860a of the payout control board 4110, and determines that the RAM clear is not instructed when the logic of the operation signal from the operation switch 860a is HI. When the operation switch 860a is determined not to be operated, on the other hand, when the logic of the operation signal from the operation switch 860a is LOW, it is determined that the RAM clear is instructed, and the operation switch 860a is operated. It is determined that

  When the operation switch 860a is operated in step S16, the RAM clear notification flag RCL-FLG is set to a value 1 (step S18). On the other hand, when the operation switch 860a is not operated in step S16, the RAM clear notification flag is set. A value 0 is set in RCL-FLG (step S20). This RAM clear notification flag RCL-FLG is stored in a RAM (hereinafter referred to as “main control built-in RAM”) built in the main control MPU 4100a, and games relating to games such as probability fluctuations, unpaid prize balls, etc. It is a flag indicating whether or not to erase information, and is set to a value of 1 when erasing game information and a value of 0 when not erasing game information. Note that the value of the RAM clear notification flag RCL-FLG set in step S18 and step S20 is stored in the general-purpose storage element (general-purpose register) of the main control MPU 4100a.

  Following step S18 or step S20, wait timer processing 2 is performed (step S22). In this wait timer process 2, the system for controlling drawing of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 by the liquid crystal control unit 4160 of the peripheral control board 4140 shown in FIG. ) In this embodiment, 2 seconds (s) is set as a time until booting (boot timer).

  Following step S22, it is determined whether or not the RAM clear notification flag RCL-FLG is 0 (step S24). As described above, the RAM clear notification flag RCL-FLG is set to a value of 1 when erasing game information and a value of 0 when not erasing game information. When the RAM clear notification flag RCL-FLG is 0 in step S24, that is, when the game information is not erased, a checksum is calculated (step S26). This checksum is calculated by regarding the game information stored in the main control built-in RAM as a numerical value and calculating the sum.

  Subsequent to step S26, whether or not the calculated checksum value (sum value) matches the checksum value (sum value) stored in the main control side power-off processing (power-off) described later. Is determined (step S28). If they match, it is determined whether or not the backup flag BK-FLG is 1 (step S30). This backup flag BK-FLG stores game backup information such as game information, checksum value (sum value) and backup flag BK-FLG in the main control built-in RAM in the main control side power-off process described later. This flag is set to a value of 1 when the main control-side power-off process is normally terminated, and a value of 0 when the main-control-side power-off process is not terminated normally.

  When the backup flag BK-FLG has a value of 1 in step S30, that is, when the main control side power-off process has been completed normally, the work area of the main control built-in RAM is set as power recovery (step S32). In this setting, the backup flag BK-FLG is set to a value 0, and the power recovery time information is read from a ROM built in the main control MPU 4100a (hereinafter referred to as “main control built-in ROM”). Time information is set in the work area of the main control built-in RAM. In addition, “recovery” means not only the state where the power is turned off but also the state where the power is turned on, the state where the power is restored after a power outage or a momentary power failure, and the detection that a high frequency has been applied. It also includes the state of returning after that.

  Subsequent to step S32, power-on command creation processing is performed (step S34). In the power-on command creation process, the game information is read from the game backup information, and various commands corresponding to the game information are stored in a predetermined storage area of the main control built-in RAM.

  On the other hand, when the RAM clear notification flag RCL-FLG is not a value 0 (value 1) in step S24, that is, when the game information is erased, or when the checksum value (sum value) does not match in step S28. Alternatively, when the backup flag BK-FLG is not the value 1 (value 0) in step S30, that is, when the main control side power-off process is not normally terminated, the entire area of the main control built-in RAM is cleared ( Step S36). Specifically, the value 0 is written in the main control built-in RAM (a predetermined value may be read from the main control built-in ROM as an initial value and set). Also, the main control MPU 4100a indicates that the logic of the operation signal from the operation switch 860a indicates that the RAM is cleared, and when the game information is deleted, the sum values do not match, or the main control side power-off process is normal. When not finished, the unique ID code stored in advance in the nonvolatile RAM of the main control MPU 4100a is taken out, and it is always the same from the fixed numerical range of the counter that updates the jackpot determination random number based on the taken out ID code. An initial value deriving process for deriving a fixed value is performed, and this fixed value is set to the big hit determination initial value determining random number used for determining the initial value of the big hit determining random number described above.

  Following step S36, the work area of the main control built-in RAM is set as an initial setting (step S38). In this setting, the initial information is read from the main control built-in ROM, and the initial information is set in the work area of the main control built-in RAM.

  Subsequent to step S38, RAM clear notification and test command creation processing is performed (step S40). In this RAM clear notification and test command creation processing, a power-on command classified into power-on shown in FIG. 29 for notifying that the main control built-in RAM is cleared and the initial setting is performed is created. The test commands classified into test relations shown in FIG. 30 for performing various inspections of the control board 4140 are created and stored as transmission information in the transmission information storage area of the main control built-in RAM.

  Subsequent to step S34 or step S40, interrupt initialization is performed (step S42). This setting is to set an interrupt cycle when a main control timer interrupt process described later is performed. In this embodiment, it is set to 4 ms.

  Subsequent to step S42, interrupt permission is set (step S44). With this setting, the main control side timer interrupt process is repeated every interrupt cycle set in step S42, that is, every 4 ms.

  Subsequent to step S44, a value A is set in the watchdog timer clear register WCL (step S46). The watchdog timer is cleared by setting value A, value B and value C in this order in this watchdog timer clear register WCL.

  Subsequent to step S46, it is determined whether or not a power failure notice signal is input (step S48). As described above, when the power of the pachinko gaming machine 1 is shut off, or when a power failure or instantaneous power failure occurs, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning voltage when the voltage becomes equal to or lower than the power failure warning voltage. The determination in step S48 is made based on this power failure notice signal.

  If no power failure warning signal is input in step S48, non-winning random number update processing is performed (step S50). In the non-winning random number update process, the above-described reach determination random number, variable display pattern random number, big hit symbol initial value determining random number, small hit symbol initial value determining random number, and the like are updated. In this way, in the non-winning random number update process, random numbers that are not involved in the winning determination (big hit determination) are updated. It should be noted that the above-described random numbers for normal symbol determination, random numbers for initial value determination for normal symbol determination, random numbers for normal symbol variation display pattern, and the like described above are also updated by this non-winning random number update process.

  Following step S50, the process returns to step S46 again, the value A is set in the watchdog timer clear register WCL, it is determined whether or not a power failure warning signal is input in step S48, and this power failure warning signal is not input. For example, a non-winning random number update process is performed in step S50, and steps S46 to S50 are repeated. Note that the processing in steps S46 to S50 is referred to as “main control side main processing”.

  On the other hand, when a power failure warning signal is input in step S48, interrupt prohibition setting is performed (step S52). With this setting, the main control side timer interrupt processing described later is not performed, writing to the main control built-in RAM is prevented, and rewriting of game information is protected.

  Subsequent to step S52, output of a power failure clear signal is started (step S53). Here, the same process as the process that started outputting the power failure clear signal in step S11 is performed. Thereby, the main control MPU 4100a can release the latch state of the D-type flip-flop MIC22.

  Subsequent to step S53, the start opening solenoid 2105, the attacker solenoid 2108, the upper special symbol display 1185, the lower special symbol display 1186, the upper special symbol storage display 1184, and the lower special symbol storage display 1187 shown in FIG. The drive signal output to the normal symbol display 1189, the normal symbol storage display 1188, the game state display 1183, the round display 1190, etc. is stopped (step S54).

  Subsequent to step S54, a checksum is calculated and the calculated value is stored (step S56). This checksum is calculated by regarding the game information in the work area of the main control built-in RAM as a numerical value excluding the storage area for the checksum value (sum value) and backup flag BK-FLG described above.

  Subsequent to step S56, a value 1 is set in the backup flag BK-FLG (step S58). Thereby, storage of game backup information is completed.

  Subsequent to step S58, the watchdog timer is cleared (step S60). As described above, the clear setting is performed by sequentially setting the value A, the value B, and the value C in the watchdog timer clear register WCL.

  Following step S60, an infinite loop is entered. In this infinite loop, the value A, the value B, and the value C are not sequentially set in the watchdog timer clear register WCL, so that the watchdog timer is not cleared. Therefore, the main control MPU 4100a is reset, and then the main control MPU 4100a performs the main control side power-on process again. Note that the processing of step S52 to step S60 and the infinite loop are referred to as “main control side power-off processing”.

  The pachinko gaming machine 1 (main control MPU 4100a) is reset when a power failure occurs or when an instantaneous power failure occurs, and performs power-on processing on the main control side when the power is restored thereafter.

  In step S28, it is checked whether or not the game backup information stored in the main control built-in RAM is normal. Are inspected. In this way, by checking the game backup information stored in the main control built-in RAM twice, it is checked whether or not the game backup information is stored by an illegal act.

[12-4. Main control timer interrupt processing]
Next, the main control timer interrupt process will be described. This main control timer interruption process is repeated every interruption period (4 ms in this embodiment) set in the main control side power-on process shown in FIGS.

  When the main control timer interrupt process is started, the main control MPU 4100a of the main control board 4100 sets a value B in the watchdog timer clear register WCL as shown in FIG. 34 (step S70). At this time, the value B is set in the watchdog timer clear register WCL following the value A set in step S46 of the main control side power-on process (main control side main process).

  Subsequent to step S70, the interrupt flag is cleared (step S72). When the interrupt flag is cleared, the interrupt cycle is initialized, and the next interrupt cycle is counted from the initial value.

  Subsequent to step S72, switch input processing is performed (step S74). In this switch input process, various signals input to input terminals of various input ports of the main control MPU 4100a are read and stored as input information in an input information storage area of the main control built-in RAM. Specifically, the detection signals from the general winning opening switches 3020 and 3020 shown in FIG. 11 for detecting the game balls that have entered the general winning openings 2104 and 2201 shown in FIG. 8, and the big winning opening shown in FIG. 11. A detection signal from the count switch 2110 shown in FIG. 11 that detects a game ball that has entered the ball 2103, an upper start port switch that is shown in FIG. 11 that detects a game ball that has entered the upper start port 2101 shown in FIG. A detection signal from 3022, a detection signal from the lower start port switch 2109 shown in FIG. 11 for detecting the game ball that has entered the lower start port 2102 shown in FIG. 8, and the gate portion 2350 shown in FIG. A detection signal from the gate switch 2352 shown in FIG. 11 for detecting the game ball, a detection signal from the magnetic detection switch 3024 for detecting fraud using the magnet shown in FIG. The payer ACK signal from the payout control board 4110 that indicates that the payout control board 4110 shown in FIG. 11 has successfully received the prize ball command transmitted in the ball control process is read and input information is stored in the input information storage area. Remember. Further, a detection signal from an upper start port switch 3022 that detects a game ball that has entered the upper start port 2101 and a detection signal from a lower start port switch 2109 that detects a game ball that has entered the lower start port 2102 are read. Then, the corresponding start opening winning command shown in FIG. 30 corresponding to this is stored as transmission information in the transmission information storage area described above. In other words, if there is a detection signal from the upper start port switch 3022, the corresponding start port winning command is stored as transmission information in the transmission information storage area, and if there is a detection signal from the lower start port switch 2109, A start opening winning command corresponding to this is stored as transmission information in the transmission information storage area.

  In the present embodiment, the detection signal from the general winning opening switches 3020 and 3020 for detecting the game balls that have entered the general winning opening 2104 and 2201, and the count switch 2110 for detecting the gaming balls that have entered the large winning opening 2103 are shown. , A detection signal from an upper start switch 3022 that detects a game ball that has entered the upper start port 2101, a detection signal from a lower start port switch 2109 that detects a game ball that has entered the lower start port 2102 , And a detection signal from the gate switch 2352 that detects a game ball that has passed through the gate portion 2350 is read as the first time when the switch input process is started, and after a predetermined time (for example, 10 μs) has elapsed. It is read again as the second time. Then, the result read at the second time is compared with the result read at the first time. It is determined whether there is a comparison result among the comparison results. Those that are not the same result are read again as the third time, and the result read at the third time is compared with the result read at the second time. It is determined again whether there is a comparison result among the comparison results. Those that are not the same result are read again as the fourth time, and the result read at the fourth time is compared with the result read at the third time. It is determined again whether there is a comparison result among the comparison results. Those with the same result are treated as having no game balls.

  As described above, in the switch input process, the detection signals from the general prize opening switches 3020 and 3020, the count switch 2110, the upper start opening switch 3022, the lower start opening switch 2109, and the gate switch 2352 are passed from the first to the third time. By performing the reading twice in total, that is, the twice reading to be compared and the twice reading to be compared for the second time to the fourth time, it is possible to avoid erroneous detection due to the influence of chattering or noise. Therefore, the reliability of the detection signals from the general winning award opening switches 3020 and 3020, the count switch 2110, the upper starting opening switch 3022, the lower starting opening switch 2109, and the gate switch 2352 can be improved.

  Subsequent to step S74, timer subtraction processing is performed (step S76). In this timer subtraction process, for example, the time during which the upper special symbol display 1185 and the lower special symbol display 1186 are turned on in accordance with the variable display pattern determined in the special symbol and special electric accessory control processing described later, In addition to the time that the normal symbol display 1189 is turned on according to the normal symbol variation display pattern determined in the normal electric accessory control process, the payout control substrate 4110 is normal for various commands transmitted by the main control board 4100 (main control MPU 4100a). When it is determined whether or not a payer ACK signal indicating that it has been received is input, time management such as an ACK signal input determination time set as a determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interruption period is set to 4 ms. Therefore, every time this timer subtraction process is performed, the fluctuation time is subtracted by 4 ms. When the subtraction result is 0, the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is accurately measured.

  In this embodiment, the ACK signal input determination time is set to 100 ms. Each time this timer subtraction process is performed, the ACK signal input determination time is subtracted by 4 ms, and the subtraction result becomes 0, thereby accurately measuring the ACK signal input determination time. The various times and the ACK signal input determination time are stored as time management information in the time management information storage area of the main control built-in RAM.

  Subsequent to step S76, a winning random number update process is performed (step S78). In the winning random number update process, the big hit determination random number, the big hit symbol random number, and the small hit symbol random number described above are updated. Further, in addition to these random numbers, a big hit symbol initial value determination random number that is updated by the non-winning random number update process of step S50 in the main control side power-on process (main control side main process) shown in FIG. And the random number for determining the initial value for the small hit symbol is also updated. The random value for determining the initial value for the big hit symbol and the random number for determining the initial value for the small hit symbol are updated in the main control side main process and the main control side timer interrupt process, respectively, thereby improving the randomness. . On the other hand, since the big hit determination random number, the big hit symbol random number, and the small hit symbol random number are random numbers related to the winning determination (big hit determination), each time the winning random number update process is performed, each counter Counts up.

  For example, the counter for updating the jackpot determination random number is an initial value updating type counter as described above, and is a predetermined fixed numerical value range from the minimum value to the maximum value (in this embodiment, the value as the minimum value). 0 to the maximum value is updated within the value 32767), and the range from the minimum value to the maximum value is incremented by incrementing by 1 each time the main control timer interrupt processing is performed. The big hit determination initial value determination random number is counted up toward the maximum value (value 32767), and then the big hit determination initial value determination random number is counted up. When the counter for updating the big hit determination random number finishes counting up within the range from the minimum value to the maximum value of the big hit determination random number, the big hit determination initial value determination random number is updated by the winning random number update process. The big hit determination initial value determination random number can be obtained by executing an initial value lottery process for drawing one value from a fixed numerical range of a counter for updating the big hit determination random number. It should be noted that the above-described random number for normal symbol determination and the random number for initial value determination for normal symbol determination are also updated by this winning random number update process. The random number for determining normal symbols is the same as the method for updating the random number for determining big hits, and the description thereof is omitted.

  In this embodiment, the big hit determination initial value determining random number, the big hit symbol initial value determining random number, and the small hit symbol initial value determining random number are processed on the main control side power-on processing (main control) shown in FIG. Update processing in step S50 in the main main processing) and the winning random number update processing in step S78 in the main control timer interrupt processing, which is the main routine, are updated each time the interrupt timer is generated. When the number of executions of the non-winning random number update process in step S50 is random by repeatedly executing the main process on the main control side within the remaining time until the next interrupt timer is generated after the process time becomes uneven. , The big hit determination initial value determining random number, the big hit symbol initial value determining random number, and the small hit symbol initial value determining random number in step S50 Or as a mechanism to update only in non Toraku random number update process.

  Subsequent to step S78, prize ball control processing is performed (step S80). In this prize ball control process, the input information is read from the above-mentioned input information storage area, and the prize ball command shown in FIG. 28 for paying out the game ball based on this input information is created, or the main control board 4100 and The self-check command shown in FIG. 28 for confirming the connection state between the board and the payout control board 4110 is created. Then, the created prize ball command and self-check command are transmitted to the payout control board 4110 as main payout serial data. For example, when one game ball enters the big prize opening 2103 shown in FIG. 8, a prize ball command for paying out 15 balls as a prize ball is created and transmitted to the payout control board 4110. When the payer ACK signal notifying that the payout control board 4110 has completed reception normally is not input within a predetermined time, a self-check command for confirming the connection state between the main control board 4100 and the payout control board 4110 is created. To the payout control board 4110.

  Subsequent to step S80, frame command reception processing is performed (step S82). The payout control board 4110 transmits various commands (frame state 1 command, error release navigation command, and frame state 2 command) of 1 byte (8 bits) classified into the state display shown in FIG. In the frame command reception process in step S82, when these various commands are normally received as payer serial data, information that informs the payout control board 4110 to that effect is stored as output information in the output information storage area of the main control built-in RAM. . Further, the command normally received as the payer serial data is shaped into a 2-byte (16-bit) command (a variety of commands (frame status 1 command, error release navigation command, frame State 2 command))), and stored in the transmission information storage area described above as transmission information.

  Subsequent to step S82, an illegal act detection process is performed (step S84). In this fraud detection process, the abnormal state related to the prize ball is confirmed. For example, when the input information is read from the above-described input information storage area and the detection signal from the count switch 2110 is input when the game state is not a big hit game state (when a game ball enters the big prize opening 2103), etc. Then, a winning abnormality display command classified into the notification display shown in FIG. 30 as an abnormal state is created, and stored as transmission information in the transmission information storage area described above.

  Subsequent to step S84, a special symbol and special electric accessory control process is performed (step S86). In this special symbol and special electric accessory control processing, the value of the counter for updating the jackpot determination random number described above is taken out, and it is determined whether or not it matches the jackpot determination value stored in advance in the main control built-in ROM. It is determined whether or not a gaming state is to be generated (referred to as “special lottery”)), or a counter value for updating the jackpot symbol random number is extracted, and the probability variation hit determination value stored in advance in the main control built-in ROM It is determined whether or not they match (determining whether or not probability fluctuations are generated). Here, “probability fluctuation” means that the probability of a big hit changes to a high probability (at the time of probability change) that is set higher than that at normal time (low probability). In the present embodiment, the value 32668 to the value 32767 are set in the low probability as the range of the big hit determination value (big hit determination range) described above, and read from the normal determination table, whereas the value 31768 in the high probability. ˜value 32767 is set and read from the probability variation determination table. As described above, in the special symbol and special electric accessory control process in step S86, the value of the counter for updating the big hit determination random number matches the big hit determination value stored in advance in the main control built-in ROM. Is determined depending on whether or not the value of the counter for updating the jackpot determination random number is included in the jackpot determination range.

  When these determination results are based on the upper start opening switch 3022, various commands related to the special figure 1 synchronization effect shown in FIG. 29 are created, while the lottery results are based on the lower start opening switch 2109. 29, various commands related to the special figure 2 tuning effect shown in FIG. 29 are created and stored in the transmission information storage area as transmission information, and the upper special symbol display 1185 or the The lighting signal output to the upper special symbol display 1185 or the lower special symbol display 1186 is set so that the lower special symbol display 1186 is lit, and is stored as output information in the output information storage area described above. In addition, depending on the game state to be generated, for example, when the game state is a jackpot game state, various commands classified as a jackpot relationship shown in FIG. Closing display command, winning prize 1 count display command, jackpot ending command, and jackpot symbol display command) are created and stored in the transmission information storage area as transmission information, or the opening / closing member 2107 shown in FIG. 8 is opened / closed. When the output of the drive signal to the attacker solenoid 2108 is set and stored in the output information storage area as output information, or when the number of times (round) when the special winning opening 2103 is opened from the closed state is two times, 2 to turn on the two-round indicator lamp 1190a of the round indicator 1190 shown in FIG. The output of the lighting signal to the wind display lamp 1190a is set and stored in the output information storage area as output information, or when the round is 15 times, the 15 round display lamp 1190b of the round indicator 1190 shown in 89 is turned on. The output of the lighting signal to the 15-round display lamp 1190b is set so as to be stored in the output information storage area as output information, or the game state indicator 1183 is lit to indicate whether or not probability fluctuation has occurred in a predetermined color. The output of the lighting signal is set and stored as output information in the output information storage area.

  Subsequent to step S86, normal symbol and normal electric accessory control processing is performed (step S88). In the normal symbol and normal electric accessory control process, the input information is read from the above-described input information storage area, and the gate winning process is performed based on the input information. In this gate winning process, it is determined from the input information whether the detection signal from the gate switch 2352 has been input to the input terminal. Based on this determination result, when a detection signal is input to the input terminal, the gate information storage area of the main control built-in RAM is extracted as gate information by extracting the counter value etc. for updating the random number for determination per normal symbol described above To remember.

  This gate information storage area is provided with 0th partition to 3rd partition (four partitions), and gate information is stored in the order of 0th partition, 1st partition, 2nd partition, and 3rd partition. It is like that. For example, when gate information is stored in the 0th to 2nd sections of the gate information storage, when the detection signal from the gate switch 2352 is input to the input terminal, the gate information is stored in the third section of the gate information storage. To do.

  The gate information stored in the 0th section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is in the 0th section of the gate information storage, the gate information of the second section of the gate information storage is in the first section of the gate information storage, The gate information of the third section of the information storage is shifted to the second section of the gate information storage, respectively, and the third section of the gate information storage becomes an empty area. For example, when gate information is stored in the first partition to the second partition of the gate information storage, the gate information of the first partition of the gate information storage is stored in the 0th partition of the gate information storage. The gate information of the two sections is shifted to the first section of the gate information storage, and the second section of the gate information storage and the third section of the gate information storage become empty areas. Here, when the gate information is stored in the first to third sections of the gate information storage, the above-described gate information is turned on so that the normal symbol storage display 1188 is turned on using the total number of stored gate information as a holding ball. Based on the above, the output of the lighting signal of the normal symbol storage display 1188 is set and stored as output information in the output information storage area described above.

  Following the gate winning process, the gate information set in the work area of the main control built-in RAM is read out, and the normal design random number is extracted from the read gate information and stored in the main control built-in ROM in advance. It is determined whether or not it matches the determination value per normal symbol (referred to as “normal lottery”). Whether or not the movable piece 2106 is opened / closed is determined based on the determination result (the lottery result of the normal lottery). In the case of performing the opening / closing operation by this determination, the pair of movable pieces 2106 is in a state of being expanded in the left-right direction, so that a gaming state in which a game ball can be received at the lower start port 2102 is achieved, which is advantageous to the player. It becomes a gaming state. The variable display pattern of the normal symbol corresponding to this determination is determined based on the above-mentioned random number for the normal symbol variable display pattern, and various commands classified as related to the common symbol synchronization effect shown in FIG. The output of the lighting signal to the normal symbol display 1189 is set so that the normal symbol display 1189 is turned on in accordance with the determined normal symbol variation display pattern, and is stored in the transmission information storage area described above. Store in the output information storage area. For example, when the value of the random number for determination per normal symbol taken out matches the determination value per normal symbol stored in advance in the main control built-in ROM, various commands related to the normal electric role effect shown in FIG. Is generated and stored as transmission information in the transmission information storage area, and the output of the drive signal to the start port solenoid 2105 is set so as to open and close the movable piece 2106, and is stored as output information in the output information storage area described above. On the other hand, when the extracted random number for normal symbol determination does not match the normal symbol determination value stored in advance in the main control built-in ROM, the normal symbol based on the normal symbol variation display pattern random number described above is used. The variable display pattern is determined, and various commands classified as related to the common figure synchronization effect shown in FIG. 29 are created and described above as the transmission information. The lighting information is stored in the signal information storage area, and the output of the lighting signal to the normal symbol display 1189 is set so that the normal symbol display 1189 is turned on according to the determined normal symbol variation display pattern. Store in the area.

  Subsequent to step S88, port output processing is performed (step S90). In this port output processing, output information is read from the output information storage area described above from the output terminals of the various output ports of the main control MPU 4100a, and various signals are output based on the output information. For example, when various commands from the payout control board 4110 are normally received from the output terminal of a predetermined output port of the main control MPU 4100a based on the output information, a main payout ACK signal is output to the payout control board 4110 or a big hit In the gaming state, a drive signal is output to an attacker solenoid 2108 that opens and closes the opening / closing member 2107 of the prize winning opening 2103, and a drive signal is output to a start opening solenoid 2105 that opens and closes the movable piece 2106. 15 round jackpot information output signal, 2 round jackpot information output signal, probability changing information output signal, special symbol display information output signal, normal symbol display information output signal, short and medium time information output information, starting opening prize information output signal, etc. Various information (game information) signals relating to the game of the game were output to the payout control board 4110 To.

  Subsequent to step S90, peripheral control board command transmission processing is performed (step S92). In this peripheral control board command transmission process, transmission information is read from the transmission information storage area described above, and this transmission information is transmitted to the peripheral control board 4140 as main peripheral serial data. This transmission information includes the various commands classified in the special figure 1 tuned effect related and the various types categorized in the special figure 2 tuned effect related shown in FIG. Commands, various commands classified as jackpot related, various commands classified as power-on, various commands classified as related to ordinary drawing effects, various commands classified as related to ordinary electric role effects, shown in FIG. Various commands classified into the notification display, various commands classified into the status display, various commands classified into the test-related, and various commands classified into others are stored. The main serial data consists of 3 bytes per packet. Specifically, the main peripheral serial data includes a status indicating a type of command having a storage capacity of 1 byte (8 bits), a mode indicating a production variation having a storage capacity of 1 byte (8 bits), and a status. And a sum value obtained by calculating the sum with the mode regarded as a numerical value, and this sum value is created at the time of transmission.

  Subsequent to step S92, a value C is set in the watchdog timer clear register WCL (step S94). By setting the value C in the watchdog timer clear register WCL in step S94, the value C is set in the watchdog timer clear register WCL following the value B set in step S70. As a result, the value A, the value B, and the value C are sequentially set in the watchdog timer clear register WCL, and the watchdog timer is cleared.

  Subsequent to step S94, the register is switched (returned) (step S96), and this routine is terminated. Here, when the main control side timer interrupt processing, which is this routine, is started, the main control MPU 4100a loads the contents of the general-purpose registers on the stack and saves them. This prevents the contents of the general-purpose register used in the main process on the main control side from being destroyed. In step S96, the contents saved on the stack are read and written to the original register. Note that the main control MPU 4100a sets the interrupt permission after the return in step S96.

[13. Various control processing of payout control board]
Next, various control processes performed by the payout control board 4110 shown in FIG. 12 will be described with reference to FIGS. FIG. 35 is a flowchart showing an example of the power-on process of the payout control unit, FIG. 36 is a flowchart showing the continuation of the power-on process of the payout control unit in FIG. 35, and FIG. 37 is a payout control unit following FIG. FIG. 38 is a flowchart showing an example of a payout control unit timer interrupt process, FIG. 39 is a flowchart showing an example of a rotation angle switch history creation process, and FIG. 40 is a sprocket. 41 is a flowchart illustrating an example of the fixed position determination skip process, FIG. 41 is a flowchart illustrating an example of a ball spot determination process, and FIG. 42 is a flowchart illustrating an example of the prize ball stock number addition process for a prize ball. 43 is a flowchart showing an example of the winning ball stock number addition process for renting a ball, and FIG. 44 shows an example of the stock monitoring process. FIG. 45 is a flowchart showing an example of a payout ball movement determination setting process, FIG. 46 is a flowchart showing an example of a payout setting process, and FIG. 47 is an example of a ball movement setting process. 48 is a flowchart illustrating an example of the retry operation monitoring process, FIG. 49 is a flowchart illustrating an example of the inconsistency counter reset determination process, and FIG. 50 is a flowchart illustrating an example of the error release operation determination process. FIG. 51 is a timing chart showing signal processing (a) and input signal confirmation processing (A) from the CR unit during a payout operation by ball lending.

  First, the payout control unit power-on processing will be described, and then the payout control unit timer interruption processing, ball removal switch operation determination processing, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball spot determination processing, award Prize ball stock count addition processing for balls, prize ball stock count addition processing for rental balls, stock monitoring processing, payout ball engagement operation determination setting processing, payout setting processing, ball engagement operation setting processing, retry operation monitoring processing, inconsistency A counter reset determination process and an error release operation determination process will be described. Ball removal switch operation determination processing, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball corner determination processing, prize ball stock number addition processing, ball rental prize ball number addition processing, stock The monitoring process, the payout ball movement determination setting process, the retry operation monitoring process, the inconsistency counter reset determination process, and the error release operation determination process are one of the main operation setting processes in step S562 in the payout control unit power-on process described later. Rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball corner determination processing, retry operation monitoring processing, inconsistency counter reset determination processing, error release operation determination processing, prize ball stock number for prize ball Addition processing, winning ball stock number addition processing for lending, stock monitoring processing, and payout ball engagement operation judgment setting processing Priority in turn has been set.

[13-1. Discharge control unit power-on processing]
When the pachinko gaming machine 1 is powered on, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 performs a payout control unit power-on process as shown in FIGS. When the payout control unit power-on process is started, the payout control MPU 4120a sets an interrupt mode (step S500). This interrupt mode is for setting the priority order of interrupts of the payout control MPU 4120a. In this embodiment, a payout control unit timer interrupt process, which will be described later, is set as the highest priority, and when an interrupt of this payout control unit timer interrupt process occurs, the process is preferentially performed.

  Subsequent to step S500, input / output setting (I / O input / output setting) is performed (step S502). In this I / O input / output setting, various input ports and various output ports of the payout control MPU 4120a are set.

  Subsequent to step S502, wait timer processing 1 is performed (step S506), and it is determined whether or not a power failure warning signal is input (step S508). The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when a power failure or a momentary power failure (a phenomenon in which the supply of power is temporarily stopped) occurs, the voltage drops and becomes smaller than the power failure warning voltage. A warning signal (paid outage warning signal) is input. Similarly, when the voltage becomes lower than the power failure warning voltage from when the power is turned on until it reaches the predetermined voltage, a power failure warning signal (paid power failure warning signal) is input from the power failure monitoring circuit 4100e of the main control board 4100. Therefore, the wait timer process 1 in step S506 is a process for waiting until the voltage becomes higher than the power failure warning voltage and stabilizes after the power is turned on. In this embodiment, the wait timer process 1 is 200 milliseconds (wait timer). ms) is set. The determination in step S508 is performed based on a power failure warning signal (paid power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100.

  Subsequent to step S508, it is determined whether or not the operation switch 860a is operated (step S512). This determination is based on the logic of the operation signal from the operation switch 860a, and when the logic of the operation signal from the operation switch 860a is HI, the operation switch 860a determines that the RAM clear is not instructed. On the other hand, when the logic of the operation signal from the operation switch 860a is LOW, it is determined that the RAM is to be instructed, and it is determined that the operation switch 860a is operated.

  When the operation switch 860a is operated in step S512, the payout RAM clear notification flag HRCL-FLG is set to 1 (step S514). On the other hand, when the operation switch 860a is not operated in step S512, the payout RAM clear is cleared. A value 0 is set to the notification flag HRCL-FLG (step S516). The payout RAM clear notification flag HRCL-FLG is stored in a RAM (hereinafter referred to as “payout control built-in RAM”) built in the payout control MPU 4120a, for example, stored in various flags and various information storage areas. (For example, the prize ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. stored in the prize ball information storage area, and the CR communication information storage area) Flag indicating whether or not the payout information relating to the payout of the PRDY signal output setting information in which the logic state of the PRDY signal is set) is to be deleted. When not deleted, the value is set to 0. The payout RAM clear notification flag HRCL-FLG set in steps S514 and S516 is stored in a general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  Subsequent to step S514 or step S516, a setting for permitting access to the payout control built-in RAM is performed (step S518). With this setting, the payout control built-in RAM can be accessed, and for example, payout information can be written (stored) or read out.

  Subsequent to step S518, the stack pointer is set (step S520). The stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) being used, or temporarily returns the return address of this routine when returning to this routine after completing the subroutine. It indicates the address that is stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S520, an initial address is set in the stack pointer, and the contents of the register, the return address, etc. are stacked on the stack from this initial address. Then, the stack pointer returns to the initial address by sequentially reading from the last stacked stack to the first stacked stack.

  Subsequent to step S520, it is determined whether or not the payout RAM clear notification flag HRCL-FLG has a value of 0 (step S522). As described above, the payout RAM clear notification flag HRCL-FLG is set to a value of 1 when the payout information is erased and to a value of 0 when the payout information is not erased.

  When the payout RAM clear notification flag HRCL-FLG is 0 in step S522, that is, when the payout information is not erased, a checksum is calculated (step S524). This checksum calculates the sum by regarding the payout information stored in the payout control built-in RAM as a numerical value.

  Subsequent to step S524, it is determined whether or not the calculated checksum value matches a checksum value stored in a payout control unit power-off process (power-off) described later (step S526). . If they match, it is determined whether or not the payout backup flag HBK-FLG is 1 (step S528). This payout backup flag HBK-FLG is a flag indicating whether or not payout backup information such as payout information and checksum value is stored in the payout control built-in RAM in the payout control unit power-off process described later. A value of 1 is set when the control unit power-off process is normally terminated, and a value of 0 is set when the payout control unit power-off process is not normally terminated.

  When the payout backup flag HBK-FLG has a value of 1 in step S528, that is, when the payout control unit power-off process has been completed normally, the work area of the payout control built-in RAM is set as power recovery (step S530). In this setting, in addition to setting a value 0 to the payout backup flag HBK-FLG, the power recovery time information is read from a ROM built in the payout control MPU 4120a (hereinafter referred to as “the payout control built-in ROM”). The power recovery information is set in the work area of the payout control built-in RAM. Accordingly, the above-mentioned payout backup information stored in the payout control built-in RAM, various flags, various information stored in various information storage areas, etc. (for example, prizes stored in the prize ball information storage area, PRDY signal output setting information in which the logic state of the PRDY signal stored in the CR communication information storage area, such as the ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, and the like, Information used for various processes is set based on payout information relating to payout of inconsistency counter reset determination time (stored in the time management information storage area). Note that “recovery” includes not only a state in which the power is turned off from a state in which the power is turned off but also a state in which the power is restored after a power failure or a momentary power failure.

  On the other hand, when the payout RAM clear notification flag HRCL-FLG is not 0 (value 1) in step S522, that is, when the payout information is erased, or when the checksum values do not match in step S526, or step If the payout backup flag HBK-FLG is not a value 1 (value 0) in S528, that is, if the payout control unit power-off process has not ended normally, the entire area of the payout control built-in RAM is cleared (step S532). ). As a result, the payout backup information stored in the payout control built-in RAM is cleared.

  Following step S532, the work area of the payout control built-in RAM is set as an initial setting (step S534). In this setting, the initial information is read from the payout control built-in ROM, and the initial information is set in the work area of the payout control built-in RAM.

  Subsequent to step S530 or step S534, interrupt initialization is performed (step S536). This setting is to set an interrupt cycle when a payout control unit timer interrupt process to be described later is performed. In this embodiment, it is set to 2 ms.

  Subsequent to step S536, interrupt permission is set (step S538). With this setting, the payout control unit timer interrupt process is repeated every interrupt cycle set in step S536, that is, every 2 ms.

  Subsequent to step S538, the value A is set in the watchdog timer clear register HWCL (step S539). The watchdog timer is cleared by setting the value A, the value B, and the value C in this watchdog timer clear register HWCL in order.

  Subsequent to step S539, it is determined whether or not a power failure warning signal (paid power failure warning signal) is input (step S540). As described above, when the power of the pachinko gaming machine 1 is cut off, or when a power failure or instantaneous power failure occurs, if the voltage falls below the power failure warning voltage, a power failure warning signal (paid power failure warning signal) is used as the power failure warning signal. 4100 is input from the power failure monitoring circuit 4100e. The determination in step S540 is made based on this power failure notice signal.

  When no power failure warning signal is input in step S540, it is determined whether or not the 2 ms elapsed flag HT-FLG is 1 (step S542). This 2 ms elapsed flag HT-FLG is a flag for measuring 2 ms in a payout control unit timer interrupt process processed every 2 ms, which will be described later. Is set.

  When the 2 ms elapsed flag HT-FLG is 0 in step S542, that is, when 2 ms has not elapsed, the process returns to step S540, and it is determined whether or not a power failure warning signal (paid power failure warning signal) is input.

  On the other hand, if the 2 ms elapsed flag HT-FLG has a value of 1 in step S542, that is, if 2 ms has elapsed, a value 0 is set in the 2 ms elapsed flag HT-FLG (step S544).

  Subsequent to step S544, the value B is set in the watchdog timer clear register HWCL (step S546). At this time, the value B is set in the watchdog timer clear register HWCL following the value A set in step S539.

  Subsequent to step S546, port output processing is performed (step S548). In this port output process, various information is read from the output information storage area of the payout control built-in RAM, and various signals are output from the output terminals of the various output ports of the payout control MPU 4120a based on the various information. In the output information storage area, for example, payer ACK information for notifying that various commands related to payout from the main control board 4100 (award ball command and self-check command shown in FIG. 28) have been normally received, and a payout motor 744 are provided. Various information such as drive information for performing drive control, prize ball information on the number of balls actually paid out by the payout motor 744, LED display information displayed on the error LED display 860b, and the like are stored. When various commands relating to payout from the main control board 4100 are normally received from the output terminal of a predetermined output port of the payout control MPU 4120a based on the output information, a payer ACK signal is output to the main control board 4100, or a payout motor 744 outputs a drive signal, and the number of balls that the payout motor 744 actually pays out the game balls (In this embodiment, every time the payout motor 744 actually pays out 10 game balls, a prize ball number information signal is outputted to the external terminal plate 784). A display signal is output to the error LED display 860b.

  Subsequent to step S548, port input processing is performed (step S550). In this port input process, various signals input to input terminals of various input ports of the payout control MPU 4120a are read and stored as input information in an input information storage area of the payout control built-in RAM. For example, an operation signal of the operation switch 860a, a detection signal from the rotation angle switch 752, a detection signal from the counting switch 751, a detection signal from the full switch 550, a BRQ signal from the CR unit 6, a BRDY signal, and a CR connection signal, The main payment board ACK signal from the main control board 4100 that informs that the main control board 4100 has normally received various commands transmitted in the command transmission process described later is read and stored as input information in the input information storage area.

  Subsequent to step S550, timer update processing is performed (step S552). In this timer update process, when the determination is made as to whether or not a ball stagnation state has occurred due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the ball swatch determination set as the determination condition is performed. The skip determination time set when the fixed position determination of the payout rotating body is not performed, and when the game balls stored in the prize ball tank 720 and the tank rail 731 shown in FIG. 1 is set as a determination condition when determining whether or not the storage space of the foul cover unit 540 shown in FIG. 1 is full with the stored game balls. When determining whether or not the number of game balls taken into the supply passage of the prize ball device 740 is greater than or equal to a predetermined number based on a detection signal from the ball break switch 750, the determination condition is as follows. In addition to performing time management such as the ball breakage determination time, the number of game balls that are received and paid out by the recess of the payout rotating body, the number of balls actually detected by the counting switch 751, and Inconsistency set with the determination condition when determining whether or not to reset the inconsistency counter INCC for monitoring whether or not the payout of the game ball due to inconsistency is repeatedly performed Time management of counter reset judgment time is performed. For example, when the sphere collision determination time is set to 5005 ms, the timer interruption period is set to 2 ms. Therefore, every time this timer update process is performed, the sphere collision determination time is subtracted by 2 ms, and the subtraction result When the value becomes 0, the ball collision determination time is accurately measured.

  In this embodiment, the skip determination time is 22.75 ms, the ball removal determination time is 60060 ms, the full tank determination time is 504 ms, the ball breakage determination time is 119 ms, and the inconsistency counter reset determination time is 7000 s (about 2 hours). Each time this timer update process is performed, the ball removal determination time, the full tank determination time, the ball breakage determination time, and the inconsistency counter reset determination time are subtracted by 2 ms, and the result of subtraction becomes 0. The removal determination time, full tank determination time, ball breakage determination time, and inconsistency counter reset determination time are accurately measured. These various determination times are stored as time management information in the time management information storage area of the payout control built-in RAM.

  Following step S552, CR communication processing is performed (step S554). In this CR communication processing, whether or not various signals (BRQ signal, BRDY signal, and CR connection signal) from the CR unit 6 are input based on the input information read from the input information storage area described above. Determine. Based on various signals from the CR unit 6, the payout control MPU 4120 a exchanges various signals with the CR unit 6. In the processing for setting the work area of the payout control built-in RAM in step S530, as described above, the payout backup information stored in the payout control internal RAM, various flags, and various information stored in the various information storage areas. (For example, the prize ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. stored in the prize ball information storage area, the PRDY stored in the CR communication information storage area, etc. Information used for various processes is set on the basis of payout information relating to payout (PRDY signal output setting information or the like in which the logic state of the signal is set).

  By this process, for example, even if there is a momentary power failure or a power failure, values such as the prize ball stock number PBS, the real ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery are stored as payout backup information The value of the award ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. immediately before the momentary power failure or power failure can be restored. As a result, when the game ball payout operation by the prize ball device 740 is being executed, even if the payout operation cannot be continued due to a momentary power failure or power failure, the payout operation should be continued at the time of power recovery. Therefore, the game balls can be paid out to the upper plate 301 and the lower plate 302 without excess or deficiency. In other words, in the CR communication process, the payout control MPU 4120a exchanges various signals with the CR unit 6 and, when paying out the game ball to the upper plate 301 or the lower plate 302, the payout control MPU4120a Even if the exchange of various signals with the unit 6 is interrupted and the payout of the game ball cannot be continued, the prize ball stock number PBS, the real ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery Etc. are restored to values such as the prize ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc., which are stored as the payout backup information and immediately before the momentary power failure or power failure. Exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 immediately before a momentary power failure or power failure And it is possible to continue from the time of power restoration, so that it is possible to continue to payout of game balls.

  As described above, the exchange of various signals between the pachinko gaming machine 1 (the payout control MPU 4120a) and the CR unit 6 is restored to the state immediately before the instantaneous power outage or stop at the time of power recovery even if the power outage stops or stops. Thus, various signals generated by the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 are not changed by the influence of the instantaneous stop or stop. Therefore, the reliability of the exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 can be enhanced.

  Various information stored in the CR communication information storage area is included in the payout backup information as described above. In the CR communication process, when power is restored, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM set in the process of setting the work area of the payout control built-in RAM in step S530. When the read PRDY signal output setting information is set to the logic state of the PRDY signal that indicates that the payout operation for paying out the rented ball is not possible, for example, the PRDY signal is paid out. The data is output to the CR unit 6 from the output terminal of the predetermined output port of the MPU 4120a. The value of the inconsistency counter INCC in the prize ball information storage area stored in the payout control built-in RAM, which is included in the payout backup information, for example, in the retry operation monitoring process performed as one process of the main action setting process Is determined whether the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH. If the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH, the retry operation is abnormal. That is, it is determined that the game ball payout operation by the prize ball device 740 is in an abnormal state, the value 1 is set to the retry error flag RTERR-FLG, and the payout ball engagement operation determination setting process For example, when the communication with the CR unit 6 is not in progress, The logic state of the PRDY signal informing of dispensing operation is not possible (LOW) is set to PRDY signal output setting information stored in the CR communication information storage area for dispensing.

  Thereby, in the CR communication process, the logic state of this PRDY signal is read from the CR communication information storage area and the PRDY signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a at the next timer interrupt from the power recovery. To the CR unit 6. Thus, for example, if the game ball payout operation by the prize ball device 740 is in an abnormal state immediately before the momentary stop, the state is restored at the time of power recovery. At an early stage, a PRDY signal can be output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6 to notify that the payout operation for paying out the ball is impossible. It can be notified that the game ball payout operation by the prize ball device 740 is in an abnormal state. As a result, it is possible to prevent the BRDY, which is a useless lending request signal from the CR unit 6, from being output at an extremely early stage from the time of power recovery.

  In the CR communication process, when the CR connection signal is read from the input information storage area of the payout control built-in RAM and the logic is HI based on the CR connection signal in the port input process of step S550, that is, a pachinko game. When the machine 1 is powered on and when the payout control board 4110 and the CR unit 6 are electrically connected via the game ball lending device connection terminal plate 869, the payout of the ball is made. When the logic state of the PRDY signal is output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a while the logic state of the PRDY signal is HI, In other words, when the pachinko gaming machine 1 is powered on, the payout control board 4110 and the CR unit 6 are used for lending devices such as game balls. When it is not electrically connected via the connection terminal board 869, in order to notify that the payout operation for paying out the rented ball is impossible, the logic state of the PRDY signal is set to LOW and the payout control MPU 4120a has a predetermined state. Is output to the CR unit 6 from the output terminal of the output port. The logical state of the EXS signal that indicates that one payout operation has been started or ended is stored as EXS signal output setting information in the CR communication information storage area of the payout control built-in RAM, and the payout control board 4110 A CR connection signal that tells whether or not the CR unit 6 is electrically connected is stored in the state information storage area as CR connection information.

  Subsequent to step S554, a full tank and out of ball check process is performed (step S556). In this full tank and out-of-ball check process, the input information is read from the above-mentioned input information storage area, and based on this input information, the accommodation space of the above-mentioned foul cover unit 540 is stored by the detection signal from the full tank switch 550. It is determined whether the game balls are full or the number of game balls taken into the supply path of the award ball device 740 is equal to or greater than a predetermined number based on a detection signal from the ball break switch 750. It is determined whether or not. For example, whether or not the storage space of the foul cover unit 540 is full with the game balls stored is determined by using the timer interruption period 2 ms and the full tank and full ball check processing at this time. The detection signal from 550 is ON, and when the detection signal from the full tank switch 550 is turned OFF in the last full (2 ms before) full ball and ball check check process, that is, the detection signal from the full tank switch 550 is ON from OFF. When the transition is made, the time for the full tank determination time (504 ms) described above is started in the timer update process in step S552. When the full tank determination time becomes 0 in the timer update process, that is, when the full tank determination time is reached, whether or not the detection signal from the full tank switch 550 is ON in this full tank and out-of-ball check process. Determine whether. In this determination, when the detection signal from the full tank switch 550 is ON, the above-mentioned state information memory stores the full tank information indicating that the storage space of the foul cover unit 540 is full with the stored game balls. Store in the area. On the other hand, when the detection signal from the full tank switch 550 is OFF, the full tank information indicating that the storage space of the foul cover unit 540 is not full with the stored game balls is stored in the state information storage area. .

  Whether or not the number of game balls taken into the supply path of the award ball apparatus 740 is equal to or greater than a predetermined number is also determined by using the timer interruption period 2 ms, When the detection signal from the ball break switch is ON, and when the detection signal from the ball break switch is turned OFF in the previous full (2 ms before) full ball and ball break check processing, that is, the detection signal from the ball break switch 750 is turned ON from OFF. When the transition is made, the timer update process in step S552 starts counting the ball breakage determination time (119 ms) described above. When the ball break determination time becomes 0 in the timer update process, that is, when the ball break determination time is reached, whether or not the detection signal from the ball break switch 750 is ON in the full tank and ball break check processing. Determine whether. In this determination, when the detection signal from the ball break switch 750 is ON, the ball break information indicating that the number of game balls taken into the supply passage of the prize ball device 740 is greater than or equal to a predetermined number is displayed. While the information is stored in the information storage area, when the detection signal from the ball break switch 750 is OFF, the ball break is transmitted to the effect that the number of game balls taken into the supply passage of the prize ball device 740 is not more than a predetermined number. Information is stored in the state information storage area.

  Following step S556, command reception processing is performed (step S558). In this command reception process, various commands related to payout from the main control board 4100 (award ball command and self-check command shown in FIG. 28) are received. When the various commands are normally received, the payer ACK information indicating that is stored in the output information storage area. On the other hand, when various commands cannot be received normally, a connection abnormality that indicates that an abnormality has occurred in the connection between the main control board 4100 and the payout control board 4110 (an abnormality has occurred in various command signals). Information is stored in the state information storage area described above.

  Following step S558, command analysis processing is performed (step S560). In this command analysis processing, the command received in step S558 is analyzed, and the analyzed command is stored as received command information in the received command information storage area of the payout control built-in RAM.

  Subsequent to step S560, main operation setting processing is performed (step S562). In this main operation setting process, operation settings such as winning balls, rental balls, ball removal and ball scoring are performed, retry operations are judged, and the number of unpaid balls (the number of winning ball stock) is monitored. To do.

  Following step S562, LED display data creation processing is performed (step S564). In this LED display data creation processing, various types of information are read from the state information storage area described above, display data to be displayed on the error LED indicator 860b of the payout control board 4110 is created, and LED display information is stored in the output information storage area described above. Remember. For example, when the above-mentioned ball piece information is read from the state information storage area and the number of game balls taken into the supply passage of the prize ball device 740 is not more than a predetermined number based on this piece of ball information, the corresponding display data (In this embodiment, a display value 1 (number “1”)) is created and LED display information is stored in the output information storage area.

  Following step S564, command transmission processing is performed (step S566). In this command transmission process, various information is read from the state information storage area described above, and various commands (frame state 1 command, error release navigation command, and frame are classified into the state display shown in FIG. (State 2 command) is created and transmitted to the main control board 4100. For example, when the out-of-ball information is read from the state information storage area, if the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or greater than a predetermined number based on this out-of-ball information, a frame state 1 command is issued. It is created and transmitted to the main control board 4100.

  Subsequent to step S566, the value C is set in the watchdog timer clear register HWCL (step S568). By setting the value C in the watchdog timer clear register HWCL in step S568, the value C is set in the watchdog timer clear register HWCL following the value B set in step S546. As a result, the value A, the value B, and the value C are sequentially set in the watchdog timer clear register HWCL, and the watchdog timer is cleared.

Following step S568, again

Returning to step S539, the value A is set in the watchdog timer clear register HWCL. In step S540, it is determined whether or not a power failure warning signal (paid power failure warning signal) is input. ) Is not input, it is determined in step S542 whether or not the 2 ms elapsed flag HT-FLG has a value of 1. If the 2 ms elapsed flag HT-FLG has a value of 1, that is, 2 ms has elapsed, step S544 is performed. In step S546, the value 0 is set in the 2 ms elapsed flag HT-FLG, the value B is set in the watchdog timer clear register HWCL in step S546, port output processing is performed in step S548, port input processing is performed in step S550, and step S552. In step S554, the timer update process is performed, and the CR communication process is performed in step S554. In step S556, a full / ball check process is performed, a command reception process is performed in step S558, a command analysis process is performed in step S560, a main operation setting process is performed in step S562, and LED display data is generated in step S564. Processing is performed, command transmission processing is performed in step S566, value C is set in watchdog timer clear register HWCL in step S568, and steps S539 to S568 are repeated. The processing from step S539 to step S568 is referred to as “payout control unit main processing”.

  Depending on the progress of the game by the main control board 4100, the processing content of the payout control unit main process varies. For this reason, the time required for the processing of the payout control MPU 4120a varies. Accordingly, the payout control MPU 4120a preferentially outputs to the main control board 4100 a payer ACK signal notifying that various commands related to payout from the main control board 4100 have been normally received in the port output processing of step S548. Yes. As a result, the payout control MPU 4120a secures the processing time so that other fluctuating processes can be sufficiently performed.

  On the other hand, when a power failure warning signal (paid power failure warning signal) is input in step S540, interrupt prohibition setting is performed (step S570). With this setting, the payout control unit timer interrupt processing described later is not performed, writing to the payout control built-in RAM is prevented, and rewriting of the payout information described above is protected.

  Subsequent to step S570, output of the drive signal to the payout motor 744 is stopped (step S574). Thereby, payout of the game ball is stopped.

  Subsequent to step S574, the watchdog timer is cleared (step S60). As described above, the clear setting is performed by sequentially setting the value A, the value B, and the value C in the watchdog timer clear register HWCL.

  Subsequent to step S576, a checksum is calculated and the calculated value is stored (step S578). The checksum is calculated by regarding the payout information in the work area of the payout control built-in RAM as a numerical value excluding the storage area for the checksum value calculated in step S524 and the payout backup flag HBK-FLG.

  Subsequent to step S578, a value 1 is set to the payout backup flag HBK-FLG (step S580). Thereby, storage of the payout backup information is completed.

  Subsequent to step S580, access prohibition to the payout control built-in RAM is set (step S582). With this setting, access to the payout control built-in RAM is prohibited and writing and reading cannot be performed, and payout backup information stored in the payout control internal RAM is protected.

  Following step S582, an infinite loop is entered. In this infinite loop, the value A, the value B, and the value C are not set in this order in the watchdog timer clear register HWCL, so that the watchdog timer is not cleared. Therefore, the payout control MPU 4120a is reset, and then the payout control MPU 4120a performs the payout control unit power-on process again. Note that the processing in step S570 to step S582 and the infinite loop are referred to as “payout control unit power-off processing”.

  The pachinko gaming machine 1 (payout control MPU 4120a) is reset when a power failure occurs or when an instantaneous power failure occurs, and performs a payout control unit power-on process upon power recovery thereafter.

  In step S526, it is checked whether or not the payout backup information stored in the payout control built-in RAM is normal, and then in step S528, whether or not the payout control unit power-off process is normally completed. Are inspected. In this way, by checking the payout backup information stored in the payout control built-in RAM twice, it is checked whether or not the payout backup information is stored by fraud.

[13-2. Payment control unit timer interrupt processing]
Next, the payout control unit timer interrupt process will be described. This payout control unit timer interruption process is repeated at every interruption period (2 ms in this embodiment) set in the payout control unit power-on process shown in FIGS.

  When the payout control unit timer interrupt process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 sets the timer interrupt to be prohibited and switches (saves) the register as shown in FIG. (Step S590). Here, the general purpose storage element (general purpose register) used in the above-described payout control unit main process is switched to the auxiliary register. By using this auxiliary register in the payout control unit timer interrupt process, the value of the general-purpose register is not overwritten. This prevents the contents of the general-purpose register used in the payout control unit main process from being destroyed.

  Subsequent to step S590, the value 1 is set to the 2 ms elapsed flag HT-FLG (step S592). This 2 ms elapsed flag HT-FLG is a flag that counts 2 ms every time this payout control unit timer interrupt processing is performed, that is, every 2 ms, a value of 1 when 2 ms elapses, and a value of 0 when 2 ms elapses. Each is set.

  Subsequent to step S592, the register is switched (returned) (step S594). This restoration is switched from the auxiliary register used in the payout control unit timer interrupt processing to the general-purpose storage element (general-purpose register). By using this general-purpose register in the payout control unit main process, the value of the auxiliary register is not overwritten. This prevents destruction of the contents of the auxiliary register used in the payout control unit timer interrupt process.

  Subsequent to step S594, interrupt permission is set (step S596), and this routine ends.

[13-3. Rotation angle switch history creation process]
Next, rotation angle switch history creation processing will be described. In this rotation angle switch history creation processing, a history of detection signals from the rotation angle switch 752 shown in FIG. 12 is created.

  When the rotation angle switch history creating process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 reads the rotation angle switch detection history information RSW-HIST from the payout control built-in RAM as shown in FIG. (Step S610). This rotation angle switch detection history information RSW-HIST is 1 byte (8 bits: most significant bits B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). A history of detection signals from the rotation angle switch 752 is stored as rotation angle switch detection history information RSW-HIST in the rotation angle switch history information storage area of the payout control built-in RAM. In step S610, rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area.

  Following step S610, it is determined whether there is a detection signal from the rotation angle switch 752 (step S612). This determination is performed based on the detection signal from the rotation angle switch 752 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S612, input information is read from this input information storage area, and it is determined whether or not there is a detection signal from the rotation angle switch 752. When there is a detection signal from the rotation angle switch 752 in the input information, the detection slit for grasping the rotation position of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted from the state where the optical axis of the rotation angle switch 752 is cut off. It is determined that the state has transitioned to the non-blocking state. On the other hand, when there is no detection signal from the rotation angle switch 752 in the input information, the detection slit determines that the optical axis of the rotation angle switch 752 has transitioned from the non-blocking state to the blocking state.

  When the detection slit is in a state where the optical axis of the rotation angle switch 752 is changed from the cutoff state to the non-blocking state in step S612, the rotation angle switch detection history information is shifted (step S614). In this rotation angle switch detection history information shift process, the rotation angle switch detection history information RSW-HIST read in step S610 is converted into the most significant bits B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2. , B2 ← B1, B1 ← the least significant bit B0, and so on, and is shifted bit by bit from the least significant bit B0 toward the most significant bit B7.

  Subsequent to step S614, the value 1 is set to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S616), and this routine is terminated.

  On the other hand, when the detection slit is in a state where the optical axis of the rotation angle switch 752 is changed from the non-blocking state to the blocking state in step S612, the rotation angle switch detection history information is shifted (step S618). In this rotation angle switch detection history information shift processing, the same processing as the rotation angle switch detection history information shift processing in step S614 is performed, and the rotation angle switch detection history information RSW-HIST read in step S610 is converted into the most significant bit. B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← Shifts bit by bit from the least significant bit B0 toward the most significant bit B7. To do.

  Subsequent to step S618, the value 0 is set to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S620), and this routine is ended.

  Thus, each time this rotation angle switch history creation process is performed, the detection slit rotates after the rotation angle switch detection history information RSW-HIST is shifted bit by bit from the least significant bit B0 toward the most significant bit B7. Depending on the state in which the optical axis of the angle switch 752 has been changed from the non-blocking state to the non-blocking state or the state in which the detection slit has shifted the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, Since the value 0 is set, a history of detection signals from the rotation angle switch 752 can be created.

[13-4. Sprocket fixed position determination skip processing]
Next, the sprocket fixed position determination skip process will be described. This sprocket fixed position determination skip process skips the determination of whether or not the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is in a fixed position when a predetermined condition is satisfied. The fixed position determination of the payout rotator is also performed when the payout of the game ball by the prize ball device 740 is completed. Thereby, rotation of the rotating shaft of the payout motor 744 can be reliably started in a state in which no ball is generated.

  When the sprocket fixed position determination skip processing is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 determines whether or not the fixed position determination skip flag SKP-FLG is 0 as shown in FIG. Is determined (step S630). The fixed position determination skip flag SKP-FLG is a flag indicating whether or not the fixed position determination of the payout rotating body is to be performed, and is 1 when the fixed position determination of the payout rotating body is not performed (when skipping). The value is set to 0 when the body position determination is performed (when skipping is not performed).

  When the fixed position determination skip flag SKP-FLG is 0 (not skipped) in step S630, that is, when the fixed position determination of the payout rotating body is performed, the rotation angle is stored from the rotation angle switch history information storage area of the payout control built-in RAM. The switch detection history information RSW-HIST is read (step S632), and it is determined whether or not it matches the fixed position determination value (step S634). This fixed position determination value is stored in the payout built-in ROM, and is “00001111B (“ B ”represents a bit)” in this embodiment, and the upper 4 bits B7 to B4 are 0 and the lower 4 Bits B3 to B0 have a value of 1. In the determination in step S634, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  Here, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST have the value 1, the above described detection slit is the optical axis of the rotation angle switch 752 continuously in four timer interruption cycles. Is a state in which the state is changed from the cut-off state to the non-cut-off state. In the occurrence of the four timer interruption cycles, the payout motor 744 shown in FIG. 12 rotates four steps. The rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. Since these first gear, second gear, and third gear have play (backlash), the payout rotating body rotates clockwise or counterclockwise. Since the rotation is designed to be equivalent to about two steps of rotation of the payout motor 744, in this embodiment, when the fixed position determination of the payout rotating body is performed, the rotation angle switch 752 Detection signal history, rotation angle switch detection history information RSW-HIST is created by the rotation angle switch history creation processing shown in FIG. 39, and the lower 4 bits B3 to B0 of the created rotation angle switch detection history information RSW-HIST, This is performed based on a detection signal from the rotation angle switch 752 when the latest four timer interruption periods occur. As a result, in the four timer interruption cycles, the payout motor 744 rotates four steps, so that it rotates more than the rotation of the payout rotator due to backlash and absorbs the rotation of the payout rotator due to backlash. Can do. Accordingly, since it is possible to prevent erroneous detection of the fixed position of the payout rotating body due to backlash, the rotational position of the payout rotating body can be correctly managed by the rotational position of the payout motor 744. In the present embodiment, the four timer interrupt cycles are 8 ms (= 2 ms × 4 times), and are set as the backlash absorption time.

  In step S634, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S632 match the lower 4 bits B3 to B0 of the fixed position determination value, the fixed position determination skip flag. A value 1 is set in SKP-FLG (step S636). Thereby, it can set so that the fixed position determination of the paying-out rotating body is not performed (skip). The payout control MPU 4120a sets the rotation position of the payout rotating body in step S636 to the fixed position of the payout rotating body.

  Subsequent to step S636, the skip determination time is set to be valid (step S638), and this routine is terminated. Here, the number of detection slits is three, which is the same as the number of recesses of the payout rotating body, and is formed equally (every 120 degrees) on the outer periphery of the rotation detection board. Further, as described above, the rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (dispensing rotary body) is designed to correspond to the 18-step rotation of the dispensing motor 744.

  The payout control MPU 4120 a manages the rotational position of the payout rotating body based on the number of steps of the payout motor 744. Specifically, (1) a transition state in which the detection slit changes the optical axis of the rotation angle switch 752 from a cutoff state to a non-blocking state (referred to as an “edge detection state”), and (2) the detection slit has a rotation angle. A state in which the optical axis of the switch 752 has transitioned from a blocked state to a non-blocked state (referred to as a “fixed position determined state”), and (3) a detection slit shifts the optical axis of the rotation angle switch 752 from a non-blocked state to a blocked state. And three states (the “fixed position determination skip state”). The edge detection state in (1) corresponds to one step rotation of the payout motor 744, the fixed position fixed state in (2) corresponds to four step rotation of the payout motor 744, and the fixed position determination skip state in (3). Corresponds to 13 steps of rotation of the payout motor 744, and the rotation position between the detection slits (120 degrees) of the rotation detection board, that is, the rotation position of the payout rotating body is managed by a total of 18 steps of rotation.

  In the fixed position determination skip state of (3), the detection slit is in a state where the optical axis of the rotation angle switch 752 has transitioned from the non-blocking state to the blocking state. Is set. As described above, since the timer interruption period is set to 2 ms, the skip determination time is 26 ms (= 2 ms × 13 steps).

  When the skip determination time becomes valid in step S638, the skip determination time is subtracted in the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. The payout control MPU 4120a subtracts the skip determination time, and when the subtraction result becomes 0, sets the initial value 0 to the fixed position determination skip flag SKP-FLG.

  On the other hand, when the fixed position determination skip flag SKP-FLG is not 0 (value 1) (when skipping) in step S630, that is, when the fixed position determination of the payout rotating body is not performed, or in step S634, step S632 is performed. If the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step 3 do not match the lower 4 bits B3 to B0 of the fixed position determination value, this routine is terminated as it is. The fixed position determination skip flag SKP-FLG set in step S636 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  The game balls supplied from the pachinko island facility are stored in the prize ball tank 720 and the tank rail 731, taken into the supply path of the prize ball device 740, and guided to the prize ball device 740. When the game balls rub against each other and are charged, electrostatic discharge is generated and noise is generated. For this reason, the prize ball device 740 is susceptible to noise and is in an environment. The rotation angle switch board 753 of the prize ball apparatus 740 shown in FIG. 3 is provided with a rotation angle switch 752, and the detection signal from the rotation angle switch 752 is affected by noise due to electrostatic discharge of the game ball. Cheap. In addition, the wiring (harness) for connecting the payout control board 4110 and the board 754 in the prize ball case 740 in the prize ball apparatus 740 shown in FIG. 3 is also affected by noise due to electrostatic discharge of the game ball. Cheap.

  Therefore, in this embodiment, in order to suppress erroneous detection due to the influence of noise, the fixed position determination skip state (3) described above, that is, the detection slit changes the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. In the transitioned state, the fixed position determination of the payout rotating body is not performed. Thereby, the precision of the fixed position determination of the paying-out rotating body is increased. In addition, since the period and period required for detecting the fixed position of the payout rotating body can be obtained by calculation in advance as described above, the skip determination time can be easily set and adjusted.

[13-5. Spherical spot detection processing]
Next, the sphere collision determination process will be described. In this ball collision determination process, it is determined whether or not a ball collision state has occurred due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted.

  When the ball collision determination process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 rotates the rotation angle from the rotation angle switch history information storage area of the payout control built-in RAM as shown in FIG. The switch detection history information RSW-HIST is read (step S640).

  Subsequent to step S640, it is determined whether or not there is a detection signal from the rotation angle switch 752 described above (step S642). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S640 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S642, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 match the lower 4 bits B3 to B0 of the fixed position determination value, the detection slit is set to the rotation angle. This routine is terminated as it is, assuming that the optical axis of the switch 752 has transitioned from the non-blocking state to the blocking state, that is, the dispensing rotator is rotating and no ball-spinning state has occurred.

  On the other hand, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step S640 and the lower 4 bits B3 to B0 of the fixed position determination value do not match in step S642, a sphere is seen. A value 1 is set in the middle flag PBE-FLG (step S644). This ball-spinning flag PBE-FLG is a flag indicating whether or not a ball-spinning state due to the payout rotating body has occurred. When the payout motor 744 performs a ball-spinning operation, the value 1 is set. When no operation is performed, the value is set to 0.

  Subsequent to step S644, the ball collision determination time is set to be valid (step S646), and this routine is terminated. When the ball stagnation determination time becomes valid, the sphere sag determination time is subtracted in the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. .

[13-6. Various prize ball stock addition processing]
Next, various prize ball stock number addition processing will be described. The prize ball stock number addition process includes a prize ball prize ball number addition process and a rental ball prize ball number addition process. The prize ball stock number addition process is performed from the main control board 4100. This is a process of adding the number of balls to be paid out based on a prize ball command, which will be described later. The prize ball stock number adding process for lending is a process of adding the number of balls to be paid out based on a lending request signal from the CR unit 6. is there. First, the award ball stock number addition process for prize balls will be described, and then the award ball stock number addition process for rental balls will be described. In this embodiment, the prize ball stock number addition process for prize balls is set to be performed preferentially, and according to the number of prize balls stock added in this prize ball stock number addition process. After the game ball is paid out by the prize ball device 740, it is set so that the number of prize ball stock for lending is added.

[13-6-1. Prize ball stock number addition process for prize balls]
When the prize ball stock number addition process for the prize ball is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 determines whether or not there is a prize ball command as shown in FIG. S650). This determination is made based on the command analyzed in the command analysis process in step S560 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the analyzed command is stored as received command information in the received command information storage area of the payout control built-in RAM. In step S650, the received command information is read from the received command information storage area to determine whether the command is a prize ball command.

  If the received command information is not a prize ball command in step S650, the routine is terminated as it is. If the received command information is a prize ball command in step S650, the prize ball number PBV corresponding to the prize ball command is determined as a prize ball. Read from the number information table (step S652). The prize ball number information table, which will be described in detail later, is an information table stored in advance in the payout built-in ROM in association with the prize ball command and the prize ball number PBV.

  Following step S652, the prize ball stock number PBS is read from the payout control built-in RAM (step S654). This award ball stock PBS represents the number of game balls that have not yet been paid out by the prize ball device 740, that is, the number of unpaid balls, and in this embodiment has a storage capacity of 2 bytes (16 bits). ing. As a result, the award ball stock number PBS can store the number of unpaid balls from 0 to 32767. The prize ball stock PBS is stored in the prize ball information storage area of the payout control built-in RAM. In step S652, the prize ball stock number PBS is read from the prize ball information storage area.

  The prize ball number PBV read in step S652 is added to the prize ball stock PBS read in step S654 (step S656), and this routine is terminated. After the addition in step S656, the prize ball command read in step S650 is erased from the received command information storage area.

[13-6-2. Addition of prize ball stock for rental balls]
Next, the processing for adding the number of winning ball stocks will be described. When the lending prize ball stock number addition process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 determines whether or not there is a lending request signal as shown in FIG. (Step S660). This determination is made based on the lending request signal from the CR unit 6 in the port input process in step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the lending request signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S660, the input information is read from the input information storage area, and it is determined whether or not there is a lending request signal.

  When there is no ball rental request signal in step S660, this routine is terminated as it is, but when there is a ball rental request signal in step S660, the prize ball stock number PBS is read from the above-mentioned prize ball information storage area of the payout control built-in RAM. (Step S662), the rented ball number RBV is added to the award ball stock number PBS (Step S664), and this routine is finished. The number of rented balls RBV is a fixed value and is stored in advance in the payout built-in ROM. In the present embodiment, the value 25 is set as the number of rented balls RBV. In addition, after adding in step S664, the rent request signal read in step S660 is deleted from the input information storage area. Further, in this embodiment, the winning ball is prioritized (the winning ball and the lending are managed separately), so even if there is a lending request signal, the lending request signal is held. When a prize ball is paid out, a rental ball is paid out. Therefore, in this embodiment, the payout of the rented ball is performed after the prize ball stock PBS reaches the value 0.

[13-7. Stock monitoring process]
Next, the stock monitoring process will be described. This stock monitoring process monitors whether or not the player continues playing the game in a state where the storage space of the foul cover unit 540 shown in FIG. 1 is filled with the stored game balls (stocked state). It is processing to do.

  When the stock monitoring process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, as shown in FIG. Reading (step S670), it is determined whether or not the read award ball stock number PBS is greater than or equal to the caution threshold TH (step S672). The caution threshold TH is a fixed value and is stored in advance in the payout built-in ROM. In the present embodiment, the value 50 is set as the caution threshold TH.

  When the prize ball stock PBS is greater than or equal to the attention threshold TH in step S672, the attention flag CA-FLG is set to a value 1 (step S674), and this routine ends. The caution flag CA-FLG indicates that the player starts stocking game balls in the accommodation space of the foul cover unit 540, and the number of game balls not paid out (the number of prize balls described above) exceeds the caution threshold TH. It is a flag indicating that it has been reached, and is set to a value of 1 when the threshold value exceeds the alert threshold value TH, and to a value of 0 when it does not reach the alert threshold value TH or more.

  On the other hand, if the winning ball stock number PBS is less than the caution threshold TH in step S672, the caution flag CA-FLG is set to 0 (step S676), and this routine is terminated.

  If the game state becomes a big hit, and the player relaxes and sees the effects unfolded on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 shown in FIG. During one round, the game ball paid out as a prize ball may not be pulled out by operating the lower plate ball removal button 354 from the lower plate 302 shown in FIG. When the game is continued in this state, the lower plate 302 is filled with game balls, and the game balls are accumulated in the accommodation space of the foul cover unit 540. When the storage space of the foul cover unit 540 is filled with game balls, as described above, the value of the award ball stock PBS increases to exceed the caution threshold TH, and is provided in the door frame 5 as a caution effect. A plurality of LEDs on various decorative boards blink. By this blinking, for example, it is possible to inform a hall clerk of paying attention to the player's game. As a result, the hall clerk can tell the player that he / she wants to remove the game ball from the lower plate 302, and the player fills the lower plate 302 (the storage space of the foul cover unit 540) with the game ball full. It is possible to prevent the game from continuing.

  In the present embodiment, the careful threshold value TH is set to a value 50 corresponding to about one fifth of the upper limit value 255 that can be represented by 1 byte (8 bits). As a result, it is possible to inform the hall clerk that the player should be alerted to the game as early as possible.

[13-8. Dispensing ball edge motion determination setting process]
Next, the payout ball engagement operation determination setting process will be described. This paying ball sliding motion determination setting processing is performed by paying out the game ball to the upper plate 301 or the lower plate 302 shown in FIG. This is a process for setting whether or not to discharge or not.

  When the payout ball engagement operation determination setting process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, as shown in FIG. 45, stores the rotation angle switch history information storage area of the above-described payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read out from (step S680).

  Following step S680, it is determined whether there is a detection signal from the rotation angle switch 752 shown in FIG. 12 (step S682). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S680 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S682, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S682, if the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 match the lower 4 bits B3 to B0 of the fixed position determination value, the retry error flag RTERR- It is determined whether FLG is a value 1 (step S684). The retry error flag RTERR-FLG is a flag indicating whether or not a retry operation described later is operating abnormally. The value is 1 when the retry operation is operating abnormally, and the retry operation is not operating abnormally (retry operation). When the operation is normal), the value is set to 0.

  If it is determined in step S682 that the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 do not match the lower 4 bits B3 to B0 of the fixed position determination value, or in step S684. When the retry error flag RTERR-FLG is not a value 1 (value 0), that is, when the retry operation is not operating abnormally, it is determined whether or not the ball ball flag PBE-FLG is a value 1 ( Step S686). This in-between-ball flag PBE-FLG is a flag that indicates whether or not a ball-bending state has occurred due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. A value of 1 is set when the motion is being performed, and a value of 0 is set when the sphere motion is not being performed.

  When the ball-picking flag PEB-FLG is not the value 1 (value 0) in step S686, that is, when the ball-pushing operation is not performed, the award ball stock is stored from the award ball information storage area of the payout control built-in RAM. The number PBS is read (step S688), and it is determined whether or not the read prize ball stock number PBS is greater than 0 (step S690). In this determination, it is determined whether or not there is a number of unpaid balls in the payout of game balls by the payout motor 744.

  When the winning ball stock number PBS is larger than 0 in step S690, that is, when there is an unpaid ball number, it is determined whether or not the storage space of the foul cover unit 540 is full of stored gaming balls ( Step S692). This determination is made on the basis of the full tank information stored in the full tank and ball-out check process in step S556 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the full tank information is stored in the state information storage area of the payout control built-in RAM described above. In step S692, the full tank information is read from the state information storage area to determine whether or not the storage space of the foul cover unit 540 is full with the stored game balls.

  When the storage space of the foul cover unit 540 is not full in step S692, the payout setting process described later is performed (step S694), and this routine is terminated. In this payout setting process, a payout operation for paying out game balls to the upper plate 301 and the lower plate 302 is performed.

  On the other hand, when the storage space of the foul cover unit 540 is full in the game ball stored in step S692, this routine is finished as it is. In the pachinko gaming machine 1 of the present embodiment, the payout motor 744 is forcibly stopped when the storage space of the foul cover unit 540 is full with the stored game balls. When a prize ball is generated while the payout motor 744 is forcibly stopped, the number of unpaid balls by the payout motor 744 increases, and the prize ball stock number PBS is added by the prize ball prize ball number addition process shown in FIG. Will increase.

  On the other hand, when the winning ball stock number PBS is not larger than 0 (value 0) in step S690, that is, when there is no unpaid ball number, this routine is ended as it is. As a result, game balls are not paid out.

  On the other hand, when the sphere engagement flag PBE-FLG is 1 in step S686, that is, when the sphere engagement operation is being performed, a sphere engagement operation setting process described later is performed (step S700), and this routine is terminated. In this ball-spinning operation setting process, a ball-spinning operation that cancels the ball-spinning state by the payout rotating body of the prize ball device 740 is performed.

  On the other hand, when the retry error flag RTERR-FLG is 1 in step S684, that is, when the retry operation is abnormal, an output stop (stop) of the drive signal to the payout motor 744 is set (step S702). . In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM described above.

  Subsequent to step S702, an error state output to the CR unit 6 is set (step S704), and this routine is terminated. In step S704, the payout control MPU 4120a is not communicating with the CR unit 6 in order to inform the CR unit 6 that the ball lending is not possible at present (the BRDY logic from the CR unit 6 is LOW, In other words, the logic of the PRDY signal is LOW, that is, the state of being lowered is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. Remember. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is transferred from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120 to the game ball lending device connection terminal plate 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rises and is held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. Thus, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6 via the gaming ball lending device connection terminal plate 869. . Note that “maintain the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (when the EXS signal falls and is held), the logic of the EXS signal is HI. In some cases (when the EXS signal is held up), the logic HI is maintained.

[13-8-1. Withdrawal setting process]
Next, the payout setting process will be described. In this payout setting process, the payout motor 744 is driven to make a setting for paying out game balls.

  When the payout setting process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 reads the drive command number DRV from the payout control built-in RAM as shown in FIG. 46 (step S710). This drive command number DRV commands the number of game balls to be paid out by the payout motor 744, and is equivalent to the prize ball stock number PBS. The drive command number DRV is stored in the prize ball information storage area of the payout control built-in RAM. In step S710, the drive command number DRV is read from the prize ball information storage area.

  Subsequent to step S710, it is determined whether the drive command number DRV is 0 (step S712). This determination is based on the drive command number DRV as to whether or not the number of game balls to be paid out by the payout motor 744 remains.

  When the drive command number DRV is 0 in step S712, that is, when the number of game balls paid out by the payout motor 744 is zero, the output stop (stop) of the drive signal to the payout motor 744 is set ( Step S714). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM described above.

  Following step S714, the winning ball stock number PBS is read from the winning ball information storage area of the payout control built-in RAM (step S716), and the real ball count PB is read (step S718). The actual ball count PB is obtained by counting the number of game balls actually paid out by the payout motor 744. This count will be described in detail later, but in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. 37, the count switch 751 shown in FIG. This is performed based on the detection signal. The real ball count PB is stored in the prize ball information storage area of the payout control built-in RAM. In step S718, the real ball count PB is read from this prize ball information storage area.

  Subsequent to step S718, the value obtained by subtracting the actual ball count PB read in step S718 from the prize ball stock number PBS read in step S716 is set to the prize ball stock number PBS and the drive command number DRV (step S720). The actual ball count PB is set to 0 (step S722), and this routine is terminated. When the drive command number DRV and the real ball count PB are 0, in step S722, the value of the prize ball stock number PBS read in step S716 is set as the drive command number DRV as it is.

  On the other hand, when the drive command number DRV is not 0 in step S712, that is, when there is a number of game balls to be paid out by the payout motor 744, an output of a drive signal to the payout motor 744 is set. (Step S724). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S724, the value 1 is subtracted from the drive command number DRV (decremented, step S726), and it is determined whether there is a detection signal from the count switch 751 (step S728). This determination is made based on the detection signal from the count switch 751 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S728, the input information is read from the input information storage area, and it is determined whether or not there is a detection signal from the counting switch 751.

  If there is a detection signal from the counting switch 751 in step S728, the actual ball count PB is incremented by 1 (incremented, step S730), and this routine is terminated. In step S730, the real ball count PB is incremented by incrementing the real ball count PB.

  On the other hand, if there is no detection signal from the counting switch 751 in step S728, this routine is ended as it is. In this way, the payout control MPU 4120a decrements the drive command number DRV in step S726, and when there is no detection signal from the count switch 751 in the determination in step S728, that is, when the actual ball count PB is not incremented. Determines that one game ball could not be paid out because the game ball was not received in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 was transmitted. Accordingly, the payout control MPU 4120a sets the value obtained by subtracting the actual ball count PB from the prize ball stock number PBS to the drive command number DRV in step S720 described above in order to pay out one ball that should be paid out again. Thereby, when there is no detection signal from the counting switch 751 in the determination of step S728, that is, when the actual ball count PB is not incremented, the value 1 which is one ball that should be paid out is included in the prize ball stock number PBS. In other words, since the value 1 which is one ball to be paid out can be rounded into the winning ball stock number PBS, a retry operation of paying out the one ball to be paid out again can be performed. By performing this retry operation, the possibility of unpaid game balls to the player can be extremely reduced, and a player's disadvantage due to unpaid game balls can be prevented.

[13-8-2. Spherical motion setting process]
Next, the spherical cornering operation setting process will be described. This ball-spinning operation setting process is a process for performing a setting to cancel the ball-spinning state by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 of the prize ball device 740 is transmitted.

  When the spherical movement operation setting process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 determines whether or not the spherical collision determination time has elapsed as shown in FIG. S750). This determination is made based on the ball collision determination time subtracted in the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the ball collision determination time is stored as time management information in the time management information storage area of the above-described payout control built-in RAM. In step S750, the time management information is read from the time management information storage area to determine whether or not the ball stagnation determination time has elapsed.

  If it is determined in step S750 that the ball collision determination time has not elapsed, the rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area of the payout control built-in RAM (step S752).

  Subsequent to step S752, it is determined whether or not there is a detection signal from the rotation angle switch 752 described above (step S754). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S752 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S754, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step S752 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the spherical motion is performed. The output of the drive signal to the payout motor 744 is set so as to be performed (step S756), and this routine is finished. In this setting, drive information for outputting a drive signal to the payout motor 744 is set and stored in the output information storage area of the payout control built-in RAM described above.

  On the other hand, in step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout motor 744 is set. The stop of the drive signal to is set (step S758). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S758, as the end of the ball bending operation, the value 0 is set in the ball bending flag PBE-FLG (step S760), and this routine is ended. This ball-spinning flag PBE-FLG is a flag indicating whether or not a ball-spinning state due to the payout rotating body has occurred. When no operation is being performed (end of the ball collapsing operation), the value is set to 0.

  On the other hand, when the ball collision determination time has elapsed in step S750, stop of the drive signal to the payout motor 744 is set (step S762). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S762, an error state output to the CR unit 6 is set (step S764). Here, in order to notify the CR unit 6 that the ball lending is not possible at present, the payout control MPU 4120a is not communicating with the CR unit 6 (the logic of BRDY from the CR unit 6 is LOW, that is, The logic of the PRDY signal is LOW, that is, the state of falling is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. To do. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is transferred from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120 to the game ball lending device connection terminal plate 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rises and is held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. Thus, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6 via the gaming ball lending device connection terminal plate 869. . Note that “maintain the logic state of the EXS signal” means that, as described above, when the logic of the EXS signal is LOW (the EXS signal falls and is held), the logic LOW is maintained and the EXS signal is maintained. When the logic of HI is HI (the EXS signal is held high), the logic HI is maintained.

  Subsequent to step S764, a value 0 is set to the ball-in-sphere flag PBE-FLG as the end of the ball-balling operation (step S766), and this routine is ended.

[13-9. Retry operation monitoring process]
Next, the retry operation monitoring process will be described. This retry operation monitoring process is a process for monitoring whether or not a retry operation for paying out a game ball that should be paid out is performed normally.

  When the retry operation monitoring process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, as shown in FIG. The detection history information RSW-HIST is read (step S770).

  Following step S770, it is determined whether there is a detection signal from the rotation angle switch 752 described above (step S772). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S770 matches the home position determination value. As described above, this fixed position determination value is stored in the payout control built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and B7 to B4 of the upper 4 bits. Is the value 0, and the lower 4 bits B3 to B0 are the value 1. In the determination in step S772, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S772, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 match the lower 4 bits B3 to B0 of the fixed position determination value, the mismatch counter INCC is set. Add 1 (increment, step S774). The inconsistency counter INCC includes the number of game balls received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the number of balls detected by the counting switch 751, The number of game balls received and paid out by the recess of the payout rotor coincides with the number of balls detected by the counting switch 751. The value is 0. The payout control MPU 4120a performs a retry operation in the payout installation process shown in FIG. 46, so that the number of game balls that are received and paid out by the concave portion of the payout rotating body by this retry operation and the actual counting switch Whether or not paying out game balls that do not match with the number of balls detected in 751 is repeatedly performed is determined by monitoring with the inconsistency counter INCC. The inconsistency counter INCC is stored in the prize ball information storage area of the payout control built-in RAM. In step S774, the inconsistency counter INCC stored in the prize ball information storage area is incremented.

  Subsequent to step S774 or in step S772, the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step S770 do not match the lower 4 bits B3 to B0 of the fixed position determination value. In some cases, it is determined whether there is a detection signal from the counting switch 751 (step S776). This determination is made based on the detection signal from the count switch 751 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, as described above, the detection signal is stored as input information in the input information storage area of the above-described payout control built-in RAM. In step S776, input information is read from this input information storage area, and it is determined whether or not there is a detection signal from the counting switch 751.

  When there is a detection signal from the counting switch 751 in step S776, the value 1 is subtracted from the inconsistency counter INCC stored in the award ball information storage area of the payout control built-in RAM (decremented, step S778).

  Subsequent to step S778 or when there is no detection signal from the counting switch 751 in step S776, it is determined whether or not the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH (step S780). In the pachinko gaming machine 1 of the present invention, it has been experimentally obtained that the probability that a game ball that does not match due to a retry operation is paid out is about one millionth, and in this embodiment, inconsistency The value 5 is set as the threshold INCTH.

  In the process for setting the work area of the payout control built-in RAM in step S530 in the payout control unit power-on process of FIG. Information used for the retry operation monitoring process is set based on the inconsistency counter INCC stored in the prize ball information storage area. By this processing, for example, even if there is a momentary power failure or a power failure, the value of the inconsistency counter INCC at the time of power recovery is restored to the value of the inconsistency counter INCC just before the momentary power failure or power failure stored as payout backup information Can be done. As a result, in the determination in step S780, the game ball payout operation (retry operation) performed by the prize ball device 740, which has been performed until immediately before a momentary power failure or power failure, can be continued from the time of power recovery. ing. Therefore, for example, immediately before a momentary power failure or power failure, if the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH in the determination of step S780, it is determined that the retry operation is operating normally, that is, a prize ball It is determined that the game ball payout operation by the device 740 is in a normal state, and it can be determined that the game ball payout operation by the prize ball device 740 is in a normal state by the determination in step S780 even during power recovery. On the other hand, when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in the determination in step S780, it is determined that the retry operation is abnormal, that is, the game ball payout operation by the prize ball device 740 is abnormal. Even when power is restored, it can be determined in step S780 that the game ball payout by the prize ball device 740 is in an abnormal state.

  If the value of the inconsistency counter INCC is smaller than the inconsistency threshold INCTH in step S780, this routine is terminated as it is. On the other hand, when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, when the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH, it is indicated that “retry error”. In order to notify, the error information indicator 860b, which is a segment indicator mounted on the payout control board 4110, sets retry error information for displaying the number “5”, and the state information storage area of the payout control built-in RAM described above Is set (stored) (step S782).

  Subsequent to step S782, the value 0 (initial value 0) is set to the inconsistency counter INCC stored in the prize ball information storage area of the payout control built-in RAM (step S784). In step S784, the mismatch counter INCC determines that the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH. Initialization is triggered by the occurrence of this internal factor. When the operation switch 860a is operated to clear the RAM when the power is turned on, the inconsistency counter INCC is initialized when the external factor occurs. When the operation switch 860a is operated when the power is turned on, as described above, the operation signal is input to the main control MPU 4100a of the main control board 4100 shown in FIG. 11 as the RAM clear signal. As described above, the main control MPU 4100a erases all the information stored in the main control built-in RAM, and outputs a RAM clear notification command to the peripheral control board 4140 shown in FIG. Thereby, the RAM clear notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG.

  Subsequent to step S784, the retry error flag RTERR-FLG is set to 1 (step S786), and this routine is terminated. This retry error flag RTERR-FLG is a flag indicating whether or not the retry operation is operating abnormally. The value is 1 when the retry operation is operating abnormally, and the retry operation is not operating abnormally (retry operation is not performed). It is set to a value of 0 when operating normally).

  The payout control MPU 4120a uses the retry error information set (stored) in the output information storage area of the payout control built-in RAM in step S782 in the payout control unit power-on process (payout control unit main process) shown in FIG. In step S566, a retry error status command is created and transmitted to the main control board 4100, and display data to be displayed on the error LED indicator 860b is created in the LED display data creation process in step S564 in the same process. The LED display information is stored in the output information storage area, and a drive signal is output to the error LED display 860b based on the LED display information stored in the output information storage area in the port output process of step S548 in the process. The number “5” is displayed on the LED display 860b. The main control board 4100 that has received the status command transmits the peripheral control board 4140 to the peripheral control board 4140 in the peripheral control board command transmission process of step S92 in the main control timer interrupt process shown in FIG. The frame decoration drive amplifier board 194 shown in FIG. 14 has a door frame side lighting / flashing command for emitting a plurality of LEDs of various decorative boards provided in the LED to emit light in a predetermined color (in this embodiment, red). The plurality of LEDs emit light with a predetermined color. As described above, the store clerk or the like who notices the light emission of the plurality of LEDs opens the main body frame 3 with respect to the outer frame 2 to thereby display the number "" on the error LED display 860b mounted on the payout control board 4110. By visually observing that “5” is displayed, it can be confirmed that a “retry error” has occurred. Thereby, in order to investigate the cause of the occurrence, the store clerk of the hall, etc., confirms the malfunction of the counting switch 751, the disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, and the like. Compared with the case where the light emission of the plurality of LEDs and the display content of the error LED indicator 860b are not notified, it can be performed very quickly.

  In addition, it has been described above that it is difficult to detect the game ball that is received by the concave portion of the payout rotating body to which the rotation of the rotary shaft of the payout motor 744 is transmitted by intentionally disabling the counting switch 751. Even if an illegal act of forcibly generating a retry operation and illegally acquiring a game ball paid out by the retry operation is performed, the value of the inconsistency counter INCC is equal to or greater than the inconsistency threshold INCTH. Since the plurality of LEDs on the various decorative boards provided on the door frame 5 emit light, a hall clerk or the like rushes to confirm the state of the pachinko gaming machine 1. If it does so, the player who performs a fraudulent act will have to be interrupted so that the act may not be discovered, and the illegal game ball by a fraudulent act cannot be continuously acquired. Even if the value of the inconsistency counter INCC coincides with the inconsistency threshold INCTH, the number of game balls that can be acquired by a player who performs an illegal act is the same as the inconsistency threshold INCTH. Therefore, damage to the hall due to the act of intentionally deactivating the counting switch 751 can be suppressed to an extremely low level.

  Further, as described above, the mismatch counter INCC determines that the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH. Initialization is triggered by the occurrence of an internal factor. As a result, the inconsistency counter INCC is not initialized when an external factor occurs, for example, that the operation switch 860a is operated to cancel the error. Therefore, even if the error release switch 860a or the like is illegally modified so that the operation signal is input to the payout control MPU 4120a, the inconsistency counter INCC is forcibly initialized by such an illegal action. There is no.

[13-10. Inconsistency counter reset judgment process]
Next, the mismatch counter reset process will be described. In this inconsistency counter reset process, the number of game balls received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the number of balls detected by the counting switch 751 This is a process for determining whether or not to reset the inconsistency counter INCC that calculates the difference between.

  When the mismatch counter reset determination process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 determines whether or not the mismatch counter reset determination time has elapsed (see FIG. 49) (see FIG. 49). Step S790). This determination is performed based on the mismatch counter reset determination time updated in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the mismatch counter reset determination time is stored as time management information in the time management information storage area of the payout control built-in RAM described above. In step S790, the time management information is read from the time management information storage area to determine whether or not the mismatch counter reset determination time has elapsed.

  If the inconsistency counter reset determination time has not elapsed in step S790, this routine is ended as it is. On the other hand, when the mismatch counter reset determination time has elapsed in step S790, the mismatch counter reset determination time is initialized (step S792). By this initialization, an initial value of 7000 s (about 2 hours) is set as the mismatch counter reset determination time.

  Subsequent to step S792, a value 0 (initial value 0) is set in the inconsistency counter INCC stored in the award ball information storage area of the payout control built-in RAM described above (step S794), and this routine is ended. As described above, the inconsistency counter INCC is detected by the counting switch 751 and the number of game balls received and received by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is a counter for calculating the difference between the number of balls, and the number of game balls received and paid out by the recess of the payout rotating body is usually equal to the number of balls detected by the counting switch 751. As a result, the value is 0. The payout control MPU 4120a performs a retry operation in the payout installation process shown in FIG. 46, so that the number of game balls that are received and paid out by the concave portion of the payout rotating body by this retry operation and the actual counting switch Whether or not paying out game balls that do not match with the number of balls detected in 751 is repeatedly performed is determined by monitoring with the inconsistency counter INCC. In the pachinko gaming machine 1 of the present invention, it has been experimentally obtained that the probability that one game ball that does not fit in due to a retry operation is paid out is about one millionth.

  Here, as described above, the pachinko gaming machine 1 includes the game board 4 and a frame body such as the main body frame 3 to which the game board 4 is mounted, and the game board 4 is exchanged (new stand replacement). Since the game specifications can be changed, the payout control board 4110 for controlling the prize ball device 740, the power supply board 851 for generating the driving power for the prize ball device 740 and the control power for the payout control board 4110 are common. Equipped on the frame side as a function. As described above, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 can determine an abnormal operation as to whether or not the retry operation is repeated by monitoring the inconsistency counter INCC. 37, the payout control unit power-off process in the payout control unit power-on process shown in FIG. 37 stores the inconsistency counter INCC immediately before the shut-off when the power is shut off, while the payout control unit power-on shown in FIG. In the process of step S530 in the time process (setting of the RAM work area when power is restored), the process is started again from the stored inconsistency counter INCC when the power is turned on.

  Then, when the game board 4 mounted on the pachinko gaming machine 1 is switched to a game board 4 'having a different game specification different from the game board 4 and turned on, the payout control is performed. The payout control MPU 4120a of the payout control unit 4120 on the substrate 4110 starts processing again from the mismatch counter INCC stored when the game board 4 is mounted on the pachinko gaming machine 1. That is, when the player plays the pachinko gaming machine 1 with the game board 4 ′ attached thereto, the mismatch counter INCC in the pachinko gaming machine 1 with the game board 4 before replacement is inherited as it is. For this reason, when a player plays the pachinko gaming machine 1 with the game board 4 ′ mounted, the probability of 1 / million million happens, and the number of game balls that do not match is generated and the inconsistency counter INCC When the inconsistency counter INCC becomes equal to or greater than the inconsistency threshold INCTH, the game board 4 is replaced with the game board 4 'and is determined as an abnormal operation of the retry operation by the payout control MPU 4120a in a short period. There is a risk. That is, in a short period of time after the game board 4 is replaced with the game board 4 ′, a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, contact failure of various connectors, and the like. In spite of this, there is a possibility that it is suddenly determined as an abnormal operation of the retry operation.

  As described above, when the game board 4 is replaced with the game board 4 ′ and it is determined as an abnormal operation of the retry operation in a short period of time, the impression that the replaced game board 4 ′ is new and easily breaks down. May be given to players. The probability of one millionth of a game ball being paid out due to a retry operation being set in the hall is that the pachinko gaming machine 1 of the present invention is installed in the hall and continuously operated for one week during the hall's business hours. In this case, it is the same as the probability that one unsuccessful game ball is paid out due to the retry operation, and therefore, in the processing of step S778 in the retry operation monitoring process shown in FIG. With a probability of 1, the value 1 is not subtracted. Then, the value 1 is incremented to the mismatch counter INCC in one week and the mismatch counter INCC becomes the value 1, and the value 1 is further incremented in the mismatch counter INCC and the mismatch counter INCC becomes the value 2 in 2 weeks. In week, value 1 is further incremented in inconsistency counter INCC, value in inconsistency counter INCC becomes value 3, in value 4 in inconsistency counter INCC is further incremented, value in inconsistency counter INCC becomes value 4, and in week 5 The value 1 is further incremented in the inconsistency counter INCC, and the inconsistency counter INCC becomes the value 5, which coincides with the inconsistency threshold INCTH described above. In other words, when 5 weeks have elapsed, the inconsistency counter INCC matches the inconsistency threshold INCTH, so that the payout control MPU 4120a determines whether the count switch 751 receives the determination in step S776 in the retry operation monitoring process shown in FIG. It is determined that there is no detection signal, and it is determined that a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, etc. In the process of step S782 in the retry operation monitoring process shown in FIG. 48, in order to notify that it is a “retry error”, the error LED display 860b, which is a segment display mounted on the payout control board 4110, displays a number “ Set retry error information to display “5” and built-in payout control R So that the set (stored) in the status information storage area of M.

  Therefore, when the payout control MPU 4120a determines that the inconsistency counter reset determination time has elapsed in the determination of step S790 in the inconsistency counter reset determination processing, that is, every 7000 s (about 2 hours), the inconsistency counter reset is repeated. By forcibly setting the inconsistency counter INCC to 0, that is, forcibly resetting the inconsistency counter INCC in the process of step S794 in the determination process, the inconsistency counter INCC that is generated with the probability of 1 / million million is increased. Invalidated. As a result, there is an error in the retry operation even though the malfunction of the counting switch 751, the disconnection of various harnesses from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, and the like have not occurred. Can be prevented from being set (stored) in the status information storage area of the payout control built-in RAM.

  Note that the game ball that is received by the recess of the payout rotating body to which the rotation of the rotary shaft of the payout motor 744 is transmitted by deliberately disabling the counting switch 751 is difficult to detect. In the case where the counting switch 751 is intentionally repeatedly deactivated for a short time even if an illegal act of forcibly generating a retry operation and illegally acquiring a game ball paid out by the retry operation is performed, In this way, when the value of the mismatch counter INCC is equal to or greater than the mismatch threshold INCTH, a plurality of LEDs on various decorative boards provided on the door frame 5 emit light, so that the store clerk or the like of the hall changes the state of the pachinko gaming machine 1 I will rush to confirm. If it does so, the player who performs a fraudulent act will have to be interrupted so that the act may not be discovered, and the illegal game ball by a fraudulent act cannot be continuously acquired. On the other hand, when the count switch 751 is intentionally repeatedly inactivated for a long time so that the value of the mismatch counter INCC does not become equal to or greater than the mismatch threshold INCTH, the mismatch counter INCC is set every 7000 s (about 2 hours). Although reset, the number of game balls that can be acquired by a player who performs fraudulent action is that the inconsistency counter INCC is up to the inconsistency threshold INCTH and the count switch 751 is intentionally set as described above. Even if the player is repeatedly inactivated for a long time, the number of game balls that can be acquired by a player who performs an illegal act can be extremely reduced.

[13-11. Error release operation determination process]
Next, the error release operation determination process will be described. In this error release operation determination process, it is determined whether or not the operation switch 860a shown in FIG. 12 is operated.

  When the error release operation determination process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 determines whether or not the operation switch 860a is operated to cancel the error, as shown in FIG. (Step S800). This determination is made based on the operation signal from the operation switch 860a in the port input process in step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the operation signal is stored as input information in the input information storage area of the payout control built-in RAM described above. In step S800, the input information is read from the input information storage area, and when the logic of the operation signal from the operation switch 860a is HI, it is determined that there is no instruction to cancel the error, and the operation switch 860a operates. On the other hand, when the logic of the operation signal from the operation switch 860a is LOW, it is determined that the error is instructed to be canceled, and it is determined that the operation switch 860a is operated.

  When the operation switch 860a is not operated in step S800, this routine is ended as it is, while when the operation switch 860a is operated in step S800, an error flag state confirmation process is performed (step S802). In this error flag state determination process, the state of the error flag corresponding to various types of error information regarding the prize ball device 740 is confirmed. For example, the state of the retry error flag RTERR-FLG indicating whether or not the retry operation is abnormal is confirmed. As described above, the retry error flag RTERR-FLG has a value of 1 when the retry operation is operating abnormally and a value of 0 when the retry operation is not operating abnormally (retry operation is operating normally), respectively. Since the payout control MPU 4120a is set, it confirms whether the value of the retry error flag RTERR-FLG is 0 or 1.

  Subsequent to step S802, state information setting processing is performed (step S804). In this status information setting process, if the status of the error flag indicates that an error has occurred based on the error flag confirmed in step S802, the status information corresponding to the error flag is described above. Is set (stored) in the status information storage area of the payout control built-in RAM. As a result, various information (status information) is read from the status information storage area in the command transmission process of step S566 in the payout control section power-on process (payout control section main process) shown in FIG. A status command is created on the basis of the command and transmitted to the main control board 4100. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally is 1, that is, when the retry operation is operating abnormally, it indicates that an error has occurred in the retry operation. When the retry error information to be transmitted is set (stored) in the status information storage area of the payout control built-in RAM, in the command transmission process of step S566 in the payout control section power-on process (payout control section main process) shown in FIG. A retry error status command is created and transmitted to the main control board 4100.

  The main control board 4100 that has received the retry error information transmits the peripheral control board 4140 to the peripheral control board 4140 in the peripheral control board command transmission process in step S92 in the main control timer interrupt process shown in FIG. Retry operation error notification processing is performed to notify that an error has occurred in the retry operation. In this retry operation error notification process, the error notification announcement of the retry operation “Check the prize ball unit.” And “Check the payout control board harness.” 2 times) By repeatedly flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG. It is supposed to be. The clerk of the hall, etc. who heard the error notification announcement of the retry operation, such as the malfunction of the counting switch 751 shown in FIG. Compared to the case where the error notification announcement of the retry operation does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, it can be confirmed very quickly. In the retry operation error notification process, a plurality of LEDs on various decorative boards provided on the door frame 5 are caused to emit light in a predetermined color (red in the present embodiment).

  Subsequent to step S804, release setting processing is performed (step S806). In this cancellation setting process, when the error flag state indicates that an error has occurred based on the error flag corresponding to the various types of error information confirmed in step S802, the error flag corresponds to the error flag. The CR unit 6 indicates that the error is forcibly stopped or the ball can be lent out by the error LED indicator 860b which is a segment indicator already mounted on the payout control board 4110. In this case, the logic of the PRDY signal described above is held at HI, that is, the state where the PRDY signal is raised, and the lending device connection terminal plate 869 such as a game ball is connected from the output terminal of the payout control MPU 4120a of the payout control unit 4120. Or output to the CR unit 6. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally, that is, when the retry operation is operating abnormally, the error LED indicator 860b has already displayed. The retry error information stored in the status information storage area of the payout control built-in RAM is “normal” in order to forcibly stop the number “5” for informing that the “retry error” is present. This is forcibly overwritten on the information on which the graphic “-” for informing the effect is displayed. Further, in order to inform the CR unit 6 that the ball can be lent out, the logic of the PRDY signal is HI, that is, the rising state is maintained, and the game ball is output from the output terminal of the predetermined output port of the payout control MPU 4120a. Output to the CR unit 6 through the equal lending device connection terminal plate 869.

  Subsequent to step S806, an error flag initialization process is performed (step S808), and this routine is terminated. In this error flag initialization process, if the error flag status indicates that an error has occurred based on the error flag corresponding to the various error information confirmed in step S802, the error flag is set. initialize. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally is 1, that is, when the retry operation is operating abnormally, the retry error flag RTERR-FLG is set to 0. Set and initialize. At this time, the logic of the PRDY signal described above is held at HI, that is, the rising state is maintained, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a through the gaming ball lending device connection terminal plate 869. .

  As described above, when the retry error flag RTERR-FLG is determined in step S780 in the retry operation monitoring process shown in FIG. 48 and the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH, this internal factor is determined. In response to the occurrence of the error, the retry error flag RTERR-FLG is set to a value of 1 in the process of step S786 of the same process. On the other hand, when the operation switch 860a is operated, this causes an external factor. When this occurs, the retry error flag RTERR-FLG is set to 0 and initialized. The retry error flag RTERR-FLG is operated to clear the RAM when the operation switch 860a is operated to clear the RAM when the power is turned on. Similar to the case where the switch 860a is operated, the initialization is triggered by the occurrence of this external factor.

[13-12. Exchange of various signals with CR unit]
Next, the CR communication process of step S554 in the payout control unit main process of the payout control part power-on process of FIG. 37 will be described using a timing chart. In this CR communication process, various signals are exchanged between the payout control board 4110 and the CR unit 6 shown in FIG. First, signal processing at the time of payout operation by ball lending will be described, and subsequently input signal confirmation processing from the CR unit 6 will be described. Here, the number of game balls of 200 yen as the amount (in this embodiment, 50 balls, and the payout operation of 25 balls of 100 yen as the amount is performed twice) is used as the number of rented balls. The case of paying out to the upper plate 301 and the lower plate 302 shown in FIG. 7 will be described. The BRQ signal, the BRDY signal, and the CR connection signal from the CR unit 6 are read out from the input information storage area of the payout control built-in RAM and stored in the read input information. Confirms the logical state of the BRQ signal, the BRDY signal, and the CR connection signal from the input information every 2 ms that is the interrupt timer period.

[13-12-1. Signal processing during payout by ball lending]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 reads out the PRDY signal output setting information from the CR communication information storage area of the payout control built-in RAM, and the read PRDY signal output setting information pays out a rental ball. When the logic state of the PRDY signal that indicates that the payout operation is possible is set, as shown in FIG. 51 (d), the payout operation for paying out the rental ball is possible. In order to transmit the signal, the logic of the PRDY signal is set to HI, that is, raised and held, and output from the output terminal of the predetermined output port of the payout control unit MPU4120a of the payout control unit 4120. It outputs to CR unit 6 via board 869 (timing H0). In this state, for example, when the player pushes the ball rental button 361 of the ball rental unit 360 shown in FIG. 2, the ball rental switch 365b is switched on (turned on). The operation signal is input as TDS shown in FIG. 13 from the frequency display board 365 to the CR unit 6 via the game ball lending device connection terminal board 869. Since the CR unit 6 to which this TDS is inputted pays out the number of game balls of 200 yen as the amount of money to the upper plate 301 or the lower plate 302 as the number of lent balls, as shown in FIG. The ball request signal BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU 4120a) via the gaming ball lending device connection terminal plate 869, and the signal is raised and held (timing H1). . This BRDY is input as a BRDY signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 51 (b), the payout control MPU 4120a to which the BRDY signal is input is set to a rental request monitoring time HA (in this embodiment, 20 milliseconds (ms) to 58 ms from the timing H1. ) Elapses from the CR unit 6 through the lending device connection terminal plate 869 such as a game ball, and the predetermined number of balls (in this embodiment, 25 balls, and 100 yen as a monetary amount). It is monitored whether or not BRQ, which is a single payout operation start request signal for paying out the payout), rises.

  The CR unit 6 pays out the number of game balls of 100 yen out of the number of game balls of 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the number of rented balls. ), The BRQ is output from the CR unit 6 to the CR unit 6 via the lending device connection terminal plate 869 such as a game ball until the rental request monitoring time HA elapses from the timing H1, and the signal is Start up and hold (timing H2). This BRQ is input as a BRQ signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 51C, the payout control MPU 4120a, when the BRQ signal rises from the timing H1 until the lending request monitoring time HA elapses, from the timing H2 to the BRQ request acknowledgment ACK monitoring time HB (in this embodiment, Is set to 20 ms ± 1 ms), the payout control MPU 4120a holds the logic of the EXS signal HI, that is, keeps the raised state, in order to notify that one payout operation has started. Is output from the output terminal of the predetermined output port and output to the CR unit 6 as EXS via the lending device connection terminal plate 869 such as a game ball (timing H3).

  As shown in FIG. 51 (b), the CR unit 6 to which this EXS has been input has a lending instruction monitoring time HC (in the present embodiment, set to 20 ms to 58 ms) from the timing H3. The BRQ that has been started up and held from timing H2 is output from the CR unit 6 to the payout control board 4110 via the gaming ball lending device connection terminal plate 869, and the signal is lowered and held (timing H4).

  As shown in FIG. 51C, the payout control MPU 4120a performs one payout operation until the payout monitoring time HD (in this embodiment, the ball payout time is set) from the timing H4. Then, only the predetermined number of rented balls, that is, the number of game balls for 100 yen is paid out to the upper plate 301 and the lower plate 302 as the number of lent balls. When the payout monitoring time HD elapses, the EXS signal that has been raised and held from the timing H3 is output from the output terminal of a predetermined output port of the payout control MPU 4120a while keeping its logic at LOW, that is, in the lowered state. , EXS is output to the CR unit 6 via the gaming ball rental device connecting terminal plate 869 (timing H5).

  Since the CR unit 6 pays out the remaining number of game balls of 100 yen out of the number of game balls of 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the rented number, FIG. ), The BRQ is transferred from the CR unit 6 to the lending device connection terminal board such as a game ball until the next request confirmation timing HE (in this embodiment, the maximum is set to 268 ms) elapses from the timing H5. 869 is output to the payout control board 4110 (payout control MPU 4120a), and the signal is raised and held (timing H6).

  Similarly, when the payout control MPU 4120a pays out the remaining 100 yen of game balls to the upper plate 301 or the lower plate 302 using the method described above, as shown in FIG. 51 (c). The EXS signal that has been raised and held is set to the logic level LOW, that is, held in the lowered state, and is output from the output terminal of the predetermined output port of the payout control MPU 4120a. It outputs to CR unit 6 via board 869 (timing H7).

  As shown in FIG. 51 (a), the CR unit 6 starts from the timing H1 until the CR unit lending completion monitoring time HF (in this embodiment, the maximum setting is 268 ms) elapses from the timing H7. The raised BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU 4120a) via the gaming ball lending device connection terminal plate 869, and the signal is lowered and held (timing H8).

  The above-described lending request monitoring time HA, BRQ request acknowledgment ACK monitoring time HB, lending instruction monitoring time HC, payout monitoring time HD, next request confirmation timing HE, CR unit lending completion monitoring time HF are the payout control shown in FIG. The time is counted in the timer update process in step S552 in the power-on process (payout control part main process).

  The payout control MPU 4120a does not communicate with the CR unit 6 when a ball breakage, ball rounding, counting switch error, retry error, full tank, etc. occurs (the logic of BRDY from the CR unit 6). Is held LOW, that is, held down, as shown in FIG. 51 (d), the PRDY signal raised and held from the timing H1 is set to LOW, that is, in a lowered state. It is held and output from the output terminal of a predetermined output port of the payout control MPU 4120a, and is output as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing H9). On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rising and being held), although not shown, the logic state of the EXS signal is maintained and paid out. It outputs from the output terminal of the predetermined | prescribed output port of control MPU4120a, and outputs to CR unit 6 via the lending apparatus connection terminal board 869, such as game balls, as EXS. “Keep the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logic of the EXS signal is HI. The logical HI is maintained when the EXS signal is held up.

  In this way, the CR unit 6 exchanges various signals with the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, and the payout control MPU 4120a uses the number of game balls for 200 yen as the amount of money as 100. By performing the payout operation of 25 balls for the yen twice, the game balls having the number of lent out balls of 50 are paid out to the upper plate 301 and the lower plate 302. A hall clerk or the like operates a setting unit (not shown) provided on the front side of the CR unit 6, and for example, the number of game balls for 100 yen as the amount of money is used for the upper plate 301 or When set to pay out to the lower plate 302, the payout control MPU 4120a performs a payout operation of 25 balls for 100 yen as a monetary amount, and the number of game balls for 500 yen as a monetary number When set to pay out to the upper plate 301 and the lower plate 302, the payout control MPU 4120a performs the payout operation of 25 balls of 100 yen as the amount of money five times, and sets the number of game balls of 1000 yen as the amount of money. When the number of rented balls is set to be paid out to the upper plate 301 or the lower plate 302, the payout control MPU 4120a performs the payout operation of 25 balls for 100 yen as the amount of money 10 times.

[13-12-2. Checking input signal from CR unit]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 is configured such that the CR unit 6 performs BRQ via the CR unit 6 via the lending device connection terminal board 869 such as a game ball even when the lending request monitoring time HA has elapsed. When the signal is not started up or when the above-described lending instruction monitoring time HC elapses, the CR unit 6 connects BRDY to the lending device such as a game ball from the CR unit 6. The CR unit 6 outputs the BRQ from the CR unit 6 to the payout control board 4110 via the terminal board 869, even when the signal has not fallen or when the next request confirmation timing HE described above has elapsed. A ball or other lending device connection terminal board 869 is used to output to the payout control board 4110 and the signal is not started up, or as described above. Even after the R unit lending completion monitoring time HF elapses, the CR unit 6 outputs BRDY to the payout control board 4110 from the CR unit 6 through the gaming ball lending device connection terminal plate 869, and the signal is lowered. If not, the above-described PRDY and EXS are used to check whether BRQ and BRDY are normal. Specifically, when the payout control MPU 4120a determines that BRQ and BRDY are not normal (timing J0) as shown in FIGS. 51 (e) and 51 (f), a predetermined period JA (in this embodiment) , 200 ms ± 1 ms), the logic of the PRDY signal is set to LOW, that is, the state of being lowered is held and output from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 Then, PRDY is output to the CR unit 6 through the gaming ball lending device connection terminal plate 869, and the logic of the EXS signal is set to LOW, that is, the state of being lowered is held and the predetermined output port of the payout control MPU 4120a Is output to the CR unit 6 through the rental device connection terminal plate 869 such as a game ball. To force (timing J1).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held down and held from the timing J1 after the elapse of a predetermined period JB (in this embodiment, 200 ms ± 1 ms) from the timing J1 as the logic HI. In other words, it is held in the raised state, output from the output terminal of a predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J2 ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal raised and held from the timing J2 after the elapse of a predetermined period JC from the timing J2 (in this embodiment, 100 ms ± 1 ms) as its logic LOW. In other words, it is held in a lowered state, outputted from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputted as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J3). ).

  Subsequently, after the elapse of a predetermined period JD (in this embodiment, 100 ms ± 1 ms) from the timing J3, the payout control MPU 4120a sets the logic of the PRDY signal held down from the timing J3 as HI. In other words, it is held in the raised state, output from the output terminal of the predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J4). ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal raised and held from the timing J4 after the elapse of a predetermined period JE (in this embodiment, 100 ms ± 1 ms) from the timing J4 as its logic LOW. In other words, it is held in a lowered state, outputted from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputted as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J5). ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held down and held from the timing J5 after the elapse of a predetermined period JF from the timing J5 (in this embodiment, 10000 ms ± 1 ms) as the logic HI. In other words, it is held in the raised state, output from the output terminal of a predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J6). ).

  The above-described predetermined period JA to predetermined period JF are timed in the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG.

[14. Various control processing of peripheral control board]
Next, various processes of the peripheral control board 4140 that receive various commands from the main control board 4100 (main control MPU 4100a) shown in FIG. 11 will be described with reference to FIGS. FIG. 52 is a flowchart showing an example of the peripheral control unit power-on process, FIG. 53 is a flowchart showing an example of the peripheral control unit V blank interrupt process, and FIG. 54 shows an example of the peripheral control unit 1 ms timer interrupt process. 55 is a flowchart illustrating an example of a peripheral control unit command reception interrupt process, and FIG. 56 is a flowchart illustrating an example of a peripheral control unit power failure warning signal interrupt process.

  As shown in FIG. 14, the peripheral control board 4140 includes a peripheral control unit 4150 and a liquid crystal and sound control unit 4160. Here, various control processes of the peripheral control unit 4150 will be described. First, the peripheral control unit power-on process will be described, followed by the peripheral control unit V blank interrupt process, the peripheral control unit 1 ms timer interrupt process, the peripheral control unit command reception interrupt process, and the peripheral control unit power failure warning signal interrupt process. . In the present embodiment, the peripheral control unit power failure warning signal interrupt processing is set as the highest priority as the interrupt processing priority, followed by the peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception interrupt processing, and peripheral control unit The order of V blank interrupt processing is set.

[14-1. Various control processes of peripheral control unit]
[14-1-1. Peripheral control unit power-on processing]
First, the peripheral control unit power-on process will be described with reference to FIG. When the pachinko gaming machine 1 is powered on, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 performs the peripheral control unit power-on process as shown in FIG. When the peripheral control unit power-on process is started, the peripheral control MPU 4150a performs an initial setting process (step S1000). This initial setting process includes a process for initializing the peripheral control MPU 4150a itself, a hot start / cold start determination process, a process for setting a wait timer after reset, and the like. The peripheral control MPU 4150a first performs a process of initializing itself. The time required for the process of initializing the peripheral control MPU 4150a is on the order of microseconds (μs), and the peripheral control MPU 4150a is initialized in a very short time. be able to. As a result, the peripheral control MPU 4150a is output from the main control board 4100, for example, in the peripheral control unit command reception interrupt processing described later, as shown in FIGS. 29 and 30 when the interrupt permission is set. Various commands such as commands relating to the control of game effects and commands relating to the state of the pachinko gaming machine 1 can be received.

  In the hot start / cold start determination processing, for the peripheral control RAM 4150c shown in FIG. 15, effect backup information (1fr) that is the contents backed up in Bank1 (1fr) and Bank2 (1fr) in the backup first area 4150cb. ) And the production backup information (1 ms), which is the contents backed up in Bank 1 (1 ms) and Bank 2 (1 ms), are compared, and Bank 3 (1 fr) and Bank 4 (1 fr) in the backup second area 4150 cc are compared. The production backup information (1fr), which is the content that is backed up at the same time, is compared, and the production backup information (the content that is backed up in Bank3 (1 ms) and Bank4 (1 ms)) ( ms), and when the compared contents match, the contents stored in Bank1 (1fr) with respect to Bank0 (1fr), which is a normally used storage area of the peripheral control RAM 4150c shown in FIG. The production backup information (1fr) and the production backup information (1ms) stored in Bank1 (1ms) with respect to Bank0 (1ms) are copied back to make a hot start, When the contents do not match (that is, when they do not match), the value 0 is forcibly written to Bank0 (1fr) and Bank0 (1 ms), which are normally used storage areas of the peripheral control RAM 4150c. And cold start.

  In the hot start / cold start determination process, the effect backup information that is backed up in Bank 1 (SRAM) and Bank 2 (SRAM) in the backup first area 4150 db is also obtained for the peripheral control SRAM 4150 d shown in FIG. (SRAM) is compared, and production backup information (SRAM), which is the contents backed up in Bank 3 (SRAM) and Bank 4 (SRAM), in the backup second area 4150 dc is compared. When the compared contents match, the production backup information (SRAM) which is the contents stored in Bank 0 (SRAM) with respect to Bank 0 (SRAM) which is the storage area normally used in the peripheral control SRAM 4150d shown in FIG. ) Is copied back to make a hot start, while when the compared contents do not match (that is, when they do not match), the value is relative to Bank0 (SRAM), which is a storage area normally used by the peripheral control SRAM 4150d. 0 is forcibly written and a cold start is made. Following such a hot start or cold start, the value 0 is forcibly written to the backup unmanaged work area 4150cf of the peripheral control RAM 4150c shown in FIG. The peripheral control MPU 4150a, after performing this initialization setting process, outputs a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 15 and the peripheral control external WDT 4150e shown in FIG. 14, and resets to the peripheral control MPU 4150a. It is made so that it won't be applied.

  Subsequent to step S1000, a current time information acquisition process is performed (step S1002). In this current time information acquisition processing, calendar information specifying the date and time and time information specifying the hour, minute and second are acquired from the RTC built-in RAM 4165aa of the RTC 41654a of the RTC control unit 4165 shown in FIG. In the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. 4, the current calendar information is set in the calendar information storage unit and the current time information is set in the time information storage unit. In the current time information acquisition process, the brightness setting process of the liquid crystal display device is also performed. In the brightness setting process of the liquid crystal display device, the peripheral control MPU 4150a acquires the brightness setting information from the RTC built-in RAM 4165aa of the RTC control unit 4165, and the game board so that the brightness of the LED included in the acquired brightness setting information is obtained. A process of turning on the backlight by adjusting the luminance of the backlight of the side liquid crystal display device 1900 is performed. As described above, the brightness setting information includes brightness adjustment information for adjusting the range of the brightness of the LED, which is the backlight of the game board side liquid crystal display device 1900, from 100% to 70% in increments of 5%, The brightness of the LED which is the backlight of the game board side liquid crystal display device 1900 that has been set is included.

  In the brightness setting process of the liquid crystal display device, specifically, the brightness of the LED included in the brightness setting information stored in the RTC built-in RAM 4165aa of the RTC control unit 4165 is 75%, and the backlight of the game board side liquid crystal display device 1900 is displayed. Is turned on by adjusting the backlight brightness of the game board side liquid crystal display device 1900 based on the brightness adjustment information included in the brightness setting information, and the brightness stored in the RTC built-in RAM 4165aa of the RTC control unit 4165. When the backlight of the game board side liquid crystal display device 1900 is turned on when the luminance of the LED included in the setting information is 80%, the backlight of the game board side liquid crystal display device 1900 is turned on based on the luminance adjustment information included in the luminance setting information. Lights with the brightness adjusted. In this liquid crystal display device luminance setting process, the same correction as the above-described luminance correction program for correcting the luminance of the game board side liquid crystal display device 1900 according to the usage time of the game board side liquid crystal display device 1900 is performed. It is not done at all. This is because the brightness setting process of the liquid crystal display device incorporates a correction program similar to the brightness correction program, so that the brightness of the LED is corrected toward 100% each time the brightness setting process of the liquid crystal display device is executed. This is to prevent it from being done.

  In the present embodiment, the peripheral control MPU 4150a acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a only once when the power is turned on. In addition, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after performing this current time information acquisition processing so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1002, the value 0 is set to the V blank signal detection flag VB-FLG (step S1006). This V blank signal detection flag VB-FLG is a flag for determining whether or not to execute a peripheral control unit steady process to be described later, and has a value of 1 when the peripheral control unit steady process is executed. Is set to 0 when not executing. The V blank signal detection flag VB-FLG, which will be described later, is executed when a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is input from the sound source built-in VDP 4160a. The value 1 is set in the part V blank signal interrupt processing. In step S1006, the V blank signal detection flag VB-FLG is initialized once by setting the value 0 to the V blank signal detection flag VB-FLG. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after setting the value 0 to the V blank signal detection flag VB-FLG so that the peripheral control MPU 4150a is not reset. Yes.

  Subsequent to step S1006, it is determined whether or not the V blank signal detection flag VB-FLG is 1 (step S1008). When the V blank signal detection flag VB-FLG is not 1 (value 0), the process returns to step S1008 again to repeatedly determine whether or not the V blank signal detection flag VB-FLG is 1. By repeating such a determination, the process waits until the peripheral control unit steady process is executed. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after determining whether or not the V blank signal detection flag VB-FLG is 1, and resets to the peripheral control MPU 4150a. It is made so that it doesn't take.

  When the V blank signal detection flag VB-FLG has a value of 1 in step S1008, that is, when the peripheral control unit steady process is executed, a value 1 is first set to the steady process flag SP-FLG (step S1009). The steady processing flag SP-FLG is set to a value of 1 when the peripheral control unit steady processing is being executed, and to a value of 0 when the peripheral control unit steady processing is completed.

  Subsequent to step S1009, 1 ms interrupt timer activation processing is performed (step S1010). In this 1 ms interrupt timer starting process, a 1 ms interrupt timer for executing a later-described peripheral control unit 1 ms timer interrupt process is started, and the number of times this 1 ms interrupt timer is started and the peripheral control unit 1 ms timer interrupt process is executed. The value 1 is set in the 1 ms timer interrupt execution count STN for counting the 1 ms timer interrupt execution count STN. This 1 ms timer interrupt execution count STN is updated by the peripheral control unit 1 ms timer interrupt processing.

  Following step S1010, lamp data output processing is performed (step S1012). In this ramp data output process, DMA serial continuous transmission to the lamp drive board 4170 shown in FIG. 14 is performed. Here, serial transmission of the serial I / O port for the lamp driving board is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial I / O port continuous transmission for the lamp driving board is started, the lamp driving board side transmission data storage area 4150caa of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 15 is shown in FIG. The game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided in the game board 4 is created by a lamp data creation process described later. Is set.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 15 designates the transmission of the lamp drive board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores the lamp drive board side transmission data storage area 4150caa. The first 1 byte of the game board side light emission data SL-DAT stored at the top address is transferred to the serial I / O port for the lamp driving board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the send buffer register. As a result, the serial I / O port for the lamp driving board transfers the written data in the transmission buffer register to the transmission shift register, and synchronizes with the light emission clock signal SL-CLK on the game board side to 1 byte of the transmission shift register. The data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac is triggered by a transmission interrupt request for the lamp drive board serial I / O port (in this embodiment, in the transmission buffer register of the lamp drive board serial I / O port). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side light emission data SL-DAT stored in the lamp drive board side transmission data storage area 4150caa is byte by byte via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transmit serial I / O port for lamp drive board By transferring and writing to the buffer register, the lamp drive board serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the light emission clock signal SL-CLK on the game board side. Transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed through the serial I / O port for the lamp driving board.

  In the ramp data output process, a DMA serial continuous transmission process to the frame decoration drive amplifier board 194 shown in FIG. 14 is performed. Also here, the frame I / O port LED serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a. When this frame decoration drive amplifier board LED serial I / O port continuous transmission is started, the frame decoration drive amplifier board side LED transmission data storage area of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. In 4150cab, door side light emission data STL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided on the door frame 5 is created by a lamp data creation process described later. Is set.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates the transmission of the frame decoration drive amplifier board LED serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and transmits the frame decoration drive amplifier board side LED transmission data storage area. The first one byte of the door-side light emission data STL-DAT stored at the head address of 4150cab is serialized for the frame decoration drive amplifier board LED via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the I / O port transmit buffer register. As a result, the frame decoration drive amplifier board LED serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door side light emission clock signal STL-CLK. Transmission of 1-byte data is started bit by bit.

  The peripheral control DMA controller 4150ac is triggered every time a transmission interrupt request for the serial I / O port for frame decoration drive amplifier board LED is generated (in this embodiment, the serial I / O for frame decoration drive amplifier board LED). 1 byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), Peripheral control CPU core 4150aa Is not using the bus, the remaining door side light emission data STL-DAT stored in the frame decoration drive amplifier board side LED transmission data storage area 4150cab is stored byte by byte in the external bus 4150h and the peripheral control bus controller 4150ad. And frame decoration via peripheral bus 4150ai By transferring and writing to the transmission buffer register of the serial amplifier I / O port for the dynamic amplifier board LED, the serial I / O port for frame decoration drive amplifier board LED writes the data of the written transmission buffer register to the transmission shift register. Transfer and start transmitting 1-byte data of the transmission shift register bit by bit in synchronization with the door side light emission clock signal STL-CLK, and perform continuous transmission by the serial I / O port for frame decoration drive amplifier board LED Yes.

  Following step S1012, operation unit monitoring processing is performed (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in the peripheral control unit 1 ms timer interruption process described later, the dial operation unit 401 is based on detection signals from various detection switches provided in the operation unit 400 shown in FIG. Rotation (rotation direction) and various information obtained by operating the pressing operation unit 405 (for example, rotation of the dial operation unit 401 created based on detection signals from various detection switches provided in the operation unit 400 (rotation direction) ) History information, operation history information of the pressing operation unit 405, etc.) Based on the operation unit information acquisition storage area 4150cai of the peripheral control RAM 4150c shown in FIG. Monitor the presence or absence of operation of the unit 405, Appropriately determined whether to reflect the state of operation of the pressure operation unit 405 to the game effects.

  Subsequent to step S1014, display data output processing is performed (step S1016). In this display data output processing, the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP 4160a in the display data creation processing described later is transmitted from the channels CH1 and CH2 shown in FIG. The data is output to the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. Thereby, various screens are drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470. In the display data output process, when the drawing exceeding the drawing capability of the sound source built-in VDP 4160a is performed, the generated drawing data for one screen (one frame) is used as the game board side liquid crystal display device 1900 and the upper plate side liquid crystal. The output to the display device 470 is canceled. This can prevent the processing time from being delayed, but although a so-called frame drop occurs, the various decorative boards provided in the game board 4 shown in FIG. 8 by the ramp data output processing in step S1012. A speaker housed in a speaker box 820 provided in the main body frame 3 shown in FIG. 5 by an effect by a plurality of LEDs and a plurality of LEDs of various decorative boards provided in the door frame 5, and a sound data output process described later, and It is a mechanism that can give priority to the synchronization with effects produced by music, sound effects, etc. according to various effects from the speaker 130 provided on the door frame 5 shown in FIG.

  Subsequent to step S1016, sound data output processing is performed (step S1018). In this sound data output processing, the sound data such as music and sound effects set in the sound source built-in VDP 4160a in the sound data creation processing described later is output to the audio data transmission IC 4160c as serialized audio data, or the music and sound effects are output. In addition, the sound data of the notification sound or notification sound is output to the audio data transmission IC 4160c as serialized audio data. When the audio data transmission IC 4160c receives the serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c is directed toward the frame decoration drive amplifier board 194 as differential serial data using the right audio data as a plus signal and a minus signal. At the same time, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as differential serial data having a plus signal and a minus signal. As a result, in addition to the stereo reproduction of music, sound effects, etc. adapted to various effects from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the notification sound and the notification sound Is also played in stereo.

  Subsequent to step S1018, scheduler update processing is performed (step S1020). In this scheduler update process, various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. 15 are updated. For example, in the scheduler update process, among the screen data arranged in time series constituting the screen generation schedule data set in the schedule data storage area 4150cae, what number screen data from the top screen data is stored in the sound source built-in VDP 4160a. The pointer is updated to indicate whether to output.

  In addition, in the scheduler update processing, among the light emission data arranged in time series constituting the light emission mode generation schedule data set in the schedule data storage area 4150cae, the number of the light emission data from the first light emission data is emitted from the various LEDs. The pointer is updated to indicate whether the mode is set.

  In the scheduler update processing, sound data such as music and sound effects, sound data of notification sound and notification sound, which are arranged in time series constituting the sound generation schedule data set in the schedule data storage area 4150cae, are instructed. Of the sound command data, the pointer is updated in order to indicate what number of sound command data from the head sound command data is to be output to the built-in sound source VDP 4160a.

  In the scheduler update process, the drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data set in the schedule data storage area 4150cae is used from the head drive data. The pointer is updated to indicate what number of drive data is to be output. The drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data is a peripheral control unit 1 ms timer interrupt which is repeatedly executed every time a 1 ms timer interrupt described later occurs. It is updated by the motor and solenoid drive process in the process. In the motor and solenoid drive processing that is repeatedly executed each time this 1 ms timer interrupt occurs, an electric drive source such as a motor or solenoid is driven according to the drive data indicated by the pointer, and the next drive specified in time series is performed. The pointer is updated to the data, and the pointer is updated every time its own processing is executed. In other words, the drive data indicated by the pointer updated in the motor and solenoid drive processing is forcibly updated in the scheduler update processing. Even if other drive data is instructed from the drive data that is supposed to be performed, it is forcibly updated to instruct the drive data that should be instructed originally in the scheduler update processing.

  Subsequent to step S1020, received command analysis processing is performed (step S1022). In the received command analysis process, various commands transmitted from the main control board 4100 are received by a peripheral control unit command reception interrupt process described later, and the received various commands are analyzed. Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt processing and stored in the reception command storage area 4150cac of the peripheral control RAM 4150c shown in FIG. The various commands stored in the received command storage area 4150cac are analyzed. The various commands shown in FIG. 29 are classified into various commands classified as related to the special figure 1 synchronized production, various commands classified as related to the special figure 2 synchronous production, various commands classified as related to the jackpot, and power-on. , Various commands categorized in relation to ordinary drawing effect, various commands categorized in relation to ordinary electric role effect, various commands categorized in notification display, and status display shown in FIG. There are various commands, various commands classified as test-related, and various commands classified into others.

  Following step S1022, warning processing is performed (step S1024). In this warning process, when the command analyzed in the received command analysis process in step S1022 includes various commands classified into the notification display shown in FIG. 30, the abnormality display mode for executing various abnormality notifications is set. The set screen generation schedule data, light emission mode generation schedule data, sound generation schedule data, electrical drive source schedule data, and the like, which are set, are the various control data of the peripheral control ROM 4150b or the peripheral control RAM 4150c of the peripheral control unit 4150. The data is extracted from the copy area 4150ce and set to 4150cae in the schedule data storage area of the peripheral control RAM 4150c. In the warning process, when multiple abnormalities occur simultaneously, the abnormality notification is performed in the order of the priority registered in advance, and the abnormality is automatically resolved and the remaining abnormality notifications are automatically transitioned to. It is supposed to be. This allows you to monitor multiple anomalies at the same time without losing the information that an anomaly has occurred due to the occurrence of another anomaly after the occurrence of the anomaly but before resolving the anomaly Can do.

  Following step S1024, RCT acquisition information update processing is performed (step S1026). In this RTC acquisition information update process, the calendar information stored in the calendar information storage unit acquired in the current time information acquisition process in step S1002 and set in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. The time information stored in the time information storage unit is updated. By this RCT acquisition information update process, the hour, minute and second as time information stored in the time information storage unit are updated, and the year and month as calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

  Subsequent to step S1026, lamp data creation processing is performed (step S1028). In this lamp data creation process, the pointer is updated in the scheduler update process in step S1020, and based on the light emission data pointed to by the pointer among the light emission data arranged in time series constituting the light emission mode generation schedule data. The game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided in the game board 4 shown in FIG. It is created by extracting from various control data copy areas 4150ce of the peripheral control ROM 4150b or peripheral control RAM 4150c of 4150, set in the lamp drive board side transmission data storage area 4150caa of the peripheral control RAM 4150c shown in FIG. Lighting on various LEDs on various decorative boards The door side light emission data STL-DAT for outputting the signal, the flashing signal or the gradation lighting signal is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and created. It is set in the frame decoration drive amplifier board side LED transmission data storage area 4150cab of the peripheral control RAM 4150c shown in FIG.

  Subsequent to step S1028, display data creation processing is performed (step S1030). In this display data creation process, the pointer is updated in the scheduler update process in step S1020, and the screen data indicated by the pointer among the screen data arranged in time series constituting the screen generation schedule data is displayed as the peripheral control unit. The data is extracted from the various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c of 4150 and output to the VDP 4160a with built-in sound source. When the screen data is input from the peripheral control MPU 4150a, the built-in sound source VDP 4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and the game board side liquid crystal display device 1900 and drawing data for one screen (one frame) to be displayed on the upper side liquid crystal display device 470 are generated on the built-in VRAM.

  Subsequent to step S1030, sound data creation processing is performed (step S1032). In the sound data creation processing, the pointer is updated in the scheduler update processing in step S1020, and the sound command data pointed to by the pointer among the sound command data arranged in time series constituting the sound generation schedule data, Extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the VDP 4160a with built-in sound source. When the sound command data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b and controls the sound source by controlling the sound source. In addition to incorporating sound data such as music and sound effects according to the track number defined in the data, an output channel to be used is set according to the output channel number.

  In the sound data creation process, every time this sound data creation process is performed (that is, every time the peripheral control unit steady process is performed), the peripheral control A / D converter 4150ak shown in FIG. The voltage divided by the resistance value at the rotation position of the knob portion of 4140a is converted into a value of 1024 steps from 0 to 1023. In this embodiment, the value of 1024 steps is divided into seven and managed as substrate volumes 0 to 6, and the sound volume is set to the substrate volume 0, the maximum volume is set to the substrate volume 6, and the substrate volume 0 to the substrate volume are set. Each volume is set to increase toward the volume 6. By controlling the liquid crystal and the built-in sound source VDP 4160a of the sound control unit 4160 so that the volume is set to the substrate volume 0 to 6, audio data is obtained as audio data obtained by serializing the sound data in the sound data output process of step S1018 described above. By outputting to the transmission IC 4160 c, music and sound effects flow from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5.

  In addition, the notification sound and the notification sound flow without depending on the volume adjustment based on the turning operation of the knob part, and the sound volume of the liquid crystal and sound control unit 4160 can be set by the program from the mute level to the maximum volume level. The built-in VDP 4160a can be controlled and adjusted. The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. For example, even when a store clerk or the like of the hall rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the hall and the door frame 5 are accommodated in the speaker box 820 provided in the main body frame 3. Although the production sound such as music and sound effects flowing from the provided speaker 130 is reduced, when the malfunction occurs in the pachinko gaming machine 1 or when the player is cheating, the volume is high (in this embodiment, The notification sound set to (maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, the screen unfolded on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 can be rendered more powerful or advantageous to the player. It is also possible to notify that there is a high possibility that the game state will be entered.

  Subsequent to step S1032, backup processing is performed (step S1034). In this backup process, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. 15 are copied to the backup first area 4150cb and the backup second area 4150cc for backup. At the same time, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control SRAM 4150d are copied to the backup first area 4150db and the backup second area 4150dc for backup.

  Specifically, in the backup process, the peripheral control RAM 4150c is backed up every frame (1 frame) in the backup target work area 4150ca shown in FIG. 15, that is, every time the peripheral control unit steady process is executed. Included in Bank 0 (1fr), lamp driving board side transmission data storage area 4150caa, frame decoration driving amplifier board side LED transmission data storage area 4150cab, reception command storage area 4150cac, RTC information acquisition storage area 4150cad, and The production information (1fr), which is the content stored in the schedule data storage area 4150cae, is used as production backup information (1fr), and Bank1 (1fr) and Bank2 (1f) of the backup first area 4150cb. Peripheral control DMA controller 4150ac in) is copied at high speed, and backup Bank3 second area 4150cc (1fr) and peripheral control DMA controller 4150ac to Bank4 (1FR) is copied at high speed.

  The high-speed copy of the contents stored in Bank 0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1fr) is designated to be copied to Bank1 (1fr) in the backup first area 4150cb, and the content stored in the first address of Bank0 (1fr) is changed to the end address of Bank0 (1fr) The stored contents are all copied in sequence starting from the first address of Bank 1 (1fr) in the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte), and the peripheral control MPU core 4150aa performs peripheral control D The content stored in Bank0 (1fr) is designated as the request factor of the A controller 4150ac, the copy to Bank2 (1fr) of the backup first area 4150cb is designated, and the content stored in the first address of Bank0 (1fr) is used as Bank0 The contents stored at the end address of (1fr) are all copied in order from the start address of Bank2 (1fr) in the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the content stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150cc to Bank3 (1fr), and Bank0 (1fr) ) To the content stored at the end address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), the first address of Bank3 (1fr) in the backup second area 4150cc continuously by a predetermined byte (for example, 1 byte) The peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, and specifies that the backup second area 4150cc is copied to Bank4 (1fr). Shi From the content stored at the beginning address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), bank 4 (1fr) in the backup second area 4150cc is continuously provided by a predetermined number of bytes (for example, 1 byte). Copy everything starting from the first address.

  In the backup process, the peripheral control SRAM 4150d is a backup target every frame (1 frame) in the backup target work area 4150da shown in FIG. 15, that is, every time the peripheral control unit steady process is executed. The peripheral control DMA controller 4150ac operates at high speed in the bank 1 (SRAM) and the bank 2 (SRAM) of the backup first area 4150db by using the production information (SRAM) stored in the Bank 0 (SRAM) as production backup information (SRAM). The peripheral control DMA controller 4150ac copies the data to the bank 3 (SRAM) and the bank 4 (SRAM) in the backup second area 4150dc at high speed.

  The high-speed copy of the contents stored in Bank 0 (SRAM) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (SRAM) is designated to be copied to Bank1 (SRAM) in backup first area 4150db, and the content stored at the beginning address of Bank0 (SRAM) is changed to the end address of Bank0 (SRAM). The stored contents are all copied in sequence starting from the first address of Bank 1 (SRAM) in the backup first area 4150db in order of predetermined bytes (for example, 1 byte), and the peripheral control MPU core 4150aa The content stored in Bank0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac, the copy to the Bank2 (SRAM) of the backup first area 4150db is designated, and the content stored in the first address of Bank0 (SRAM) To the contents stored at the end address of Bank 0 (SRAM) are copied in order from the start address of Bank 2 (SRAM) in the backup first area 4150 db in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the contents stored in the Bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150dc to the Bank 3 (SRAM), and the Bank 0 (SRAM). ) To the content stored at the end address of Bank0 (SRAM) to the content stored at the end address of Bank0 (SRAM) by a predetermined number of bytes (for example, 1 byte) continuously, the top address of Bank3 (SRAM) in backup second area 4150dc The peripheral control MPU core 4150aa copies the contents stored in the bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac to the bank 4 (SRAM) of the backup second area 4150dc. P2 is specified, and the content stored in the bank 0 (SRAM) start address to the content stored in the bank 0 (SRAM) end address is continuously backed up by a predetermined byte (for example, 1 byte) in a second backup area 4150dc. Are all copied in order from the top address of Bank 4 (SRAM).

  Subsequent to step S1034, WDT clear processing is performed (step S1036). In this WDT clear processing, a clear signal is output to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1036, as the execution of the peripheral control unit steady process is completed, a value of 0 is set in the steady process flag SP-FLG (step S1038), and the process returns again to step S1006, and the value 0 is set in the V blank signal detection flag VB-FLG. Is set and initialized, and the determination in step S1008 is repeated until the value 1 is set to the V blank signal detection flag VB-FLG in the peripheral control unit V blank signal interrupt processing described later. That is, in step S1008, the process waits until a value 1 is set in the V blank signal detection flag VB-FLG. If it is determined in step S1008 that the V blank signal detection flag VB-FLG is 1, the process proceeds from step S1009 to step S1009. The process of S1038 is performed, and the process returns to step S1006 again. As described above, when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value of 1, processing in steps S1009 to S1038 is performed. The processing in steps S1009 to S1038 is referred to as “peripheral control unit steady processing”.

  The peripheral control unit steady process starts with setting the value 1 to the steady processing flag SP-FLG, assuming that the peripheral control unit steady process is being executed in step S1009, and the 1 ms interrupt timer starting process in step S1010. Step S1012, Step S1014,..., And Step S1036. Finally, in Step S1038, the execution of the peripheral control unit steady process is completed, and when the steady processing flag SP-FLG is set to 0, the process is completed. Will be. The peripheral control unit steady process is executed when the V blank signal detection flag VB-FLG is 1 in step S1008. As described above, the V blank signal detection flag VB-FLG is executed when the V blank signal indicating that the screen data from the peripheral control MPU 4150a can be accepted is input from the sound source built-in VDP 4160a. The value 1 is set in the peripheral control unit V blank signal interrupt processing described later. In the present embodiment, since the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is set to approximately 30 fps per second as described above, V The interval at which the blank signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, the peripheral control unit steady process is repeatedly executed about every 33.3 ms.

[14-1-2. Peripheral control unit V blank signal interrupt processing]
Next, a V blank signal indicating that the screen data from the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 can be received is input from the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160. The peripheral control unit V blank signal interrupt processing executed with this as an opportunity will be described. When the peripheral control unit V blank signal interrupt processing is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether the steady processing flag SP-FLG is 0 as shown in FIG. S1045). As described above, the steady processing flag SP-FLG has a value of 1 when the peripheral control unit steady processing in steps S1009 to S1038 in the peripheral control unit power-on processing of FIG. It is set to a value of 0 when execution of the process is completed.

  If the steady process flag SP-FLG is not 0 (value 1) in step S1045, that is, if the peripheral control unit steady process is being executed, this routine is terminated. On the other hand, when the steady processing flag SP-FLG is 0 in step S1045, that is, when the execution of the peripheral control unit steady processing is completed, the value 1 is set to the V blank signal detection flag VB-FLG (step S1050). This routine ends. As described above, the V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady process. When the part steady process is not executed, the value is set to 0.

  In this embodiment, it is determined in step S1045 whether or not the steady processing flag SP-FLG is 0, that is, whether or not the peripheral control unit steady processing has been completed, and the peripheral control unit steady processing has been completed. Sometimes the value 1 is set to the V blank signal detection flag VB-FLG in step S1050. This is because the V blank signal is input and the V blank signal is input when the peripheral control unit steady processing is being executed. When the value 1 is set to the signal detection flag VB-FLG, it is assumed that the peripheral control unit steady process is executed in step S1008 in the peripheral control unit power-on process of FIG. Forcibly canceling in the middle and starting execution of the peripheral control unit steady process from the beginning, so to prevent this, when the peripheral control unit in FIG. 52 is turned on The peripheral control unit V blank signal, which is this routine, indicates that the peripheral control unit steady processing is being executed by setting the value 1 to the steady processing flag SP-FLG in step S1009 in the processing (peripheral control unit steady processing). In addition to notifying the interrupt processing, the peripheral control unit steady state processing is completed by setting the steady processing flag SP-FLG to 0 in step S1038 in the peripheral control unit power-on processing (peripheral control unit steady state processing) of FIG. This is communicated to the peripheral control unit V blank signal interrupt process, which is this routine, so that the steady processing flag SP-FLG is 0 in the determination of step S1045 in the peripheral control unit V blank signal interrupt process, which is this routine. It is determined whether or not there is, that is, whether or not the peripheral control unit steady process has been executed. In other words, this is a measure for the case where the peripheral control unit steady-state processing cannot be completed before the next V blank signal is input and the next V blank signal is input, so-called processing failure.

  As a result, in the current peripheral control unit steady process, if the process cannot be completed in about 33.3 ms and the process is dropped, the next determination is made in step S1008 in the peripheral control unit power-on process of FIG. It is in a state of waiting until the V blank signal is input. That is, the time required to execute the current peripheral control unit steady process that has been dropped is about 66.6 ms. Normally, a peripheral control unit 1 ms timer interrupt process, which will be described later, is repeatedly executed every time a 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 in the peripheral control unit power-on process (peripheral control unit steady process) in FIG. Is executed only 32 times for one peripheral control unit steady process. However, if there is a current peripheral control unit steady process that has been dropped as described above, the peripheral control unit 1 ms timer interrupt process is not performed 64 times. No, it is executed only 32 times. In other words, even if the peripheral control unit steady process has failed, the consistency between the presentation progress state by the peripheral control unit steady process and the presentation progress state by the peripheral control unit 1 ms timer interrupt process, which is timer interrupt control, is consistent. It is designed not to collapse. Therefore, even if the peripheral control unit steady process is lost, it is possible to reliably match the progress state of the performance.

[14-1-3. Peripheral control unit 1ms timer interrupt processing]
Next, the peripheral control unit 1 ms timer interrupt process that is repeatedly executed every time the 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 52 will be described. . When the peripheral control unit 1 ms timer interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 determines whether the 1 ms timer interrupt execution count STN is smaller than 33 times as shown in FIG. Is determined (step S1100). As described above, this 1 ms timer interrupt execution count STN is determined by this routine when the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process of step S1010 in the peripheral control part steady process of the peripheral control part power-on process of FIG. It is a counter that counts the number of times a peripheral control unit 1 ms timer interrupt process is executed. In the present embodiment, since the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 is set to approximately 30 fps per second as described above, V The interval at which the blank signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, since the peripheral control unit steady process is repeatedly executed about every 33.3 ms, after starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process, the next peripheral control unit steady process is performed. The peripheral control unit 1 ms timer interrupt process is executed only 32 times before. Specifically, when the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady process, the first 1 ms timer interrupt is generated first, then the second,... Will occur.

  When the number of 1 ms timer interrupt executions STN is not smaller than 33 in step S1100, that is, when the 33rd 1 ms timer interrupt is generated and the peripheral control unit 1 ms timer interrupt processing is started, this routine is terminated as it is. In the present embodiment, when the 33rd 1 ms timer interrupt occurs accidentally before the next generation of the V blank signal, in the present embodiment, the peripheral control unit 1 ms timer interrupt process is the peripheral control unit V as the priority of interrupt processing. Although set higher than the blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, the V blank signal is a signal that governs the entire system of the peripheral control board 4140. In order to execute the peripheral control unit V blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. Then, after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control unit 1 ms timer interrupt process is newly started by the first 1 ms timer interrupt generation. ing.

  On the other hand, when the 1 ms timer interrupt execution count STN is smaller than 33 in step S1100, the value 1 is added to the 1 ms timer interrupt execution count STN (increment, step S1102). By adding 1 to this 1 ms timer interrupt execution count STN, the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process of step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. The number of times that the peripheral control unit 1 ms timer interrupt process, which is this routine, is executed is increased by one.

  Subsequent to step S1102, motor and solenoid drive processing is performed (step S1104). In this motor and solenoid drive processing, the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 15 is arranged in time series. According to the drive data indicated by the pointer among the drive data of the electrical drive sources such as the motor and the solenoid, the electrical drive sources such as the motor and the solenoid of the frame decoration drive amplifier board 194 and the motor drive board 4180 shown in FIG. And the pointer is updated to the next drive data defined in time series, and the pointer is updated each time the motor and solenoid drive processing is executed.

  Specifically, in the motor and solenoid drive processing, DMA serial continuous transmission processing to the frame decoration drive amplifier board 194 is performed. Here, the frame I / O port motor serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When this frame decoration drive amplifier board motor serial I / O port continuous transmission starts, first, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c is stored. A drive signal to the dial drive motor 414 of the operation unit 400 shown in FIG. 7 based on drive data indicated by a pointer among drive data of electric drive sources such as motors and solenoids arranged in time series. 15 is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c shown in FIG. Frame decoration It is set to send a dynamic amplifier board-side motor data storage area 4150Caf. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the frame decoration drive amplifier board motor serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores frame decoration drive amplifier board side motor transmission data. Frame decoration drive amplifier board motor via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai with the first byte of the door side motor drive data STM-DAT stored in the head address of the area 4150caf Transfer and write to the transmission buffer register of the serial I / O port. As a result, the frame decoration drive amplifier board motor serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door side motor drive clock signal STM-CLK. The 1-byte data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac is triggered every time a transmission interrupt request for the frame decoration drive amplifier board motor serial I / O port is generated (in this embodiment, the frame decoration drive amplifier board motor serial I / O 1 byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), Peripheral control CPU core 4150aa When the bus does not use the bus, the remaining door side motor drive data STM-DAT stored in the frame decoration drive amplifier board side motor transmission data storage area 4150caf is stored byte by byte, external bus 4150h, peripheral control bus controller 4150ad, and via peripheral bus 4150ai, By transferring and writing to the transmission buffer register of the decorative drive amplifier board motor serial I / O port, the frame decoration drive amplifier board motor serial I / O port transmits the data of the written transmission buffer register to the transmission shift register. 1 byte data of the transmission shift register is started bit by bit in synchronization with the door side motor drive clock signal STM-CLK, and the frame decoration drive amplifier board motor serial I / O port continuously transmits. Is going.

  In the motor and solenoid drive processing, DMA serial continuous transmission processing to the motor drive board 4180 is performed. Also here, serial transmission of the motor drive board serial I / O port is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial I / O port continuous transmission for the motor drive board is started, first, when configuring the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c attached externally A motor for moving various movable bodies provided in the game board 4 shown in FIG. 8 based on drive data indicated by a pointer among drive data of electric drive sources such as motors and solenoids arranged in series. The game board side motor drive data SM-DAT for outputting the drive signal to the solenoid and the solenoid is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and created. Peripheral control RAM 415 shown in FIG. Set to the motor drive board side transmission data storage area 4150cag of c. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the motor drive board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores it in the head address of the motor drive board side transmission data storage area 4150cag. The first 1 byte of the game board side motor drive data SM-DAT thus obtained is transmitted to the serial I / O port for the motor drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to register. As a result, the serial I / O port for motor drive board transfers the written data of the transmission buffer register to the transmission shift register, and 1 of the transmission shift register is synchronized with the game board side motor drive clock signal SM-CLK. Start transmitting byte data bit by bit.

  The peripheral control DMA controller 4150ac is triggered by the transmission interrupt request for the motor drive board serial I / O port (in this embodiment, in the transmission buffer register of the motor drive board serial I / O port). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150cag is transferred byte by byte via the external bus 4150h, peripheral control bus controller 4150ad, and peripheral bus 4150ai. , Serial I / O port for motor drive board By transferring and writing to the transmission buffer register, the motor drive board serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and the game board side motor drive clock signal SM-CLK and Synchronously, transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed by the serial I / O port for the motor drive board.

  Following step S1104, movable body information acquisition processing is performed (step S1106). In this movable body information acquisition process, it is determined whether or not detection signals from various detection switches provided on the game board 4 are input, thereby history information (for example, original position history information) of detection signals from the various detection switches. , The movable position history information, etc.) are created and set in the movable body information acquisition storage area 4150cah of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. From the history information of the detection signals from the various detection switches set in the movable body information acquisition storage area 4150cah, the original positions and the movable positions of the various movable bodies provided on the game board 4 can be acquired.

  Subsequent to step S1106, an operation unit information acquisition process is performed (step S1108). In this operation unit information acquisition process, it is determined whether or not detection signals from various detection switches provided in the operation unit 400 are input, whereby history information of detection signals from various detection switches (for example, a dial operation unit) Rotation (rotation direction) history information 401, operation history information of the pressing operation unit 405, etc.) is created, and the operation unit information acquisition storage area of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. Set to 4150cai. The rotation direction of the dial operation unit 401 and the presence / absence of the operation of the pressing operation unit 405 can be acquired from the history information of detection signals from various detection switches set in the operation unit information acquisition storage area 4150cai.

  Subsequent to step S1108, backup processing is performed (step S1110), and this routine is terminated. In this backup process, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. 15 are copied to the backup first area 4150cb and the backup second area 4150cc for backup. At the same time, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control SRAM 4150d are copied to the backup first area 4150db and the backup second area 4150dc for backup.

  Specifically, in the backup process, the peripheral control RAM 4150c executes the peripheral control unit 1ms timer interrupt process, which is this routine, every time the 1ms interrupt timer is generated in the backup target work area 4150ca shown in FIG. Each time, the frame decoration drive amplifier board-side motor transmission data storage area 4150caf, the motor drive board-side transmission data storage area 4150cag, and the movable body information acquisition storage area 4150cah included in Bank0 (1 ms) to be backed up. The production information (1 ms), which is the content stored in the operation unit information acquisition storage area 4150cai, is used as production backup information (1 ms), and Bank 1 (1 ms) and Bank 2 (1) in the backup first area 4150 cb Peripheral control DMA controller 4150ac in s) is copied at high speed, and backup Bank3 second area 4150cc (1ms) and peripheral control DMA controller 4150ac to Bank4 (1 ms) is copied at high speed.

  Briefly describing the high-speed copying of the contents stored in Bank 0 (1 ms) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1 ms) is designated to be copied to Bank1 (1 ms) in backup first area 4150cb, and the content stored at the beginning address of Bank0 (1 ms) is changed to the end address of Bank0 (1 ms). The stored contents are all copied in sequence starting from the first address of Bank 1 (1 ms) in the backup first area 4150cb in succession to a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa performs peripheral control D. The content stored in Bank 0 (1 ms) as the request factor of the A controller 4150ac is designated to be copied to Bank 2 (1 ms) in the backup first area 4150cb, and the content stored in the first address of Bank 0 (1 ms) is used as Bank 0 The contents stored at the end address of (1 ms) are all copied in order from the start address of Bank 2 (1 ms) of the backup first area 4150cb in succession by predetermined bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the contents stored in Bank0 (1 ms) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the second backup area 4150cc to Bank3 (1 ms), and Bank0 (1 ms) ) To the content stored at the end address of Bank 0 (1 ms) from the content stored at the head address of) in the backup second area 4150 cc of bank 3 (1 ms) The peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1ms) as the request factor of the peripheral control DMA controller 4150ac, and specifies the copy to Bank4 (1ms) in the backup second area 4150cc. Shi Bank 4 (1 ms) in the backup second area 4150 cc from the content stored at the beginning address of Bank 0 (1 ms) to the content stored at the end address of Bank 0 (1 ms) continuously by a predetermined byte (for example, 1 byte) Copy everything starting from the first address.

  As described above, in the peripheral control unit 1 ms timer interruption process, various processes related to the effects in steps S1104 to S1108 are executed as the progress of the effects within a period of 1 ms. On the other hand, in the peripheral control unit steady process in the peripheral control unit power-on process of FIG. 52, the various processes related to the effects in steps S1012 to S1032 described above are performed as the progress of the effects within a period of about 33.3 ms. doing. In the peripheral control unit 1 ms timer interrupt process, when the 1 ms timer interrupt execution count STN is not smaller than the value 33 in step S1100, that is, when the first 1 ms timer interrupt is generated and the peripheral control unit 1 ms timer interrupt process is started. Since this routine is ended as it is, even if the occurrence of the 33rd 1 ms timer interrupt happens to occur before the next V blank signal, the peripheral control unit by this 33rd 1 ms timer interrupt. The start of the 1 ms timer interrupt process is forcibly canceled, and after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control is newly performed by the first 1 ms timer interrupt. 1ms timer division It is adapted to start the actual processing. That is, the consistency between the progress state of the effect by the peripheral control unit steady process and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process which is the timer interrupt control is not lost. Therefore, it is possible to reliably match the progress of the production.

  Further, as described above, the interval at which the V blank signal is output varies somewhat depending on the liquid crystal sizes of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470, and the peripheral control MPU 4150a and the built-in sound source VDP 4160a are different. Even in the manufacturing lot of the mounted peripheral control board 4140, the interval at which the V blank signal is output may change somewhat. In this embodiment, since the V blank signal is a signal that dominates the entire system of the peripheral control board 4140, if the occurrence of the first 1 ms timer interrupt happens to precede the next generation of the V blank signal, the peripheral control is performed. In order to execute the part V blank interrupt process, the start of the peripheral control part 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. That is, in this embodiment, even if the interval at which the V blank signal is output changes slightly, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. A time shift due to a slight change in the interval at which the V blank signal is output can be absorbed.

[14-1-4. Peripheral control unit command reception interrupt processing]
Next, the peripheral control unit command reception interrupt process for receiving various commands from the main control board 4100 will be described. The peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 starts to transmit main commands as serial data when various commands from the main control board 4100 are started. One byte (8 bits) of information is taken into the reception buffer at the board serial I / O port, and when this fetching is completed, an interrupt is generated as a trigger, and peripheral control unit command reception interrupt processing is performed. The main circumference serial data is composed of 3 bytes per packet, the status is assigned as the first byte, the mode is assigned as the second byte, and the status and mode are regarded as numerical values as the third byte and the total The sum value that is calculated is assigned.

  When the peripheral control unit command reception interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether or not the 1-byte reception period timer has timed out as shown in FIG. 55 (step S1200). The 1-byte reception period timer sets a period during which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100.

  When the 1-byte reception period timer has not timed out in step S1200, that is, when it is within a period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100, the peripheral The 1-byte information received from the reception buffer of the main I / O port for the main control board incorporated in the control MPU 4150a is fetched (step S1202), and the value 1 is added to the reception counter SRXC (increment, step S1204). This reception counter SRXC is a counter indicating the number of times the data has been extracted from the reception buffer. When the status, which is the first byte of the main peripheral serial data, is extracted from the reception buffer, the value is 1, and the mode is the second byte of the main peripheral serial data. The value is 2 when extracted from the reception buffer, and the value is 3 when the sum value, which is the third byte of the main serial data, is extracted from the reception buffer. The reception counter SRXC is set to an initial value 0 when the power is turned on.

  Subsequent to step S1204, it is determined whether or not the reception counter SRXC has a value of 3, that is, whether or not the sum value that is the third byte of the main peripheral serial data has been extracted from the reception buffer (step S1206). In this determination, the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data, and the sum value that is the third byte of the main peripheral serial data are sequentially received from the reception buffer. It is determined whether or not it has been taken out.

  When the reception counter SRXC is not the value 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is still the second byte of the main peripheral serial data, and the third byte of the main peripheral serial data When the sum values are not sequentially taken out from the reception buffer, the 1-byte reception period timer is set (step S1208), and this routine is terminated. By setting the 1-byte reception period timer in step S1208, the mode that is the second byte of the main circumference serial data or the period during which the sum value that is the third byte of the main circumference serial data can be received is set.

  On the other hand, when the reception counter SRXC has a value of 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data, and the main peripheral serial data 3 When the sum value which is the byte is taken out from the reception buffer in order, the initial value 0 is set in the reception counter SRXC (step S1210), and the sum value is calculated (step S1212). In this calculation, the status that is the first byte of the main circumference serial data and the mode that is the second byte of the main circumference serial data, which have already been extracted from the reception buffer in step S1202, are regarded as numerical values and the sum (sum value). ) Is calculated.

  Subsequent to step S1212, it is determined whether or not the sum value, which is the third byte of the main serial data already extracted from the reception buffer in step S1202, matches the sum value calculated in step S1212 (step S1212). S1214). The sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 is the sum value allocated as the third byte of the main circumference serial data from the main circumference serial data from the main control board 4100. Therefore, it should match the sum value calculated in step S1212. However, the pachinko gaming machine 1 is supplied with game balls from the pachinko island facility, and when the game balls rub against each other and are charged, electrostatic discharge is generated to generate noise, so the pachinko gaming machine 1 is affected by noise. The environment is susceptible. Therefore, in this embodiment, the peripheral controller 4150 side regards the status assigned as the first byte of the received main circumference serial data and the mode assigned as the second byte of the main circumference serial data as numerical values. The sum (sum value) is calculated, and the calculated sum value matches the sum value allocated as the third byte of the main circumference serial data among the main circumference serial data from the main control board 4100. It is determined whether or not. As a result, the peripheral control MPU 4150a determines whether or not the main peripheral serial data is changed to the main peripheral serial data different from the normal due to the influence of noise between the main control board 4100 and the peripheral control board 4140. be able to.

  In step S1214, if the sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 matches the sum value calculated in step S1212, the received main circumference serial data is received. 15 shows the status allocated as the first byte and the mode allocated as the second byte of the main peripheral serial data, as shown in FIG. (Step S1216), and this routine is terminated. The reception command storage area 4150cac is used as a ring buffer, and the status allocated as the first byte of the main circumference serial data and the mode allocated as the second byte of the main circumference serial data are: It is stored in the peripheral control unit reception ring buffer of 4150cac. This "peripheral control unit reception ring buffer" is a buffer that is used so that the end and the top of the buffer are connected. Data is sequentially stored from the beginning of the buffer, and when it reaches the end of the buffer, it returns to the beginning. Remember. When storing the peripheral control MPU 4150a in the peripheral control unit reception ring buffer in step S1216, the peripheral control MPU 4150a is allocated as the received status of the main peripheral serial data as the first byte and the main peripheral serial data as the second byte. Are stored in association with each other, and the sum value allocated as the third byte is discarded.

  On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, it exceeds the period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100. Sometimes, or in step S1214, if the sum value that is the third byte of the main peripheral serial data already extracted from the reception buffer in step S1202 and the sum value calculated in step S1212 do not match, this routine is directly executed. finish.

[14-1-5. Peripheral control unit power failure warning signal interrupt processing]
Next, the peripheral control unit power failure warning signal executed when the power failure warning signal (peripheral power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100 shown in FIG. The interrupt process will be described. When the peripheral control unit power failure warning signal interruption process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 14 first activates a 2 microsecond timer (step S1300), and a power failure notification signal (peripheral power failure notification). It is determined whether or not a signal is input (step S1302). If no power failure warning signal (peripheral power failure warning signal) is input in this determination, this routine is terminated as it is.

  On the other hand, when a power failure warning signal is input in step S1302, it is determined whether or not 2 microseconds have elapsed (step S1304). In this determination, it is determined whether or not the timer started in step S1300 has passed 2 microseconds. If it is determined in step S1304 that 2 macroseconds have not elapsed, the process returns to step S1302 to determine whether or not a power failure warning signal has been input. If a signal is input, it is determined again in step S1304 whether 2 microseconds have elapsed. That is, in the determination in step S1304, it is determined whether or not the power failure warning signal is continuously input for 2 microseconds after the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started.

  When the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started in step S1304 and the power failure warning signal is continuously input for 2 microseconds, power saving processing is performed (step S1306). In this power saving process, the backlights of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 470 are sequentially turned off, the motors and solenoids provided in the game board 4 are turned off, and various LEDs are turned off sequentially. By suppressing the power consumption of the entire system of the pachinko gaming machine 1 by the above, stable operation is ensured only for a period of 20 milliseconds, which is the time during which the peripheral control MPU 4150a can operate even when the power of the pachinko gaming machine 1 is cut off. .

  Subsequent to step S1306, command reception standby processing is performed (step S1308). In this command reception standby process, assuming that there are various commands being transmitted by the main control board 4100, the peripheral control MPU 4150a can receive at least a period of 17 milliseconds so that the command being transmitted can be received. It is supposed to wait. When a command is received, the peripheral control unit command reception interrupt process described above is started, and the received command storage area 4150cac (peripheral control unit reception ring buffer of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. ) Stores the received command.

  Subsequent to step S1308, command backup processing is performed (step S1310). In the backup processing of this command, the contents stored in the received command storage area 4150cac included in Bank0 (1fr) in the backup target work area 4150ca shown in FIG. 15 are changed to Bank1 (1fr) and The peripheral control DMA controller 4150ac copies to Bank2 (1fr) at high speed, and the peripheral control DMA controller 4150ac copies to Bank3 (1fr) and Bank4 (1fr) in the backup second area 4150cc at high speed.

  The high-speed copy of the contents stored in the received command storage area 4150cac included in Bank0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. Specify the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as the request factor of the control DMA controller 4150ac, and copy to the received command storage area included in Bank1 (1fr) of the backup first area 4150cb Then, from the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr), the end address of the received command storage area 4150cac included in Bank0 (1fr) is stored. Are copied in order from the start address of the received command storage area included in Bank1 (1fr) of the backup first area 4150cb in succession to a predetermined byte (for example, 1 byte), and the peripheral control MPU core The content stored in the received command storage area 4150cac included in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac is transferred to the received command storage area included in Bank2 (1fr) of the backup first area 4150cb. From the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr) to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr) by designating copy , A predetermined number of bytes (e.g., 1 byte) all copies sequentially from the start address of the received command storage area included in the Bank2 (1FR) of the backup successively by the first area 4150Cb.

  Subsequently, the peripheral control MPU core 4150aa includes the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as a request factor of the peripheral control DMA controller 4150ac in Bank3 (1fr) of the backup second area 4150cc. To the received command storage area 4150cac included in Bank0 (1fr) from the contents stored in the start address of the received command storage area 4150cac included in Bank0 (1fr). All the contents up to the specified contents are copied in order from the start address of the received command storage area included in Bank 3 (1fr) of the backup second area 4150cc in succession by a predetermined byte (for example, 1 byte), and peripheral control is performed. The PU core 4150aa uses the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as a request factor of the peripheral control DMA controller 4150ac, and the received command storage area included in Bank4 (1fr) of the backup second area 4150cc. From the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr) to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr) All the data are copied sequentially from the start address of the received command storage area included in Bank4 (1fr) of the backup second area 4150cc successively by a predetermined byte (for example, 1 byte).

  Subsequent to step S1310, it is determined whether a power failure warning signal (peripheral power failure warning signal) is input (step S1312). If a power failure warning signal is input in this determination, WDT clear processing is performed (step S1314). In this WDT clear process, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 15 and the peripheral control external WDT 4150e shown in FIG. 14 so that the peripheral control MPU 4150a is not reset. .

  On the other hand, when the power failure warning signal is not input in step S1312, or following step S1314, the process returns to step S1312, and it is determined whether the power failure warning signal is input. That is, it is determined indefinitely whether or not a power failure warning signal (peripheral power failure warning signal) is input. By continuing the determination infinitely in this way, when the power failure warning signal (peripheral power failure warning signal) is not input in step S1312, the peripheral control MPU 4150a clears the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e. Cannot be output and the peripheral control MPU 4150a is reset. On the other hand, when a power failure warning signal is input in step S1312, the WDT clear process is performed in step S1314, and the peripheral control MPU 4150a is not reset. If the peripheral control MPU 4150a is reset, the peripheral control unit power-on process shown in FIG. 52 is started again.

  As described above, when the power failure warning signal (peripheral power failure warning signal) continues to be input in the infinite loop as determined in step S1312, the peripheral control is performed immediately before the power failure state is established by executing the WDT clear process in step S1314. The MPU 4150a is not reset. On the other hand, when the input of the power failure warning signal is not continued in the infinite loop and is canceled in the determination in step S1312, the WDT clear process is not executed, so the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e are The output of the clear signal is interrupted. As a result, even if the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started erroneously due to noise or the like and the noise is generated beyond the period of 2 microseconds, the determination of step S1302 is passed. If the input of the power failure warning signal (peripheral power failure warning signal) is canceled without being continued in the infinite loop as determined in S1312, the peripheral control MPU 4150a is reset because the WDT clear process in step S1314 is not executed. Therefore, it is possible to cope with such noise by automatically resetting and returning.

  According to the pachinko gaming machine 1 of the present embodiment described above, the main control board 4100 in FIG. 11 and the payout control board 4110 in FIG. 12 are provided. The main control board 4100 is a start area in which a game ball fired by the hitting ball launcher 650 in FIG. The main control MPU 4100a of FIG. 11 which is a game control microprocessor for controlling the progress of the game based on having entered the upper start port 2101 and the lower start port 2102 is mounted. The payout control board 4110 controls payout of the game ball by the prize ball device 740 in FIG. 5 based on the prize ball commands in FIGS. 28A and 28B which are payout commands from the main control board 4100. The payout control MPU 4120a of FIG. 12, which is a processor, is mounted.

  The main control MPU 4100a, which is a game control microprocessor, includes at least a RAM (main control built-in RAM) built in the main control MPU 4100a. The main control built-in RAM can store information related to the game even after the power is shut off.

  The payout control MPU 4120a, which is a payout control microprocessor, includes at least a RAM (payout control built-in RAM) built in the payout control MPU 4120a. The payout control built-in RAM can store information related to payout even after the power is shut off.

  The pachinko gaming machine 1 of this embodiment further includes an operation switch 860a shown in FIG. If the operation switch 860a is operated within the period in which the determination process of step S16 in the main control side power-on process in FIG. 32 is performed after the power is turned on, the information regarding the game stored in the main control built-in RAM is erased. 19 is output from the main control MPU 4100a, which is a game control microprocessor, and the operation is performed during the period in which the determination process of step S512 in the payout control unit power-on process of FIG. Then, a RAM clear function for outputting the RWMCLR signal of FIG. 24 to the payout control MPU 4120a as a payout control microprocessor as a RAM clear signal for erasing information related to payout stored in the payout control built-in RAM, and power on 32, the main control side power-on process in FIG. When the period of time during which the determination process of step S16 is performed (or the period of time during which the determination process of step S512 in the payout control unit power-on process in FIG. 35 is performed from when the power is turned on) has passed, the prize ball device 740 An error canceling function for outputting the RWMCLR signal of FIG. 24 to the main control MPU 4100a which is the game control microprocessor and outputting it to the payout control MPU 4120a as the error control signal for canceling the error which has occurred with respect to It is something that combines.

  As described above, when the operation switch 860a is operated within the period in which the determination process of step S16 in the main control side power on process of FIG. 32 is performed from when the power is turned on, the game stored in the main control built-in RAM. 19 is output to the main control MPU 4100a, which is a game control microprocessor, and the determination process of step S512 in the payout control unit power-on process of FIG. 35 is performed from power-on. 24, the RAM clear signal for outputting the RWMCLR signal shown in FIG. 24 to the payout control MPU 4120a serving as the payout control microprocessor is output as a RAM clear signal for erasing the payout information stored in the payout control built-in RAM. Functions and processing when the main control side power is turned on in FIG. Is operated after the period during which the determination process in step S16 is performed (or the period during which the determination process in step S512 is performed in the payout control unit power-on process in FIG. 35) from when the power is turned on. An error canceling function for outputting to the payout control MPU 4120a as the payout control microprocessor without outputting the RWMCLR signal of FIG. 24 to the main control MPU4100a as the game control microprocessor as an error clearing signal for canceling the error that has occurred regarding 740 Thus, the pachinko gaming machine 1 can be provided with two different functions, a RAM clear function and an error release function, by an operation with one operation switch 860a. Therefore, a RAM clear function and an error cancel function can be provided while contributing to cost reduction.

[15. Another example]
It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

  For example, in the embodiment described above, the pachinko gaming machine 1 has been described as an example. However, a gaming machine to which the present invention can be applied is not limited to a pachinko gaming machine, and a gaming machine other than a pachinko gaming machine, such as a slot machine or The present invention can also be applied to a fusion game machine in which a pachinko game machine and a slot machine are fused (one that uses a game ball to play a slot game).

  DESCRIPTION OF SYMBOLS 1 ... Pachinko machine (game machine), 2 ... Outer frame, 3 ... Main body frame, 4 ... Game board, 5 ... Door frame, 192 ... Handle relay terminal board, 470 ... Upper plate side liquid crystal display device, 650 ... Launch ball launch Device, 740 ... Prize ball device, 784 ... External terminal board, 851 ... Power supply board, 860a ... Operation switch (operation switch), 860b ... Error LED display, 1100 ... Game area, 1900 ... Game board side liquid crystal display device, 4100 ... main control board (game control board), 4100a ... main control MPU, 4110 ... payout control board (payout control board), 4120 ... payout control section, 4120a ... payout control MPU, 4140 ... peripheral control board, 4150 ... peripheral control section 4160 ... Liquid crystal and sound control unit, 4165 ... RTC control unit, 4170 ... Lamp drive substrate, 4180 ... Motor drive substrate.

Claims (1)

A game control microprocessor is mounted that controls the progress of the game based on the fact that the game ball launched by the ball striking device launches toward the game area defined on the game board and enters the start area provided in the game area. Game control board
A payout control board on which a payout control microprocessor for controlling payout of game balls by the payout device based on a payout command from the game control board is mounted;
A gaming machine comprising
The game control microprocessor is at least
Game control RAM capable of storing game-related information even after power-off
With
The payout control microprocessor is at least:
A payout control RAM capable of storing information relating to payout even after the power is turned off.
With
A RAM clear signal for erasing the information relating to the game stored in the game control RAM and the information relating to the payout stored in the payout control RAM when operated within a predetermined period from when the power is turned on. RAM clear function for outputting to the game control microprocessor and the payout control microprocessor respectively, and to cancel the error generated with respect to the payout device when operated after a predetermined period from the time of power-on. And an error canceling function for outputting the error canceling signal to the payout control microprocessor without outputting the error canceling signal to the game control microprocessor.

Images