JP2015050266A - Substrate processing system, substrate processing method, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate processing system and the like which can execute an operation of processing a common substrate among a plurality of application and development devices.SOLUTION: A first control unit 6 of a first application and development device 1a and a second control unit 6 of a second application and development device 1b generate a transport schedule 73 being a transport path for each substrate W in the devices 1a and 1b, transport of the substrate W is controlled on the basis of the transport schedule, and inter-device transport mechanisms 50a and 50b perform single wafer transport of the substrate W between the devices 1a and 1b. For a substrate W to be subjected to irregular processing, which is to be transported to and processed in both of the devices 1a and 1b by the inter-device transport mechanisms 50a and 50b, the control unit 6 of one of the application and development devices 1a and 1b generates a general transport schedule for the entire transport path across both of the application and development devices 1a and 1b and transmits a partial transport schedule 73b for the other of the application and development devices 1a and 1b, out of the general transport schedule to the control unit 6 of the other.

Description

  The present invention relates to a technique for processing a substrate using a plurality of coating and developing apparatuses.

  In the photoresist process, which is one of the semiconductor manufacturing processes, a resist is applied to the surface of a semiconductor wafer (hereinafter referred to as a wafer), which is a substrate, and the resist is exposed in a predetermined pattern and then developed to form a resist pattern. doing. Such processing is performed using a system in which an exposure apparatus is connected to a coating / developing apparatus for coating and developing resist.

  In this way, since the coating / developing apparatus and the exposure apparatus share a series of processes in cooperation with each other, when trouble occurs in one apparatus, the other apparatus can operate normally. Even so, the utilization rate must be reduced.

  For example, Patent Document 1 discloses an exposure apparatus for two substrate processing apparatuses (corresponding to coating and developing apparatuses) that are arranged adjacent to each other and are connected to an exposure apparatus and perform resist coating and development. The structure which connected between the interface parts which comprise these connection parts with the board | substrate conveyance conveyor is described. When this substrate transport conveyor is used, it is possible to perform resist coating, development processing, and exposure processing on the other substrate processing apparatus or exposure apparatus when trouble occurs on one side of the substrate processing apparatus or exposure apparatus. There is a possibility that the operating rate of the apparatus in which no trouble has occurred can be kept high.

  Here, in the coating and developing apparatus, in addition to the above-described resist coating and developing processes, a number of processing modules for executing various types of processes associated with these processes are mounted. For this reason, the wafer processed in the coating / developing apparatus needs to be carried into each processing module through a complicated transfer path, and various processes must be executed in the correct order. In this respect, in Reference 1, when two substrate processing apparatuses are connected via a substrate transfer conveyor, wafers are placed in an accurate order on a number of processing modules arranged between these substrate processing apparatuses. A technique for conveying is not disclosed.

  Reference 2 also discloses a resist coating processing apparatus (one unit), an exposure processing unit (two units) connected to a post-exposure bake processing unit, development processing along an automatic substrate transfer line such as OHT (Overhead Hoist Transport). Describes a substrate processing system that controls the transfer of substrates to each device while grasping the load of OHT using a computer system (MES: Manufacturing Execution System) that arranges the devices (one unit) and performs overall control between the devices. Has been. However, even in the example described in the cited document 2, a technique for accurately transporting a wafer to each processing module when processing performed in a common coating and developing apparatus is shared by a plurality of coating and developing apparatuses. There is no disclosure.

JP 2006-24643 A: Paragraph 0050, FIG. Japanese Patent No. 4584872: paragraph 0048, FIG.

  The present invention has been made under such circumstances, and the object thereof is common to the operations in which a plurality of coating and developing devices each independently transport and process a substrate and the plurality of coating and developing devices. An object of the present invention is to provide a substrate processing system, a substrate processing method, and a storage medium storing the method, which are capable of carrying out and processing the substrate.

The substrate processing system of the present invention forms a coating film including a resist film on a carrier block into which a carrier containing a plurality of substrates is loaded, and a substrate taken out of the carrier in the carrier block, and performs an exposure process. A first coating and developing apparatus each including a processing block for performing development processing on a subsequent substrate, and an interface block connected to the exposure apparatus for transferring the substrate between the processing block and the exposure apparatus; A second coating and developing device;
The first coating / developing apparatus and the second coating / developing apparatus are respectively provided to create a transport schedule that is a transport path for each substrate in the coating / developing apparatus, and based on the transport schedule, the first A first control unit that performs transport control of the substrate in the coating and developing apparatus; a second control unit that performs transport control of the substrate in the coating and developing apparatus;
An inter-device transport mechanism for transporting a substrate between the first coating and developing device and the second coating and developing device,
Exposure connected to one processing block of the first coating, developing device and second coating, developing device and the other of the first coating, developing device, second coating, developing device. When a carrier containing a to-be-modified processing substrate that is a substrate processed using the apparatus is carried into one of the carrier blocks of the first coating, developing device, second coating, and developing device, Comprehensive transport which is the entire transport path of the substrate straddling between the first coating and developing device and the second coating and developing device by one of the first control unit and the second control unit. A schedule is created, and a partial transport schedule corresponding to a transport schedule in the coating and developing apparatus to which the other control unit belongs is transmitted from one control unit to the other control unit. It is characterized in.

  In the present invention, “when a carrier containing a to-be-processed substrate is loaded into a carrier block, which is a timing for creating a comprehensive conveyance schedule” includes, for example, the following cases. That is, in this example, when the substrate is processed in the first coating / developing apparatus, a problem occurs in the exposure apparatus connected to the first coating / developing apparatus, and the first coating / developing is already performed. When the substrate paid out from the carrier of the carrier block in the apparatus is once collected by the carrier, an overall conveyance schedule is created. In this case, the substrate once collected in the carrier is processed using the processing block in the first coating / developing apparatus, and then the exposure apparatus connected to the second coating / developing apparatus is used. As a result, exposure is performed and an irregularly processed substrate is obtained.

The substrate processing system may have the following configuration.
(A) When the irregular processing substrate is loaded into the coating and developing apparatus to which the other control unit belongs by the inter-device transport mechanism, the other control unit transports the substrate based on the partial transport schedule. Be configured for control.
(B) The one control unit that creates the comprehensive conveyance schedule is a control unit of a coating and developing apparatus to which a carrier block into which a carrier containing the irregularly processed substrate is carried belongs.
(C) After the series of processing ends, the modified processing substrate returns to the carrier in the carrier block in which the carrier containing the modified processing substrate is loaded. Alternatively, after the series of processing is completed, the carrier that stores the modified processing substrate of the first coating, developing device, and second coating, developing device is not carried in the modified processing substrate. Return to the carrier of the coating and developing device.
(D) The anomaly processing performed on the to-be-modified processing substrate is in a state where a defect occurs in the other processing block of the first coating, the developing device, and the second coating, the developing device. A process using one processing block and an exposure apparatus connected to the other coating and developing apparatus.

(E) The inter-device transport mechanism transports the irregularly treated substrate between the interface block of the first coating / developing device and the interface block of the second coating / developing device. Be provided.
(F) When the inter-device transport mechanism that transports the substrate between the interface blocks is a first inter-device transport mechanism, the first coating, the carrier block of the developing device, and the second first coating And a second inter-device transport mechanism for transporting the irregularly processed substrate one by one to the carrier block of the developing device.
(G) The inter-device transport mechanism includes a substrate holding unit that holds the substrate to be processed, a first application of the substrate holding unit, a delivery position of the substrate on the developing device side, a second first application, And a moving mechanism for moving between the substrate transfer position on the developing device side.
(H) The first coating and developing device and the second coating and developing device include a pressure adjusting unit that adjusts the pressure of the space in each coating and developing device to a pressure higher than an external pressure, and the device. A partition wall that partitions a space in which a substrate is transported by the transport mechanism, a space in each coating and developing device, and a shutter that opens and closes an opening provided in the partition wall for loading and unloading the substrate to be processed And providing.

  The present invention provides a substrate on one side of the coating / developing apparatus for the irregularly processed substrate which is transported across the first and second coating and developing apparatuses via the inter-device transport mechanism and processed. And a partial transport schedule relating to the transport path in charge of the coating and developing apparatus on the other side is transmitted to the coating and developing apparatus on the other side. In this case, since the coating and developing apparatus on the other side controls the transport of the substrate based on the partial transport schedule instead of the transport schedule created independently, the substrate that is transported and processed beyond the frame of the apparatus However, accurate conveyance control can be performed while avoiding missing or overlapping of processing and conveyance destinations.

1 is an external perspective view of a coating and developing system according to an embodiment. FIG. 2 is a cross-sectional plan view of a coating and developing apparatus provided in the coating and developing system. 2 is an external perspective view of the coating and developing apparatus. FIG. It is a vertical side view of the coating and developing apparatus. It is a vertical front view of an interface block. It is a perspective view which shows the structural example of the conveyance mechanism between apparatuses. It is a 1st expansion longitudinal cross-sectional view of the conveyance part between apparatuses. It is a 2nd expansion longitudinal cross-sectional view of the conveyance part between apparatuses. FIG. 2 is a block diagram showing an electrical configuration of the coating and developing system. It is explanatory drawing which shows an example of the conveyance schedule of each machine. It is explanatory drawing which shows an example of a comprehensive conveyance schedule. It is a flowchart which shows operation | movement of the application | coating and developing apparatus by the side of A machine. It is a flowchart which shows operation | movement of the application | coating and developing apparatus by the B machine side. It is a schematic diagram which shows the conveyance path | route of the wafer based on the conveyance schedule of each said machine. It is a schematic diagram which shows the conveyance path | route of the wafer based on the said comprehensive conveyance schedule. It is a schematic diagram which shows the conveyance path | route in the case of conveying a wafer in parallel with two exposure apparatuses. It is a schematic diagram which shows the other example of the conveyance path | route of a wafer based on a comprehensive conveyance schedule. It is an external appearance perspective view of the application | coating and developing system which concerns on 2nd Embodiment. It is a 1st schematic diagram which shows the conveyance path | route of the wafer in a said 2nd application | coating and developing system. It is a 2nd schematic diagram which shows the conveyance path | route of the wafer in a said 2nd application | coating and developing system.

  First, the configuration of a coating and developing system (substrate processing system) to which the present invention is applied will be described with reference to FIGS. As shown in FIG. 1, the coating and developing system of this example has two coating and developing devices 1 a and 1 b (first coating, developing device, second coating and developing device) that transfer the inter-device transport module 5. The coating and developing devices 1a and 1b are further connected to an exposure device D4. Hereinafter, the coating / developing apparatus 1a on one side may be referred to as “A machine”, and the coating / developing apparatus 1b on the other side may be referred to as “B machine”.

  In the coating / developing system of this example, the coating / developing apparatuses 1a and 1b have a substantially common configuration, and therefore are disposed on the left hand side of the inter-unit transport module 5 when viewed from the front side (carrier block D1 side described later). The configuration of the coating and developing apparatus 1a will be described as an example.

  In the coating and developing apparatus 1a, a carrier block D1, a processing block D2, and an interface block D3 are linearly connected. An exposure device D4 is further connected to the interface block D3. Hereinafter, the arrangement direction of the blocks D1 to D3 will be described as the front-rear direction, and the one end side where the carrier block D1 is disposed will be the front side.

  The carrier block D1 has a role of carrying the wafer W in and out of the carrier C made of FOUP (Front Opening Unified Pod) or the like containing a plurality of wafers W of the same lot and the coating / developing apparatus 1a. As shown in FIG. 2, the carrier block D <b> 1 includes a mounting table 21 for the carrier C, an opening / closing part 22 for opening and closing the lid of the carrier C, and a transfer arm 23 for taking out and transferring the wafer W from the carrier C. ing.

  As shown in FIGS. 3 and 4, first to sixth unit blocks B <b> 1 to B <b> 6 for performing liquid processing on the wafer W are stacked in order from the bottom in the processing block D <b> 2. For convenience of explanation, “BCT” is a process for forming a lower antireflection film on the wafer W, “COT” is a process for forming a resist film on the wafer W, and a process for forming a resist pattern on the exposed wafer W is performed. Sometimes expressed as “DEV”. In this example, two BCT layers B1, B2, COT layers B3, B4, and DEV layers B5, B6 are stacked from the bottom. In the same type of unit block, the wafer W is transferred and processed in parallel with each other.

  As representative of these unit blocks, FIG. 2 illustrates COT layers B3 and B4. The COT layers B3 and B4 are provided with a transport region 31 so as to extend in a direction from the carrier block D1 to the interface block D3, and a plurality of sides are provided on one side of the transport region 31 (for example, the left hand as viewed from the front side). The shelf units U are arranged side by side in the front-rear direction. Further, a resist film forming module COT, which is a liquid processing module that performs liquid processing by supplying various chemicals to the surface of the rotating wafer W on the other side (for example, the right hand as viewed from the front side) of the transfer region 31. And a protective film forming module ITC are provided side by side in the front-rear direction.

  The resist film forming module COT supplies a resist to the wafer W to form a resist film. The protective film forming module ITC supplies a predetermined processing liquid onto the resist film and forms a protective film for protecting the resist film. Each shelf unit U includes a heating module (not shown), and the transfer area 31 is provided with transfer arms F3 and F4 which are transfer mechanisms for the wafer W.

  The other unit blocks B1, B2, B5 and B6 are configured in substantially the same manner as the unit blocks B3 and B4 except that the chemicals supplied to the wafer W are different. The unit blocks B1 and B2 include antireflection film forming modules instead of the resist film forming module COT and the protective film forming module ITC as liquid processing modules, and the unit blocks B5 and B6 include a developing module. In FIG. 4, the transfer arms of the unit blocks B1 to B6 are indicated as F1 to F6.

  On the front side of the processing block D2, a tower T1 extending in the vertical direction across each of the unit blocks B1 to B6 and a wafer W that can be moved up and down for delivering a wafer W between a plurality of modules provided in the tower T1. An arm 32 is provided. The tower T1 is provided with a plurality of modules stacked in the vertical direction. Among these modules, the delivery module TRS provided corresponding to the height of each of the unit blocks B1 to B6 is a unit. It is used when the wafer W is transferred between the transfer arms F1 to F6 in the blocks B1 to B6.

  As a specific example of the module provided in the tower T1, the above-described transfer module TRS used when the wafer W is transferred between the unit blocks B1 to B6, and the temperature control for adjusting the temperature of the wafer W. There are a module CPL, a buffer module BU for temporarily storing a plurality of wafers W, a hydrophobizing module ADH for hydrophobizing the surface of the wafers W, and the like. In order to simplify the description, the hydrophobic treatment module ADH, the temperature control module CPL, and the buffer module BU are not shown. Further, in the description of the processing operation to be described later, description regarding the operation of these modules is omitted.

  As shown in FIGS. 4 and 5, the interface block D3 includes towers T2, T3, and T4 extending in the vertical direction across the unit blocks B1 to B6. In the interface block D3, an interface arm 41 that can be raised and lowered to transfer the wafer W between the tower T2 and the tower T3, and an elevator that can move up and down to transfer the wafer W between the tower T2 and the tower T4. And an interface arm 43 for transferring the wafer W between the tower T2 and the exposure apparatus D4.

  The tower T2 includes a delivery module TRS, a buffer module BU for storing and retaining a plurality of wafers W before exposure processing, a buffer module BU for storing a plurality of wafers W after exposure processing, and temperature adjustment of the wafers W. Although the temperature control module CPL etc. to be performed are laminated | stacked mutually, similarly to the case of tower T1, illustration of buffer module BU and temperature control module CPL is abbreviate | omitted.

  In addition, a plurality of post-exposure cleaning modules PIR for cleaning the wafer W after the exposure processing are stacked in the vertical direction on the tower T3 disposed on the right hand side of the tower T2 when viewed from the front side. Yes. On the other hand, a plurality of back surface cleaning modules BST for cleaning the back surface of the wafer W before being loaded into the exposure apparatus D4 are stacked in a vertical direction on the tower T4 disposed on the left hand side of the tower T2.

The configuration of the coating / developing apparatus 1a (A machine 1a) has been described above. However, the coating / developing apparatus 1b (B machine 1b) is different from that shown in FIG. -It is configured in substantially the same way as the A machine 1a shown in FIG.
In the present embodiment, the place where the wafer W is placed on the transfer path in the coating and developing apparatuses 1a and 1b is called a module.

  In this way, each of the coating and developing devices 1a and 1b contains a large number of various modules, and the wafer W is processed while being transferred between these modules. In the coating and developing system of this example, the wafer W is transferred between the coating and developing apparatus 1a (A machine 1a) and the coating and developing apparatus 1b (B machine 1b) via the inter-device transport module 5. It is also possible to process the wafer W using the exposure apparatus D4 connected to the counterpart interface block D3.

  As shown in FIG. 1 and the like, the inter-device transfer module 5 of this example is provided so as to connect the interface blocks D3 of the A machine 1a and the B machine 1b, and the upper position of the tower T3 of the A machine 1a and the B machine The wafer W is transferred to and from the upper position of the tower T4 of 1b. As shown in FIG. 6, the inter-device transport module 5 has a configuration in which two inter-device transport mechanisms 50a and 50b are stacked one above the other. For example, the upper inter-device transport mechanism 50a includes the A machine 1a to the B machine. The wafer W is transported toward 1b, and the lower inter-device transport mechanism 50b transports the wafer W from the B machine 1b to the A machine 1a.

  Each inter-device transfer mechanism 50a, 50b transfers the wafer W between the transfer arm 51a that transfers the wafer W to and from the interface arm 41 of the machine A 1a and the interface arm 42 of the machine B 1b. An arm 51b, a slider 503 that is a substrate holding unit that carries the wafer W between the transfer arms 51a and 51b, and the slider 503 are supported so as to be movable in the horizontal direction, and the transfer arms 51a and 51b themselves. This is a single-wafer transport type transport mechanism including an arm unit 502 that moves between the base unit 501 and the base unit 501 that drives the arm unit 502 and the slider 503.

  The delivery arm 51a is provided on the top of the tower T3 on the A machine 1a side, and the delivery arm 51b is provided on the top of the tower T4 on the B machine 1b side. The delivery arms 51 a and 51 b have a structure in which three support pins 511 for supporting the wafer W are provided on the upper surface of a U-shaped plate member having two different sides extending in parallel. The wafer W is transferred between the slider 503 and the interface arms 41 and 42 by raising and lowering the transfer arms 51a and 51b. The transfer arms 51a and 51b are horizontally arranged with the U-shaped opening portion directed toward the traveling path side of the slider 503. When the wafer W is transferred, the sliders are placed inside the region surrounded by the U-shaped plate material. 503 enters.

The slider 503 has a structure in which three support pins 504 for supporting the wafer W are provided on the upper surface of a rectangular plate material, and the lower surface side thereof is connected to a drive mechanism (not shown) provided in the arm portion 502. ing.
The arm portion 502 is configured by providing a driving mechanism for the slider 503 in a flat T-shaped housing, and is arranged horizontally with the base end portion of the T-shaped vertical bar held by the base portion 501. Thereby, the arm part 502 can move the slider 503 in the horizontal direction along the upper surface of the T-shaped horizontal bar.

The base portion 501 is configured by providing a driving mechanism for moving the arm portion 502 in the horizontal direction in a flat casing. Accordingly, the arm unit 502 is moved while moving the slider 503 on the arm unit 502, and the wafer W is transferred in a two-stage stroke. The arm unit 502 and the base unit 501 correspond to a moving mechanism that moves the slider 503.
As shown in FIG. 5, the inter-device transport mechanisms 50a and 50b are housed in the casing 52 and transport the wafer W in a space partitioned from the outside (for convenience of illustration, FIG. Only the delivery arm 51a of the mechanism 50a, 50b is shown).

  Here, as schematically shown in FIG. 5, a fan filter unit (FFU) 44, which is a pressure adjusting unit, is disposed on the ceiling of the coating and developing devices 1a and 1b, and the inside of each coating and developing device 1a and 1b. The pressure is adjusted so that the pressure in the space becomes higher than the external pressure, thereby preventing the entry of particles and the like from the outside.

On the other hand, when trouble occurs on one side of these coating / developing apparatuses 1b and 1a, troublesome coating occurs when the other side of the coating / developing apparatuses 1a and 1b performs processing of the wafer W. The pressure adjustment by the FFU 44 may not be normally performed in the developing devices 1b and 1a. In such a case, if the space in the two coating and developing devices 1a and 1b is connected via the inter-device transport module 5, the space in the coating and developing devices 1a and 1b in which no trouble has occurred. There is also a risk that the pressure fluctuates and particles enter.
Therefore, the inter-device transport module 5 of this example is provided with a partition wall 53 that partitions the space in the interface block D3 of each coating and developing device 1a, 1b and the space in the housing 52 of the inter-device transport module 5. (FIG. 5).

  7 and 8 are enlarged views of the connection portion between the interface block D of the coating and developing apparatus 1a (A machine 1a) and the inter-apparatus transport module 5. FIG. As shown in these drawings, the interface arm 43 in the inter-unit transfer module 5 is positioned at two height positions on the partition wall 53 where the wafer W is transferred between the interface arm 43 and the transfer arm 51a. Is provided with an opening 531 for allowing the air to enter. These openings 531 are opened and closed by a shutter 54.

  The shutter 54 is disposed on the inner side of the inter-device transport module 5, and protrudes gradually in the arrangement direction of the partition wall 53 from the lower side to the upper side at two locations on the surface facing the partition wall 53. A lid portion 541 having a tapered surface formed as described above is provided. On the other hand, a taper formed so as to gradually protrude from the upper side to the lower side in the arrangement direction of the shutter 54 so that the taper surface of the lid portion 541 can be brought into contact with each opening 531. A surface receiving portion 55 having a surface is provided.

  Each surface receiving portion 55 is provided with an opening 551, and the opening 551 can be hermetically closed by bringing the tapered surfaces of the lid portion 541 and the surface receiving portion 55 into contact with each other. As a result, the space between the interface block D3 and the inter-device transport module 5 is partitioned, and the entry of airflow between the coating and developing device 1a and the inter-device transport module 5 is suppressed (FIG. 8).

  On the other hand, the shutter 54 is provided with an opening 542 at an intermediate height position between the upper and lower lids 541. When the wafer W is transferred, the opening 542 is provided at the height of the upper opening 531. The interface arm 43 is advanced through the lower openings 531, 551, and 541 that are in communication with each other (FIG. 7). The height of the shutter 54 is set such that when the shutter 54 is raised, the lower end portion thereof is positioned above the lower-stage openings 531 and 551. As a result, when the shutter 54 is moved upward, the lower opening 531 is also opened (FIG. 7).

  The partition wall 53 and the shutter 54 described above are also provided at the connection portion between the interface block D3 on the coating and developing device 1b (B machine 1b) side and the inter-device transport module 5, and The opening 531 can be opened and closed independently. As a result, the shutter 54 on the other side can be closed while the wafer W is being transferred by the interface block D3 on one side of the A machine 1a and the B machine 1b. Thereby, it is possible to avoid communication between the two interface blocks D3 and to suppress pressure fluctuations in the coating and developing devices 1a and 1b in which no trouble has occurred.

  Further, how to transfer the wafer W between the interface arm 43, the transfer arm 51a, and the slider 503 will be described with reference to FIGS. When the wafer W is transferred from the interface arm 43 to the transfer arm 51a, the transfer arm 51a is retracted while being lowered downward (see the interface arm 43 and the transfer arm 51a on the upper stage side in FIG. 7). When the interface arm 43 enters the housing 52 of the inter-device transfer module 5 and reaches the upper side of the transfer arm 51a, the transfer arm 51a is lifted to receive the wafer W from the interface arm 43 to the transfer arm 51a. hand over. Thereafter, the interface arm 43 is retracted and retracted from the inter-device transfer module 5 (see the delivery arm 51a on the lower side of FIG. 7). The transfer of the wafer W from the transfer arm 51a to the interface arm 43 is executed by moving the interface arm 43 and the transfer arm 51a in the reverse order of these operations. Further, the transfer of the wafer W between the interface arm 42 and the transfer arm 51b on the side of the B machine 1b is the same as the above example.

  Next, the delivery of the wafer W from the delivery arm 51a to the slider 503 will be described. The slider 503 enters the inside of the delivery arm 51a waiting at the upper position with the wafer W supported (FIG. 8). The upper transfer arm 51a and the slider 503). When the slider 503 reaches the lower side of the wafer W supported by the transfer arm 51a, the transfer arm 51a is lowered and the wafer W is transferred from the transfer arm 51a to the slider 503. Thereafter, the slider 503 is moved toward the delivery arm 51b (see the delivery arm 51a and the slider 503 on the lower side in FIG. 8). The transfer of the wafer W from the slider 503 to the transfer arm 51a is executed by moving the transfer arm 51a and the slider 503 in the reverse order of these operations. Further, the transfer of the wafer W between the slider 503 and the transfer arm 51b on the side of the B machine 1b is the same as the above example.

  In the coating and developing system having the above-described configuration, as shown in FIG. 9, each coating and developing apparatus 1 a and 1 b includes a control unit 6 (first control unit and second control unit) and a memory 7. Having a computer. The control unit 6 includes a CPU (Central Processing Unit) 61 and a program storage unit 62. The program storage unit 62 takes out the wafer W from the coating and developing devices 1a and 1b, that is, the carrier C, and enters the transfer path. A group of steps (commands) for control related to the operation until the processed wafers W are stored in the carrier C while the wafers W are transferred along the units B1 to B6. The program is recorded. This program is stored in a storage medium such as a hard disk, a compact disk, a magnetic optical disk, or a memory card, and installed in the computer therefrom. In FIG. 9, the program storage unit 62 and the memory 7 to be described later are described as separate storage media, but they may be configured by a common storage medium.

  In addition to the program for executing these operations, each program storage unit 62 includes a transfer in which the transfer destination and transfer order of each wafer W in the carrier C (that is, the transfer path of each wafer W) are arranged in time series. A scheduler program 621 for creating a schedule, and each conveyance mechanism (conveyance arm 23, delivery arm 32, conveyance arms F1 to F6, interface arms 41 to 43) based on the conveyance schedule, and a conveyance route set by the conveyance schedule And a transfer control program 622 for transferring the wafer W along the line.

  A transfer recipe 72 and a process recipe 71 are stored in the memory 3 as data for creating a transfer schedule for the wafer W. In the transfer recipe 72, information for setting a transfer path from the time when the wafer W unloaded from the carrier C is processed by the coating, developing devices 1a and 1b and the exposure device D4 and loaded into the original carrier C is set. Yes. When a plurality of modules of the same type are provided, it is possible to identify each module, select a transport destination, and create a transport schedule.

  The processing recipe 71 includes the contents of processing executed in each processing module (for example, in the case of a liquid processing module, in the case of a heating module or temperature control module CPL, such as the rotation speed of the wafer W or the supply time of a chemical solution). , Temperature setting value, temperature control time, etc.) are set. The processing recipe 71 can be selected from a plurality of types according to information set on the wafer W in the carrier C.

  On the other hand, the contents of processing executed by the coating, developing devices 1a and 1b and the exposure device D4 are set in advance on the wafer W in the carrier C which is transported in the factory and processed by each processing device. ing. As information for managing the processing contents, a control job (CJ) and a process job (PJ) are set for the wafer W in the carrier C. CJ is a PJ group unit set for each wafer W, and is set for each lot in this example. In the PJ, information for specifying a processing recipe to be performed on each wafer W is set.

For example, it is assumed that each carrier C has a structure in which 25-stage slots for holding the wafer W in a horizontal posture are stacked in the vertical direction. The CJ includes an ID that is an individual number of each CJ and information that identifies the carrier C in which the CJ having the ID is set.
A plurality of PJs can be set in each CJ. In the PJ, an ID that is an individual number of each PJ and information for specifying a wafer W on which the PJ having the ID is set (for example, FIG. 10). , Corresponding to the symbols “A01, A02,...” Of the transport schedules 73, 73a, 73b shown in FIG. 11 and information for specifying the processing recipe 71 to be executed. The wafer W on which each PJ is performed is specified by the slot position of the carrier C.

  Information related to the CJ and PJ is individually set for each carrier C and the wafer W stored therein, and each control unit 6 manages devices in the factory via the communication unit 8. Communicate with the host computer 80 to acquire these information.

  The control unit 6 operated by the scheduler program 621 selects a process recipe 71 to be executed on the wafer W based on information set in the PJ, and can execute a process set in the process recipe 71. Select a module. Then, a transfer recipe 72 including a transfer module TRS, a buffer module BU, and the like through which the wafer W passes before being loaded into each process module is selected, and each wafer W is selected based on the transfer recipe 72. Determine the transport route.

  When the transfer path is determined for the wafers W in the lot and the transfer destinations and transfer orders of the wafers W are arranged in time series, a transfer schedule 73 relating to the lot is created as shown in FIG. Is done. In the figure, the left and right columns indicate transfer destination modules, and the vertical rows indicate transfer destinations of the wafers W in each transfer step. These transfer steps are arranged in the transfer schedule 73 in chronological order. Proceed from top to bottom.

The control unit 6 operated by the transfer control program 622 operates each transfer mechanism based on the transfer schedule 73 and moves the wafer W to the wafer W based on the transfer source and transfer destination information set for the wafer W in each transfer step. Transport.
In a normal operation that does not use the inter-apparatus transport module 5, the coating and developing apparatuses 1a and 1b are each based on a transport schedule 73 created independently, and each of the coating and developing apparatuses 1a and 1b and the exposure apparatus D4 connected thereto. The wafers W are transferred independently and the processing is executed.

  On the other hand, the coating and developing devices 1a and 1b of this example are transported across both coating and developing devices 1a and 1b using the inter-device transport module 5, and are shared by these devices 1a and 1b. For the wafer W (variable processing substrate) to be processed, a transfer schedule (total transfer schedule) is created by the coating and developing devices 1a and 1b on one side, and the coating and developing device 1b on the other side. 1a has a function of operating based on a part of this transport schedule (partial transport schedule).

  As an example of the sharing of processing, the processing block D2 (BCT layer) is applied to the wafer W in the carrier C placed on the carrier block D1 of the A machine 1a due to a defect in the processing block D2 on the B1b machine side. (B1, B2, COT layers B3, B4, DEV layers B5, B6) are executed on the A machine 1a side, and processing in the interface block D3 and exposure processing are executed on the B machine 1b side.

  In this case, for example, information indicating that the wafer W of the lot is to be shared by the A machine 1a and the B machine 1b (i.e., the substrate to be modified) is set in the CJ. When this information is set, the control unit 6 of the A machine 1a creates a general transfer schedule including the modules of both the A machine 1a and the B machine 1b and the inter-device transfer module 5 as the transfer destination of the wafer W. .

  As a specific example, a transfer recipe 72 including the module of the B machine 1b as a transfer destination is stored in the memory 7 of the A machine 1a. Based on the information obtained from the CJ that the A machine 1a and the B machine 1b share the process and the process recipe set in the PJ of each wafer W is obtained. A transfer recipe 72 including a process module capable of executing the process performed on the wafer W on the transfer path is selected.

  When the transfer path is determined for the wafers W in the lot and the transfer destinations and transfer orders of the wafers W are arranged in chronological order, a general transfer schedule as outlined in FIG. 11 is created. In this comprehensive transport schedule, the inter-device transport module 5 ("SHUA (upper inter-device transport mechanism 50a), SHUB (lower inter-device transport mechanism 50b)" in the transport schedules 73a and 73b) is used as a transport destination module. In addition, the conveyance schedule 73a on the A machine 1a side and the conveyance schedule 73b (partial conveyance schedule) on the B machine 1b can be identified.

  Furthermore, the control part 6 of A machine 1a transmits the conveyance schedule 73b performed by the module by the side of B machine 1b among this comprehensive conveyance schedule toward B machine 1b. In addition to the transfer schedule 73b, the B machine 1b acquires information for selecting the processing recipe 71 set on the wafer W to be processed, and acquires it from the A machine 1a instead of the transfer schedule 73 created by itself. The wafer W is processed based on the transfer schedule 73b.

The operation of the coating and developing system having the above-described configuration will be described. First, an outline of the processing of the wafer W in a normal operation in which the application / development apparatuses 1a and 1b do not use the inter-device transfer module 5 will be described.
The wafers W are unloaded from the carrier C one by one for each lot, and are transferred by the transfer arm 23 to the transfer module TRS0 of the tower T1 in the processing block D2. The wafer W of the transfer module TRS0 is distributed by the transfer arm 32 to the BCT layers B1 and B2 via the transfer modules TRS1 and TRS2.

The wafers W carried into the BCT layers B1 and B2 are processed while being transported in the order of the antireflection film forming module → the heating module → TRS1 (TRS2), and then transferred by the transfer arm 32 to the transfer modules TRS3 and TRS4, respectively. To the COT layers B3 and B4.
The wafers W carried into the COT layers B3 and B4 are processed while being transferred in the order of resist film forming module → heating module → protective film forming module ITC → heating module → tower T2 delivery module TRS.

  The wafer W loaded into the transfer module TRS of the tower T2 is loaded into a buffer module SBU (not shown), and then loaded into the back surface cleaning module BST of the tower T4 by the interface arm 42 to perform back surface cleaning. The wafer W after the back surface cleaning is carried into the exposure apparatus D4 by the interface arms 42, 41, 43 via the temperature control module CPL (not shown) of the tower T2.

The wafer W after exposure is transferred by the interface arms 43 and 41 to the transfer module TRS of the tower T2 → the post-exposure cleaning module PIR of the tower T3, cleaned, and then passed through the transfer modules TRS5 and TRS6 of the tower T2. It is distributed to the DEV layers B5 and B6.
The wafers W carried into the DEV layers B5 and B6 are processed while being transported in the order of the heating module → the development module → the heating module → the transfer module TRS of the tower T1, and returned to the carrier C via the transport arm 23.

  Next, in the coating / developing system including the coating / developing apparatuses 1a and 1b for executing these operations, independent processing is performed by the A machine 1a and B machine 1b on the normal wafer W, and the wafer W of the irregularly processed substrate. On the other hand, the operation | movement which switches the process shared and performed with the A machine 1a and the B machine 1b is demonstrated. Here, an example of the processing assumed in the description relating to the creation of the general conveyance schedule in FIG. 10 (in the processing block D2 on the side of the A machine 1a due to a problem occurring in the processing block D2 on the side of the B machine 1a) BCT, COT, and DEV will be described, and exposure processing and the like will be performed in the interface block D3 and exposure apparatus D4 on the B machine 1b side). In this case, FIG. 12 shows an operation flow on the A machine 1a side, and FIG. 13 shows an operation flow on the B machine 1b side.

  When the carrier C is loaded into the carrier block D1 of the A machine 1a for the operation on the A machine 1a side (start of FIG. 12), information related to the processing of the wafer W is acquired from the host computer 80 (step S101). If the information to use the B machine 1b is not set in the acquired information (for example, CJ set in the lot in the carrier C) (step S102; NO), the A machine 1a is the wafer to be processed. A transfer schedule 73 (FIG. 10) for processing W by itself is created (step S103), and the process is executed while transferring the wafer W along the transfer path described above based on the transfer schedule 73. (Step S104). When all the wafers W in the carrier C have been processed, the operation ends (END).

  On the other hand, if the information related to the processing of the wafer W is set to use the B machine 1b (step S102; YES), the wafer W is processed by the own machine and the B machine 1b. A general conveyance schedule (FIG. 11) is created (step S105), and a partial conveyance schedule 73b executed by the B machine 1b is transmitted (step S106). Then, the A machine 1a carries the wafer W on the basis of the carrying schedule 73a for the own machine, executes only the process in charge of the own machine (step S107), and finishes the process for all the wafers W in the carrier C. When finished, end the operation.

  Regarding the operation of the B machine 1b executed in parallel with the operation of the A machine 1a, when the carrier C is loaded into the carrier block D1 of the B machine 1b (start of FIG. 13), information related to the processing of the wafer W is displayed. Obtained from the host computer 80 (step S201). If the processing information can be acquired (step S202; YES), the B machine 1b creates a transfer schedule 73 (FIG. 10) for processing the wafer W to be processed by itself (step S203). Then, the process is executed while the wafer W is being transferred along the transfer path described above (step S204). When all the wafers W in the carrier C have been processed, the operation ends (END).

  On the other hand, if the information related to the processing of the wafer W is not acquired because the carrier C is not placed on the carrier block D1 (step S202; NO), whether or not the partial transfer schedule 73b is received from the A machine 1a. (Step S205). When the partial transfer schedule 73b is received (step S205; YES), the B machine 1b, when the wafer W is transferred from the A machine 1a side to the B machine 1b side, the wafer based on the received partial transfer schedule 73b. W is transported, and the process in charge of itself is executed (step S206). When all the wafers W transferred from the A machine 1a have been processed, the operation ends (END). On the other hand, when the partial transfer schedule 73b is not received (step S205; NO), the B machine 1b does not process the wafer W (end).

By these operations, when the A machine 1a and the B machine 1b operate independently, the wafer W is transferred and processed in parallel by the A machine 1a and the B machine 1b as schematically shown in FIG. Done.
On the other hand, when the wafer W is processed by the A machine 1a and the B machine 1b, the wafer W on which an antireflection film or a resist film is formed in the processing block D2 of the A machine 1a as shown in FIG. Is transferred to the interface block D3 of the B machine 1b through the inter-apparatus transfer module 5, and after backside cleaning, exposure processing in the exposure apparatus D4, and post-exposure cleaning, it is transferred again to the A machine 1a. Then, development processing is performed in the processing block D2 of the A machine 1a, and the original carrier C is accommodated.

  The coating and developing system according to this embodiment has the following effects. With respect to the wafer W (variable processing substrate) to be transferred and processed across the A machine 1a and B machine 1b via the inter-device transfer module 5, one side (A machine 1a in the above example) A common transport schedule (transport schedules 73a and 73b) is created at, and a partial transport schedule 73b related to the transport route in charge of the other side is transmitted toward the other side (B machine 1b in the above example). In this case, the B machine 1b on the other side controls the transfer of the wafer W on the basis of the partial transfer schedule 73b instead of the transfer schedule 73 that is uniquely created. Even for the wafer W to be processed, accurate transfer control can be performed while avoiding processing and transfer destination omission and duplication.

  In the case where the processing is shared between the A machine 1a and the B machine 1b, the A machine 1a has its own machine in addition to the processing of the wafer W for performing the exposure process by the exposure apparatus D4 connected to the B machine 1b. The processing of the wafer W for performing the exposure process may be performed in parallel by the exposure apparatus D4 connected to (FIG. 16). In general, the coating and developing apparatuses 1a and 1b have a larger number of sheets that can be processed per unit time than the exposure apparatus D4. Therefore, the processing of the wafer W subjected to the exposure process in both exposure apparatuses D4 can be performed in parallel. . For example, in the coating / developing apparatus 1a shown in FIG. 4, the processing of the wafer W to be exposed on the A machine 1a side is executed in the unit blocks B1, B3, and B5, and the B machine is used in the unit blocks B2, B4, and B6. The case where the process of the wafer W subjected to the exposure process on the 1b side is executed may be considered.

  Further, the wafer W taken out from the carrier C placed on the carrier block D1 of the A machine 1a may be returned to the carrier C of the carrier block D1 of the B machine 1b. In the example of FIG. 17, the processing block D2 on the A machine 1a side shares the processing of the BCT layers B1, B2, COT layers B3, B4, and the processing block D2 on the B machine 1a side shares the processing of the DEV layers B5, B6. In addition, an example is shown in which exposure processing is performed by the exposure apparatus D4 connected to the B machine 1a. The carrier C into which the processed wafer W is loaded may be taken out on the A machine 1a side, and the emptied carrier C may be transferred to the B machine 1b side. Further, a carrier C different from the carrier C from which the wafer W is taken out on the A machine 1a side may be prepared on the B machine 1b side.

  FIG. 18 shows carrier blocks of the A machine 1a and the B machine 1b in addition to the inter-device transfer module 5a (first inter-device transfer mechanism) that transfers the wafer W between the interface blocks D3 of the A machine 1a and the B machine 1b. An example of a coating and developing system provided with an inter-device transfer module 5b (second inter-device transfer mechanism) for transferring a wafer W between D1 sheets is shown. The inter-device transfer module 5b is provided so as to connect spaces in which the transfer arm 23 is provided, for example.

The inter-device transfer module 5b can transfer the wafer W between the carrier C mounted on the carrier block D1 of the A machine 1a and the processing block on the B machine 1b side.
For example, FIG. 19 shows that the wafer W is taken out from the carrier C placed on the carrier block D1 on the A machine 1a side, transferred to the B machine 1b via the inter-device transfer module 5b, and then the BCT layer B1 on the B machine 1b side. An example in which processing is performed in B2 and COT layers B3 and B4 is shown. In this case, the wafer W is subjected to exposure processing by the exposure apparatus D4 connected to the B machine 1b, and transferred to the A machine 1a via the inter-apparatus transfer module 5a, and then the DEV layer B5 on the A machine 1a side. , B6 and return to carrier C.

  Also, FIG. 20 shows that the wafer W is taken out from the carrier C placed on the carrier block D1 on the A machine 1a side, processed as it is in the BCT layers B1, B2, COT layers B3, B4 on the A machine 1a side, and then between the apparatuses. The example which conveys to the inner face block D3 of the B machine 1b via the conveyance module 5a is shown. In this case, the wafer W is exposed by the exposure apparatus D4 on the B machine 1b side, processed by the DEV layers B5 and B6 on the B machine 1b side, and then the A machine 1a side via the inter-device transfer module 5b. Return to career C.

  As in the above example, when the processing in the processing block D2 is shared between the A machine 1a and the B machine 1b, the two types of sharing patterns shown in FIGS. 19 and 20 can be considered. In this case, for example, in addition to the information indicating that the processing is shared by both the A machine 1a and the B machine 1b, information on which pattern to select is selected as CJ information by the host computer. You may acquire from 80.

  In each of the embodiments described above, the coating / developing devices 1a and 1b responsible for part of the processing on the other side (in the example of FIG. 15, the side of the A machine 1a on which the carrier C is placed on the carrier block D1). In the above, the case of creating the general conveyance schedule (conveyance schedules 73a and 73b) has been described. However, the creation of the general conveyance schedules 73a and 73b is not limited to this example. For example, the application / development apparatus 1b on the side (for example, the machine in which the trouble is generated) that shares a part of the processing of the own machine, for example. 1a (the B machine 1b side in the example shown in the figure) may be used to create a general conveyance schedule.

Further, the transfer path of the wafer W is not limited to the patterns illustrated in FIGS. 15, 16, 19, and 20, and various patterns may be adopted.
For example, in the example of FIG. 20 including two inter-apparatus transfer modules 5a and 5b, the carrier C is loaded into the coating and developing apparatus 1b → the wafer W is transferred to the A machine 1a via the inter-apparatus transfer module 5b → the A machine 1a Process in BCT layers B1, B2, COT layers B3, B4 → Transfer to B machine 1b via inter-apparatus transport module 5a, exposure process in exposure apparatus D4 connected to B machine 1b → Inter-apparatus transport module 5a Conveying to machine A 1a → Processing in DEV layers B5 and B6 of machine A 1a → Conveying path such as transferring wafer W to machine B 1b via inter-device carrying module 5b and returning it to carrier C can be considered. . For example, when the B machine 1b monitors the availability of its own processing block D2 or the like without going through the host computer 80 and determines that the wafer W in the carrier C placed on the carrier block D1 cannot be processed, It is conceivable to adopt this transport route when requesting the sharing of processing from the B machine 1b to the A machine 1a as needed.

  Furthermore, the present invention can also be applied when trouble occurs on the exposure apparatus D4 side. The exposure apparatus connected to the A machine 1a when the settings of the exposure apparatus D4 connected to the A machine 1a and the B machine 1b are common and the common processing is performed in the A machine 1a and the B machine 1b. When trouble occurs in D4, as shown in FIG. 15, the transfer destination of the wafer W in the middle of processing may be changed to the exposure apparatus D4 on the B machine 1b side to continue the processing.

  Further, the configuration of the transfer schedules 73, 73a, and 73b is not limited to that illustrated in FIGS. 10 and 11 as long as it defines an actual transfer path through which each wafer W is transferred. For example, instead of creating the transfer schedules 73, 73a, 73b that determine the transfer route of all the wafers W when the carrier C is placed on the carrier block D1, immediately before taking out the wafers W from the carrier C one by one. In addition, a transfer schedule for each wafer W may be created after confirming the usage status of the modules in the coating and developing apparatuses 1a and 1b.

  Furthermore, the coating and developing system to which the present invention is applicable may include three or more coating and developing devices 1a to 1c. For example, when the interface blocks D3 of the A machine 1a and the B machine 1b are connected by the inter-device transfer module 5a, and further, the interface block D3 of the B machine 1b and the C machine 1c are connected by the inter-device transfer module 5c, the A Consider the case where each process is performed in the processing block D2 of the machine 1a, the exposure process is performed by the exposure apparatus D4 connected to the C machine 1c, and the process is performed again in the processing block D2 of the A machine 1a. In this case, the wafer W passes through the interface block D3 of the B machine 1b, but the B machine 1b forms a part of the inter-device transfer mechanism, and the A machine 1a and the C machine 1c are the first and second machines. It can be considered that it corresponds to a coating and developing apparatus.

  Further, the inter-device transfer mechanisms 50 a and 50 b that transfer the wafer W for each sheet are not limited to the case where the wafer W is mounted on the slider 503 and transferred. For example, a plurality of wafer holding units for holding the wafers W may be arranged in the vertical direction with a space therebetween, and these wafer holding units may be connected to a common moving mechanism to transfer a plurality of wafers W simultaneously. This example also corresponds to an inter-device transfer mechanism that executes single wafer transfer in that the wafer W is held and transferred to each wafer holder by each wafer.

W Wafer 1a Coating and developing device (A machine)
1b Coating and developing device (B machine)
23 Transport mechanism 32 Delivery arms 41, 42, 43
Interface arm 5, 5a, 5b
Inter-device transfer module 50a, 50b
Inter-device transport mechanism 53 Partition wall 531 Opening 54 Shutter 541 Lid 61 CPU
73, 73a, 73b
Transport schedule 8 communication section

Claims (16)

A carrier block into which a carrier containing a plurality of substrates is loaded, and a coating film including a resist film is formed on the substrate taken out of the carrier in the carrier block, and development processing is performed on the substrate after exposure processing. A first coating / developing apparatus and a second coating / developing apparatus, each of which includes a processing block that performs the processing, and an interface block that is connected to the exposure apparatus and transfers the substrate between the processing block and the exposure apparatus. ,
The first coating / developing apparatus and the second coating / developing apparatus are respectively provided to create a transport schedule that is a transport path for each substrate in the coating / developing apparatus, and based on the transport schedule, the first A first control unit that performs transport control of the substrate in the coating and developing apparatus; a second control unit that performs transport control of the substrate in the coating and developing apparatus;
An inter-device transport mechanism for transporting a substrate between the first coating and developing device and the second coating and developing device,
Exposure connected to one processing block of the first coating, developing device and second coating, developing device and the other of the first coating, developing device, second coating, developing device. When a carrier containing a to-be-modified processing substrate that is a substrate processed using the apparatus is carried into one of the carrier blocks of the first coating, developing device, second coating, and developing device, Comprehensive transport which is the entire transport path of the substrate straddling between the first coating and developing device and the second coating and developing device by one of the first control unit and the second control unit. A schedule is created, and a partial transport schedule corresponding to a transport schedule in the coating and developing apparatus to which the other control unit belongs is transmitted from one control unit to the other control unit. A substrate processing system, characterized in that.   When the irregularly processed substrate is loaded into the coating and developing apparatus to which the other control unit belongs, the other control unit performs transport control of the substrate based on the partial transport schedule by the inter-device transport mechanism. The substrate processing system according to claim 1, wherein the substrate processing system is configured as described above.   3. The control unit of the coating and developing apparatus according to claim 1, wherein the one control unit that creates the comprehensive transport schedule is a control unit of a coating and developing apparatus to which a carrier block into which a carrier storing the irregularly processed substrate is carried belongs. The substrate processing system as described.   4. The modified processing substrate returns to the carrier in the carrier block into which the carrier containing the modified processing substrate is loaded after a series of processing ends. A substrate processing system according to claim 1.   After the series of processing is completed, the modified processing substrate is one of the first coating / developing device and the second coating / developing device in which the carrier containing the modified processing substrate is not carried. 4. The substrate processing system according to claim 1, wherein the substrate processing system returns to the carrier of the coating and developing apparatus.   The irregular processing performed on the irregular processing substrate is performed in a state where a defect occurs in the other processing block of the first coating, the developing device, and the second coating, and the developing device. 6. The substrate processing system according to claim 1, wherein the processing is performed using a block and an exposure apparatus connected to the other coating and developing apparatus.   The inter-device transport mechanism is provided so as to transport the irregular processing substrate between the interface block of the first coating / developing device and the interface block of the second coating / developing device. The substrate processing system according to claim 1, wherein the substrate processing system is a substrate processing system.   When the inter-device transport mechanism that transports the substrate between the interface blocks is the first inter-device transport mechanism, the carrier block of the first coating and developing device and the second coating and developing device of the second The substrate processing system according to claim 7, further comprising a second inter-device transport mechanism for transporting the irregularly processed substrate one by one to and from the carrier block.   The inter-device transport mechanism includes a substrate holding unit that holds a substrate to be processed, a substrate delivery position on the first coating and developing device side of the substrate holding unit, and a second first coating and developing device side. A substrate processing system according to claim 1, further comprising a moving mechanism that moves the substrate between the substrate transfer positions.   The first coating / developing device and the second coating / developing device include a pressure adjusting unit that adjusts the pressure in the space in each coating / developing device to a pressure higher than the external pressure, and the inter-device transport mechanism. A partition wall that divides a space in which the substrate is transported, a space in each coating and developing device, and a shutter that opens and closes an opening provided in the partition wall in order to load and unload the modified substrate. The substrate processing system according to claim 1, further comprising a substrate processing system. A carrier block into which a carrier containing a plurality of substrates is loaded, and a coating film including a resist film is formed on the substrate taken out of the carrier in the carrier block, and development processing is performed on the substrate after exposure processing. A first coating / developing apparatus and a second coating / developing apparatus, each of which includes a processing block that performs the processing, and an interface block that is connected to the exposure apparatus and transfers the substrate between the processing block and the exposure apparatus. ,
The first coating / developing apparatus and the second coating / developing apparatus are respectively provided to create a transport schedule that is a transport path for each substrate in the coating / developing apparatus, and based on the transport schedule, the first A first control unit that performs transport control of the substrate in the coating and developing apparatus; a second control unit that performs transport control of the substrate in the coating and developing apparatus;
An inter-device transport mechanism for transporting a substrate between the first coating and developing device and the second coating and developing device,
Exposure connected to one processing block of the first coating, developing device and second coating, developing device and the other of the first coating, developing device, second coating, developing device. When a carrier containing a to-be-modified processing substrate that is a substrate processed using the apparatus is carried into one of the carrier blocks of the first coating, developing device, second coating, and developing device, Comprehensive transport which is the entire transport path of the substrate straddling between the first coating and developing device and the second coating and developing device by one of the first control unit and the second control unit. Creating a schedule;
A step of transmitting a partial transfer schedule corresponding to a transfer schedule in the developing apparatus to which the other control unit belongs in the total transfer schedule from one control unit to the other control unit. Processing method.   The one control unit that executes the step of creating the comprehensive conveyance schedule is a control unit of a coating and developing apparatus to which a carrier block into which a carrier storing the substrate to be processed is carried belongs. 11. The substrate processing method according to 11.   The substrate processing according to claim 11 or 12, wherein after the series of processing is completed, the modified processing substrate returns to the carrier in the carrier block in which the carrier storing the modified processing substrate is loaded. Method.   After the series of processing is completed, the modified processing substrate is one of the first coating / developing device and the second coating / developing device in which the carrier containing the modified processing substrate is not carried. The substrate processing method according to claim 11, wherein the substrate processing method returns to the carrier of the coating and developing apparatus.   The irregular processing performed on the irregular processing substrate is performed in a state where a defect occurs in the other processing block of the first coating, the developing device, and the second coating, and the developing device. 15. The substrate processing method according to claim 11, wherein the processing is performed using a block and an exposure apparatus connected to the other coating and developing apparatus.   A storage medium storing a computer program used in a substrate processing system for processing a substrate, wherein the program includes steps for executing the substrate processing method according to any one of claims 11 to 15. A storage medium characterized by being rare.