JP2015049769A - Communication device, encoder device and serial communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce occurrence of errors.SOLUTION: A communication device performs a data transfer between a transmitter 1 and a receiver 2 by serial communication, and the transmitter 1 comprises: a first code generation part 15 that generates a first code (a CRC code) for performing a cyclic redundancy check of data; a second code generation part 15 that generates a second code (an ECC code) for performing an error detection and correction of the data; and a transmission part 15 that transmits a serial communication type signal including at least the data, the first code and the second code.

Description

  The present invention relates to a communication device, an encoder device, and a serial communication method.

  The encoder device is widely used as a sensor for detecting a rotational position displacement of an industrial robot or the like. In a control system using an encoder device, data transmission is performed between the encoder device and the control device using a bidirectional serial communication method. In this type of control system, the encoder device generates a check code for performing a cyclic redundancy check on data corresponding to the detected rotational position displacement. Then, the encoder device adds the generated check code to the encoded signal and transmits it to the control device (see, for example, Patent Document 1).

JP 2009-271592 A

  In the control system as described above, the control device performs a cyclic redundancy check based on the check code of the encode signal. As a result, the control device can control the control target based on highly reliable data. However, for example, when there is a large noise source near the transmission line, it is easily affected by noise during signal transmission. In this case, an error frequently occurs in the cyclic redundancy check, and the controller may be stopped.

  An aspect of the present invention aims to reduce the occurrence of errors.

  According to the first aspect of the present invention, there is provided a communication device that performs data transmission by serial communication between a transmission device and a reception device, and the transmission device performs a first code for performing a cyclic redundancy check on data. A first code generation unit for generating data, a second code generation unit for generating a second code for performing error detection and error correction on the data, and at least data, a first code, and a second code There is provided a communication device including a transmission unit that transmits a signal of a serial communication method.

  According to the second aspect of the present invention, a first code generation unit that generates a first code for performing cyclic redundancy check on data, and a second code for performing error detection and error correction on the data There is provided an encoder device including a second code generation unit that generates a signal and a transmission unit that transmits at least data, a first code, and a serial communication system signal including the second code.

  According to a third aspect of the present invention, there is provided a serial communication method for performing data transmission by serial communication, wherein a first code for performing cyclic redundancy check on data is generated, and error detection is performed on data Generating a second code for performing error correction, transmitting a signal of a serial communication scheme including at least data, a first code, and a second code, and a serial communication method including the second code.

  According to the aspect of the present invention, the occurrence of errors can be reduced.

It is a block diagram which shows the structure of a control system. It is a block diagram which shows the structure of the encoder apparatus shown in FIG. It is a block diagram which shows the structure of the high-order control apparatus shown in FIG. It is a figure which shows the format structure of the encoding signal in 1st Embodiment. It is a figure which shows the data allocation of each data field. It is a flowchart which shows an example of the transmission process of the encoding signal by a signal processing part. It is a flowchart which shows an example of the reception process of the encoding signal by a control part. It is a figure which shows the format structure of the encoding signal in 2nd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to this. In the drawings, in order to describe the embodiment, the scale may be changed as appropriate, for example, by partially enlarging or emphasizing.

<First Embodiment>
FIG. 1 is a block diagram showing the configuration of the control system. A control system SYS shown in FIG. 1 includes a plurality (n) of encoder devices (transmitting devices, receiving devices) 1-1 to 1-n and a higher-level control device (transmitting device, receiving device, control device) 2. Prepare. As shown in FIG. 1, the plurality of encoder devices 1-1 to 1-n and the upper control device 2 are connected to each other via a transmission line (serial communication line) 3.

  The plurality of encoder devices 1-1 to 1-n are mounted on, for example, a plurality of motors (control objects) that drive the robot, for example. Each encoder device 1-1 to 1-n detects the rotational position displacement of each motor (or the rotational position displacement or position displacement of a member driven by the motor). Each encoder device 1-1 to 1-n stores position data representing the rotational position displacement of each motor. Each encoder device 1-1 to 1-n receives a command signal for notifying a command transmitted from the host control device 2. Then, in response to receiving the command signal, the encoder devices 1-1 to 1-n transmit an encode signal for notifying position data to the upper control device 2 via the transmission line 3.

  The host control device 2 transmits command signals to the encoder devices 1-1 to 1-n via the transmission line 3. Further, the host control device 2 receives the encoded signals transmitted from the encoder devices 1-1 to 1-n. And the high-order control apparatus 2 controls each motor corresponding to each encoder apparatus 1-1 to 1-n based on the position data contained in an encoding signal. For example, the host control device 2 performs control to rotate each motor by a predetermined amount. By such control, the host control device 2 controls the operation of the robot.

  The transmission line 3 is composed of, for example, a pair of differential transmission lines 3a and 3b. A termination resistor 4 is connected between the differential transmission line (SD +) 3a and the differential transmission line (SD−) 3b. A command signal and an encode signal are transmitted by differential serial communication (for example, based on the RS485 standard) through the transmission line 3 including the pair of differential transmission lines 3a and 3b. A pair of power supply lines Vcc and ground lines GND from the host control device 2 are connected to the encoder devices 1-1 to 1-n. That is, power for the encoder devices 1-1 to 1-n is supplied from the host control device 2.

  As described above, each of the encoder apparatuses 1-1 to 1-n transmits an encode signal and receives a command signal. From this, each encoder apparatus 1-1 to 1-n functions as a transmission apparatus and a reception apparatus in the communication apparatus. The host control device 2 transmits a command signal and receives an encoded signal. Therefore, the host control device 2 also functions as a transmission device and a reception device in the communication device.

  FIG. 2 is a block diagram showing a configuration of the encoder device shown in FIG. The encoder devices 1-1 to 1-n shown in FIG. 1 have the same configuration. Therefore, in the following description, any one of the encoder devices 1-1 to 1-n will be described as the encoder device 1. As shown in FIG. 2, the encoder device 1 includes a light emitting unit 11, a rotating disk 12, a light receiving unit 13, a waveform shaping circuit 14, a signal processing unit (a first code generation unit, a second code generation unit, a signal generation unit, A transmission unit) 15, a transmission / reception driver unit 16, and a storage unit 17.

  The light emitting unit 11 emits light to the rotating disk 12. The rotating disk 12 rotates directly or via a power transmission mechanism such as a gear device in accordance with the rotational displacement of the rotating shaft of the motor (or the rotational displacement or positional displacement of a member driven by the motor). A minute slit is formed in the rotating disk 12. The light emitted from the light emitting unit 11 passes through the slit of the rotating disk 12 according to the rotational displacement of the rotating disk 12, and is blocked by the portion of the rotating disk 12 where there is no slit. The light receiving unit 13 receives the light emitted from the light emitting unit 11 through the slit of the rotating disk 12 when the rotating disk 12 is in a predetermined rotational displacement. In addition, the light receiving unit 13 outputs an output signal to the waveform shaping circuit 14 in response to light reception. The waveform shaping circuit 14 shapes the output signal from the light receiving unit 13. The waveform shaping circuit 14 outputs the waveform-shaped signal to the signal processing unit 15. The signal processing unit 15 detects the rotational position displacement of the rotating disk 12 by performing predetermined arithmetic processing on the signal from the waveform shaping circuit 14. Thus, the encoder device 1 detects the rotational position displacement of the motor (or the rotational position displacement or position displacement of the member driven by the motor) by detecting the rotational position displacement of the rotating disk 12.

  The transmission / reception driver unit 16 performs a process of transmitting / receiving a signal to / from the host control device 2. In the present embodiment, the transmission / reception driver unit 16 performs a process of transmitting the encoded signal to the host control device 2. In addition, the transmission / reception driver unit 16 performs a process of receiving a command signal transmitted from the host control device 2. The storage unit 17 stores position data representing the rotational position displacement of the rotating disk 12 detected by the signal processing unit 15.

  The signal processing unit 15 reads the position data stored in the storage unit 17 in response to receiving the command signal transmitted from the host control device 2. Then, the signal processing unit 15 generates a CRC code for performing a cyclic redundancy check on the read position data. Here, the cyclic redundancy check is a method of detecting whether or not an error has occurred during transmission mainly in transmission of digital data in serial communication. On the data transmission side (the encoder device 1 or the host control device 2 in the present embodiment), redundant data called CRC code is generated using a cyclic algorithm (generation polynomial) for the data to be transmitted. Then, the data transmitting side adds the generated redundant data to the original data and transmits it. The data receiving side (the encoder device 1 or the host control device 2 in the present embodiment) applies the same algorithm as the transmitting side to the data to calculate redundant data. The receiving side determines whether or not the data is transmitted without error by determining whether or not the CRC code calculated on the transmitting side matches the CRC code calculated on the receiving side. In the present embodiment, the CRC code may be referred to as a “first code”.

  Further, the signal processing unit 15 generates an ECC code (ECC: Error Correcting Code) for performing error detection and correction on the read position data. The ECC code refers to redundant data added separately from the original data in order to correct a bit error (error) of the data. In the present embodiment, the signal processing unit 15 generates a Hamming code as an ECC code. Here, the Hamming code is a linear error correction code capable of detecting and correcting data errors. In the present embodiment, the ECC code may be referred to as a “second code”. Details of the ECC code will be described later (see FIG. 5).

  Further, the signal processing unit 15 generates an encoded signal having a serial communication format configuration based on the position data, the ECC code, and the CRC code. Then, the signal processing unit 15 transmits the generated encoded signal to the host control device 2 via the transmission / reception driver unit 16.

  FIG. 3 is a block diagram showing a configuration of the host controller shown in FIG. As shown in FIG. 3, the host controller 2 includes a transmission / reception driver unit 21, a control unit (reception unit, error detection unit, error correction unit, cyclic redundancy check unit) 22, and a memory 23. The transmission / reception driver unit 21 performs a process of transmitting / receiving a signal to / from each encoder device 1-1 to 1-n. In the present embodiment, the transmission / reception driver unit 21 performs a process of transmitting command signals to the encoder apparatuses 1-1 to 1-n. In addition, the transmission / reception driver unit 21 performs a process of receiving encoded signals transmitted from the encoder apparatuses 1-1 to 1-n.

  The control unit 22 generates a command signal having a serial communication format configuration. Then, the control unit 22 transmits the generated command signal to the encoder devices 1-1 to 1-n via the transmission / reception driver unit 21. Further, the control unit 22 receives encoded signals transmitted from the encoder devices 1-1 to 1-n via the transmission / reception driver unit 21. Then, based on the ECC code included in the received encoded signal, the control unit 22 performs error detection processing on the position data and ECC code included in the encoded signal. In addition, when a 1-bit error is detected in the position data or the ECC code by the error detection process, the control unit 22 performs an error correction process for correcting the 1-bit error. Note that error detection processing and error correction processing may be collectively referred to as error detection correction processing.

  In addition, when no error is detected by the error detection process, and when a 1-bit error is corrected by the error correction process, the control unit 22 performs positional data (if error correction process is executed, after error correction process) Cyclic redundancy check is performed on (position data). Further, when it is determined by the cyclic redundancy check that there is no error, the control unit 22 controls the rotation amount of each motor corresponding to each encoder device 1-1 to 1-n based on the position data. The control unit 22 determines that the encoded signal is not normally received when an error of 2 bits or more is detected by the error detection process and when it is determined that there is an error by the cyclic redundancy check. In this case, the control unit 22 does not control the rotation amount of the motor based on the position data included in the encode signal. Alternatively, the control unit 22 transmits a command signal requesting the encoder apparatus 1 to retransmit the encoded signal.

  The memory 23 stores encoded signal data (information such as position data, ECC code, and CRC code). The control unit 22 performs error detection processing, error correction processing, and cyclic redundancy check based on the position data, ECC code, and CRC code stored in the memory 23.

  As described above, in this embodiment, error detection and error correction are performed using an ECC code as well as data error detection using a cyclic redundancy check using a CRC code. Although error detection (cyclic redundancy check) using a CRC code has a higher bit error detection capability than error detection using an ECC code, it cannot correct a bit error. On the other hand, error detection and error correction using ECC codes can correct bit errors, but have a low bit error detection capability. Also, error detection and error correction using an ECC code alone may cause error correction if a burst error (a continuously appearing error) or a multi-bit error occurs. Lack of ability. For this reason, in this embodiment, error detection and error correction using an ECC code are performed so that error correction can be performed. At the same time, error detection using a CRC code is performed in order not to reduce the error detection capability.

  Next, a specific example of the configuration of the encode signal will be described. FIG. 4 is a diagram showing the format configuration of the encoded signal in the first embodiment. In FIG. 4, a command signal for notifying the command A, an encoding signal for notifying the data A (for example, motor position data) corresponding to the command A, and a command signal for notifying the command B The encoding signal for notifying data B (for example, motor position data) corresponding to the command B is transmitted on the transmission line 3. 4 enlarges and displays the encode signal for notifying the data A and enlarges and displays the data in the data field DF0 constituting the encode signal.

  In the example shown in FIG. 4, the encode signal is composed of four data fields DF0 to DF3. As shown in FIG. 4, the data field DF0 is composed of 23 bits. Specifically, the data field DF0 includes a 1-bit start bit (“Start bit” in FIG. 4), a 1-bit stop bit (“Stop bit” in FIG. 4), and a 16-bit data bit (FIG. 4). "D0 to D15: Data bit") and 5 parity bits ("P1, P2, P4, P8, P16: Parity bit for ECC" in FIG. 4).

  Here, the start bit is a bit indicating the start (that is, the first) of the data field DF0. The start bit is binary “0” data, and is set to the first bit of the data field DF0. The stop bit is a bit indicating the end (that is, the last) of the data field DF0. The stop bit is binary “1” data, and is set to the last bit of the data field DF0.

  The data bits (D0 to D15) are bits for setting binary data (position data) to be notified to the host controller 2. The data bits (D0 to D15) are set from the bit next to the start bit to the bit before the stop bit, respectively. The leading bit of the data bit is referred to as LSB (Least Significant Bit). The last bit of the data bits is called MSB (Most Significant Bit).

  The parity bits (P1, P2, P4, P8, P16) are ECC bits (that is, ECC codes). The parity bit (P1) is inserted into the bit immediately before the stop bit. The parity bit (P2) is inserted into the bit immediately before the parity bit (P1). The parity bit (P4) is inserted between the data bit (D14) and the data bit (D15). The parity bit (P8) is inserted between the data bit (D11) and the data bit (D12). The parity bit (P16) is inserted between the data bit (D4) and the data bit (D5).

  Note that the data fields DF1 to DF3 also have a data configuration common to the data field DF0 (a common bit length and a common bit arrangement). That is, the data fields DF1 to DF3 are also composed of 1 start bit, 1 stop bit, 16 data bits, and 5 parity bits, and the arrangement of these bits is also common to the data field DF0. It has become.

  FIG. 5 is a diagram showing data allocation of each data field. As shown in FIG. 5, in the data field DF0, the first three bits (D0 to D2) of the data bits are “001” as a synchronization code (sync code, Sync. Code) used for synchronization of serial communication. A fixed value is set. In the data field DF0, position data is set in the fourth and subsequent bits (D3 to D15) of the data bits. In the data fields DF1 and DF2, position data is set in all bits (D0 to D15). In the data field DF3, position data is set in the first 8 bits (D0 to D7) of the data bits. In the data field DF3, the CRC code generated by the signal processing unit 15 is set in the ninth and subsequent bits (D8 to D15) of the data bits. The CRC code is obtained by the signal processor 15 by removing the start bit, stop bit, and ECC parity bits (P1, P2, P4, P8, P16) in each data field DF0 to DF3, that is, each data field DF0. Generated for data bits (D0 to D15) of DF3.

  Further, as shown in FIG. 5, the parity bit (P1) constituting the ECC code is generated by the signal processing unit 15 as data bits (D15, D14, D12, D11, D9, D7, D5, D4, D2, D0). Calculated by taking exclusive OR. The parity bit (P2) is calculated by the signal processing unit 15 taking an exclusive OR of the data bits (D15, D13, D12, D10, D9, D6, D5, D3, D2). The parity bit (P4) is calculated by the signal processing unit 15 taking an exclusive OR of the data bits (D14, D13, D12, D8, D7, D6, D5, D1, D0). The parity bit (P8) is calculated by the signal processing unit 15 taking an exclusive OR of the data bits (D11, D10, D9, D8, D7, D6, D5). The parity bit (P16) is calculated by the signal processing unit 15 taking an exclusive OR of the data bits (D4, D3, D2, D1, D0).

  As shown in FIGS. 4 and 5, the parity bits (P1, P2, P4, P8, P16) constituting the ECC code are added at positions that do not overlap with the synchronization code used for serial communication synchronization. . That is, the synchronization code is added to the first three bits (D0 to D2) of the data bits in the data field DF0, whereas the parity bits (P1, P2, P4, P8, P16) It is added to the 1st bit, 2nd bit, 4th bit, 8th bit and 16th bit from the MSB side in fields DF0 to DF3.

  Since the synchronization code needs to be synchronized at the start of signal reception, it is always added to the first 3 bits (D0 to D2) of the data bits in the data field DF0. Temporarily, parity bits (P1, P2, P4, P8, P16) are added to the 1st, 2nd, 4th, 8th, and 16th bits from the LSB side in each data field DF0 to DF3, respectively. Then, the parity bits (P1, P2) are arranged at the position where the synchronization code should be arranged in the data field DF0. In this case, synchronization cannot be established between the encoder device 1 and the host control device 2 at the start of signal reception. In order to avoid such a situation, the parity bits (P1, P2, P4, P8, P16) are the first bit, the second bit, the fourth bit from the MSB side in each data field DF0 to DF3, respectively. It is added to the 8th, 16th and 16th bits.

  Next, a serial communication method using the control system SYS will be described.

  FIG. 6 is a flowchart illustrating an example of an encoding signal transmission process by the signal processing unit. In the process shown in FIG. 6, first, the signal processing unit 15 determines whether or not a command signal transmitted from the host controller 2 has been received (step S1). The signal processing unit 15 repeatedly executes the process of step S1 until a command signal is received. When determining that the command signal has been received, the signal processing unit 15 reads position data, which is a binary digital signal corresponding to the command signal stored in the storage unit 17 (step S2). Then, the signal processing unit 15 generates an 8-bit CRC code for the position data (step S3). As described above, the signal processing unit 15 generates an 8-bit CRC code for the data bits (D0 to D15) of the data fields DF0 to DF3, using a generator polynomial previously determined with the host controller 2. To do.

  Further, the signal processing unit 15 generates a 5-bit ECC code (P1, P2, P4, P8, P16) for the position data (including the CRC code generated in step S3) for each data field (step S4). . As described above, the signal processing unit 15 generates a 5-bit ECC code by performing an exclusive OR operation (XOR operation) on predetermined data bits in each of the data fields DF0 to DF3.

  Next, the signal processing unit 15 generates an encoded signal having a serial communication format configuration based on the position data, the CRC code, and the ECC code (step S5). Specifically, the signal processing unit 15 inserts “0” into the start bits of the data fields DF0 to DF3 and inserts “1” into the stop bits of the data fields DF0 to DF3. Further, the signal processing unit 15 inserts “001” as a synchronization code in the first three bits (D0 to D2) of the data bits in the data field DF0. In addition, the signal processing unit 15 inserts position data into data bits (except for the bit position of the synchronization code) in each of the data fields DF0 to DF3. Further, the signal processing unit 15 inserts the 8-bit CRC code generated in step S3 into the last 8 bits (D8 to D15) of the data bits in the final data field DF3. In addition, the signal processing unit 15 inserts the 5-bit ECC code generated in step S4 into predetermined bit positions (see FIG. 4) in the data fields DF0 to DF3. Thereafter, the signal processing unit 15 transmits the encoded signal generated in step S5 to the host control device 2 via the transmission / reception driver unit 16 (step S6).

  FIG. 7 is a flowchart illustrating an example of an encoding signal reception process performed by the control unit. In the process shown in FIG. 7, after detecting the start bit in the first data field DF0 of the encoded signal (step S11), the control unit 22 detects the synchronization code (“001”) (step S12). When detecting the synchronization code, the control unit 22 sequentially receives serial data after the synchronization code (digital data of the data fields DF0 to DF3) (step S13). Specifically, the control unit 22 receives data bits and parity bit data of the data field DF0 after detecting the synchronization code. After that, the control unit 22 recognizes the switching of the data field by detecting the stop bit and the start bit of the next data field, and then receives the data bit and parity bit data of each data field. The control unit 22 stores the received serial data in the memory 23. In this way, the serial communication can be synchronized with the encoder device 1 by sequentially receiving the serial data after the control unit 22 detects the synchronization code. Therefore, it is possible to prevent the synchronization deviation between the encoder device 1 and the host control device 2 from occurring.

  Next, the control unit 22 performs error detection (error detection) using an ECC code for each data field based on the received serial data (step S14). Specifically, the control unit 22 calculates the following values of C1, C2, C4, C8, and C16.

  C1 is calculated by taking the exclusive OR of the parity bit (P1) and the data bits (D15, D14, D12, D11, D9, D7, D5, D4, D2, D0). That is, the control unit 22 calculates the value of C1 by performing an XOR operation of C1 = XOR of bits (P1, D15, D14, D12, D11, D9, D7, D5, D4, D2, D0). C2 is calculated by taking the exclusive OR of the parity bit (P2) and the data bits (D15, D13, D12, D10, D9, D6, D5, D3, D2). That is, the control unit 22 calculates the value of C2 by performing an XOR operation of C2 = XOR of bits (P2, D15, D13, D12, D10, D9, D6, D5, D3, D2). C4 is calculated by taking the exclusive OR of the parity bit (P4) and the data bits (D14, D13, D12, D8, D7, D6, D5, D1, D0). That is, the control unit 22 calculates the value of C4 by performing an XOR operation of C4 = XOR of bits (P4, D14, D13, D12, D8, D7, D6, D5, D1, D0). C8 is calculated by taking the exclusive OR of the parity bit (P8) and the data bits (D11, D10, D9, D8, D7, D6, D5). That is, the control unit 22 calculates the value of C8 by performing an XOR operation of C8 = XOR of bits (P8, D11, D10, D9, D8, D7, D6, D5). C16 is calculated by taking the exclusive OR of the parity bit (P16) and the data bits (D4, D3, D2, D1, D0). That is, the control unit 22 calculates the value of C16 by performing an XOR operation of C16 = XOR of bits (P16, D4, D3, D2, D1, D0).

  Then, the control unit 22 calculates the value of C by substituting the values of C16, C8, C4, C2, and C1 into the calculation formula of C = C16 * 16 + C8 * 8 + C4 * 4 + C2 * 2 + C1. For example, when the value of C is 0, it means that no bit error has occurred in all bits (21 bits) except the start bit and stop bit in the data field. In addition, when the value of C is 1, it means that a bit error has occurred in the first bit (that is, the bit of D0) of the bits other than the start bit and the stop bit in the data field. Further, when the value of C is 10, it means that a bit error has occurred in the 10th bit (that is, the bit of D8) of the bits excluding the start bit and stop bit in the data field. In addition, when the value of C is 21, it means that a bit error has occurred in the 21st bit (that is, the bit of P1) of the bits other than the start bit and the stop bit in the data field. Further, when the value of C is 22 or more, it means that a bit error of 2 bits or more has occurred in the bits other than the start bit and stop bit in the data field.

  The control unit 22 determines whether or not the value of C calculated in step S14 is 0 (step S15). When the control unit 22 determines that the value of C is 0, the control unit 22 proceeds to the process of step S16. Further, when determining that the value of C is not 0, the control unit 22 determines whether or not the value of C is any one of 1 to 21 (step S17). When it is determined that the value of C is any of 1 to 21, the control unit 22 determines that a 1-bit error has occurred and performs a 1-bit error correction process (error correction process) ( Step S18). Specifically, the control unit 22 specifies the position of an erroneous bit based on the value of C, and inverts the value of the bit. That is, “1” is set to “0”, and “0” is set to “1”. And the control part 22 transfers to the process of step S16. If the control unit 22 determines that the value of C is not any of 1 to 21, that is, if it is determined that the value of C is 22 or more, an error (error) of 2 bits or more exists. Is determined (step S20). In this case, since the received data is abnormal, the control unit 22 stops the control of the motor (control target) based on the data. Alternatively, the control unit 22 transmits a command signal requesting the encoder apparatus 1 to retransmit the encoded signal.

  The control unit 22 executes the processes in steps S15, S17, and S18 as described above for each data field. Only when an error of 2 bits or more is not detected in all of the four data fields DF0 to DF3 (Yes in Step S15, Yes in Step S17), the control unit 22 executes the process of Step S16. To do. That is, when an error of 2 bits or more is detected in one data field among the four data fields DF0 to DF3 (No in step S17), the control unit 22 does not execute the process in step S16.

  When the control unit 22 determines that no bit error has occurred in the process of step S15 (error detection process) (Yes in step S15), the data bit data (D0 to D15) in each normal data field DF0 to DF3. ) Is executed (step S16). In addition, when the control unit 22 performs a 1-bit error correction process based on the detection of a 1-bit bit error in the process of step S17 (error detection process) (Yes in step S17, step S18), A cyclic redundancy check is performed on the data bits data (D0 to D15) of the data fields DF0 to DF3 after the error correction process (step S16).

  In the process of step S16, the control unit 22 generates an 8-bit CRC code for the data bits (D0 to D15) of the data fields DF0 to DF3, using a generator polynomial previously determined with the encoder device 1. To do. Then, the control unit 22 determines whether or not the generated CRC code matches the CRC code added to the data field DF3 of the encoded signal. When it is determined that the CRC codes match, the control unit 22 determines that no error (error) exists in the data bits (D0 to D15) of the data fields DF0 to DF3 (No in step S16, step S16). S19). In this case, the control part 22 performs control of a motor (control object) based on normal data (position data).

  On the other hand, when determining that the CRC codes do not match, the control unit 22 determines that an error exists in the data bits (D0 to D15) of the data fields DF0 to DF3 (step S16). Yes, step S20). In this case, since the received data is abnormal, the control unit 22 stops the control of the motor based on the data. Alternatively, the control unit 22 transmits a command signal requesting the encoder apparatus 1 to retransmit the encoded signal.

  As described above, according to the first embodiment, data transmission is performed by serial communication between the transmission device (encoder device 1 in the above example) and the reception device (higher level control device 2 in the above example). The communication device, the transmission device 1, includes a first code generation unit (a part of the signal processing unit 15) that generates a first code (CRC code) for performing cyclic redundancy check on data. A second code generation unit (a part of the signal processing unit 15) for generating a second code (ECC code) for performing error detection and error correction on the data, and at least the data, the first code And a transmission unit (a part of the processing unit of the signal processing unit 15) that transmits a serial communication system signal including the second code. According to such a configuration, the occurrence of errors (bit errors) can be reduced. That is, by adding an ECC code to a signal, it is possible to correct an error within the range of error correction capability of the ECC code. Further, by adding a CRC code to a signal, it is possible to detect an error with a higher detection capability than the ECC code.

  In the first embodiment described above, the receiving device 2 receives a signal transmitted from the transmitting device 1 (a part of the processing unit of the control unit 22), and the data error based on the second code. An error detection unit (a part of the control unit 22) that performs detection, and an error correction unit (a part of the control unit 22) that corrects an error when a data error is detected by the error detection unit And a cyclic redundancy check unit (a part of the control unit 22) that performs a cyclic redundancy check of data based on the first code. According to such a configuration, it is possible to perform a cyclic redundancy check on data after performing error correction on the data. Therefore, it is possible to prevent a situation in which errors frequently occur in the cyclic redundancy check.

  In the first embodiment described above, the signal includes a plurality of fields, and the second code generation unit generates a second code for the data of each field. According to such a configuration, it is possible to detect and correct errors in units of fields. Accordingly, the error detection capability and the error correction capability are improved. Further, the first code generation unit generates a first code for data of a plurality of fields. According to such a configuration, high error detection capability can be ensured, and the first code generation process can be simplified as compared with the case where the first code is generated for each field. As a result, the processing burden on the transmission device and the reception device does not increase.

  In addition, according to the first embodiment described above, the signal generation unit (part of the processing unit of the control unit 22) that generates a serial communication method signal is provided, and the signal generation unit is configured to synchronize communication in the signal. The second code is added at a position that does not overlap with the synchronization code (sync code) used in the above. According to such a configuration, it is possible to avoid a situation in which synchronization cannot be added between the transmission device 1 and the reception device 2 without adding a synchronization code.

  In the first embodiment described above, the signal generation unit adds the second code from the most significant side of the signal, so that the second code can be surely arranged at a position that does not overlap with the synchronization code. Further, since the second code is a Hamming code, an error of 1 bit per field can be corrected.

  In the first embodiment described above, the transmission device is the encoder device 1 that transmits an encoded signal including position data as data, and the reception device controls a control target (for example, a motor) based on the position data. It is a control device (high-order control device 2). According to such a configuration, it is possible to reduce the occurrence of errors (bit errors) in data transmitted by serial communication in the control system SYS using the encoder device.

  In the first embodiment described above, the addition of the CRC code and the ECC code in the encoded signal transmitted from the encoder apparatus 1 to the upper control apparatus 2 has been described. However, a CRC code and an ECC code may also be added to a command signal transmitted from the host control device 2 to the encoder device 1. That is, the transmission device may be a control device (higher-order control device 2) that transmits a command signal including a command as data, and the reception device may be the encoder device 1 that transmits an encode signal in response to the command.

  In order to realize such a configuration, the host controller 2 corresponds to the signal processing unit (first code generation unit, second code generation unit, signal generation unit, transmission unit) 15 shown in FIG. Should be provided. In addition, the encoder apparatus 1 may have a configuration corresponding to the control unit (reception unit, error detection unit, error correction unit, cyclic redundancy check unit) 22 illustrated in FIG. The data structure of the command signal may be the data structure of the encode signal shown in FIGS. 4 and 5 or a data structure close thereto.

Second Embodiment
In the first embodiment described above, the signal processing unit 15 is configured to add the ECC code from the most significant side of the data bits so that the ECC code does not overlap with the synchronization code. However, in the second embodiment, the signal processing unit 15 is configured to add the ECC code from the least significant side of the data bits.

  FIG. 8 is a diagram illustrating a format configuration of an encode signal in the second embodiment. In the data field DF0 of the encode signal shown in FIG. 8, unlike the data field DF0 of the encode signal shown in FIG. 4, 3 bits “000” are added to the head of the data field DF0 as a start bit. The 3-bit start bit “000” serves to indicate the start (that is, the first) of the data field DF0 and also serves as a synchronization code. In the case of this data configuration, the bit length of the data field DF0 is increased by 2 bits to 25 bits.

  In such a configuration, the control unit 22 detects the start bit “000” in the first data field DF0 of the encode signal, and then serial data after the start bit “000” (digital data of each data field DF0 to DF3). Are received sequentially. Thereby, it is possible to synchronize serial communication with the encoder device 1 and to add an ECC code from the least significant side of the data bits.

  Note that only the start bit of the data field DF0 of the encoded signal shown in FIG. 8 is 3 bits, and the start bits of the other data fields DF1 to DF3 are 1 bit “0”. However, the present invention is not limited to this configuration, and the start bits of all the data fields DF0 to DF3 may be 3 bits “000”. Also, in the command signal transmitted from the host control device 2 to the encoder device 1, the start bit may be set to 3 bits “000” as shown in FIG.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various modifications or improvements can be added to the above-described embodiment without departing from the spirit of the present invention. In addition, one or more of the requirements described in the above embodiments may be omitted. Such modifications, improvements, and omitted forms are also included in the technical scope of the present invention. In addition, the configurations of the above-described embodiments and modifications can be applied in appropriate combinations.

  The above-described control system SYS shown in FIG. 1 is a bus-connected (Multi-Point) control system in which one host control device 2 is connected to a plurality of encoder devices 1-1 to 1-n via a transmission line 3. Met. However, the control system is not limited to such a connection type control system, but is a one-to-one connection type (Point-to-point) control system in which one host control device is connected to one encoder device via a transmission line. There may be. For example, a system in which an encoder device measures the rotational position displacement of a servo motor as a control target, and a servo amplifier as a host control device controls the drive of the servo motor based on an encode signal (position data) from the encoder device It is.

  In FIG. 7 described in the first embodiment, the control unit 22 performs error detection and error correction using an ECC code (see steps S15, S17, and S18), and then error detection using a CRC code (cyclic redundancy check: Step S16) is performed. However, the control unit 22 may perform error detection using the CRC code before error detection and error correction using the ECC code. In this case, when no error is detected in the error detection using the CRC code, the control unit 22 determines that there is no error without executing the error detection using the ECC code. On the other hand, when an error is detected in error detection using the CRC code, the control unit 22 performs error detection using the ECC code. When the controller 22 detects a 1-bit error in the error detection using the ECC code, the controller 22 executes a 1-bit error correction process. Then, the control unit 22 again performs error detection using a CRC code based on the data after error correction processing. Further, the control unit 22 determines that there is an error when an error of 2 bits or more is detected in the error detection by the ECC code. According to such a configuration, when the error detection by the CRC code does not frequently determine that there is an error, the number of executions of the error detection process by the ECC code can be reduced, and the processing load can be reduced. it can.

  In each of the above embodiments, the encoder device 1 is configured to read the position data stored in the storage unit 17 in response to receiving the command signal transmitted from the host control device 2. . However, the encoder device 1 detects the rotational position displacement of the motor in response to receiving the command signal transmitted from the host control device 2, and obtains position data corresponding to the detected rotational position displacement. Also good.

  In each of the above-described embodiments, the plurality of encoder devices 1-1 to 1-n are assigned identification information for identifying each device, and each of the encoder devices 1-1 to 1-n includes an encoder signal. You may make it add identification information to.

  In each of the above embodiments, the number of data fields of the encode signal is four, but it may be less than four or five or more. In the first embodiment described above, the bit length (number of bits) of each of the data fields DF0 to DF3 of the encode signal is 23 bits, but may be less than 23 bits or 24 bits or more.

  Further, the data configuration of the encode signal and the command signal may be the same or different. For example, the number of encoded signal data fields may be different from the number of command signal data fields, and the bit length of each data field may be different. Further, the signal processing unit 15 (or the control unit 22) may generate a CRC code for each data field. Further, the signal processing unit 15 (or the control unit 22) may divide one data field into two or more sections and generate an ECC code in each section. The CRC code is inserted in the latter half of the final data field, but may be inserted in a data field different from the final data field. Further, although the Hamming code is used as the ECC code, an ECC code other than the Hamming code (for example, a cyclic Hamming code) may be used.

  DESCRIPTION OF SYMBOLS 1 ... Encoder apparatus (transmission apparatus, reception apparatus), 2 ... High-order control apparatus (transmission apparatus, reception apparatus, control apparatus), 3 ... Transmission line, 15 ... Signal processing part (1st code generation part, 2nd code generation part) , Signal generation unit, transmission unit), 17 ... storage unit, 22 ... control unit (reception unit, error detection unit, error correction unit, cyclic redundancy check unit), 23 ... memory

Claims (12)

A communication device that performs data transmission by serial communication between a transmission device and a reception device,
The transmitter is
A first code generator for generating a first code for performing cyclic redundancy check on the data;
A second code generation unit for generating a second code for performing error detection and error correction on the data;
And a transmission unit that transmits a signal of a serial communication method including at least the data, the first code, and the second code. The receiving device is:
A receiver for receiving the signal transmitted from the transmitter;
An error detection unit that performs error detection of the data based on the second code;
When an error in the data is detected by the error detection unit, an error correction unit that corrects the error; and
The communication apparatus according to claim 1, further comprising: a cyclic redundancy check unit that executes the cyclic redundancy check of the data based on the first code. The signal is composed of a plurality of fields,
The communication apparatus according to claim 1, wherein the second code generation unit generates the second code for each field of data.   The communication apparatus according to claim 3, wherein the first code generation unit generates the first code for the data of the plurality of fields. A signal generation unit for generating a signal of the serial communication method;
The communication apparatus according to claim 1, wherein the signal generation unit adds the second code to a position in the signal that does not overlap with a synchronization code used for communication synchronization.   The communication apparatus according to claim 5, wherein the signal generation unit adds the second code from the most significant side of the signal.   The communication apparatus according to claim 1, wherein the second code is a Hamming code. The transmission device is an encoder device that transmits an encoding signal including position data as the data,
The communication device according to claim 1, wherein the reception device is a control device that controls a control target based on the position data. The transmission device is a control device that transmits a command signal including a command as the data,
The communication device according to claim 1, wherein the reception device is an encoder device that transmits an encoded signal in response to the command. A first code generator for generating a first code for performing cyclic redundancy check on the data;
A second code generation unit for generating a second code for performing error detection and error correction on the data;
An encoder apparatus comprising: a transmission unit that transmits at least a signal of a serial communication method including the data, the first code, and the second code. A serial communication method for transmitting data by serial communication,
Generating a first code for performing a cyclic redundancy check on the data;
Generating a second code for performing error detection and error correction on the data;
A serial communication method including transmitting a signal of a serial communication method including at least the data, the first code, and the second code. Receiving the signal;
Performing error detection of the data based on the second code;
If an error in the data is detected by the error detection, correcting the error;
The serial communication method according to claim 11, further comprising: executing the cyclic redundancy check of the data based on the first code.

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