JP2015044727A - MANUFACTURING METHOD FOR SiC EPITAXIAL WAFER - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for an SiC epitaxial wafer that reduces short carrot defects generated in an epitaxial layer.SOLUTION: A manufacturing method for an SiC epitaxial wafer includes a step S4 of supplying a first gas containing a silicon atom and a second gas containing a carbon atom to an SiC substrate to form a silicon carbide semiconductor layer by epitaxial growth on the SiC substrate, a step S5 of stopping supply of at least one of the first gas and the second gas to the SiC substrate for 20 seconds or longer and annealing the SiC substrate under a reducing gas atmosphere, and a step S6 of supplying the first gas containing a silicon atom and the second gas containing a carbon atom to the SiC substrate to form a silicon carbide semiconductor layer by epitaxial growth on the SiC substrate.

Description

  The present invention relates to an epitaxial wafer manufacturing method used for SiC power devices and the like.

  SiC (silicon carbide) has attracted attention as a power device material for power control in recent years because of its large band gap, dielectric breakdown field strength, saturation drift velocity, and thermal conductivity compared to Si (silicon). In SiC power devices, power loss can be significantly reduced and miniaturization can be achieved, and energy saving can be realized during power supply power conversion. For this reason, the SiC power device is considered to be a key device for realizing a low-carbon society, such as a high-performance electric vehicle and a high-performance solar cell system.

  In manufacturing a SiC power device, it is necessary to epitaxially grow an active region of a semiconductor device on a SiC bulk substrate in advance by a CVD method (Chemical Vapor Deposition) or the like. Here, the active region is a cross-sectional region including a growth direction axis which is formed after the doping density and film thickness in the crystal are precisely controlled. The reason why the epitaxial layer is required in addition to the bulk substrate is that the doping density and the film thickness are almost prescribed by the specifications of the device, and usually the accuracy is higher than that of the bulk substrate.

  In this specification, an epitaxially grown wafer on a (bulk) substrate is called an epitaxial wafer. The device is manufactured by performing various processes on the epitaxial wafer. For this reason, if some regions in the epitaxial wafer surface have a smaller dielectric breakdown electric field than other regions, or if a current flowing when a certain electric field is applied is larger than other regions, the electrical Adversely affects the physical properties. That is, for example, the withstand voltage characteristic is inferior, or a leak current flows due to a relatively small applied voltage. Therefore, it can be said that the number (device yield) in which devices having desired characteristics are manufactured from a single wafer is primarily defined by the uniformity of electrical characteristics in the epitaxial layer.

  Various current leak defects caused by epitaxial growth are known as a cause of hindering the uniformity of electrical characteristics in the epitaxial layer. A feature common to current leak defects is that the periodicity of atomic arrangement in the crystal is locally incomplete along the crystal growth direction. As one of current leak defects caused by stacking faults, carrot defects generated by SiC epitaxial growth are known. The carrot defect is characterized by the surface shape of the epitaxial layer.

  As a method for suppressing the occurrence of carrot defects, for example, Patent Document 1 discloses a method of interrupting epitaxial growth by introducing an etching gas instead of a source gas during an epitaxial growth process to form a highly doped defect buffer layer. ing. Carrot defects are terminated by the highly doped defect buffer layer, and then epitaxial growth is performed again.

Special table 2007-525402 gazette

  In recent years, SiC devices having a high breakdown voltage have been actively developed, and an epitaxial layer serving as a device active layer has been made thicker. Up to now, the origin of carrot defects has been mostly near the interface with the SiC substrate. However, as the thickness of the epitaxial layer increases, the number of carrot defects with the origin in the epitaxial layer away from the interface with the SiC substrate increases. This has been clarified by the inventors' research.

  A carrot defect having an origin in the epitaxial layer is referred to as a short carrot defect in this specification because its length is shorter than that of a carrot defect generated near the interface with the SiC substrate. The short carrot defect occurs because the internal stress increases due to the thickening of the epitaxial layer. Therefore, if the epitaxial layer is made thicker by further increasing the breakdown voltage of the SiC device in the future, it is important to reduce short carrot defects in order to obtain a high-quality epitaxial wafer.

  However, according to the method of Patent Document 1, in order to prevent the propagation of carrot defects generated from the interface with the SiC substrate, a highly doped defect buffer layer is formed in the vicinity of the interface. Reduction of carrot defects has been difficult. In addition, since it is necessary to introduce an etching gas and etch the epitaxial layer by several μm after epitaxial growth, there is also a problem that productivity is inferior from the viewpoints of material gas utilization efficiency, etching gas cost, and process time. .

  In view of the above-described problems, an object of the present invention is to provide a method for manufacturing an SiC epitaxial wafer that reduces short carrot defects.

  The SiC epitaxial wafer manufacturing method of the present invention includes (a) a step of preparing an SiC substrate having an off angle of less than 5 degrees and a polytype of 4H, and (b) a silicon carbide semiconductor layer on the SiC substrate. And (b1) supplying a first gas containing silicon atoms and a second gas containing carbon atoms to the SiC substrate to epitaxially grow a silicon carbide semiconductor layer on the SiC substrate. (B2) After step (b1), the supply of at least one of the first and second gases to the SiC substrate is stopped for 20 seconds or more, and the SiC substrate is annealed in a reducing gas atmosphere; b3) After the step (b2), the first gas containing silicon atoms and the second gas containing carbon atoms are supplied to the SiC substrate to epitaxially form the silicon carbide semiconductor layer on the SiC substrate. Comprising the steps of, a.

  The SiC epitaxial wafer manufacturing method of the present invention includes (a) a step of preparing an SiC substrate having an off angle of less than 5 degrees and a polytype of 4H, and (b) a silicon carbide semiconductor layer on the SiC substrate. And (b1) supplying a first gas containing silicon atoms and a second gas containing carbon atoms to the SiC substrate to epitaxially grow a silicon carbide semiconductor layer on the SiC substrate. (B2) After step (b1), the supply of at least one of the first and second gases to the SiC substrate is stopped for 20 seconds or more, and the SiC substrate is annealed in a reducing gas atmosphere; b3) After the step (b2), the first gas containing silicon atoms and the second gas containing carbon atoms are supplied to the SiC substrate to epitaxially form the silicon carbide semiconductor layer on the SiC substrate. Comprising the steps of, a. Since the internal stress generated in the epitaxial layer is reduced by annealing in the step (b2), short carrot defects can be suppressed.

1 is a cross-sectional view showing a structure of a SiC epitaxial wafer according to a first embodiment. 3 is a flowchart showing a manufacturing process of the SiC epitaxial wafer according to the first embodiment. It is a figure which shows the temperature profile and gas sequence in a reaction furnace in the manufacturing process of the SiC epitaxial wafer which concerns on Embodiment 1. FIG. It is a figure which shows the change of the short carrot defect reduction rate by the continuous growth film thickness of an epitaxial layer. It is a figure which shows the change of the short carrot defect reduction rate by the supply stop time of source gas. It is a figure which shows the Nomarski differential interference optical microscope image of a Carrot defect. It is a figure which shows the Nomarski differential interference optical microscope image of a short carrot defect. 6 is a cross-sectional view showing a structure of a SiC epitaxial wafer according to a second embodiment. FIG.

<A. Prerequisite technology>
FIG. 6 shows a Nomarski differential interference optical microscope image of a carrot defect observed in a bright field condition. When an epitaxial layer was grown on a 4H-SiC substrate of 4 ° off by 30 μm, carrot defects were generated in the epitaxial layer. Since epitaxial growth proceeds in step flow mode, carrot defects generally extend in the <11-20> direction. One of the causes of carrot defects is lattice strain caused by the difference in impurity concentration between the SiC substrate and the epitaxial layer. For this reason, carrot defects tend to be generated from the vicinity of the interface with the SiC substrate where the lattice strain is maximized.

  When the distance in the depth direction from the outermost surface of the epitaxial layer to the origin of occurrence of carrot defects is d, the length in the <11-20> direction (carrot defect length) is L, and the substrate off angle is θ, the following equation is established. .

  In the example of FIG. 6, L = 420 μm, and d≈30 μm from the equation (1). Therefore, it can be seen that the carrot defect in FIG. 6 occurs near the interface with the SiC substrate and is caused by lattice distortion.

  However, when the film thickness of the epitaxial layer is increased to about 30 μm, a carrot defect having d that is clearly smaller than the film thickness occurs. FIG. 7 shows a Nomarski differential interference optical microscope image of carrot defects observed under bright field conditions for another region of the same sample as FIG. The carrot defect length of FIG. 7 is about 200 μm, which is clearly shorter than the carrot defect length of FIG. Further, from the formula (1), d = 16 μm. That is, it can be seen that the starting point of the occurrence of the carrot defect is not in the vicinity of the interface with the SiC substrate but in the epitaxial layer.

  Therefore, in this specification, the carrot defect of FIG. 7 is distinguished from the carrot defect of FIG. 6 and is referred to as a short carrot defect. More precisely, when the film thickness of the epitaxial layer is t (μm), a case where td ≦ 5 (μm) is satisfied is a normal carrot defect, and a case where td> 5 (μm) is satisfied is a short carrot. It is defined as a defect.

  According to an investigation by the inventor, there are no academic reports on short carrot defects at this time. This is because a short-carrot defect does not exist in a device-developed epitaxial wafer having a breakdown voltage of 2 kV or less. As a result of increasing the epitaxial layer thickness by increasing the breakdown voltage of SiC devices in recent years and improving high-speed growth technology for defect observation capability and cost reduction, the existence of short carrot defects was found for the first time. When an epitaxial wafer having a growth film thickness of 30 μm is manufactured, the generation ratio of carrot defects and short carrot defects is approximately 1. Therefore, in order to produce a high-quality epitaxial wafer, it is important to reduce short carrot defects.

<B. Embodiment 1>
<B-1. Configuration>
FIG. 1 is a cross-sectional view showing the structure of SiC epitaxial wafer 10 according to the first embodiment. The SiC epitaxial wafer 10 includes an SiC substrate 1 having an off angle of 4 degrees, a diameter of 3 inches, and a polytype of 4H, and an epitaxial layer E formed on the SiC substrate 1. The epitaxial layer E is formed by a multi-stage growth method, which will be described later, which is formed by alternately repeating epitaxial growth and annealing treatment. The epitaxial layer E is formed in order by a plurality of epitaxial growth steps, and is sequentially formed. It has a multilayer structure composed of the epitaxial layer E3. The thickness of the epitaxial layer E is, for example, 30 μm, and the thickness of each of the epitaxial layers E1 to E3 is, for example, 10 μm. The epitaxial layer E is not limited to the three layers shown in FIG.

<B-2. Manufacturing process>
FIG. 2 is a flowchart showing a manufacturing process of SiC epitaxial wafer 10. Hereinafter, the manufacturing process of the SiC epitaxial wafer 10 will be described with reference to FIG.

  First, a planarization process is performed on the SiC substrate 1 by chemical mechanical polishing using mechanical polishing and a chemical solution exhibiting acidity or alkalinity. Furthermore, ultrasonic cleaning is performed using acetone to remove organic substances from the surface of the SiC substrate 1. In addition, a cleaning process using sulfuric acid / hydrogen peroxide, a cleaning process using ammonia / hydrogen peroxide, and a cleaning process using hydrochloric acid / water are performed on the SiC substrate 1. The preceding is the pre-epitaxial process (step S1).

  Next, the SiC substrate 1 is introduced into an epitaxial growth apparatus. For example, the SiC substrate 1 is placed on a graphite substrate holder coated with SiC and placed in a reaction furnace in a CVD apparatus. In order to prevent unintended molecules and atomic impurities remaining in the reaction furnace from entering the epitaxial layer, the reaction furnace is evacuated to a high vacuum state.

  Thereafter, reducing gas is introduced into the reaction furnace. As the reducing gas, for example, hydrogen gas that can also be used as a carrier gas for carrying the source gas is used. The pressure of the reaction furnace is controlled so that the degree of vacuum is maintained at, for example, about 5 to 25 kPa in a state where the reducing gas is introduced into the reaction furnace and the surface of the SiC substrate 1 is in contact with the reducing gas species. In this embodiment, an example under the above pressure will be described in detail. Generally, a suitable pressure can be changed by a CVD apparatus. Specifically, a reduced pressure atmosphere of 1 kPa to 70 kPa is used. Is preferred.

  Next, the substrate holder and the SiC substrate 1 are heated by a high frequency induction current. Then, the temperature of SiC substrate 1 is raised to a temperature higher than the epitaxial growth temperature, for example, 1550 ° C. in a reducing gas atmosphere, and held for a certain time (step S2). By this annealing treatment in the reducing gas, SiC dust adhering to the SiC substrate 1 is selectively removed without damaging the SiC substrate 1. As a result, the occurrence of carrot defects caused by SiC dust can be suppressed, and the flatness of the epitaxial wafer can be improved.

  Next, the furnace temperature is lowered to an epitaxial growth temperature (for example, 1500 ° C. or higher and 1600 ° C. or lower) (step S3). Generally, the furnace temperature is controlled by a high frequency induction current.

  After the furnace temperature is stabilized, the source gas is supplied into the reaction furnace and the first epitaxial growth is performed (step S4). Thereby, the first epitaxial layer E1 is formed on the SiC substrate 1. Here, the source gas (hereinafter referred to as source gas) is a gas containing carbon atoms and a gas containing silicon atoms.

  When the first epitaxial layer E1 is grown by a certain thickness or more, the supply of the source gas is stopped for a short time and annealing is performed (step S5). Thereafter, the source gas is supplied again to perform the second epitaxial growth (step S6). Thereby, the second epitaxial layer E2 is formed on the first epitaxial layer E1.

  Next, it is determined whether or not the epitaxial layer E has reached a predetermined film thickness (step S7). Now, assuming that the first epitaxial layer E1 and the second epitaxial layer E2 are each 10 μm and the epitaxial layer E is grown to 30 μm, the annealing process (step S5) is performed again in a reducing gas atmosphere, and the third epitaxial growth is performed. It performs (step S6). Thereby, the third epitaxial layer E3 is formed on the second epitaxial layer E2. Steps S5 and S6 are repeated until the epitaxial layer E has a predetermined thickness. When the epitaxial layer E reaches a predetermined film thickness, the temperature in the reaction furnace is lowered while supplying the reducing gas (step S8).

  According to the SiC epitaxial wafer manufacturing process according to the first embodiment described above, an epitaxial layer having a desired film thickness is obtained by alternately repeating the epitaxial layer growth process and the annealing process in a reducing gas atmosphere. Get. Such an epitaxial layer growth method is referred to as a multi-stage growth method.

  FIG. 3 shows a temperature profile and a gas sequence in the reaction furnace in the manufacturing process of the SiC epitaxial wafer 10. In addition, the code | symbol attached | subjected to the arrow of the upper part of a figure respond | corresponds with the step number of each process of FIG. Hereinafter, steps S2 to S8 in FIG. 2 will be described in detail with reference to FIG.

  First, the temperature in the reaction furnace is raised to a temperature Tp in a reducing gas atmosphere and held for a certain time (step S2).

  Thereafter, the temperature in the furnace is lowered to the growth temperature Tg (step S3), and then the supply of the source gas is started to grow the first epitaxial layer E1 (first layer) (step S4). Note that it is not necessary to wait for the temperature to drop to the growth temperature Tg to supply the source gas, and time may be shortened by starting the supply of the source gas in the middle of the temperature drop from the temperature Tp to the growth temperature Tg. .

  Since a suitable flow rate of the raw material gas is determined by the structure of the reaction furnace, the pressure in the furnace, and the growth rate, it cannot be generally determined. In the CVD apparatus of the present embodiment, silane diluted 20% with hydrogen as a source gas containing silicon atoms and propane as a source gas containing carbon atoms are used, and the supply thereof is started almost simultaneously. Layer growth was performed. The growth temperature Tg is, for example, 1450 ° C. or higher and 1600 ° C. or lower. Note that N-type doping nitrogen gas may be supplied simultaneously with the source gas as necessary. The flow rate is controlled so that the N-type dope concentration is 1 × 10 15 / cm 3 or more and 1 × 10 16 / cm 3 or less. Further, an organometallic material containing Al, B, or Be may be supplied for p-type doping. Further, HCl gas may be used in combination in order to increase the growth speed. Further, dichlorosilane may be used as a source gas containing silicon atoms.

  When the first epitaxial layer E1 reaches a certain thickness, the supply of the source gas excluding the reducing gas is stopped and annealing is performed (step S5). At this time, the thickness of the first epitaxial layer E1 is preferably 10 μm or less. While the supply of the source gas is stopped, the first epitaxial layer E1 is maintained at a high temperature in a reducing gas atmosphere. This time is preferably longer than 20 seconds. This is because it is difficult to control the gas flow rate in a time shorter than 20 seconds, and furthermore, the effect of annealing is not sufficiently exhibited. On the other hand, for a long time of 120 seconds or more, the surface roughness of the epitaxial layer due to the influence of the reducing gas becomes remarkable, and an adverse effect on the device can be considered. Further, if annealing is performed for a long time in a reducing gas atmosphere, the throughput of the epitaxial growth process is reduced and the manufacturing cost is increased. Therefore, the annealing time should be shortened as much as possible. For the above reasons, it is desirable that the time for stopping the supply of the source gas be 20 seconds or more and less than 120 seconds.

  In the annealing process, the gas species must be reducible. This is because the epitaxial layer is extremely hot, and if oxygen atoms are present in the furnace, the oxidation reaction proceeds rapidly on the surface of the epitaxial layer due to radiation energy and high temperature properties, making it impossible to obtain an ideal epitaxial layer. It is.

  After the annealing process (step S5), the source gas and, if necessary, the doping gas are supplied again, and the second epitaxial layer E2 (second layer) is formed on the first epitaxial layer E1 with a constant thickness of 10 μm or less. (Step S6). At this time, the impurity concentration of the second epitaxial layer E2 may be the same as the impurity concentration of the first epitaxial layer E1, or may vary according to device characteristics. Further, the growth rate of the second epitaxial layer E2 may be changed from the growth rate of the first epitaxial layer E1 as necessary. Even if the second epitaxial layer E2 is formed, if the epitaxial layer E does not reach the predetermined film thickness, the above-described annealing step (step S5) and the epitaxial layer growth step (step S6) are repeated. In FIG. 3, step S4 and step S5 are alternately repeated (N-1) times to grow the epitaxial layer in multiple stages, and the epitaxial layer E having a predetermined thickness is formed by growing the Nth epitaxial layer EN (Nth layer). doing.

<B-3. Reduction rate of carrot defects>
4 and 5 are graphs showing the reduction rate of short carrot defects when an epitaxial layer having a thickness of 30 μm is formed by the multistage growth method. FIG. 4 shows the dependence of the reduction rate of short carrot defects on the number of multi-stage growths. The vertical axis shows the reduction rate of short carrot defects, and the horizontal axis (bottom) shows the thickness of the epitaxial layer grown continuously at a time. Yes. Further, the horizontal axis (upper part) shows the number of times of stopping the supply of source gas. The source gas supply stop time is all 120 seconds. From the graph, it can be seen that the shorter the number of continuous growth film thickness per time and the larger the number of times of stopping supply of the source gas, that is, the higher the number of annealing steps, the higher the reduction rate of short carrot defects. When the continuous growth film thickness is 10 μm or 15 μm, the short carrot defect reduction rate is about 20%. However, when the continuous growth film thickness is 5 μm or less, the short carrot defect reduction rate can be 50% or more.

  FIG. 5 shows the dependence of the reduction rate of short carrot defects on the source gas supply stop time, the vertical axis shows the reduction rate of short carrot defects, and the horizontal axis shows the source gas supply stop time. The continuous growth film thickness per time of the epitaxial layer was 5 μm. From this figure, it can be seen that even when the source gas supply stoppage time is as short as 20 seconds, the reduction rate of short carrot defects is 30%. In addition, when the source gas supply stop time is 30 seconds or more, the reduction rate of short carrot defects further increases to 50% or more. Further, even if the annealing process is further extended to 120 seconds, the reduction rate of short carrot defects is 60%, and the reduction effect is saturated. From the above, it has been clarified that the time required for the annealing process required to reduce short carrot defects is 20 seconds or more.

  In the annealing process, the etching amount of the reducing gas to the epitaxial layer is estimated to be about several tens of nm. The quality of the etching and the epitaxial layer are irrelevant in principle, both microscopically and macroscopically. Therefore, it is reasonable to think that such a reduction in the density of short carrot defects is due to annealing in a reducing gas atmosphere. That is, by maintaining the SiC epitaxial wafer at a high temperature in a reducing gas atmosphere, the arrangement of silicon atoms and carbon atoms in the epitaxial layer E, and the structure of crystal defects including various dislocations, the Gibbs free energy is It is thought that it is reconfigured to become the smallest. Short carrot defects are considered to occur in order to reduce the internal stress formed in the crystal as a result of continuous epitaxial growth for a long time. By the above-described annealing, the internal stress and lattice strain of the system composed of the SiC substrate 1 and the epitaxial layer E are reduced. Therefore, it is considered that short carrot defects having an origin in the epitaxial layer are reduced.

  In this embodiment, the growth film thickness of the epitaxial layer E is set to 30 μm, but the effect of the multistage growth method is particularly effective when the growth film thickness of the epitaxial layer is large. For example, the film thickness may be 16 μm or more.

<B-4. Effect>
In the method for manufacturing SiC epitaxial wafer 10 according to the first embodiment, (b1) a first gas containing silicon atoms and a second gas containing carbon atoms are supplied to epitaxially grow a silicon carbide semiconductor layer on SiC substrate 1. And (b2) after step (b1), the supply of at least one of the first and second gases to the SiC substrate 1 is stopped for 20 seconds or more, and the SiC substrate 1 is annealed in a reducing gas atmosphere; (B3) After the step (b2), supplying a first gas containing silicon atoms and a second gas containing carbon atoms to the SiC substrate 1, and epitaxially growing a silicon carbide semiconductor layer on the SiC substrate 1. Prepare. By using a multi-stage growth method that repeats epitaxial growth with annealing interposed therebetween, it is possible to suppress the occurrence of short carrot defects, and thus the SiC epitaxial wafer 10 manufactured in this way has a high yield. Further, by setting the gas stop time to 20 seconds or longer in the step (b2), the control of the gas flow rate can be easily adjusted, the effect of annealing can be sufficiently exhibited, and the occurrence of short carrot defects can be suppressed. .

  In addition, in the method for manufacturing the SiC epitaxial wafer according to the first embodiment, after the step (b4), at least one of the first and second gases to the SiC substrate 1 is stopped for 20 seconds or longer after the step (b3). 1 is annealed in a reducing gas atmosphere, and steps (b3) and (b4) are alternately repeated one or more times until the silicon carbide semiconductor layer has a predetermined thickness. The occurrence of short carrot defects can be suppressed by using a multi-stage growth method in which epitaxial growth is repeated a plurality of times with annealing interposed.

  Further, if the gas stop time in steps (b2) and (b4) is less than 120 seconds, the surface roughness of the epitaxial layer due to the influence of the reducing gas can be prevented.

  Moreover, the favorable suppression rate of a short carrot defect can be acquired by making the film thickness of the silicon carbide semiconductor layer epitaxially grown at once into 10 micrometers or less.

  Further, by setting the film thickness of the silicon carbide semiconductor layer to be epitaxially grown at a time to 5 μm or less, a further better suppression rate of short carrot defects can be obtained.

<C. Second Embodiment>
<C-1. Configuration>
FIG. 8 is a cross-sectional view showing the structure of SiC epitaxial wafer 20 according to the second embodiment. The SiC epitaxial wafer 20 includes an SiC substrate 2 having an off angle of 4 degrees, a diameter of 3 inches, and a polytype of 4H, and an epitaxial layer E ^* formed on the SiC substrate 2. Epitaxial layer E ^* is formed by a multi-stage growth method of forming repeatedly epitaxial growth and annealing are alternately formed in this order by a plurality of epitaxial growth, the first epitaxial layer E ^{* 1,} the second epitaxial layer E ^* 2 , A third epitaxial layer E ^* 3, a fourth epitaxial layer E ^* 4, and a fifth epitaxial layer E ^* 5. The thickness of the epitaxial layer E, for example a 40 [mu] m, the thickness of each epitaxial layer ^E * 1 through E ^* 3 is for example 10 [mu] m, epitaxial layer ^E * 4, ^{E *} 5 each thickness 6μm of a 4 [mu] m. The epitaxial layer E ^* is not limited to the five layers shown in FIG.

  When the final growth film thickness was large, it was found that the proportion of short carrot defects having a starting point near the surface of the epitaxial growth film among the short carrot defects was relatively high. This is probably because the stress of the growth film accumulates as the growth progresses, and a short carrot defect occurs when a stress above a certain level is applied. This is also seen in epitaxial wafers using the multi-step growth method, where stress that could not be alleviated in the annealing step of the multi-step growth method was accumulated as the film grew and appeared as short carrot defects at the end of growth. It is thought that there is. In the future, as the development of high breakdown voltage devices progresses, it is expected that the thickness of the epitaxial film will increase further, and further reduction of short carrot defects is required. A manufacturing process for more efficiently reducing short carrot defects having a starting point near the surface of the epitaxially grown film will be described.

<C-2. Manufacturing process>
The manufacturing process of SiC epitaxial wafer 20 will be described with respect to differences from the first embodiment along the flowchart of FIG. After growing the epitaxial layer E ^* 1 to a certain film thickness in step S4, the supply of the source gas is stopped for a short time, and an annealing process is performed (step S5). Thereafter, the supply of the source gas is started again to grow the epitaxial layer E ^* 2 (step S6). The growth film thickness at this time is set to be equal to or less than the growth film thickness in the previous epitaxial growth process. In other words, in this case, the epitaxial layer E ^{* 2} of the film thickness is equal to or less than the thickness of the epitaxial layer E ^{* 1.} Steps S5 and 6 are repeated until the epitaxial layer E ^* reaches a predetermined film thickness (Yes in step S7). That is, as the epitaxial growth is repeated, the interval between the annealing steps becomes narrower. As described above, by increasing the number of annealing steps toward the end of the growth step and relaxing the stress of the epitaxial growth film, it is possible to more efficiently reduce short carrot defects. The time for one annealing step may be increased as the epitaxial growth step is repeated, or may be constant.

<C-3. Effect>
The manufacturing method of SiC epitaxial wafer 20 according to the second embodiment includes (b1) supplying a first gas containing silicon atoms and a second gas containing carbon atoms to epitaxially grow a silicon carbide semiconductor layer on SiC substrate 1. And (b2) after step (b1), the supply of at least one of the first and second gases to the SiC substrate 1 is stopped for 20 seconds or more, and the SiC substrate 1 is annealed in a reducing gas atmosphere; (B3) After the step (b2), supplying a first gas containing silicon atoms and a second gas containing carbon atoms to the SiC substrate 1, and epitaxially growing a silicon carbide semiconductor layer on the SiC substrate 1. Prepare. And the growth film thickness of the silicon carbide semiconductor layer in a process (b3) shall be below the growth film thickness of the silicon carbide semiconductor layer in a process (b1). As the epitaxial growth proceeds, the stress of the epitaxially grown film is relieved by reducing the thickness of the epitaxially grown film to be grown at one time and shortening the interval for annealing. Therefore, it is possible to more efficiently reduce short carrot defects.

  Further, as the step (b3) is repeated, the growth thickness of the silicon carbide semiconductor layer in the step (b3) is reduced. As the epitaxial growth proceeds, the stress of the epitaxially grown film is relieved by reducing the thickness of the epitaxially grown film to be grown at one time and shortening the interval for annealing. Therefore, it is possible to more efficiently reduce short carrot defects.

  In the present invention, the embodiments can be appropriately modified and omitted within the scope of the invention.

1 SiC substrate, 10, 20 SiC epitaxial wafer, E, E ^* epitaxial layer, E1, E1 ^* first epitaxial layer, E2, E2 ^* second epitaxial layer, E3, E3 ^* third epitaxial layer, E4 ^* fourth epitaxial Layer, E5 ^* 5th epitaxial layer, EN Nth epitaxial layer.

Claims (8)

(A) preparing an SiC substrate having an off angle of less than 5 degrees and a polytype of 4H;
(B) a step of epitaxially growing a silicon carbide semiconductor layer on the SiC substrate,
The step (b)
(B1) supplying a first gas containing silicon atoms and a second gas containing carbon atoms to the SiC substrate to epitaxially grow the silicon carbide semiconductor layer on the SiC substrate;
(B2) After the step (b1), stopping the supply of at least one of the first and second gases to the SiC substrate for 20 seconds or more, and annealing the SiC substrate in a reducing gas atmosphere;
(B3) after the step (b2), supplying a first gas containing silicon atoms and a second gas containing carbon atoms to the SiC substrate, and epitaxially growing the silicon carbide semiconductor layer on the SiC substrate; Comprising
Manufacturing method of SiC epitaxial wafer. The step (b)
(B4) After the step (b3), further comprising the step of stopping the supply of at least one of the first and second gases to the SiC substrate for 20 seconds or more and annealing the SiC substrate in a reducing gas atmosphere. ,
The steps (b3) and (b4) are alternately repeated one or more times until the thickness of the silicon carbide semiconductor layer reaches a predetermined thickness.
The manufacturing method of the SiC epitaxial wafer of Claim 1. The stop time in the step (b2) is less than 120 seconds.
The manufacturing method of the SiC epitaxial wafer of Claim 1. The stop time in the steps (b2) and (b4) is less than 120 seconds.
The manufacturing method of the SiC epitaxial wafer of Claim 2. The steps (b1) and (b3) are steps of epitaxially growing the silicon carbide semiconductor layer having a thickness of 10 μm or less.
The manufacturing method of the SiC epitaxial wafer in any one of Claim 1 to 4. The steps (b1) and (b3) are steps of epitaxially growing the silicon carbide semiconductor layer having a thickness of 5 μm or less.
The manufacturing method of the SiC epitaxial wafer of Claim 5. The growth thickness of the silicon carbide semiconductor layer in the step (b3) is equal to or less than the growth thickness of the silicon carbide semiconductor layer in the step (b1).
The manufacturing method of the SiC epitaxial wafer in any one of Claim 1 to 6. The growth thickness of the silicon carbide semiconductor layer in the step (b3) is equal to or less than the growth thickness of the silicon carbide semiconductor layer in the step (b1).
As the step (b3) is repeated, the growth thickness of the silicon carbide semiconductor layer in the step (b3) is reduced.
The manufacturing method of the SiC epitaxial wafer of Claim 2 or 4.