JP2015041175A - Memory management device, control method, program, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory management device which can efficiently use a physical memory even after a restart due to occurrence of memory failure.SOLUTION: A memory management device comprises: a memory module including a plurality of storage elements; memory determination means which, on the basis of pieces of identification information identifying the respective storage elements included in the memory module, determines a physical address assigned to the storage element identified by the identification information; and control means which performs control for using the storage element of specific physical address among the plurality of storage elements. When a failure occurs in at least one of the plurality of storage elements, the memory determination means holds the identification information of the storage element in which the failure occurs, and after a restart, determines a physical address of the storage element in which the failure has occurred on the basis of the held identification information. The control means performs control for using the storage element other than the storage element of the physical address determined by the memory determination means among the plurality of storage elements.

Description

  The present invention relates to a memory management device, a control method, a program, and a recording medium.

  When a memory failure occurs in a system, a method is known in which a memory in which the failure has occurred is detected and the detected memory is not used.

  For example, Patent Document 1 describes a device that detects a data storage mechanism in which a failure has occurred during operation and replaces it with replacement data and usable data.

  Patent Document 2 describes that a block in which a failure has occurred during operation is degenerated, degenerate information indicating that the block is degenerated is written in the block, and the degeneration status of the block is based on the read result of the degenerate information. A cache memory device for determining the above is described.

  Patent Document 3 describes a display device that, when an abnormality is detected in a memory to which a drawing area is assigned, reassigns the drawing area to an area excluding the abnormal area from the entire memory area. ing.

Special table 2011-521397 gazette International Publication No. 2007/097019 JP 2007-219096 A

  High-end servers operating in mission-critical areas are required to minimize the impact on the system when a failure occurs. Further, in the case of a failure accompanying a system failure in a high-end server, it may be necessary to replace the failed part by maintenance.

  However, when the system is a backbone system or the like, depending on the operation state, it may be necessary to quickly recover from the system down rather than performing maintenance. For this reason, it is required to operate the system stably while minimizing the influence of the failure even after the occurrence of the failure.

  In the techniques of Patent Documents 1 and 2, a block in which a failure has occurred during operation is detected and data replacement or block degeneration operation is performed. However, after the system is restarted due to a system down or the like, the failure occurs. The generated memory itself may be detected and the memory may be degenerated and operated.

  In recent years, the capacity of memories such as DIMMs (Dual Inline Memory Modules) has increased, and there is a single DIMM having a capacity of 64 GB. For this reason, when performing the operation | movement which degenerates a memory like the technique of patent document 2, such DIMM1 will be degenerated. However, as the capacity of a DIMM increases, there is a possibility that the performance of the entire system is lowered and the system cannot be stably operated just by degenerating one DIMM.

  In the technique of Patent Document 3, the drawing area is reassigned to the area excluding the abnormal area in a specific area such as the drawing area and the display area. However, the physical memory (for example, DIMM or the like) is used. ) Is not disclosed about a method for efficiently using the capacity.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory management device that efficiently uses physical memory even after restart after a memory failure occurs. .

  A memory management device according to an aspect of the present invention includes a memory module that includes a plurality of storage elements, and a storage that is specified by the specific information from specific information that specifies each of the plurality of storage elements included in the memory module. A memory specifying means for specifying a physical address assigned to the element, and a control means for controlling which of the plurality of storage elements to use a storage element of, the memory specifying means, When a failure occurs in at least one of the plurality of storage elements, the specific information of the storage element in which the failure has occurred is retained, and after restart, the physical address of the storage element in which the failure has occurred is determined from the retained specific information. The control unit uses a storage element other than the storage element of the physical address specified by the memory specifying unit among the plurality of storage elements. To so that control.

  A control method according to an aspect of the present invention is a control method of a memory management device including a memory module including a plurality of storage elements, and when a failure occurs in at least one of the plurality of storage elements, the failure occurs. The specific information for specifying the generated storage element is held, and after the restart, the physical address assigned to the storage element specified by the specific information from the held specific information, and the storage in which the failure has occurred A physical address of the element is specified, and control is performed to use a storage element other than the storage element of the specified physical address among the plurality of storage elements.

  The program according to one aspect of the present invention holds specific information for specifying the storage element in which the failure has occurred and restarts when a failure occurs in at least one of the plurality of storage elements included in the memory module. A process of identifying a physical address of the storage element that is a physical address assigned to the storage element specified by the specific information from the stored specific information later, and among the plurality of storage elements, And causing the computer to execute a process of controlling to use a storage element other than the storage element having the specified physical address.

  According to the memory management device of the present invention, physical memory can be used efficiently even after restart after a memory failure occurs.

It is a block diagram which shows the structure of the memory management apparatus which concerns on embodiment of this invention. It is a functional block diagram which shows the function structure of the memory management apparatus which concerns on embodiment. It is a figure which shows an example of the information which shows whether the DRAM number of each DRAM, the physical address allocated to each DRAM, and each DRAM can be used by OS. It is a flowchart which shows the flow of a process of the memory management apparatus which concerns on embodiment. It is a figure which shows an example of the information which shows whether the DRAM number of each DRAM after a failure generate | occur | produces, the physical address allocated to each DRAM, and each DRAM can be used by OS. The figure which shows an example of the information which shows whether the DRAM number of each DRAM after a failure generate | occur | produces, the physical address allocated to each DRAM, and each DRAM can be used by OS based on the comparison form is there.

<Embodiment>
Embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a memory management device according to an embodiment of the present invention. As shown in FIG. 1, the memory management device 1 according to the present embodiment includes a CPU 10 and a plurality of DIMMs 11 to 18. In the present embodiment, description will be given by adopting DIMM as a memory module, but the present invention is not limited to this. Further, in the present embodiment, description is made by taking an example where there are eight DIMMs, but the present invention is not limited to this.

  The CPU 10 controls the entire memory management device 1. The DIMMs 11 to 18 are connected to the CPU 10 as shown in FIG. FIG. 1 shows a typical connection example between the CPU 10 and the DIMMs 11 to 18.

  Each of the DIMMs 11 to 18 includes six storage elements (DRAMs 110 to 115, 120 to 125, 130 to 135, 140 to 145, 150 to 155, 160 to 165, 170 to 175, 180 to 185). . In the present embodiment, a DRAM (Dynamic Random Access Memory) is used as a memory element. However, the present invention is not limited to this. Further, the number of DRAMs included in each DIMM is not limited to six.

  A physical address is assigned to each DRAM. In the following description, the physical address described in the present embodiment is a physical address for a real memory allocated in hardware such as a typical personal computer.

  Next, the functional configuration of the memory management device 1 according to the present embodiment will be described with reference to FIG. FIG. 2 is a functional block diagram showing a functional configuration of the memory management device 1 according to the present embodiment.

  As shown in FIG. 2, the memory management device 1 includes a memory specifying unit 101 and a memory control unit 102. The memory specifying unit 101 and the memory control unit 102 are realized by the CPU 10. In FIG. 2, DIMMs 11 to 18 in FIG. 1 are represented as DIMM groups.

  When a failure occurs in at least one of the DRAMs, the memory specifying unit 101 specifies the failed (failed) DRAM (failed DRAM), and holds location information of the specified failed DRAM. Here, the DRAM position information is information for specifying each DRAM, for example, information (specific information) indicating which DIMM of which DIMM the failed DRAM is. In the present embodiment, description is made by adopting a DRAM number as information for specifying the location of each DRAM, but the present invention is not limited to this.

  The memory specifying unit 101 specifies the physical address of the failed DRAM from the stored location information of the failed DRAM and notifies the memory control unit 102 of the physical address.

  The operation of the memory specifying unit 101 may be a typical management firmware failure specifying function such as BMCFW (Baseboard Management Controller Firmware).

  The memory control unit 102 controls which physical address DRAM is used among the plurality of DRAMs. That is, the memory control unit 102 controls to exclude the DRAM specified by the physical address from the memory management device 1 based on the physical address of the failed DRAM notified from the memory specifying unit 101. Specifically, the memory control unit 102 specifies that the failed DRAM is not a DRAM that can be used by the memory management device 1, and uses the DRAM that can be used by the OS of the memory management device 1. Start up.

  Note that the memory control unit 102 may be a function included in the OS of the memory management device 1.

  FIG. 3 is a diagram showing an example of information indicating the DRAM number of each DRAM, the physical address assigned to each DRAM, and whether each DRAM can be used by the OS.

  The rightmost column in FIG. 3 shows information (usability information) indicating whether or not each DRAM can be used by the OS of the memory management device 1. In FIG. 3, “◯” indicates that each DRAM can be used by the OS, and “X” indicates that it is not usable. As shown in FIG. 3, it can be seen that each DRAM can use an OS (Operation System).

  As shown in FIG. 3, the physical number of the DRAM and the availability information are associated with the DRAM number that identifies the DRAM. The information shown in FIG. 3 may be recorded in a memory (not shown) or may be recorded in a memory built in the CPU 10.

  Next, the operation of the memory management device 1 will be described with reference to FIG. FIG. 4 is a flowchart illustrating a processing flow of the memory management device 1 when a memory failure occurs. Each process of FIG. 4 is performed by program control of CPU10.

  Here, the memory failure will be described. A memory failure that is a target of the present embodiment may occur using a typical DIMM, a single bit (single bit) error (continuous operation failure) of a DRAM, and a multi-bit (multi bit). Error (failure that cannot be continued).

  The memory management device 1 in the present embodiment performs the operation shown in FIG. 4 when the memory failure occurs. In FIG. 4, each of steps S1 to S7 is simply represented by reference numerals S1 to S7 in the following description.

  As shown in FIG. 4, when a failure occurs, the memory specifying unit 101 first specifies a failed DRAM (S1). Then, the memory specifying unit 101 holds the specified location information of the failed DRAM in a non-illustrated non-volatile memory (S2).

  After that, when the memory management device 1 is restarted due to various restart factors (for example, OS update or other operation continuation failure) including a memory failure (S3), the memory specifying unit 101 With reference to the information shown in FIG. 3, the physical address of the failed DRAM is specified from the location information of the failed DRAM held in S2 (S4).

  The memory specifying unit 101 notifies the memory control unit 102 of the physical address of the failed DRAM specified in S4 (S5). Then, the memory control unit 102 excludes the notified physical address from the memory management device 1 (S6), and activates the memory management device 1 using a DRAM that can be used at the present time (S7).

  Here, the operation of the memory management device 1 will be further described by taking as an example a case where a multi-bit error has occurred in the DRAM 113 in the DRAM shown in FIG.

  First, when a memory failure occurs, the memory specifying unit 101 specifies a failed DIMM (in this example, DIMM 11) and a failed DRAM (DRAM 113). The memory specifying unit 101 holds location information (DRAM number) of the specified failed DRAM (DRAM 113).

  After that, when the continuous operation is not possible due to a failure of the DIMM 11 or when the device is restarted due to other factors (such as OS Update), the memory specifying unit 101 has a failure that was retained at the time of restart. The physical address “0x00000003” is specified from the position of the DRAM 113.

  The memory specifying unit 101 notifies the memory control unit 102 of the specified physical address “0x00000003”. Then, the memory control unit 102 performs control so that the physical address “0x00000003” notified from the memory specifying unit 101 is not used from the memory management device 1. That is, the memory control unit 102 excludes the DRAM 113 with the physical address “0x00000003” from the DRAM used by the memory management device 1.

  Then, the memory control unit 102 activates the memory management device 1 without performing memory access to the DRAM 113.

  As a result, the memory management device 1 can be activated in a state where only the DRAM 113 is degenerated, and can be brought into an operation state.

  FIG. 5 shows an example of information indicating the DRAM number of each DRAM, the physical address assigned to each DRAM, and information indicating whether each DRAM can be used by the OS at this time. As shown in FIG. 5, it can be seen that the column indicating whether the OS is available or not in the row of the DRAM 113 is “x”.

  Thus, since only the DRAM 113 is degenerated, the OS cannot use only the physical address corresponding to the failed DRAM 113 as shown in FIG. Accordingly, the memory capacity of the memory management device 1 is reduced by one DRAM from the time before the occurrence of the memory failure in the operation after the above processing.

<Comparison form>
Next, a comparative form for comparison with the above embodiment of the present invention will be described. The memory management device 2 according to the comparative form is the memory management device 2 in the prior art. The hardware configuration of the memory management device 2 according to the comparison form is the same as that of the memory management device 1 of FIG. Further, it is assumed that the physical address for each DRAM of the memory management device 2 before the failure and the information indicating whether or not the OS is usable are the same as those in FIG.

  In the memory management device 2 according to the comparative embodiment, an operation when a memory failure occurs during operation will be described.

  For example, when a single bit error occurs in the memory management device 2, a reduced operation is performed by a function of preventive degeneration (degeneration before a multi-bit error causing a system down), which is a typical high-end server function. Is called. Here, the preventive degeneration function refers to, for example, when a single bit error frequently occurs in a certain period (for example, 20 or more single bit errors have occurred within 24 hours from the same DIMM, etc.) The function is such that the DIMM is reserved, and the DIMM is degenerated at the next restart (such as an error of another factor).

  Further, in the memory management device 2, for example, when a multi-bit error occurs, the continuous operation is impossible. For example, after the system is restarted, the DIMM is degenerated.

  In the memory management device 2 according to the comparison mode, when a memory failure occurs in the DRAM 113 of the DIMM 11, the high-end server identifies the failed DIMM (DIMM 11) by a failure identification function of general management firmware (such as BMC).

  Thereafter, when the continuous operation is disabled due to a failure of the DIMM 11 or when the device is restarted due to other factors (such as OS Update), the failed DIMM 11 is automatically degraded by the management firmware at the time of restart. Then, the memory management device 2 is activated in a state in which the failed DIMM 11 is degenerated, and enters an operation state.

  FIG. 6 shows an example of information indicating the physical address assigned to each DRAM and whether or not each DRAM can be used by the OS. As shown in FIG. 6, since the DIMM 11 is degenerated, the OS cannot use the physical addresses of the DRAMs 110, 111, 112, 113, 114, and 115 including the failed DRAM 113. Therefore, in the memory management device 2 according to the comparative embodiment, in the operation after the occurrence of the failure, the memory capacity is reduced by one DIMM from before the occurrence of the memory failure.

(Effect of the memory management device 1)
As described above, the memory management device 1 according to the embodiment of the present invention can efficiently use physical memory even after restart after a memory failure occurs.

  The reason is that the memory specifying unit 101 specifies and holds the location of the failed DRAM, and notifies the memory control unit 102 of the physical address of the failed DRAM. This is because the memory management device 1 is activated without accessing the memory.

  Therefore, even after the system is restarted after a memory failure occurs, it is possible to degenerate in units of DRAM. As a result, the memory degeneration capacity can be minimized, and the physical memory can be used efficiently. In addition, since the OS of the memory management device 1 does not access the failed DRAM, the system can be operated stably.

  3 and 5 may be recorded in a memory (not shown) or built in the CPU 10 as the DRAM number identifying the DRAM and the physical address of the DRAM and the availability information may be associated with each other. It may be recorded and managed in a separate memory.

  Then, when a failure occurs in at least one of the plurality of DIMMs, the memory control unit 102 may update the availability information of the DIMM in which the failure has occurred. Further, the memory control unit 102 may control to use a DIMM that can be used by the OS of the memory management device 1 among a plurality of DIMMs with reference to the availability information.

  Even when such information is used, the memory management device 1 according to the embodiment can efficiently use the physical memory even after restarting after the occurrence of a memory failure.

  Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

1 Memory management device 10 CPU
11-18 DIMM
101 Memory specifying unit 102 Memory control unit

Claims (6)

A memory module including a plurality of storage elements;
Memory specifying means for specifying a physical address assigned to a storage element specified by the specific information from specific information for specifying each of the plurality of storage elements included in the memory module;
Control means for controlling which of the plurality of storage elements to use the storage element of which physical address,
The memory specifying unit holds specific information of the storage element in which a failure has occurred when a failure occurs in at least one of the plurality of storage elements, and after restarting, the failure has occurred from the stored specific information. Identify the physical address of the storage element,
The memory control apparatus, wherein the control unit controls to use a storage element other than the storage element of the physical address specified by the memory specifying unit among the plurality of storage elements. The specific information of the storage element is associated with availability information indicating whether the storage element is usable in a memory management device,
2. The memory according to claim 1, wherein the control unit controls which of the plurality of storage elements is to be used with reference to the availability information. Management device.   3. The control unit according to claim 2, wherein, when a failure occurs in at least one of the plurality of storage elements, the control unit updates the availability information of the storage element in which the failure has occurred to be unusable. Memory management device. A method for controlling a memory management device including a memory module including a plurality of storage elements,
When a failure occurs in at least one of the plurality of storage elements, specific information for specifying the storage element in which the failure has occurred is retained, and after restart, specified by the specific information from the retained specific information A physical address assigned to the storage element, wherein the physical address of the storage element in which the failure has occurred is identified;
A control method comprising: controlling a storage element other than the storage element having the specified physical address among the plurality of storage elements. When a failure occurs in at least one of the plurality of storage elements included in the memory module, the specific information for specifying the storage element in which the failure has occurred is retained, and the specific information is retained from the retained specific information after the restart. A process of specifying a physical address of the storage element in which a failure has occurred, which is a physical address assigned to the storage element specified by
A program for causing a computer to execute a process of controlling to use a storage element other than the storage element of the specified physical address among the plurality of storage elements.   A recording medium on which the program according to claim 5 is recorded.

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