JP2015037285A - Voltage generation circuit and method of controlling voltage generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement a shorter time to set an output voltage at a predetermined value than before while suppressing an increase in power consumption.SOLUTION: A voltage generation circuit has: a first voltage generation section for outputting a first voltage to a first signal line in response to a start signal; a second voltage generation section for outputting a second voltage to a second signal line on the basis of the first voltage; a buffer section for outputting an output voltage in response to the first voltage; and a switch section for connecting an output terminal of the second voltage generation section to an output voltage terminal in a first period in which the second voltage is lower than the first voltage, and connecting an output terminal of the buffer section to the output voltage terminal when the second voltage is equal to or higher than the first voltage. The second voltage generation section has an acceleration section for providing a higher capability of generating the second voltage in a second period in which a difference of the first voltage from the second voltage is equal to or smaller than a first value within the first period, than in the period in which the difference of the first voltage from the second voltage is larger than the first value.

Description

  The present invention relates to a voltage generation circuit and a method for controlling the voltage generation circuit.

  For example, the voltage generation circuit includes a resistance dividing circuit that generates a reference voltage and an amplifier that generates an output voltage in response to the input voltage and the reference voltage (see, for example, Patent Document 1). In this type of voltage generation circuit, a switch is disposed between the resistor string and the power supply line to reduce power consumption during non-operation.

  In addition, the voltage generation circuit includes a resistance dividing circuit that generates a reference voltage, and an amplifier that supplies a current to the output node when the power supply is started based on the difference between the output voltage and the reference voltage (for example, Patent Literature 2).

JP 2006-128909 A JP 2007-166298 A

  The time from when the voltage generation circuit starts to operate until the output voltage is set to a predetermined value is shortened by lowering the output impedance of the amplifier or applying a high voltage during the period until the output voltage is set. Become. However, the power consumption increases as the output impedance of the amplifier is lowered, and if a high voltage is applied during the period until the output voltage is set, an overshoot is likely to occur in the output voltage. When the overshoot occurs and the settling time of the output voltage increases, the time reduction effect until the output voltage is set to a predetermined value is reduced. Conventionally, a voltage generation circuit that shortens the time until the output voltage is set to a predetermined value while suppressing an increase in power consumption has not been proposed.

  The voltage generation circuit of the present disclosure aims to shorten the time until the output voltage is set to a predetermined value while suppressing an increase in power consumption as compared with the conventional one.

  According to one aspect, the voltage generation circuit includes a first voltage generation unit that outputs a first voltage to the first signal line in response to the activation signal, and a second signal based on the first voltage. A second voltage generating section for outputting a second voltage to the line; a buffer section for receiving the first voltage and outputting an output voltage; and a second period in which the second voltage is smaller than the first voltage. A switch unit that connects the output terminal of the second voltage generator to the output voltage terminal, and connects the output terminal of the buffer unit to the output voltage terminal when the second voltage is equal to or higher than the first voltage; In the second period, the difference between the second voltage and the first voltage in the first period is equal to or less than the first value. Has an accelerating portion that increases the second voltage generation capability as compared to a period larger than the first value.

  According to another aspect, a method for controlling a voltage generation circuit outputs a first voltage to a first signal line in response to an activation signal, and outputs a second voltage to a second signal line based on the first voltage. Is output by the second voltage generator, and the difference between the second voltage and the first voltage is equal to or less than the first value in the first period in which the second voltage is smaller than the first voltage. In the second period, the second voltage generator has a second voltage generation capability higher than that in the period in which the difference between the second voltage and the first voltage is greater than the first value, The voltage is received by the buffer unit to output the output voltage, the output terminal of the second voltage generation unit is connected to the output voltage terminal in the first period, and the buffer unit when the second voltage is equal to or higher than the first voltage Connect the output terminal to the output voltage terminal.

  The voltage generation circuit and the control method for the voltage generation circuit disclosed in the present disclosure can shorten the time until the output voltage is set to a predetermined value while suppressing an increase in power consumption, as compared with the related art.

It is a figure which shows one Embodiment of the control method of a voltage generation circuit and a voltage generation circuit. It is a figure which shows another embodiment of a voltage generation circuit. FIG. 3 is a diagram illustrating an example of the operation of the voltage generation circuit illustrated in FIG. 2. It is a figure which shows the example of the signal in the operation | movement of the voltage generation circuit shown in FIG. 3, and the state of an element. It is a figure which shows another embodiment of a voltage generation circuit. FIG. 6 is a diagram illustrating an example of the operation of the voltage generation circuit illustrated in FIG. 5. FIG. 7 is a diagram showing an example of signals and element states in the operation of the voltage generation circuit shown in FIG. 6. It is a figure which shows another embodiment of a voltage generation circuit. It is a figure which shows the example of operation | movement of the voltage generation circuit shown in FIG. FIG. 10 is a diagram showing an example of signals and element states in the operation of the voltage generation circuit shown in FIG. 9.

  Hereinafter, embodiments will be described with reference to the drawings. A signal line through which a signal or voltage is transmitted uses the same symbol as the signal name or voltage name, and a resistance value of the resistor element uses the same symbol as the resistor element.

  FIG. 1 shows an embodiment of a voltage generation circuit and a method for controlling the voltage generation circuit. The voltage generation circuit VGEN1 of this embodiment includes bias circuits B1 and B2, a buffer unit BUF, and a switch unit SW. The bias circuit B2 includes an acceleration unit ACC. For example, the voltage generation circuit VGEN1 is mounted on a semiconductor integrated circuit and functions as a constant voltage generation circuit that generates a constant voltage supplied to an internal circuit in the semiconductor integrated circuit.

  The bias circuit B1 generates a voltage on the signal line REF1 in response to the change of the enable signal EN from an inactive state (for example, low level) to an activated state (for example, high level). For example, the bias circuit B1 outputs a high level voltage to the signal line REF1 while the enable signal EN is inactive, and outputs the reference voltage VR1 to the signal line REF1 in response to the activation of the enable signal EN. The bias circuit B1 is an example of a first voltage generator that outputs a first voltage to the signal line REF1 in response to the enable signal EN. The enable signal EN is an example of an activation signal that changes the state of the voltage generation circuit VGEN1 from the standby state to the operating state. In the following description, the standby state is also referred to as a power-down state.

  The bias circuit B2 outputs a low level voltage to the signal line REF2 while the enable signal EN is inactive, and outputs a voltage to the signal line REF2 based on the voltage generated on the signal line REF1 after the enable signal EN is activated. To do. The bias circuit B2 is an example of a second voltage generation unit that outputs a second voltage to the signal line REF2 based on the first voltage generated on the signal line REF1.

  For example, the leakage current in the bias circuit B1 can be suppressed by the bias circuit B1 outputting the power supply voltage to the signal line REF1 during the deactivation of the enable signal EN. Similarly, the leakage current in the bias circuit B2 can be suppressed by the bias circuit B2 outputting the ground voltage to the signal line REF2 during the deactivation of the enable signal EN. As a result, the power consumption in the standby state of the voltage generation circuit VGEN1 can be reduced as compared with the case where the leakage current in the bias circuits B1 and B2 is not suppressed.

  The buffer unit BUF outputs an output voltage VO according to the voltage REF1. For example, the buffer unit BUF outputs the output voltage VO having the same value as the reference voltage VR1 when receiving the reference voltage VR1 via the signal line REF1. Note that the output voltage VO output from the buffer unit BUF may be different from the reference voltage VR1.

  The switch unit SW connects the output of the bias circuit B2 to the output terminal OUT during the period T1 when the voltage REF2 does not reach the voltage REF1. Thereby, the output voltage OUT changes following the voltage REF2 in the period T1. Further, the switch unit SW connects the output of the buffer unit BUF to the output terminal OUT when the voltage REF2 reaches the voltage REF1. As a result, the output voltage OUT becomes the output voltage VO corresponding to the voltage REF1 during the period T3 after the voltage REF2 reaches the voltage REF1.

  The acceleration unit ACC outputs to the signal line REF2 compared to when the difference between the voltage REF2 and the voltage REF1 is larger than the value V1 in the period T2 in which the difference (REF1-REF2) between the voltage REF2 and the voltage REF1 is equal to or less than the value V1. Increase the voltage generation capability. Thereby, the period T1 until the output voltage OUT reaches the expected value (VR1 in this example) can be shortened as compared with the case where the acceleration unit ACC is not used. Further, by switching the connection of the switch unit SW when the voltage REF2 reaches the voltage REF1, the output of the voltage REF2 exceeding the value VR1 from the output terminal OUT can be suppressed. That is, it is possible to suppress the occurrence of overshoot in the output voltage OUT, and it is possible to suppress an increase in the settling time of the output voltage OUT.

  Since the voltage REF2 is output from the output terminal OUT until the voltage REF2 reaches the voltage REF1, the buffer unit BUF can be designed without considering the shortening of the period T1. That is, the driving capability of the buffer unit BUF can be made smaller than that of the voltage generation circuit without the bias circuit B2 and the switch unit SW, and an increase in power consumption of the buffer unit BUF can be suppressed.

  As described above, in the embodiment shown in FIG. 1, the period T1 until the voltage at the output terminal OUT reaches the value VR1 can be shortened without increasing the power consumption. Furthermore, even when the period T1 is shortened, it is possible to suppress a voltage exceeding the value VR1 from being output from the output terminal OUT.

  FIG. 2 shows another embodiment of the voltage generation circuit. Elements that are the same as or similar to those described in the embodiment shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The voltage generation circuit VGEN2 of this embodiment includes bias circuits B1a and B2a, a comparator CMP, a differential amplifier AMP, switches SW2 and SW3, and a capacitor CAP. For example, the voltage generation circuit VGEN2 is mounted on a semiconductor integrated circuit and functions as a constant voltage generation circuit that generates a constant voltage supplied to an internal circuit in the semiconductor integrated circuit.

  The bias circuit B1a includes resistance elements Rah and Rbh and a switch SW1 connected in series between the power supply line VDD and the ground line VSS. The power supply line VDD is an example of a first power supply line or a third power supply line, and the ground line VSS is an example of a second power supply line or a fourth power supply line. For example, the switch SW1 is an nMOS transistor having a gate connected to the enable signal line EN, a source connected to the ground line VSS, and a drain connected to one end of the resistance element Rbh. The bias circuit B1a sets the switch SW1 to an off state while the enable signal EN is at a low level (for example, VSS), and outputs a high level (VDD) to the signal line REF1 connected between the resistance elements Rah and Rbh. . Further, the bias circuit B1a sets the switch SW1 to the ON state while the enable signal EN is at a high level (for example, VDD), and generates a reference voltage VR1 on the signal line REF1 according to the resistance ratio of the resistance elements Rah and Rbh. To do. The bias circuit B1a is an example of a first voltage generator that outputs a first voltage to the signal line REF1 in response to the enable signal EN.

  During the operation period of the voltage generation circuit VGEN2 after the enable signal EN is set to the high level, the reference voltage VR1 is set to the voltage shown in the equation (1). In other words, the bias circuit B1a is designed to generate the reference voltage VR1 shown in Expression (1). The resistance values of the resistance elements Rah and Rbh are set such that the reference voltage VR1 is lower than the value obtained by subtracting the threshold voltage Vth (absolute value) of the pMOS transistor TR1 (TR2) from the power supply voltage VDD. Hereinafter, the threshold voltage of the pMOS transistor will be described as an absolute value.

  The bias circuit B2a includes transistors TR2 and TR1, a resistance element Rc, and transistors TR4 and TR3 connected in series between the power supply line VDD and the ground line VSS. For example, the transistors TR2 and TR1 are pMOS transistors, and the transistors TR4 and TR3 are nMOS transistors. The transistor TR1 has a gate connected to the signal line REF1, a drain connected to the signal line REF2, and a source connected to the drain of the transistor TR2. The signal line REF2 is connected to one end of the resistance element Rc, the gate of the transistor TR2, the input terminal (−) of the comparator CMP, and one end of the input / output node of the switch SW2. The gate of the transistor TR4 is connected to the control signal line CO2, and the gate of the transistor TR3 is connected to the signal line CO1. As illustrated in FIG. 3, the transistor TR3 is an example of an accelerating unit that increases the generation capability of the voltage REF2 during the startup state (2) in which the difference between the voltages REF1 and REF2 is equal to or less than the value V1.

  The bias circuit B2a receives the high level voltage REF1 while the enable signal EN is at the low level, sets the transistor TR1 to the cutoff state, and sets the signal line REF2 to the low level (VSS). The bias circuit B2a generates the voltage VR2 on the signal line REF2 during the operation period of the voltage generation circuit VGEN2 after the enable signal EN is set to the high level. The bias circuit B2a is an example of a second voltage generation unit that outputs a second voltage to the signal line REF2 based on the first voltage generated on the signal line REF1.

  The voltage VR2 generated during the period when the enable signal EN is at the high level is set to a value shown in Expression (2). In other words, the bias circuit B2a is designed to generate the voltage VR2 shown in Expression (2). In Expression (2), Veff1 is an effective voltage (also referred to as an overdrive voltage) obtained by subtracting the threshold voltage Vth of the transistor TR1 from the gate-source voltage Vgs (absolute value) of the transistor TR1. 3). Hereinafter, the gate-source voltage Vgs of the pMOS transistor will be described as an absolute value.

  Further, the resistance value Rc of the resistance element Rc in the bias circuit B2a is expressed by Expression (4), where K is a specific constant of the transistor TR1 and Vth is the threshold voltage of the transistor TR1. The constant K is expressed by equation (5). In Expression (5), μ represents the mobility of holes in the transistor TR1, Cox represents the capacitance value of the gate oxide film per unit area, W represents the gate width of the transistor TR1, and L represents the transistor TR1. Indicates the gate length.

  The comparator CMP compares the voltage REF1 received at the input terminal (+) with the voltage REF2 received at the input terminal (−), and generates a control signal CO2 for controlling the switches SW2 and SW3 according to the comparison result. The differential amplifier AMP outputs a voltage corresponding to the voltage REF1 received at the input terminal (+) and the voltage OUT received at the input terminal (−) to the signal line CO1. The signal line CO1 is connected to the output terminal OUT via the switch SW3. The input terminal (−) of the differential amplifier AMP is connected to the output terminal OUT, and is connected to the signal line REF2 via the switch SW2.

  For example, the switch SW2 has an nMOS whose gate is connected to the control signal line CO2, one of the drain and the source is connected to the signal line REF2, and the other of the drain and the source is connected to the input terminal (−) of the differential amplifier AMP. It is a transistor. For example, the switch SW3 is a pMOS transistor whose gate is connected to the control signal line CO2, one of the drain and the source is connected to the signal line CO1, and the other of the drain and the source is connected to the output terminal OUT. Capacitor CAP equivalently shows the load of the internal circuit in the semiconductor integrated circuit connected to output terminal OUT of voltage generation circuit VGEN2.

  A transistor with a circle on the gate indicates a pMOS transistor, and a transistor without a circle on the gate indicates an nMOS transistor. Further, the transistors denoted by reference numerals SW1, SW2, and SW3 function as switches and are short-circuited or opened according to the voltage received at the gate. The switches SW1 and SW2 are positive logic switches that are short-circuited when receiving a high level (for example, VDD) at the gate. The switch SW3 is a negative logic switch that is short-circuited when a low level (for example, VSS) is received at the gate. Transistors labeled TR1, TR2, TR3, and TR4 operate in a saturation region, a linear region, or a cutoff region depending on a gate voltage, a drain voltage, and a source voltage. The drain-source resistance of the MOS transistor has a relationship of cutoff region >> saturation region >> linear region.

  The drain-source current Ids in the saturation region is defined by the equation (6), the constant K in the equation (6) is defined by the equation (5), and the condition when the transistor operates in the saturation region is as follows: It is defined by equation (7). That is, the saturation region is when the gate-source voltage Vgs is larger than the threshold voltage Vth of the transistor and the drain-source voltage Vds is larger than the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs. This is the operation area.

  The drain-source current Ids in the linear region is defined by Equation (8), the constant K in Equation (8) is defined by Equation (5), and the conditions for the transistor to operate in the linear region are: It is defined by equation (9). That is, in the linear region, the gate-source voltage Vgs is larger than the threshold voltage Vth of the transistor, and the drain-source voltage Vds is smaller than the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs. This is the operation area.

  The drain-source Ids in the cutoff region is defined by Equation (10), and the condition when the transistor operates in the cutoff region is defined by Equation (11). That is, the cutoff region is an operation region when the gate-source voltage Vgs is lower than the threshold voltage Vth of the transistor.

  FIG. 3 shows an example of the operation of the voltage generation circuit VGEN2 shown in FIG. That is, FIG. 3 shows another embodiment of the method for controlling the voltage generation circuit. In FIG. 3, the enable signal EN is set from low level to high level in the power down state in which the voltage generation circuit VGEN2 stops the operation of generating the output voltage OUT, and the voltage generation circuit VGEN2 enters the operation state. For example, the voltage generating circuit VGEN2 operates in response to a change from the low level to the high level of the enable signal EN through the startup state (1), the startup state (2), and the startup state (3) that are transient states. It becomes a state. Further, the voltage generation circuit VGEN2 changes from the operating state to the power-down state in response to the change of the enable signal EN from the high level to the low level during the operating state.

  The period of the activated state (1) and the activated state (2) is an example of a first period in which the voltage REF2 does not reach the value VR1. The period of the activated state (2) is an example of a second period in which the difference between the voltages REF1 and REF2 (REF1-REF2) is equal to or less than the first value V1.

  First, in the power-down state, the switch circuit SW1 of the bias circuit B1a is set to the OFF state by the low level enable signal EN, and the signal line REF1 is maintained at the power supply voltage VDD (FIG. 3A). In the power down state, the signals CO1 and CO2 are held at a high level (VDD) (FIGS. 3B and 3C). Therefore, the transistor TR3 of the bias circuit B2a that receives the signal CO1 at the gate and the transistor TR4 of the bias circuit B2a that receives the signal CO2 at the gate operate in the linear region.

  The transistor TR1 of the bias circuit B2a receives the voltage REF1 (VDD) at the gate and operates in the cutoff region. The voltage REF2 is set to the ground voltage VSS (0 V) via the resistance element Rc and the transistors TR3 and TR4 operating in the linear region (FIG. 3D). The transistor TR2 of the bias circuit B2a receives a high level signal REF2 at its gate and operates in a linear region.

  The comparator CMP receives a high level (VDD) signal REF1 and a low level (VSS) signal REF2, and outputs a high level (VDD) control signal CO2. Thereby, the standby power of the comparator CMP can be reduced as compared with the case where the comparator CMP receives a voltage other than the power supply voltage VDD and the ground voltage VSS during the power-down state. In other words, the standby power of the comparator CMP can be reduced without mounting a pull-up circuit or the like that receives the enable signal EN or the like during the power down state and fixes the internal node at the power supply voltage VDD or the ground voltage VSS. Can be reduced.

  The switch SW2 is set to the ON state by the high level control signal CO2, the low level signal REF2 is supplied to the differential amplifier AMP and the output terminal OUT, and the output terminal OUT is set to the low level (VSS) (FIG. 3). (E)).

  The differential amplifier AMP receives a high level signal REF1 and a low level signal REF2, and outputs a high level (VDD) signal CO1. Thereby, the standby power of the differential amplifier AMP can be reduced as compared with the case where the differential amplifier AMP receives a voltage other than the power supply voltage VDD and the ground voltage VSS during the power-down state. In other words, the differential amplifier AMP waits without mounting a pull-up circuit or the like that receives the enable signal EN or the like during the power down state and fixes the internal node at the power supply voltage VDD or the ground voltage VSS. Electric power can be reduced. The switch SW3 receives the high-level control signal CO2 at the gate and is set to an off state, and the connection between the output of the differential amplifier AMP and the output terminal OUT is cut off.

  In the power down state, a positive feedback loop from the comparator CMP to the bias circuit B2a via the control signal line CO2 and a positive feedback loop from the differential amplifier AMP to the bias circuit B2a via the signal line CO1 are generated. The signal REF2 is latched at 0V by two positive feedback loops, and the output terminal OUT is fixed at 0V.

  The through current flowing between the power supply line VDD and the ground line VSS in the bias circuit B1a can be ignored by the OFF state of the switch SW1. In the bias circuit B2a, since the transistor TR1 operates in the cutoff region, a through current flowing between the power supply line VDD and the ground line VSS can be ignored. For this reason, the standby current of the voltage generation circuit VGEN2 is smaller than the standby current of the voltage generation circuit having a bias circuit that constantly flows a leakage current.

  Next, in response to the change of the enable signal EN from the low level (VSS) to the high level (VDD), the state of the voltage generation circuit VGEN2 changes from the power-down state to the startup state (1). When the switch SW1 is set to the on state by the high level enable signal EN, the bias circuit B1a operates as a resistance dividing circuit and generates the reference voltage VR1 on the signal line REF1. The voltage of the signal line REF1 decreases to the value VR1 according to the resistance ratio of the resistance elements Rah and Rbh (FIG. 3 (f)). Since the load of the signal line REF1 is smaller than the load of the signal line (REF2 or BIAS) to which the capacitor CAP is connected, the voltage change of the signal line REF1 is faster than the voltage change of the signal line REF2 or the output terminal OUT. .

  According to the above equation (1), the reference voltage VR1 of the signal line REF1 is lower than “VDD−Vth”. Therefore, when the signal line REF1 becomes the reference voltage VR1, the transistor TR1 operates in the saturation region. Accordingly, the bias circuit B2a causes a current to flow from the power supply line VDD to the ground line VSS, generates a voltage divided by the resistance element Rc in the signal line REF2, and the signal line REF2 rises to the vicinity of the reference voltage VR1 ( FIG. 3 (g)). For example, the drive capability of the transistors TR1 and TR2 is designed to be higher than the drive capability of other pMOS transistors (for example, SW3), so that the voltage rise of the signal line REF2 can be made steep. .

  When a current flows between the drain and source of the transistor TR1 operating in the saturation region, the operation region of the transistor TR2 becomes a saturation region. Further, since the current flowing between the drain and source of the transistors TR2 and TR1 also flows between the drain and source of the transistors TR4 and TR3, the operation region of the transistors TR4 and TR3 becomes a saturation region.

  In the activated state (1), since the voltage REF1 is higher than the voltage REF2, the comparator CMP continues to output the high level (VDD) control signal CO2 (FIG. 3 (h)). The switch SW2 receives the high level control signal CO2 and is maintained in the ON state, and maintains the connection between the signal line REF2 and the output terminal OUT. For this reason, the output voltage OUT rises to the vicinity of the reference voltage VR1 following the voltage REF2 (FIG. 3 (i)).

  In other words, in the startup state (1), the differential amplifier AMP does not contribute to the generation of the voltage of the output terminal OUT, and therefore the driving capability of the differential amplifier AMP does not consider the rise of the voltage of the output terminal OUT. Can be designed. Therefore, the driving capability and input capacity of the differential amplifier AMP can be reduced as compared with the conventional case. As a result, the resistance values of the resistance elements Rah and Rbh of the bias circuit B1a can be designed to be higher than the conventional one, and the power consumption of the bias circuit B1a can be suppressed.

  As the voltage REF2 approaches the reference voltage VR1 of the signal line REF1, the increasing speed of the voltage REF2 gradually decreases due to the first-order time constant. Further, when the difference between the voltages REF1 and REF2 supplied to the differential amplifier AMP becomes small, the voltage of the signal line CO1 starts to decrease from the power supply voltage VDD (FIG. 3 (j)).

  In the activated state (2), due to a decrease in the voltage of the signal line CO1, the gate-source voltage of the transistor TR3 decreases and the drain-source resistance increases. Thus, the current flowing from the power supply line VDD to the ground line VSS in the bias circuit B2a is smaller than that in the startup state (1), and the rising speed of the voltage REF2 is higher than that in the startup state (1) (FIG. 3 ( k)). That is, the rising speed of the voltage REF2 increases during a period in which the difference between the voltages REF1 and REF2 is equal to or less than the value V1. The function of the accelerating unit of the bias circuit B2a that increases the generation capability of the voltage REF2 in the activated state (2) is that the drain-source resistance of the transistor TR3 increases in accordance with the decrease in the output voltage CO1 of the differential amplifier AMP. It is realized by.

  Since the switch SW2 receives the high level control signal CO2 and is set to the on state, the output voltage OUT rises following the voltage REF2 (FIG. 3 (l)). That is, the output voltage OUT rises to the reference voltage VR1 at a higher speed than in the prior art.

  As shown by the voltage waveform of the signal line REF2 and the output terminal OUT, the positive feedback loop functions when the rise of the voltage REF2 due to the first-order time constant becomes slow. As a result, the voltage REF2 and the output voltage OUT can be sharply raised as compared with the case where the voltage REF2 is raised by the primary time constant.

  When the voltage REF2 rises to the value VR1, the signal CO1 output from the differential amplifier AMP becomes the ground voltage VSS (FIG. 3 (m)). The operation region of the transistor TR3 becomes a cut-off region when the gate-source voltage becomes lower than the threshold voltage of the transistor TR3. Since the operation region of the transistor TR3 is changed to the cut-off region, no current flows between the drain and the source of the transistor TR3, and the transistor TR4 operates in the linear region because the drain voltage becomes almost equal to the source voltage.

  In the activated state (3), when the voltage REF2 exceeds the voltage REF1, the comparator CMP reduces the voltage of the control signal CO2 from the power supply voltage VDD to the ground voltage VSS (FIG. 3 (n)). As the voltage of the control signal CO2 decreases, the switch SW2 is set to the off state and the switch SW3 is set to the on state. The voltage of the control signal CO2 is used to control the switches SW2 and SW3 and the transistor TR4 that operates similarly to the switch. For this reason, it is not required that the elements in the comparator CMP have high accuracy, and the element size in the comparator CMP can be reduced as compared with a case in which high accuracy is required. As a result, the layout size of the comparator CMP can be reduced, and the power consumption of the comparator CMP can be reduced.

  As the voltage REF2 increases, the operation state of the transistor TR1 changes from the saturation region to the linear region, and the operation region of the transistor TR2 changes from the saturation region to the cutoff region.

  When the OFF timing of the switch SW2 is delayed from the design value due to the decrease in the voltage of the control signal CO2 because the threshold voltage of the nMOS transistor as the switch SW2 is lower than the design value, the signal line REF2 and the output terminal OUT Release of connection with is delayed. As a result, an overshoot that is higher than the value VR1 occurs in the waveform of the output voltage OUT that rises following the voltage REF2 (FIG. 3 (o)).

  However, when the voltage REF2 rises to the value VR2 (= VR1 + Veff1) shown in Equation (2), the operation region of the transistor TR2 becomes a cutoff region. For this reason, it is possible to prevent the overshoot generated at the output terminal OUT from becoming larger than the effective voltage (Veff1; that is, VR2-VR1) of the transistors TR1 and TR2. In other words, since it is not necessary to consider the overshoot that occurs at the output terminal OUT, the drive capability of the bias circuit B2a can be increased compared to when overshoot is taken into consideration, and the signal line REF2 is generated. The time constant of voltage can be reduced.

  When the threshold voltage of the nMOS transistor that is the switch SW2 is manufactured to the design value, the OFF timing of the switch SW2 is as designed, and no overshoot occurs in the waveform of the output voltage OUT.

  Furthermore, since it is not necessary to consider the overshoot generated at the output terminal OUT, it is not required that the elements in the bias circuit B2a have high accuracy. As a result, the element size in the bias circuit B2a can be reduced and the layout size of the bias circuit B2a can be reduced as compared with the case where high accuracy is required.

  The operation region of the transistor TR4 that receives the control voltage CO2 that decreases toward the ground voltage VSS at the gate is a cut-off region, and the through current flowing from the power supply line VDD to the ground line VSS in the bias circuit B2a can be ignored. As a result, the voltage of the signal line REF2 rises to the power supply voltage VDD (FIG. 3 (p)). That is, the ground voltage VSS of the control signal line CO2 and the power supply voltage VDD of the signal line REF2 are determined by a positive feedback loop from the comparator CMP to the transistor TR4 via the control signal line CO2 (latch operation). The operation of each element in the voltage generation circuit VGEN2 is determined by the latch operation by the comparator CMP and the transistor TR4.

  When the switch SW2 is set to the OFF state due to the decrease in the voltage of the control signal CO2, the connection between the input terminal (−) of the differential amplifier AMP and the signal line REF2 by the switch SW2 is released. When the switch SW3 is set to the ON state due to a decrease in the voltage of the control signal CO2, the signal line CO1 that is the output of the differential amplifier AMP is input to the output terminal OUT and the differential amplifier AMP via the switch SW3. Connected to terminal (-). Thereby, the differential amplifier AMP functions as a voltage follower circuit, and steadily outputs the reference voltage VR1 of the signal line REF1 to the signal line CO1 and the output terminal OUT (FIGS. 3 (q) and (r)).

  That is, the differential amplifier AMP functions as a low output impedance buffer unit that receives the reference voltage VR1 from the signal line REF1 and outputs a voltage equal to the reference voltage VR1 to the output terminal OUT. The transistor TR3 that receives the reference voltage VR1 of the signal line CO1 at its gate operates in a linear region.

  In the operating state, the differential amplifier AMP operating as a voltage follower circuit outputs a voltage equal to the reference voltage VR1 of the signal REF1 to the output terminal OUT and the signal line CO1 (FIGS. 3 (s) and (t)). The transistor TR3 operates in the linear region by the reference voltage VR1 of the signal line CO1. However, since the operation region of the transistor TR4 that receives the voltage (VSS) of the control signal CO2 at the gate is a cut-off region, no current flows through the bias circuit B2a, and power consumption does not increase.

  On the other hand, when the enable signal EN is changed from the high level to the low level and returns from the operating state to the power-down state, the bias circuit B1a sets the switch SW1 to the off state and sets the signal line REF1 to the power supply voltage VDD (FIG. 3 (u)). In the bias circuit B2a, the operation region of the transistor TR1 transitions to the cutoff region due to the change of the signal line REF1 to the power supply voltage VDD, and the voltage REF2 decreases toward the ground voltage VSS due to the off-leakage of the transistors TR3 and TR4 ( FIG. 3 (v)).

  When the voltage REF1 becomes higher than the voltage REF2, the comparator CMP changes the voltage of the control signal CO2 from the ground voltage VSS to the power supply voltage VDD (FIG. 3 (w)). As a result, the switch SW2 is set to the on state, and the signal line REF2 is connected to the input terminal (−) and the output terminal OUT of the differential amplifier AMP. Further, the switch SW3 is set to an off state, and the connection between the signal line CO1 that is the output of the differential amplifier AMP and the output terminal OUT is released. The differential amplifier AMP receives the high level of the signal line REF1 and the low level of the signal line REF2, and changes the signal line CO1 from the reference voltage VR1 to the power supply voltage VDD (FIG. 3 (x)). Then, the voltage of the output terminal OUT changes to the ground voltage VSS according to the voltage of the signal line REF2 (FIG. 3 (y)).

  FIG. 4 shows an example of signals and element states in the operation of the voltage generation circuit VGEN2 shown in FIG. “ON” of the switches SW1, SW2, and SW3 indicates an on state (short circuit), and “OFF” of the switches SW1, SW2, and SW3 indicates an off state (open). Since signals and element states in the operation of the voltage generation circuit VGEN2 have already been described with reference to FIG. 3, description thereof is omitted here.

  As described above, when the threshold voltage of the nMOS transistor serving as the switch SW2 is manufactured to the design value, the off timing of the switch SW2 is as designed, and no overshoot occurs in the waveform of the output voltage OUT. In this case, in the startup state (3), the output voltage OUT does not rise to the value VR2, but is maintained at the value VR1.

  As described above, in the embodiment shown in FIGS. 2 to 4 as well, as in the embodiment shown in FIG. 1, the period until the voltage at the output terminal OUT reaches the value VR1 is shortened without increasing the power consumption. can do.

  Furthermore, in this embodiment, the signal lines connected to the differential amplifier AMP are switched by the switches SW2 and SW3. As a result, the differential amplifier AMP functions as a circuit for generating the signal CO1 that accelerates the increase in the voltage REF2 in the activated state (2), and the reference voltage VR1 is applied to the output terminal OUT in the activated state (3) and the operating state. It can function as an output voltage follower circuit.

  Since a positive feedback loop (latch structure) is generated between the bias circuit B2a and the differential amplifier AMP, and between the bias circuit B2a and the comparator CMP, the voltage at the output terminal OUT is compared with the conventional case. The reference voltage VR1 can be raised at a high speed. Further, the positive feedback loop allows the voltage generation circuit VGEN2 to operate autonomously without receiving a control signal, and to output a voltage equal to the reference voltage VR1 to the output terminal OUT. Furthermore, by cutting off the through current path in the bias circuit B2a in the operating state by the positive feedback loop, it is possible to suppress an increase in current consumption.

  The transistor TR4 of the bias circuit B2a is controlled using the signal CO1 output from the output terminal OUT during the start-up state (3) and the operating state. For this reason, even when the threshold voltage of the transistor deviates from the standard value due to fluctuations in the manufacturing conditions of the voltage generation circuit VGEN2 and the OFF timing of the switch SW2 is delayed with respect to the design value, it occurs at the output terminal OUT Overshoot can be minimized.

  The comparator CMP generates a control signal CO2 according to the difference between the voltages REF1 and REF2, and the switches SW2 and SW3 are operated by the control signal CO2. Thereby, the connection between the signal line REF2 and the output terminal OUT in the activated state (2) and the switching between the signal line CO1 and the output terminal OUT in the activated state (3) can be smoothly performed.

  FIG. 5 shows another embodiment of the voltage generation circuit. Elements that are the same as or similar to those described in the embodiment shown in FIG. 2 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The voltage generation circuit VGEN3 of this embodiment includes bias circuits B1a and B2a, an inverter IV, a differential amplifier AMP, switches SW2, SW3 and SW4, and a capacitor CAP. In other words, the voltage generation circuit VGEN3 deletes the comparator CMP from the voltage generation circuit VGEN2 shown in FIG. 2, and adds an inverter IV and a switch SW4. Note that the gate of the nMOS transistor serving as the switch SW2 operates in response to the output signal CO1 output from the differential amplifier AMP. For example, the voltage generation circuit VGEN3 is mounted on a semiconductor integrated circuit and functions as a constant voltage generation circuit that generates a constant voltage supplied to an internal circuit in the semiconductor integrated circuit.

  The bias circuit B1a is designed to generate the reference voltage VR1 shown in Expression (1), and the bias circuit B2a is designed to generate the voltage VR2 shown in Expression (2). The resistance value of the resistance element Rc in the bias circuit B2a is designed to a value shown in Expression (4).

  For example, the inverter IV is a CMOS inverter in which a pMOS transistor PT and an nMOS transistor NT are connected in series between a power supply line VDD and a ground line VSS. The inverter IV receives the signal REF2 at the input, inverts the logic indicated by the voltage of the signal line REF2, and outputs the inverted signal as the control signal CO2. For example, the threshold voltage of the inverter IV is designed to a value VTI higher than the voltage VR2 shown in the equation (2). The inverter IV is an example of a buffer circuit that outputs a control signal CO2 when the reference voltage REF2 rises to a value VTI higher than the reference voltage VR1. The control signal CO2 is an example of a detection signal indicating that the reference voltage REF2 has increased to a value VTI higher than the reference voltage VR1.

  The switch SW4 is an nMOS transistor whose gate is connected to the control signal line CO2, one of its drain and source is connected to the switch SW2, and the other of its drain and source is connected to the input terminal (−) of the differential amplifier AMP. .

  FIG. 6 shows an example of the operation of the voltage generation circuit VGEN3 shown in FIG. That is, FIG. 6 shows another embodiment of the method for controlling the voltage generation circuit. Detailed descriptions of the same or similar operations as those in FIG. 3 are omitted.

  In FIG. 6, as in FIG. 3, the enable signal EN is set from the low level to the high level during the power-down state in which the voltage generation circuit VGEN3 stops operating, and the voltage generation circuit VGEN3 enters the operation state. In response to the change from the low level to the high level of the enable signal EN, the voltage generation circuit VGEN3 enters the operating state through the transitional state of the startup state (1), the startup state (2), and the startup state (3). Become. Furthermore, the voltage generation circuit VGEN3 enters a power-down state in response to a change from the high level to the low level of the enable signal EN during the operation state.

  The operations in the power down state, the start state (1), the start state (2), and the operation state are the same as those in FIG. That is, the function of the comparator CMP shown in FIG. 2 is realized by the inverter IV and the switch SW4 in the power down state, the start state (1), the start state (2), and the operation state in the voltage generation circuit VGEN3. The switch SW4 connects the switch SW2 and the input terminal (−) of the differential amplifier AMP during a period when the voltage of the control signal CO2 is high.

  In the activated state (3), when the voltage of the signal line REF2 exceeds the voltage VTI, which is the threshold voltage of the inverter IV, the inverter IV reduces the voltage of the control signal CO2 from the power supply voltage VDD to the ground voltage VSS (FIG. 6 (a)). Due to the decrease in the voltage of the control signal CO2, the switch SW4 is set to the off state, the switch SW3 is set to the on state, and the operation region of the transistor TR4 becomes a cut-off region.

  When the transistor TR4 operates in the cutoff region, the through current flowing from the power supply line VDD to the ground line VSS in the bias circuit B2a can be ignored. As a result, the voltage of the signal line REF2 rises to the power supply voltage VDD (FIG. 6B). That is, the ground voltage VSS of the control signal line CO2 and the power supply voltage VDD of the signal line REF2 are determined by a positive feedback loop from the inverter IV to the transistor TR4 via the control signal line CO2 (latch operation).

  When the switch SW4 is set to an off state and the switch SW3 is set to an on state due to a decrease in the voltage of the control signal CO2, the signal line CO1 that is the output of the differential amplifier AMP is output via the switch SW3 to the output terminal OUT. And the input terminal (−) of the differential amplifier AMP. Thereby, the differential amplifier AMP functions as a voltage follower circuit and outputs the reference voltage VR1 to the signal line CO1 and the output terminal OUT (FIGS. 6C and 6D).

  Similarly to FIG. 3, when the off timing of the switch SW2 due to the decrease in the voltage of the control signal CO2 is delayed from the design value due to the threshold voltage of the switch SW2 being lower than the design value, the signal line REF2 and the output Release of connection with the terminal OUT is delayed. As a result, an overshoot higher than the reference voltage VR1 occurs at the output terminal OUT, but the operating region of the transistor TR2 becomes a cut-off region due to a rise in the voltage of the signal line REF2. For this reason, it is possible to prevent the overshoot generated at the output terminal OUT from becoming larger than the effective voltage (Veff1; that is, VR2-VR1) of the transistors TR1 and TR2 (FIG. 6E). When the threshold voltage of the nMOS transistor that is the switch SW2 is manufactured to the design value, the OFF timing of the switch SW2 is as designed, and no overshoot occurs in the waveform of the output voltage OUT.

  When the signal line CO1 rises to the reference voltage VR1 by the differential amplifier AMP that operates as a voltage follower circuit, the switch SW2 enters an indeterminate state in which the ON state and the OFF state cannot be determined, and the transistor TR3 may operate in the linear region. is there. However, since the signal line REF2 is disconnected from the differential amplifier AMP by the switch SW4 that receives the low level of the control signal CO2 at the gate, the voltage of the signal line REF2 is not transmitted to the output terminal OUT.

  Further, since the transistor TR4 that receives the low level of the control signal CO2 at the gate disconnects the signal line REF2 and the ground line VSS in the bias circuit B2a, the voltage of the signal line REF2 does not decrease. That is, the latch operation by the positive feedback loop from the inverter IV to the transistor TR4 via the control signal CO2 is maintained.

  FIG. 7 shows an example of signals and element states in the operation of the voltage generation circuit VGEN3 shown in FIG. Detailed description of the same or similar state as in FIG. 4 is omitted. FIG. 7 is the same as the state of FIG. 4 except the following states. Note that the condition when the transistor operates in the saturation region is defined by Equation (7), and the condition when the transistor operates in the linear region is defined by Equation (9), and the transistor operates in the cutoff region. Is defined by the equation (11).

  The state of the switch SW4 is the ON state ON in the power down state, the startup state (1), and the startup state (2), and changes from the ON state ON to the OFF state OFF in the startup state (3). Further, the state of the switch SW4 in the operating state is an off state.

  In the activated state (2), the voltage of the signal line REF2 rises to the value VTI that is the threshold voltage of the inverter IV, and the voltage of the output terminal OUT rises to the value VR2 shown in Expression (2). In the activated state (2), the switch SW2 changes from the on state to the off state due to a decrease in the voltage of the signal line CO1.

  In the activated state (3), the voltage of the signal line REF2 changes from the value VTI to the power supply voltage VDD, and the switch SW2 changes from the off state to the indeterminate state according to the change of the control signal CO2 from the low level to the value VR1. To do. The state of the switch SW2 in the operating state is indefinite depending on the voltage value VR1 of the control signal CO2.

  As described above, when the threshold voltage of the nMOS transistor serving as the switch SW2 is manufactured to the design value, the off timing of the switch SW2 is as designed, and no overshoot occurs in the waveform of the output voltage OUT. In this case, in the startup state (2) and the startup state (3), the output voltage OUT does not increase to the value VR2, but is maintained at the value VR1.

  As described above, in this embodiment as well, as in the embodiment shown in FIG. 1, the period until the voltage at the output terminal OUT reaches the value VR1 can be shortened without increasing the power consumption.

  Similarly to the embodiments shown in FIGS. 2 to 4, the differential amplifier AMP can function as a signal CO1 generation circuit or a voltage follower circuit by the switching operation by the switches SW2, SW3, and SW4. The voltage generation circuit VGEN2 can be operated autonomously by a positive feedback loop generated between the bias circuit B2a and the differential amplifier AMP and between the bias circuit B2a and the comparator CMP. As a result, the voltage at the output terminal OUT can be raised to the reference voltage VR1 at a higher speed than in the prior art. Furthermore, by cutting off the through current path in the bias circuit B2a in the operating state by the positive feedback loop, it is possible to suppress an increase in current consumption. Even when the threshold voltage of the transistor that is the switch SW2 is deviated from the standard value and the off timing of the switch SW2 is delayed from the design value, the overshoot generated at the output terminal OUT can be minimized. .

  Furthermore, in this embodiment, the circuit scale of the voltage generation circuit VGEN3 can be reduced by generating the control signal CO2 using the inverter IV having a simpler circuit configuration than the comparator CMP.

  FIG. 8 shows another embodiment of the voltage generation circuit. Elements that are the same as or similar to those described in the embodiment shown in FIGS. 2 and 5 are given the same reference numerals, and detailed descriptions thereof are omitted. In FIG. 8, a transistor starting with the symbol “P” indicates a pMOS transistor, and a transistor starting with the symbol “N” indicates an nMOS transistor.

  The voltage generation circuit VGEN4 of this embodiment includes bias circuits B1a, B2b, B3, B4, a differential amplifier AMP, transistors NT1, PT2, a capacitor CAP, and an inverter IV2. For example, the voltage generation circuit VGEN4 is mounted on a semiconductor integrated circuit and functions as a constant voltage generation circuit that generates a constant voltage supplied to an internal circuit in the semiconductor integrated circuit.

  Similarly to FIG. 2, the capacitor CAP equivalently shows the load of the internal circuit in the semiconductor integrated circuit connected to the output terminal OUT of the voltage generation circuit VGEN4. The inverter IV2 is a CMOS inverter, for example, and outputs an enable signal / EN obtained by inverting the logic level of the enable signal EN.

  The bias circuit B1a is the same or similar circuit as the bias circuit B1a in FIG. The bias circuit B1a sets the signal line REF1 to the reference voltage VR1 according to the equation (1) during a period when the enable signal EN is at a high level, and sets the voltage of the signal line REF1 to the power supply voltage VDD during a period when the enable signal EN is at a low level. Set to.

  The bias circuit B2b includes transistors P21, P22, N21, N22, and N23 connected in series between the power supply line VDD and the ground line VSS, and a transistor P23 connected in series between the power supply line VDD and the ground line VSS. N24 and N25.

  The gate of the transistor P21 is connected to the signal line REF2 which is the drain of the transistor P22, and the gates of the transistors P22 and P23 are connected to the signal line REF1. The gates of the transistors N21 and N24 are connected to the drain of the transistor N24 and the gates of the transistors N42 and N43 of the bias circuit B4. The gates of the transistors N22 and N25 are connected to the signal line REF3, and the gate of the transistor N23 is connected to the signal line CO1.

  The transistors P21, P22, N22, and N23 correspond to the transistors TR2, TR1, TR4, and TR3 of the bias circuit B2a shown in FIG. 2, respectively, and the transistor N21 corresponds to the resistance element Rc of the bias circuit B2a shown in FIG. To do. The transistors N21 and N24 function as a current mirror circuit while the source is connected to the ground line VSS. As illustrated in FIG. 9, the transistor N23 accelerates to increase the generation capability of the voltage output to the signal line REF2 during the startup state (1) in which the voltage difference between the signal lines REF1 and REF2 is equal to or lower than the reference voltage VR1. It is an example of a part.

  Similarly to the bias circuit B2a shown in FIG. 2, the bias circuit B2b generates a voltage on the signal line REF2 according to the voltage of the signal line REF1. The bias circuit B2b is designed to generate the voltage VR2 on the signal line REF2 according to the equation (2) during the period when the signal line REF1 is set to the reference voltage VR1. The bias circuit B2b operates by receiving the voltage of the signal line CO1 whose voltage decreases as the voltage of the signal line REF2 increases at the gate of the transistor N23. For this reason, the voltage of the signal line REF2 rises to the reference voltage VR1 lower than the voltage VR2 in the startup state (1) shown in FIG.

  The bias circuit B3 includes transistors P31, N31, N32, N33, and N34 connected in series between the power supply line VDD and the ground line VSS, and a transistor P32 connected in series between the power supply line VDD and the ground line VSS. P33, N35, N36, and N37.

  The gates of the transistors P31 and P32 are connected to the drain of the transistor P33. The gate of transistor P33 receives enable signal / EN, and the gate of transistor N32 receives enable signal EN. The transistor P33 that receives the enable signal / EN and the transistor N32 that receives the enable signal EN function as switches.

  The gate and drain of the transistor N31 are connected to the signal line REF3. The gates of the transistors N33 and N35 are connected to the signal line REF1, and the gate of the transistor N34 is connected to the source of the transistor N31. The gate of the transistor N36 is connected to the signal line REF3, and the gate of the transistor N37 is connected to the signal line CO1.

  After the enable signal EN is set to the high level, the bias circuit B3 generates the voltage VR3 shown in the equation (12) on the signal line REF3 in the startup state (1) shown in FIG. The bias circuit B3 is an example of a third voltage generator that outputs a voltage VR3 higher than the reference voltage VR1 by a predetermined value to the signal line REF3. The bias circuit B3 is designed to generate the voltage VR3 shown in Equation (12). In the equation (12), the symbol Veffn is an effective voltage obtained by subtracting the threshold voltage Vth of the transistors N31 and N33 from the gate-source voltage Vgs of the transistors N31 and N33, as in the equation (3).

  The bias circuit B4 includes transistors P41, P42, P43, N41, and N42 connected in series between the power supply line VDD and the ground line VSS, and a transistor P44 connected in series between the power supply line VDD and the ground line VSS. P45, N43, and N44.

  The gate of the transistor P41 is connected to the drain of the transistor P42, and the gates of the transistors P42 and P44 are connected to the drain of the transistor P45. Transistor P45 receives enable signal / EN at its gate and functions as a switch. The gate and drain of the transistor P43 are connected to the signal line REF4.

  The transistor N41 receives the enable signal EN at its gate and functions as a switch. The gates of the transistors N42 and N43 are connected to the gates of the transistors N21 and N24 and the drain of the transistor N24 of the bias circuit B2b. The gate of the transistor N44 is connected to the signal line REF3.

In the starting state (1) after the enable signal EN is set to the high level, the bias circuit B4 generates the voltage VR4 shown in Expression (13) on the signal line REF4. The bias circuit B4 is an example of a fourth voltage generator that outputs a voltage VR4 that is lower than the reference voltage VR1 by a predetermined value to the signal line REF4.
The bias circuit B4 is designed to generate the voltage VR4 shown in Equation (13). In the equation (13), the symbol Veffp is an effective voltage obtained by subtracting the threshold voltage Vth of the transistor P42 from the gate-source voltage Vgs of the transistor P42, as in the equation (3). The symbol Veffp is an effective voltage obtained by subtracting the threshold voltage Vth of the transistor P43 from the gate-source voltage Vgs of the transistor P43.

  As in FIG. 2, the differential amplifier AMP has an input terminal (+) connected to the signal line REF1, an input terminal (−) connected to the output terminal OUT, and an output connected to the signal line CO1.

  The transistor NT1 has a gate connected to the signal line REF3, one of the drain and the source connected to the signal line REF2, and the other of the drain and the source connected to the input terminal (−) and the output terminal OUT of the differential amplifier AMP. The transistor NT1 is an nMOS transistor, and is arranged instead of the switch SW2 shown in FIG.

  The transistor PT2 has a gate connected to the signal line REF4, one of the drain and the source connected to the signal line CO1, and the other of the drain and the source connected to the output terminal OUT. The transistor PT2 is a pMOS transistor, and is arranged instead of the switch SW3 shown in FIG.

  The constants Kp, Kp / 4, Kp / 9 shown in the transistors P22, P21, P23 and the constants Kp, Kp, Kp / 4, Kp / 9 shown in the transistors P42, P43, P41, P44 are “Kp” in the pMOS transistor. This corresponds to the constant K shown in Equation (5). “Kn” of the constants Kn, Kn, Kn / 4, and Kn / 9 shown in the transistors N31, N33, N34, and N35 corresponds to the constant K shown in Expression (5) in the nMOS transistor.

The ratio of the constants Kp and Kn shown in FIG. 8 is set in order to facilitate the calculation of the expressions (1), (2), and (12) for designing the voltage values VR1, VR2, and VR3. However, if the ratio of the constant Kn shown in FIG. 8 is Kn / a, Kn / b, Kn / c, if b> a and c ² ≧ b ² + a ² are satisfied, a = It may be a positive real number other than 1, b = 4, and c = 9.

  The constants K of the pMOS transistors excluding the transistors P45 and P33 and the pMOS transistor for which the constant Kp is designated are designed to have the same value. Similarly, the constants K of the nMOS transistors excluding the switch SW1, the transistors N41 and N32, and the nMOS transistor for which the constant Kn is designated are designed to have the same value.

  FIG. 9 shows an example of the operation of the voltage generation circuit VGEN4 shown in FIG. That is, FIG. 9 shows another embodiment of the method for controlling the voltage generation circuit. Detailed description of the same or similar operations as those in FIGS. 3 and 6 will be omitted. The operation of the bias circuit B1a is the same as that of FIG. 3, and the voltage waveform of the signal line REF1 is the same as that of FIG.

  In the example shown in FIG. 9, when the enable signal EN is set from the low level to the high level, the voltage generation circuit VGEN4 changes the startup state (1) and the startup state (2), which are transitional states from the power-down state. After that, it becomes operational. Furthermore, the voltage generation circuit VGEN3 enters a power-down state in response to a change from the high level to the low level of the enable signal EN during the operation state.

  First, in the power down state, the enable signal EN is set to a low level (VSS), and the enable signal / EN is set to a high level (VDD). Therefore, the switch SW1 and the transistors N32, P33, N41, and P45 that function as the switches are set to an off state.

  In the power down state, the bias circuit B1a sets the signal line REF1 to the power supply voltage VDD (FIG. 9 (a)). The transistors P22 and P23 of the bias circuit B2b operate in the cutoff region by receiving the high level (VDD) of the signal line REF1 at the gate. The transistors N22 and N25 of the bias circuit B2b operate in a linear region by receiving the high level (VDD) of the signal line REF3 at the gate. The transistor N23 of the bias circuit B2b operates in a linear region by receiving the high level (VDD) of the signal line CO1 at the gate.

  Since the transistor P23 is in the cutoff region, the transistor N24 whose drain and gate are connected to the drain of the transistor P23 lowers the gate voltage and moves to the cutoff region. However, the gate voltage of the transistor N24 has a value that balances the leakage current in the cutoff region shown in Expression (10) with the leakage current of the transistor P23. That is, the gate voltage of the transistor N24 becomes a voltage close to the ground voltage VSS by the exponential function shown in Expression (10). At this time, since the transistors N21 and N24 whose gates are connected to each other function as a current mirror circuit, the voltage of the signal line REF1 is set to the ground voltage VSS by the off-leak current of the transistor N21 (FIG. 9B).

  In the power down state, the transistor N37 of the bias circuit B3 operates in the linear region by receiving the high level (VDD) of the signal line CO1 at the gate. The transistors N33 and N35 receive the high level (VDD) of the signal line REF1 at their gates, and the transistors N32 and P33 receive the enable signals EN and / EN at their gates, respectively. Work in the region. As a result, the gate voltages of the transistors P32 and P31 are equivalent to the ground voltage VSS and operate in a linear region. The operation of the transistors P31 and N33 in the linear region and the cutoff of the transistor N32 set the voltage of the signal line REF3 to the power supply voltage VDD (FIG. 9C). The transistors N34 and N36 operate in a linear region with a gate voltage equivalent to the power supply voltage VDD, and N31 operates in a cutoff region with the gate and source having the same potential.

  In the bias circuit B4, the transistors N42 and N43 function as a current mirror circuit together with the transistors N21 and N24 of the bias circuit B2b. The gate voltages of the transistors P42 and P44 are set to a low level, and the transistors P42 and P44 operate in a linear region. Since the transistor N41 receives the low level (VSS) enable signal EN at the gate and is cut off, the voltage of the signal line REF4 is set to the power supply voltage by the current supplied from the power supply line VDD via the transistors P41, P42, and P43. It is set to VDD (FIG. 9 (d)). In the transistor P43, the gate, the drain, and the source have the same potential (VDD), and the transistor P43 operates in the cutoff region.

  The transistor NT1 receives the high level (VDD) of the signal line REF3 at its gate and operates in a linear region. The input terminal (−) and the output terminal OUT of the differential amplifier AMP are set to the same ground voltage VSS as the voltage of the signal line REF2. Setting is made (FIG. 9E). The transistor PT2 operates in the cutoff region by receiving the high level (VDD) of the signal line REF4 at the gate. The differential amplifier AMP has a high level on the signal line CO1 according to the high level (VDD) of the signal line REF1 received at the input terminal (+) and the low level (VSS) of the signal line REF2 received at the input terminal (−). (VDD) is output (FIG. 9F).

  In the power-down state, each of the bias circuits B1a, B2b, B3, and B4 shuts off any of the transistors, so that no through current flows between the power supply line VDD and the ground line VSS. As a result, the standby current of the voltage generation circuit VGEN4 can be reduced as compared with the standby current of the voltage generation circuit having a bias circuit that constantly flows a leak current.

  Next, in response to the change of the enable signal EN from the low level (VSS) to the high level (VDD), the state of the voltage generation circuit VGEN4 changes from the power-down state to the startup state (1). Similarly to FIG. 3, the bias circuit B1a sets the signal line REF1 to the reference voltage VR1 (FIG. 9 (g)). The inverter IV2 receives the enable signal EN at the high level and outputs the enable signal / EN at the low level (VSS).

  In the activated state (1), the transistors P22 and P23 of the bias circuit B2b operate in the saturation region by receiving the reference voltage VR1 at the gate. Similarly to the bias circuit B2a shown in FIG. 2, the transistors P21, P22, N21, N22, and N23 operate, so that the voltage of the signal line REF2 rises from the ground voltage VSS to the reference voltage VR1 (FIG. 9). (H)).

  In the bias circuit B4, the transistor P45 receives the low level enable signal / EN at the gate and is turned on, and the drain voltage of the transistor P45 rises. The transistor N41 receives the high level enable signal EN at the gate and is turned on. The transistors N42 and N43 operate as a current mirror circuit together with the transistors N21 and N24 of the bias circuit B2b. Thereby, the bias circuit B4 operates in the same manner as the bias circuit B2b, and generates the voltage VR4 on the signal line REF4 according to the equation (13). That is, the voltage of the signal line REF4 is set to the voltage VR4 that is lower than the reference voltage VR1 by the threshold voltage of the transistor P43 (FIG. 9 (i)). The transistor P43 is a standard pMOS transistor included in the voltage generation circuit VGEN4.

  In the bias circuit B3, the transistor P33 receives the low level enable signal / EN at the gate and is turned on, and the drain voltage of the transistor P33 rises. As a result, the current flowing through the transistors P31 and P32 (functioning as a current mirror circuit) whose gate is connected to the drain of the transistor P33 is smaller than that in the power-down state.

  The transistor N32 receives the high level enable signal EN at the gate and is turned on. The transistors N33 and N35 receive the reference voltage VR1 of the signal line REF1 at their gates and operate in the saturation region. Thereby, the bias circuit B3 generates the voltage VR3 on the signal line REF3 according to the equation (12). That is, the voltage of the signal line REF3 is set to a voltage VR3 that is higher than the reference voltage VR1 by the threshold voltage of the transistor N31 (FIG. 9 (j)). The transistor N31 is an nMOS transistor having standard electrical characteristics arranged in a semiconductor integrated circuit on which the voltage generation circuit VGEN4 is mounted.

  In the activated state (1), the difference between the voltage of the signal line REF3 and the voltage of the signal line REF2 is equal to or higher than the threshold voltage of the transistor NT1, so that the transistor NT1 operates in the linear region or the saturation region. The transistor NT1 transmits the voltage of the signal line REF2 to the input terminal (−) and the output terminal OUT of the differential amplifier AMP. As a result, the voltage at the output terminal OUT rises to the reference voltage VR1 following the rise in the voltage of the signal line REF2 (FIG. 9 (k)).

  In the transistor NT1 that receives the voltage VR3 of the signal line REF3 at the gate, the gate-source voltage decreases and the drain-source resistance gradually increases as the voltage of the signal line REF2 increases. When the voltage of the signal line REF2 rises to the value VR1, the gate-source voltage of the transistor NT1 becomes equal to the threshold voltage of the transistor NT1. Thereby, the voltage of the signal line REF2 higher than the value VR1 is not transmitted to the output voltage OUT through the transistor NT1, and it is possible to suppress the occurrence of overshoot in the output voltage OUT.

  Further, when the voltage of the signal line REF2 reaches the reference voltage VR1, the gate-source voltage (voltage difference between REF1 and REF2) of the transistor NT1 becomes equal to the threshold voltage of the transistor NT1. As a result, the drain-source resistance of the transistor NT1 further decreases, and the gain becomes substantially zero. Therefore, the voltage of the signal line CO1 that changes toward the reference voltage VR1 can be smoothly changed without greatly deviating from the reference voltage VR1. It decreases (FIG. 9 (l)). In other words, the voltage of the signal line CO1 is made lower than the reference voltage VR1 by operating the differential amplifier AMP as an inverting amplifier in which the resistance value R1 gradually increases (resistance ratio R2 / R1 gradually decreases). Without being changed to the reference voltage VR1.

  As a result, the voltage generation circuit VGEN4 accelerates the bias circuit B2a that increases the generation capability of the voltage REF2 at the time of the startup state (1) prior to the startup state (2) like the voltage generation circuits VGEN1, VGEN2, and VGEN3. This function can be realized by increasing the drain-source resistance of the transistor N23 in accordance with the decrease in the output voltage CO1 of the differential amplifier AMP.

  Since the gate voltage of the transistor NT1 is the value VR3, the transistor NT1 is cut off when the voltage of the signal line REF2 and the voltage of the output terminal OUT reach the value VR1, and the signal line REF2 is transmitted to the output terminal OUT. Overshoot due to will not occur.

  Next, in the activated state (2), the drain current of the transistor N37 of the bias circuit B3 decreases due to the voltage of the signal line CO1 lowered to the reference voltage VR1, and the gate voltages of the transistors P31 and P32 increase. As a result, the ability to supply drain current from the power supply line VDD to the transistor N31 decreases, and the voltage of the signal line REF3 decreases (FIG. 9 (m)). The transistor N37 is an example of a first suppression circuit that decreases the reference voltage REF3 in response to a decrease in the output voltage CO1 from the differential amplifier AMP.

  When the voltage of the signal line REF3 is lowered, the drain current of the transistor N36 of the bias circuit B3 is further reduced, so that the voltage of the signal line REF3 is further lowered. The transistor N36 is an example of a second suppression circuit that further decreases the voltage of the signal line REF3 in response to a decrease in the voltage of the signal line REF3.

  As the voltage of the signal line REF3 decreases, the transistors N22 and N25 of the bias circuit B2b operate in the cutoff region, and the voltage of the signal line REF2 rises to the power supply voltage VDD (FIG. 9 (n)).

  On the other hand, as the voltage of the signal line REF3 decreases, the drain current of the transistor N44 of the bias circuit B4 decreases, and the gate voltages of the transistors P42 and P44 increase. As a result, the drain current of the transistor P42 decreases, the drain current supply capability from the power supply line VDD to P43 decreases, and the voltage of the signal line REF4 decreases (FIG. 9 (o)). The transistor N44 is an example of a third suppression circuit that decreases the voltage of REF4 in response to the voltage decrease of REF3.

  In this way, the bias circuit B3 fixes the voltage of the signal line REF3 to the ground voltage VSS (latch operation) using the decrease in the voltage of the signal line CO1 in the activated state (1) as a trigger. Similarly, using the decrease in the voltage of the signal line CO1 and the decrease in the voltage of the signal line REF3 as triggers, the bias circuit B2b fixes the voltage of the signal line REF2 to the power supply voltage VDD (latch operation). Similarly, with the voltage drop of the signal line REF3 as a trigger, the bias circuit B4 uses the AMP and the output CO1 of the inverting amplifier composed of NT1 and NT2 and the voltage of the REF4 to the ground voltage VSS through the drop of the output signal line REF3 of the bias circuit B3. (Latch operation).

  When the gate-source voltage of the transistor NT1 becomes lower than the threshold voltage of the transistor NT1 due to the rise of the voltage of the signal lines REF2 and OUT and the decrease of the voltage of the signal line REF3, the operation region of the transistor NT1 becomes a cutoff region. On the other hand, the voltage between the gate and source of the transistor PT2 gradually increases as the voltage of the signal line REF4 decreases. The drain-source voltage Vds of the transistor PT2 becomes small due to the rise of the voltage of the output terminal OUT and the fall of the voltage of the signal line CO1. As shown in Expression (9), when the drain-source voltage Vds of the transistor PT2 becomes smaller than the value obtained by subtracting the threshold voltage Vth of the transistor PT2 from the gate-source voltage Vgs, the operation region of the transistor PT2 is From the saturation region to the linear region.

  In this embodiment, the transistor NT1 is arranged instead of the switch SW2 shown in FIG. 2, and the transistor PT2 is arranged instead of the switch SW3 shown in FIG. As a result, the transistor NT1 can be gradually shifted from the linear region to the cutoff region via the saturation region from the activation state (1) to the activation state (2), and the transistor PT2 can be transitioned via the saturation region. The transition from the blocking region to the linear region can be made gradually. That is, the voltage output to the output terminal OUT can be gradually switched from the voltage of the signal line REF2 to the voltage of the signal line CO1, and can be smoothly raised to the value VR1.

  Since the output of the differential amplifier AMP and the input terminal (−) are connected via the transistor PT2, the differential amplifier AMP starts operation as a voltage follower circuit in the activated state (2). That is, the differential amplifier AMP outputs the same voltage as the reference voltage VR1 of the signal line REF1 to the signal line CO1 and the output terminal OUT (FIGS. 9 (p) and (q)).

  In the operating state, the voltages of the signal lines REF3 and REF4 are reduced to the ground voltage VSS, and the state at the end of the startup state (2) is maintained. That is, the differential amplifier AMP operates as a voltage follower circuit during the period of the operation state, and steadily outputs the reference voltage VR1 of the signal line REF1 to the signal line CO1 and the output terminal OUT (FIG. 9 (r), ( s)).

  When the enable signal EN is changed from the high level to the low level and returns from the operating state to the power-down state, the bias circuit B1a sets the switch SW1 to the off state and sets the signal line REF1 to the power supply voltage VDD (FIG. 9 ( t)).

  In the bias circuit B2b, when the signal line REF1 changes to the power supply voltage VDD, the operation region of the transistor P22 changes from the linear region to the cutoff region. The transistor N32 of the bias circuit B3 is cut off in response to the low level enable signal EN, and the transistors N33 and N35 operate in the linear region in response to the high level of the signal line REF1. The transistors P45 and N41 of the bias circuit B4 are cut off in response to the enable signals / EN and EN, respectively. Thereby, the voltages of the signal lines REF3 and REF4 start to rise (FIG. 9 (u)).

  When the voltage of the signal line REF1 becomes higher than the reference voltage VR1 of the output terminal OUT, the differential amplifier AMP changes the voltage of the signal line CO1 from the reference voltage VR1 to the power supply voltage VDD (FIG. 9 (v)). As the voltage of the signal line CO1 increases, the operation region of the transistor N23 of the bias circuit B2b changes from the cutoff region to the linear region, and the voltage of the signal line REF2 is decreased (FIG. 9 (w)).

  In the bias circuit B3, the transistor N36 operates in the linear region in response to the increase in the voltage of the signal line REF3, and the transistor N37 operates in the linear region in response to the increase in the voltage of the signal line CO1. As a result, the gate voltages of the transistors P31 and P32 decrease, and the voltage of the signal line REF3 increases to the power supply voltage VDD.

  The transistor N44 of the bias circuit B4 operates in the linear region in response to a rise in the voltage of the signal line REF3. The transistor P45 receives the high level enable signal / EN at the gate and is cut off, and the gate voltages of the transistors P42 and P43 decrease. Since the transistor N41 receives the low level enable signal EN and shuts off at the gate, the voltage of the signal line REF4 rises to the power supply voltage VDD.

  As the voltage of the signal line REF3 increases, the transistor NT1 operates in the linear region, and as the signal line REF4 increases, the transistor PT2 operates in the cutoff region. Thus, the output terminal OUT is connected to the signal line REF2 via the transistor NT1, and decreases following the decrease in the voltage of the signal line REF2 (FIG. 9 (x)).

  FIG. 10 shows an example of signals and element states in the operation of the voltage generation circuit VGEN4 shown in FIG. The meanings of symbols such as “OFF”, “ON”, and “Linear” indicating the signal and element states are the same as those in FIG. Since signals and element states in the operation of the voltage generation circuit VGEN4 have already been described with reference to FIG. 9, description thereof is omitted here.

  As described above, in the embodiment shown in FIGS. 8 to 10, as in the embodiment shown in FIG. 1, the period until the voltage at the output terminal OUT reaches the value VR1 is shortened without increasing the power consumption. can do.

  Similarly to the embodiments shown in FIGS. 2 to 4, the differential amplifier AMP can function as a signal CO1 generation circuit or a voltage follower circuit by the switching operation by the transistors NT1 and PT2. The voltage generation circuit VGEN4 can be operated autonomously by a positive feedback loop generated between the bias circuit B2b and the differential amplifier AMP. As a result, the voltage at the output terminal OUT can be raised to the reference voltage VR1 at a higher speed than in the prior art. Furthermore, by cutting the through current path in the bias circuit B2b in the operating state by the positive feedback loop, it is possible to suppress an increase in current consumption.

  Furthermore, in this embodiment, the rising speed of the voltage of the signal line REF2 can be increased from the start state (1), and the period until the voltage of the output terminal OUT reaches the value VR1 can be shortened.

  In the startup state (1), the inverting amplifier including the amplifier AMP and the transistors PT2 and NT1 can reduce the voltage of the signal line CO1 from the beginning of the startup state (1). For this reason, the rising speed of the signal line REF2 through the transistor N23 from the start point of the activation state (1) increases, and the period until the output voltage OUT reaches the value VR1 can be further shortened. Further, since the gate voltage of the transistor NT1 is the value VR3, the transistor NT1 becomes a cut-off region when the voltage of the signal line REF2 becomes larger than the value VR1 from the start state (1) to the start state (2), and the signal line REF2 Is not transmitted to the output terminal OUT. Similarly, since the gate voltage of the transistor PT2 is the value VR4, the transistor PT2 becomes a linear region when the voltage of the signal line CO1 and the output terminal OUT approaches the value VR1 from the activated state (1) to the activated state (2). As a result, the voltage of the signal line CO1 is fed back to the input terminal (−) of the differential amplifier AMP to form a voltage follower circuit, so that the voltage of the signal line CO1 and the output terminal OUT does not fall below the value VR1.

  By supplying the voltage of the signal line CO1 to the bias circuit B3, the voltage of the signal line REF3 can be autonomously lowered in the activated state (2). By feeding back the voltage of the signal line REF3 to the bias circuit B3, the voltage of the signal line REF3 can be further lowered in the startup state (2). Further, by supplying the voltage of the signal line REF3 to the bias circuit B4, the voltage of the signal line REF4 can be autonomously lowered in the activated state (2). As a result, the voltage generation circuit VGEN4 can be operated autonomously, and the output voltage OUT can be raised to the reference voltage VR1 at a higher speed than in the prior art.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A first voltage generator that outputs a first voltage to the first signal line in response to the activation signal;
A second voltage generator for outputting a second voltage to a second signal line based on the first voltage;
A buffer unit that receives the first voltage and outputs an output voltage;
An output terminal of the second voltage generator is connected to an output voltage terminal in a first period in which the second voltage is smaller than the first voltage, and the second voltage is equal to or higher than the first voltage. And a switch unit for connecting the output terminal of the buffer unit to the output voltage terminal.
The second voltage generation unit includes the second voltage and the second voltage in the second period in which a difference between the second voltage and the first voltage is equal to or less than a first value in the first period. A voltage generation circuit comprising: an accelerating unit that increases a generation capability of the second voltage compared to a period in which a difference from the first voltage is greater than the first value.
(Appendix 2)
The first voltage generator outputs a voltage higher than the first voltage to the first signal line before receiving the activation signal,
The voltage generation circuit according to claim 1, wherein the second voltage generation unit outputs a voltage lower than the first voltage when the first voltage is not output to the first signal line. .
(Appendix 3)
The buffer unit includes a differential amplifier having a first input terminal connected to the output terminal of the first voltage generation unit and a second input terminal connected to the output voltage terminal;
The switch part is
When the second voltage is smaller than the first voltage, the output terminal of the second voltage generator is connected to the second input terminal of the differential amplifier, and the second voltage is the first voltage. A first switch that cuts off the connection between the output terminal of the second voltage generator and the second input terminal of the differential amplifier when the voltage is equal to or higher than
When the second voltage is smaller than the first voltage, the connection between the output terminal of the differential amplifier and the output voltage terminal is cut off, and when the second voltage is equal to or higher than the first voltage. The voltage generation circuit according to claim 1 or 2, further comprising: a second switch that connects an output terminal of the differential amplifier to the output voltage terminal.
(Appendix 4)
A comparator that compares the first voltage with the second voltage and generates a control signal for controlling the operation of the first switch and the second switch according to the comparison result;
The second voltage generator includes a first transistor and a second transistor having a first polarity, a resistance element, and a third transistor and a fourth transistor having a second polarity,
A source of the first transistor is connected to a first power line;
The gate of the first transistor, the drain of the second transistor, and one end of the resistance element are connected to the output terminal of the second voltage generator,
A source of the second transistor is connected to a drain of the first transistor;
A gate of the second transistor is connected to an output terminal of the first voltage generator;
A drain of the third transistor is connected to the other end of the resistance element;
A gate of the third transistor receives the control signal;
A drain of the fourth transistor is connected to a source of the third transistor;
A gate of the fourth transistor is connected to an output terminal of the differential amplifier;
A source of the fourth transistor is connected to a second power line;
The voltage generation according to claim 3, wherein the acceleration unit increases a resistance value between a drain and a source of the fourth transistor in accordance with a decrease in an output voltage of an output terminal of the differential amplifier. circuit.
(Appendix 5)
The resistance element has a drain connected to a drain of the second transistor, a source connected to a drain of the third transistor, and a gate connected to a voltage line having a predetermined voltage. The voltage generation circuit according to appendix 4, wherein the voltage generation circuit is a transistor.
(Appendix 6)
A third voltage generator for outputting a third voltage having a second value higher than the first voltage;
A fourth voltage generator that outputs a fourth voltage that is lower than the first voltage by a third value;
The first switch is disposed between an output terminal of the second voltage generating unit and a second input terminal of the differential amplifier, and the third voltage is input to a gate, A transistor having a threshold value and having a second polarity;
The second switch is disposed between an output terminal of the differential amplifier and the output voltage terminal, and the fourth voltage is input to a gate and has a threshold value of the third value. 4. The voltage generation circuit according to appendix 3, wherein the voltage generation circuit includes a transistor having polarity.
(Appendix 7)
The transistor having the first polarity is a pMOS transistor;
The voltage generation circuit according to appendix 6, wherein the transistor having the second polarity is an nMOS transistor.
(Appendix 8)
The second voltage generator includes a first transistor and a second transistor having the first polarity, a resistance element, and a third transistor and a fourth transistor having the second polarity. ,
A source of the first transistor is connected to a first power line;
The gate of the first transistor, the drain of the second transistor, and one end of the resistance element are connected to the output terminal of the second voltage generator,
A gate of the second transistor is connected to an output terminal of the first voltage generator;
A drain of the third transistor is connected to the other end of the resistance element;
A gate of the third transistor receives the third voltage;
A drain of the fourth transistor is connected to a source of the third transistor;
A gate of the fourth transistor is connected to an output terminal of the differential amplifier;
The voltage generation circuit according to appendix 6 or appendix 7, wherein a source of the fourth transistor is connected to a second power supply line.
(Appendix 9)
The third voltage generator is
9. The voltage generation circuit according to claim 6, further comprising: a first suppression circuit that reduces the third voltage in response to a decrease in the output voltage from the differential amplifier.
(Appendix 10)
The third voltage generator is
The voltage generation circuit according to any one of appendix 6 to appendix 9, further comprising a second suppression circuit that lowers the third voltage in response to a decrease in the third voltage.
(Appendix 11)
The third voltage generator is
A fifth transistor having the first polarity, a sixth transistor having the second polarity, and a third switch connected in series between the first power supply line and the second power supply line; And a seventh transistor and an eighth transistor having the second polarity;
A ninth transistor having the first polarity connected in series between the first power line and the second power line; a fourth switch; and a tenth transistor having a second polarity. A transistor, an eleventh transistor and a twelfth transistor;
The fifth transistor has a source connected to the first power supply line, a drain connected to the output terminal of the third voltage generator and the drain of the sixth transistor, and a gate connected to the ninth transistor. Connected to the gate of
The sixth transistor has a gate and a drain connected to the output terminal of the third voltage generator, a source connected to one end of the third switch and the gate of the eighth transistor,
The seventh transistor has a drain connected to the other end of the third switch, a source connected to the drain of the eighth transistor, a gate connected to the output terminal of the first voltage generator,
The eighth transistor has a source connected to the second power supply line,
The third switch connects a source of the sixth transistor and a drain of the seventh transistor in response to the activation signal;
The ninth transistor has a source connected to the first power line, a drain connected to one end of the fourth switch, a gate connected to the other end of the fourth switch,
The tenth transistor has a drain connected to the gate of the ninth transistor, a source connected to the drain of the eleventh transistor, and a gate connected to the output terminal of the first voltage generator,
The eleventh transistor has a source connected to the drain of the twelfth transistor, a gate connected to the output terminal of the third voltage generator,
The twelfth transistor has a source connected to the second power supply line, a gate connected to an output terminal of the differential amplifier,
The appendix 6 to appendix 9, wherein the fourth switch connects the drain of the ninth transistor and the drain of the tenth transistor in response to the activation signal. Voltage generation circuit.
(Appendix 12)
The fourth voltage generator is
The voltage generation circuit according to any one of appendix 6 to appendix 11, further comprising a third suppression circuit that lowers the fourth voltage in response to a decrease in the third voltage.
(Appendix 13)
The fourth voltage generator is
A thirteenth transistor, a fourteenth transistor and a fifteenth transistor having the first polarity connected in series between the first power supply line and the second power supply line, a fifth switch, and the first switch A sixteenth transistor having a polarity of two;
A seventeenth transistor having the first polarity connected in series between the first power supply line and the second power supply line, a sixth switch, and an eighteenth switch having a second polarity. A transistor and a nineteenth transistor,
The thirteenth transistor has a source connected to the first power supply line, a drain connected to the source of the fourteenth transistor, a gate connected to the source of the fifteenth transistor,
The fourteenth transistor has a source connected to the drain of the thirteenth transistor, a drain connected to the gate of the thirteenth transistor, a gate connected to the gate of the seventeenth transistor,
The fifteenth transistor has a gate and a drain connected to the output terminal of the fourth voltage generator and one end of the fifth switch,
The sixteenth transistor has a drain connected to the other end of the fifth switch, a source connected to the second power supply line, a gate connected to a voltage generation node of the second voltage generation unit,
The fifth switch connects the drain of the fifteenth transistor and the drain of the sixteenth transistor in response to the activation signal,
The seventeenth transistor has a source connected to the first power supply line, a drain connected to one end of the sixth switch, a gate connected to the other end of the sixth switch,
The eighteenth transistor has a drain connected to the other end of the sixth switch, a source connected to the drain of the nineteenth transistor, and a gate connected to a voltage generation node of the second voltage generator. ,
The nineteenth transistor has a source connected to the second power supply line, a gate connected to the output terminal of the third voltage generator,
The appendix 6 to appendix 12, wherein the sixth switch connects a drain of the seventeenth transistor and a drain of the eighteenth transistor in response to the activation signal. Voltage generation circuit.
(Appendix 14)
A buffer circuit for outputting a detection signal when the second voltage rises to a third voltage higher than the first voltage;
The buffer unit includes a differential amplifier having a first input terminal connected to the output terminal of the first voltage generation unit and a second input terminal connected to the output voltage terminal;
The switch part is
The second voltage generator is disposed between the output terminal of the second voltage generator and the second input terminal of the differential amplifier, and the difference between the first voltage and the second voltage is less than or equal to the first value. A first switch that is set from an on state to an off state when the output signal output from the differential amplifier indicates that
Between the output terminal of the second voltage generator and the second input terminal of the differential amplifier, it is arranged in series with the first switch, and is set to an on state before the detection signal is output. A second switch that is set to an off state in response to the output of the detection signal;
The differential amplifier is disposed between the output terminal and the output voltage terminal, and is set to an off state before the detection signal is output, and is set to an on state in response to the output of the detection signal. 3. The voltage generation circuit according to appendix 1 or appendix 2, characterized by comprising:
(Appendix 15)
The second voltage generator includes a first transistor and a second transistor having a first polarity, a resistance element, and a third transistor and a fourth transistor having a second polarity,
A source of the first transistor is connected to the first power line;
The gate of the first transistor, the drain of the second transistor, and one end of the resistance element are connected to the output terminal of the second voltage generator,
A source of the second transistor is connected to a drain of the first transistor;
A gate of the second transistor is connected to an output terminal of the first voltage generator;
A drain of the third transistor is connected to the other end of the resistance element;
A gate of the third transistor receives the detection signal;
A drain of the fourth transistor is connected to a source of the third transistor;
A gate of the fourth transistor is connected to an output terminal of the differential amplifier;
15. The voltage generation circuit according to appendix 14, wherein a source of the fourth transistor is connected to the second power supply line.
(Appendix 16)
The first voltage generator includes a first resistance element, a second resistance element, and a switch,
The first resistance element is connected to a third power supply line and one end of the second resistance element,
The second resistance element is connected to one end of the first resistance element and one end of the switch,
The switch is connected to the other end of the second resistance element and a fourth power supply line,
The switch is set from an off state to an on state in response to the activation signal,
16. The supplementary note 1 to supplementary note 15, wherein the first voltage generator outputs the first voltage from a connection node of the first resistive element and the second resistive element. Voltage generator circuit.
(Appendix 17)
Outputting a first voltage to the first signal line in response to the activation signal;
Based on the first voltage, the second voltage generator outputs the second voltage to the second signal line,
In the second period in which the difference between the second voltage and the first voltage is less than or equal to the first value in the first period in which the second voltage is smaller than the first voltage, the second voltage The second voltage generator has a higher generation capability of the second voltage than a period in which the difference between the first voltage and the first voltage is greater than the first value,
Receiving the first voltage at the buffer unit and outputting an output voltage;
The output terminal of the second voltage generation unit is connected to the output voltage terminal during the first period, and the output terminal of the buffer unit is connected to the output voltage terminal when the second voltage is equal to or higher than the first voltage. And a voltage generating circuit control method.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  ACC: Acceleration unit; AMP: Differential amplifier; B1, B2, B2a, B2b, B3, B4 ... Bias circuit; BUF ... Buffer unit; CAP ... Capacitor; CMP ... Comparator; CO1 ... Signal line; EN ... enable signal; IV ... inverter; OUT ... output terminal; REF1, REF2, REF3, REF4 ... signal line; SW ... switch part; SW1, SW2, SW3, SW4 ... switch; VGEN1, VGEN2, VGEN3, VGEN4 ... voltage generation Circuit; VO ... Output voltage

Claims (9)

A first voltage generator that outputs a first voltage to the first signal line in response to the activation signal;
A second voltage generator for outputting a second voltage to a second signal line based on the first voltage;
A buffer unit that receives the first voltage and outputs an output voltage;
An output terminal of the second voltage generator is connected to an output voltage terminal in a first period in which the second voltage is smaller than the first voltage, and the second voltage is equal to or higher than the first voltage. And a switch unit for connecting the output terminal of the buffer unit to the output voltage terminal.
The second voltage generation unit includes the second voltage and the second voltage in the second period in which a difference between the second voltage and the first voltage is equal to or less than a first value in the first period. A voltage generation circuit comprising: an accelerating unit that increases a generation capability of the second voltage compared to a period in which a difference from the first voltage is greater than the first value. The first voltage generator outputs a voltage higher than the first voltage to the first signal line before receiving the activation signal,
2. The voltage generator according to claim 1, wherein the second voltage generator outputs a voltage lower than the first voltage when the first voltage is not output to the first signal line. 3. circuit. The buffer unit includes a differential amplifier having a first input terminal connected to the output terminal of the first voltage generation unit and a second input terminal connected to the output voltage terminal;
The switch part is
When the second voltage is smaller than the first voltage, the output terminal of the second voltage generator is connected to the second input terminal of the differential amplifier, and the second voltage is the first voltage. A first switch that cuts off the connection between the output terminal of the second voltage generator and the second input terminal of the differential amplifier when the voltage is equal to or higher than
When the second voltage is smaller than the first voltage, the connection between the output terminal of the differential amplifier and the output voltage terminal is cut off, and when the second voltage is equal to or higher than the first voltage. The voltage generation circuit according to claim 1, further comprising: a second switch that connects an output terminal of the differential amplifier to the output voltage terminal. A comparator that compares the first voltage with the second voltage and generates a control signal for controlling the operation of the first switch and the second switch according to the comparison result;
The second voltage generator includes a first transistor and a second transistor having a first polarity, a resistance element, and a third transistor and a fourth transistor having a second polarity,
A source of the first transistor is connected to a first power line;
The gate of the first transistor, the drain of the second transistor, and one end of the resistance element are connected to the output terminal of the second voltage generator,
A source of the second transistor is connected to a drain of the first transistor;
A gate of the second transistor is connected to an output terminal of the first voltage generator;
A drain of the third transistor is connected to the other end of the resistance element;
A gate of the third transistor receives the control signal;
A drain of the fourth transistor is connected to a source of the third transistor;
A gate of the fourth transistor is connected to an output terminal of the differential amplifier;
A source of the fourth transistor is connected to a second power line;
4. The voltage according to claim 3, wherein the acceleration unit increases a resistance value between a drain and a source of the fourth transistor according to a decrease in an output voltage of an output terminal of the differential amplifier. Generation circuit. A third voltage generator for outputting a third voltage having a second value higher than the first voltage;
A fourth voltage generator that outputs a fourth voltage that is lower than the first voltage by a third value;
The first switch is disposed between an output terminal of the second voltage generating unit and a second input terminal of the differential amplifier, and the third voltage is input to a gate, A transistor having a threshold value and having a second polarity;
The second switch is disposed between an output terminal of the differential amplifier and the output voltage terminal, and the fourth voltage is input to a gate and has a threshold value of the third value. The voltage generation circuit according to claim 3, comprising a transistor having polarity. The second voltage generator includes a first transistor and a second transistor having the first polarity, a resistance element, and a third transistor and a fourth transistor having the second polarity. ,
A source of the first transistor is connected to a first power line;
The gate of the first transistor, the drain of the second transistor, and one end of the resistance element are connected to the output terminal of the second voltage generator,
A gate of the second transistor is connected to an output terminal of the first voltage generator;
A drain of the third transistor is connected to the other end of the resistance element;
A gate of the third transistor receives the third voltage;
A drain of the fourth transistor is connected to a source of the third transistor;
A gate of the fourth transistor is connected to an output terminal of the differential amplifier;
The voltage generation circuit according to claim 5, wherein a source of the fourth transistor is connected to a second power supply line. A buffer circuit for outputting a detection signal when the second voltage rises to a third voltage higher than the first voltage;
The buffer unit includes a differential amplifier having a first input terminal connected to the output terminal of the first voltage generation unit and a second input terminal connected to the output voltage terminal;
The switch part is
The second voltage generator is disposed between the output terminal of the second voltage generator and the second input terminal of the differential amplifier, and the difference between the first voltage and the second voltage is less than or equal to the first value. A first switch that is set from an on state to an off state when the output signal output from the differential amplifier indicates that
Between the output terminal of the second voltage generator and the second input terminal of the differential amplifier, it is arranged in series with the first switch, and is set to an on state before the detection signal is output. A second switch that is set to an off state in response to the output of the detection signal;
The differential amplifier is disposed between the output terminal and the output voltage terminal, and is set to an off state before the detection signal is output, and is set to an on state in response to the output of the detection signal. 3. The voltage generation circuit according to claim 1, further comprising: 3 switches. The second voltage generator includes a first transistor and a second transistor having a first polarity, a resistance element, and a third transistor and a fourth transistor having a second polarity,
A source of the first transistor is connected to the first power line;
The gate of the first transistor, the drain of the second transistor, and one end of the resistance element are connected to the output terminal of the second voltage generator,
A source of the second transistor is connected to a drain of the first transistor;
A gate of the second transistor is connected to an output terminal of the first voltage generator;
A drain of the third transistor is connected to the other end of the resistance element;
A gate of the third transistor receives the detection signal;
A drain of the fourth transistor is connected to a source of the third transistor;
A gate of the fourth transistor is connected to an output terminal of the differential amplifier;
The voltage generation circuit according to claim 7, wherein a source of the fourth transistor is connected to the second power supply line. Outputting a first voltage to the first signal line in response to the activation signal;
Based on the first voltage, the second voltage generator outputs the second voltage to the second signal line,
In the second period in which the difference between the second voltage and the first voltage is less than or equal to the first value in the first period in which the second voltage is smaller than the first voltage, the second voltage The second voltage generator has a higher generation capability of the second voltage than a period in which the difference between the first voltage and the first voltage is greater than the first value,
Receiving the first voltage at the buffer unit and outputting an output voltage;
The output terminal of the second voltage generation unit is connected to the output voltage terminal during the first period, and the output terminal of the buffer unit is connected to the output voltage terminal when the second voltage is equal to or higher than the first voltage. And a voltage generating circuit control method.

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