JP2015037277A - Address generation circuit and address generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of an interleaving circuit and a de-interleaving circuit by reducing comparison/subtraction elements and thus dispensing with a large scale modulo operation circuit and also by reducing a ROM size to be stored.SOLUTION: An address generation device for dividing, by a predetermined divisor, the sum of a first result of multiplication of an ordinal number by a first constant and a result of multiplication of the square of the ordinal number by a second constant to generate a remainder as an address includes: first arithmetic means for dividing the first result by the divisor to produce a first intermediate remainder; second arithmetic means for dividing a predetermined function of the ordinal number by the divisor to produce a second intermediate remainder; and third arithmetic means for dividing the sum of the first intermediate remainder and the second intermediate remainder by the divisor to produce a final remainder. The final remainder is the address.

Description

  The present invention relates to an address generation circuit and an address generation method for generating an address.

  When wireless communication is performed using a mobile phone or the like, turbo codes are widely used for transmitting and receiving signals. For example, a turbo code is used at the time of communication by LTE (Long Term Evolution) which is a standard standardized by a standardization organization participating in a 3GPP (Third Generation Partnership Project) project (see Non-Patent Document 1).

  In the encoding and decoding by the turbo code, an interleaving process by an interleave circuit (sometimes referred to as “interleaver”) and a deinterleave process by a deinterleave circuit (sometimes called “deinterleaver”) are performed. These processes will be described with reference to the drawings.

  First, FIG. 1 shows a basic configuration of a turbo encoder. Referring to FIG. 1, the turbo encoder 101 includes a first encoding circuit 102, a second encoding circuit 103, and an interleave circuit 104.

  The turbo encoder 101 is connected to the transmitter 105. The signal input to the turbo encoder 101 is output to the transmitter 105 through three routes.

  Specifically, a route for outputting the input signal as it is to the transmitter 105 (output corresponds to S1 in the figure), and a route for outputting the input signal to the transmitter 105 via the first encoding circuit 102. (The output corresponds to S2 in the figure), and a route (output is output to the transmitter 105 via the second encoding circuit 103 after the input data is rearranged by the interleave circuit 104 for the input signal. Corresponding to S3 ′ in the figure, in the figure and in the following description, the signal after the interleaving process is denoted by “′” to indicate that the signal is the signal after the interleaving process. 3). The transmitter 105 multiplexes these three route signals. Specifically, the signal S1 is multiplexed as payload, and the signal S2 and the signal S3 'are multiplexed as parity bits. Then, the transmitter 105 performs communication by sending the multiplexed data to the communication destination device.

  Next, a turbo decoder and a receiver included in a communication destination apparatus to which the transmitter 105 has transmitted a signal (corresponding to S1 to S3 'in the figure) will be described with reference to FIG. Referring to FIG. 2, the turbo decoder 202 includes a deinterleave circuit 203, a first decode circuit 204, an interleave circuit 205, a second decode circuit 206, and a demultiplexer 207. The turbo decoder 202 is connected to the receiver 201.

  The receiver 201 receives a signal (corresponding to S1 to S3 'in the drawing) sent from the transmitter 105. Then, the receiver 201 inputs the signal S <b> 1 that is a payload among the received signals to the first decoding circuit 204. In addition, the receiver 201 inputs signals S 2 and S 3 ′ that are parity bits among the received signals to the demultiplexer 207.

  The deinterleaving circuit 203 executes deinterleaving, which is a process for returning the arrangement order of the first likelihood information signals (corresponding to S11 in the figure) obtained by the previous iterative decoding process.

  Next, the first decoding circuit 204 performs decoding using the signal S1, the signal S2, and the first likelihood information signal after deinterleaving output from the deinterleaving circuit 203 (corresponding to S11 in the figure). To do.

  Then, the first decoding circuit 204 outputs the decoding result to the interleaving circuit 205 as a second likelihood information signal (corresponding to S12 in the figure). In addition, the first decoding circuit 204 outputs the signal S1 to the interleave circuit 205.

  Next, the interleaving circuit 205 performs interleaving, which is a rearrangement process, on the second likelihood information signal (corresponding to S12 in the figure) output from the first decoding circuit 204 and the signal S1.

  Second decoding circuit 206 performs decoding using interleaved signal S1 ′ output from interleaving circuit 205, second likelihood information signal after interleaving (corresponding to S12 ′ in the figure), and signal S3 ′. To do. Then, the second decoding circuit 206 outputs the decoding result as a first likelihood information signal. The output signal is output to the outside as a decoding result after being deinterleaved by the deinterleave circuit 203.

  Here, the interleaving process and the deinterleaving process are processes for rearranging data. Specifically, the data rearranged by the interleaving process is restored to the original order by the deinterleaving process and becomes the data array before the interleaving process is performed.

  The reason for performing these processes is to improve the error correction capability by turbo decoding by changing the burst error, which is an event in which errors in the transmission path are concentrated at a certain point of time, into a random error.

  On the transmitting side, the interleaving circuit performs data interleaving processing on data of a block size K in which a predetermined number of bits of data are grouped.

The rearrangement is performed by setting the output bit order to the bit order corresponding to “(f1 × i + f2 × i ² ) mod K” with respect to the bit order input to the interleave circuit.

  Here, f1 and f2 are arbitrary values defined according to the block size K, respectively. I is an index of information bits. Possible values of i are i = 0, 1, 2,... K−1.

  Here, for example, in the LTE standard, the range that the data block K can take is K = 40 to 6144. There are 188 possible values for the data block K. That is, in the LTE standard, 188 interleave patterns are defined.

  As a specific example, if the block size K = 40 is taken as an example, it is defined that f1 = 3 and f2 = 10. The information bits input to the interleave circuit in the data order of i = 0, 1, 2,... K−1 are rearranged in the data order of i = 0, 13, 6, 19.

  On the other hand, the deinterleave circuit provided on the receiving side uses the data order i = 0, 13, 6, 19... 7 rearranged by this interleaving process as the original data order, i = 0, 1, 2. ... Deinterleaving is performed to return to K-1.

  An example of a communication device that performs such interleaving and deinterleaving is described in, for example, Patent Document 1 and Patent Document 2.

Special table 2013-509824 gazette Special table 2012-503248 gazette

“TS 36.212 Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding”, [online], 3GPP, [searched on July 9, 2013], Internet <URL: http://www.3gpp.org /ftp/Specs/archive/36_series/36.212/>

Next, an example of an interleave circuit will be described with reference to FIG. Interleaving circuit 300 represented in Figure 3, write counter 301, a read counter 302, f1 multiplier 303, ^{i 2} multiplier 304, f2 multiplier 305, adder 306, a modulo operation circuit (in the figure as "MODULO" 307) and Dual Port RAM 308.

  The write counter 301 sets the head of a block of block size K to “0” and increments the value every time an information bit is input to generate a write address of the dual port RAM 308.

  On the other hand, the read counter 302 increments the counter every time information bits are read and generates i as an information bit index.

  The f1 multiplier 303 is a multiplier that multiplies i generated by the read counter 302 by f1 that is a value set according to the value of K, and calculates f1 × i.

The i ² multiplier 304 generates i ² from i generated by the read counter 302.

Thereafter, the set is a value multiplying the f2 and i ² in accordance with the value of K by f2 multiplier 305.

Further, the adder 306 performs addition to generate a value of (f1 × i + f2 × i ² ). Finally, the modulo arithmetic circuit 307 generates a read address of the Dual Port RAM 308 corresponding to (f1 × i + f2 × i ² ) mod K. Then, the written information bits are read according to the read address, thereby performing interleave processing on the block data.

Next, an example of a deinterleave circuit will be described with reference to FIG. Deinterleaving circuit 400 represented in Figure 4, write counter 401, a read counter 402, f1 multiplier 403, ^{i 2} multiplier 404, f2 multiplier 405, an adder 406, a modulo operation circuit (in the figure "MODULO" 407 and Dual Port RAM 408.

  The write counter 401 increments the counter every time an information bit is read, and generates i as an information bit index.

  The f1 multiplier 403 is a multiplier that multiplies i generated by the write counter 401 and f1 that is a value set according to the value of K, and calculates f1 × i.

The i ² multiplier 404 generates i ² from i generated by the write counter 401.

Thereafter, the set is a value multiplying the f2 and i ² in accordance with the value of K by f2 multiplier 405.

Further, the adder 406 performs addition to generate a value of (f1 × i + f2 × i ² ). Finally, the modulo arithmetic circuit 407 generates a write address of the Dual Port RAM 408 corresponding to (f1 × i + f2 × i ² ) mod K. Then, data for the block size is written according to this write address.

  The read counter 402 performs the process while incrementing the value for each read data. Thereby, the deinterleaving process is realized.

  As described above, the interleaving process and the deinterleaving process are common in that an address for rearranging data is generated, but is different in that the generated address is used as a read address or a write address.

  In both the interleaving process and the deinterleaving process, a modulo arithmetic circuit 307 is required to realize the mod K calculation process. The modulo arithmetic circuit 307 is realized by a circuit combining a comparison circuit and a subtraction circuit (hereinafter referred to as “comparison subtraction element” as appropriate).

The scale of this modulo arithmetic circuit will be specifically examined by taking LTE as an example. If the maximum value of (f1 × i + f2 × i ² ) defined by LTE is represented by a binary number, 28 bits are required. If 6144, which is the maximum value that K can take, is expressed in binary, 13 bits are required. For this reason, normally, a modulo arithmetic circuit requires a large number of comparison and subtraction elements, resulting in a large circuit scale.

A typical circuit configuration example in the case of providing a modulo arithmetic circuit is shown in FIG. The first-stage comparison / subtraction element 501-1 compares the block size K represented by 13 bits with the higher 13 bits of 28 bits representing (f1 × i + f2 × i ² ). The comparison subtraction element 501 of the first stage is indicated by the upper 13 bits of it towards the value indicated by the upper 13 bits of ^{(f1 × i + f2 × i} 2) is greater than the block size K, (f1 × i + f2 × i 2) The value obtained by subtracting the block size K from the value to be subtracted is output. Otherwise, the upper 13 bits of (f1 × i + f2 × i ² ) are output as they are to the next comparison subtraction element 501-2. To do. The output of the first stage comparison / subtraction element 501-1 is represented by 12 bits. Next, the comparison / subtraction element 501-2 of the next stage uses (f1 × i + f2 × i ² ) as a bit lower than the 12-bit LSB (least significant bit) input from the comparison / subtraction element 501-1 of the first stage. By adding the 14th bit from the higher order, 13 bits are obtained, and the same arithmetic processing as that of the first stage comparison / subtraction element 501-1 is performed. This operation is repeated until the least significant bit of (f1 × i + f2 × i ² ). Therefore, the necessary number of the comparison subtraction elements 501 is the number obtained by adding 1 to the difference between the number of bits necessary to represent (f1 × i + f2 × i ² ) and the number of bits necessary to represent the block size K. (In this example, 28−13 + 1 = 16), and it is necessary to configure a number of comparison subtraction elements. Further, if the comparison subtraction element is configured by software, it is necessary to repeat the comparison subtraction operation by this number.

  Thus, when a modulo arithmetic circuit is realized by a large number of comparison and subtraction elements, the circuit scale becomes large. Thus, as a method for reducing the circuit scale by eliminating the need for such a large number of comparison and subtraction elements, all interleave patterns of all block sizes are stored in advance in a ROM (Read Only Memory) or the like. There is a way. However, if this method is used, it is necessary to own a large number of block sizes and data for each information index, and a large-scale ROM is required.

  Specifically, this ROM size is the ROM capacity having a value obtained by multiplying the value 355248 obtained by adding all the block sizes K and the bit width 13 bits necessary to represent the maximum value 6144 of K. That is, 355248 × 13 bits = 4618224 bits are required. Therefore, it becomes necessary to prepare a ROM having a large storage capacity of 4618224 bits or more.

  Therefore, the present invention eliminates the need for a large-scale modulo arithmetic circuit by reducing the comparison and subtraction elements, and also reduces the circuit size in the interleave circuit and the deinterleave circuit by reducing the ROM size to be stored. An object is to provide an address generation circuit, an address generation method, and an address generation program.

  According to the first aspect of the present invention, a sum of a first result obtained by multiplying an ordinal by a first constant and a result obtained by multiplying the square of the ordinal by a second constant is a predetermined divisor. An address generation device for generating a remainder obtained by dividing as an address, the first calculation means for obtaining a first intermediate remainder by dividing the first result by the divisor, and a predetermined function of the ordinal number Second computing means for obtaining a second intermediate remainder by dividing by the divisor, third computing means for obtaining a final remainder by dividing the sum of the first intermediate remainder and the second intermediate remainder by the divisor, And an address generating device characterized in that the final remainder is the address.

  According to the second aspect of the present invention, a sum of a first result obtained by multiplying an ordinal by a first constant and a result obtained by multiplying the square of the ordinal by a second constant is a predetermined divisor. An address generation method of generating a remainder obtained by dividing as an address, wherein a first calculation step of obtaining a first intermediate remainder by dividing the first result by the divisor, and a predetermined function of the ordinal number, A second operation step of obtaining a second intermediate residue by dividing by the divisor, and a third operation step of obtaining a final residue by dividing the sum of the first intermediate residue and the second intermediate residue by the divisor, The address generation method is characterized in that the final remainder is the address.

  According to the present invention, the circuit scale in the interleave circuit and the deinterleave circuit is reduced by eliminating the comparative subtraction element, thereby eliminating the need for a large-scale modulo arithmetic circuit and reducing the ROM size to be stored. It becomes possible.

It is a block diagram showing the specific example of a structure of the turbo encoder in a general technique. It is a block diagram showing the specific example of a structure of the turbo decoder in a general technique. It is a block diagram showing the specific example of a structure of the interleave circuit in a general technique. It is a block diagram showing the specific example of a structure of the deinterleaving circuit in a general technique. It is a block diagram showing the specific example of the modulo arithmetic circuit in a general technique. It is a block diagram showing the interleave circuit which is one of the fundamental structures of embodiment of this invention. It is a table | surface (1/6) showing about the data series circulated by the period of K / GCD. It is a table | surface (2/6) showing about the data series circulated by the period of K / GCD. It is a table | surface (3/6) showing about the data series circulated by the period of K / GCD. It is a table | surface (4/6) showing about the data series circulated by the period of K / GCD. It is a table | surface (5/6) showing about the data series circulated by the period of K / GCD. It is a table | surface (6/6) showing about the data series circulated by the period of K / GCD. It is a table | surface (1/6) showing the value which totaled the value of the value of f1, the value of f2, the value of GCD, the value of K / GCD, and all the block sizes of K / GCD for every block size K. It is a table | surface (2/6) showing the value which totaled the value of the value of f1, the value of f2, the value of GCD, the value of K / GCD, and all the block sizes of K / GCD for every block size K. It is a table | surface (3/6) showing the value which totaled the value of the value of f1, the value of f2, the value of GCD, the value of K / GCD, and all the block sizes of K / GCD for every block size K. It is a table | surface (4/6) showing the value which totaled the value of the value of f1, the value of f2, the value of GCD, the value of K / GCD, and all the block sizes of K / GCD for every block size K. It is a table | surface (5/6) showing the value which totaled the value of the value of f1, the value of f2, the value of GCD, the value of K / GCD, and all the block sizes of K / GCD for every block size K. It is a table | surface (6/6) showing the value which totaled the value of the value of f1, the value of f2, the value of GCD, the value of K / GCD, and all the block sizes of K / GCD for every block size K. It is an image figure showing an example of the data structure of ROM in embodiment of this invention. It is a block diagram showing the deinterleave circuit which is one of the fundamental structures of embodiment of this invention.

  First, an outline of an embodiment of the present invention will be described. Embodiments of the present invention relate to address generation for performing rearrangement processing. As a specific example, the present invention can be applied to an interleave circuit and a deinterleave circuit for turbo encoding and decoding used in LTE.

In this embodiment, by using the greatest common divisor (GCD) of f2 and K, the calculation circuit scale of (f1 × i + f2 × i ² ) mod K by interleaving and deinterleaving is reduced, and the problem to be solved To solve.

  More specifically, a periodic pattern, which is a data pattern that is periodically repeated (cyclically cycled), is obtained by using the value calculated by GCD and K of f2 and K described above. By using the pattern, it is possible to perform address control for interleaving with a simple calculation circuit without performing modulo arithmetic. The above is the outline of the embodiment of the present invention.

  Next, the interleave circuit 600 according to the present embodiment will be described with reference to FIG. Here, the interleave circuit 600 can be used as the interleave circuit 104 shown in FIG. 1, for example.

  Referring to FIG. 6, the interleave circuit 600 includes an f1 adder 601, an f1 comparison subtractor 602, a comparator 603, an f2 calculation counter 604, an offset adder 605, a ROM 606, an f1, f2 adder 607, and an f1, f2 comparison subtractor. 608, a write counter 609 and a dual port ROM 610.

Here, in the present embodiment, when calculating (f1 × i + f2 × i ² ) mod K, the calculation unit of f1 × i and the calculation unit of f2 × i ² are separately calculated. If this way of separating includes a calculation of the first f1 × calculation of i is performed (f1 × i) mod K, separated in the calculation of the f2 × calculation of ^{i 2} is performed (f2 × ⁱ 2) mod K . Then, both calculation results are added together, and mod K is calculated for the sum obtained as a result.

Specifically, the calculation unit of f1 × i includes an f1 adder 601 and an f1 comparison subtracter 602. The calculation of the f2 × ^{i 2} includes a comparator 603, f2 calculation counter 604, the offset adder 605 and ROM 606. Furthermore, performs addition of f1 × i calculator and f2 × ^{i 2} calculator respective calculation results f1, f2 adder 607, f1 with respect to the sum obtained by adding, f2 comparator subtractor 608 mod Calculate K and obtain the remainder. The numerical value of the remainder generated in this way is used as a read address of the Dual Port ROM 610.

  In this case, on the calculation side of f1 × i, it is only necessary to add f1 for each read information bit. If the value after the addition is equal to or greater than the value of K, the value of K is calculated from the value after the addition. Subtract. Therefore, (f1 × i) mod K can be calculated by the adder circuit 601 and the f1 comparison / subtraction circuit 602.

On the other hand, the scale of the modulo arithmetic circuit can be reduced on the calculation side of f2 × i ² as described below.

Using the GCD values of f2 and K, the same result can be obtained even if the calculated part of (f2 × i ² ) mod K is [f2 × {i ² mod (K / GCD)}] mod K Can do. Then, by {i ² mod (K / GCD)}, i ² changes to a data sequence that circulates in a cycle of K / GCD.

Thus, one by one (f2 × ⁱ 2) instead of one by one calculates the value of mod K, stores the value of the previously calculated (f2 × ⁱ 2) mod K as data in ROM. Then, by referring to the value of (f2 × i ² ) mod K corresponding to the block size K of the data to be processed this time, a simple configuration can be achieved without using a large-scale modulo calculation. . In this respect, the smaller the value of K / GCD, the smaller the capacity of data to be stored in the ROM.

Next, i ² has changed to a data sequence that circulates in a cycle of K / GCD, and the value of (f2 × i ² ) mod K is also a data sequence that circulates in a cycle of K / GCD. Description will be made with reference to specific examples of Table 1 described in 7-1 to FIGS.

  Table 1 shows a sequence of each cyclic data when the block size K = 6144, f1 = 263, and f2 = 480. In this case, GCD (greatest common divisor) of f2 and K = 96. Therefore, K / GCD = 64.

  The first column in Table 1 represents the value of i that is an index of information bits.

  Further, the second column in Table 1 shows the calculation result by the normal means by (f1 × i + f2 × i ^ 2) mod K.

  On the other hand, the calculation result of (f1 × i) mod K dividedly calculated according to this embodiment is shown in the third column of Table 1. Also, i ^ 2 mod (K / GCD) is shown in the fourth column in Table 1. Further, (f2 × i ^ 2) mod (K / GCD) is shown in the fifth column in Table 1. Further, the calculation result of f1 × i in the third column in Table 1 and (f2 × i ^ 2) mod (K / GCD) in the fifth column in Table 1 are added, and mod K is further added to the addition value. The calculation result of the calculation is shown in the sixth column of Table 1.

  Although information bits i = 0 to 6143, i = 0 to 192 are described for the sake of omission. After i = 193, the same cycle is repeated.

  Referring to Table 1 below, for example, the value of i ^ 2 mod (K / GCD) in the fourth column of i = 0 to 63 and the value of (f2 × i ^ 2) mod (K / GCD) in the fifth column Is the same as the group of i ^ 2mod (K / GCD) values in the fourth column from i = 64 to 127 and the group of (f2 × i ^ 2) mod (K / GCD) values in the fifth column. (I.e., the value of i ^ 2 mod (K / GCD) in the fourth column and the value of (f2 * i ^ 2) mod (K / GCD) in the fifth column coincide with each other at positions 64 rows apart). Therefore, it can be seen that the periodic pattern is consistent with K / GCD = 64.

  Table 1 shows the values of the example of K = 6144, f1 = 263, f2 = 480, but the fourth column and the fifth column in the same pattern of K / GCD in the other block sizes as well. Is obtained.

  Next, the description will be continued with reference to Table 2 described in FIGS. The first column of Table 2 represents all possible values of the block size K when interleaving and deinterleaving in LTE. The second column represents the value of f1 corresponding to the block size K. Furthermore, the third column shows the value of f2 corresponding to the block size K. Furthermore, the GCD values of f2 and K are shown in the fourth column. Further, the fifth column represents the value of K / GCD. In addition, the bottom row represents a value obtained by summing up all the block sizes of K / GCD.

When the K / GCD for each interleave block size is examined, the minimum value is 2 and the maximum value is 112. Also, 3304 is obtained by adding K / GCD for each block size for all block sizes. Therefore, the number of bits required for all block sizes is 3304 × 13 bits = 42952 bits, and the configuration can be made if there is a ROM of about 43k. Such a ROM can store all (f2 × i ² ) mod K for all block sizes K.

  The 13-bit is the data width stored in the ROM address and corresponds to the bit width necessary to represent the maximum value 6144 of the block size K.

  That is, in this embodiment, the number of bits necessary for all block sizes is set to a maximum value 6144 of K with respect to the value 355248 obtained by adding all the block sizes K described in the column of the problem to be solved by the present invention. The 461822 bits, which is a value obtained by multiplying the bit width of 13 bits to be satisfied, is 42952 bits, and the storage capacity can be reduced to about 1/100.

  Next, the operation of each part of this embodiment will be described in detail with reference to FIG. 6 again.

  First, in this embodiment, before starting the operation for calculating the read address of the interleave circuit, information is set as follows according to an instruction from a control unit (not shown) such as a CPU.

  The write counter 609 generates the write address of the dual port ROM 610 by setting the head of the block to “0” and incrementing the value for each input data. Then, the dual port ROM 610 writes input data to the entry of the generated address until writing of data for the block size K is completed.

When the data writing for the block size K is completed, the read control is performed so that the read address is in the address order according to the generation formula (f1 × i + f2 × i ² ) mod K corresponding to the designated block size K. Thus, the interleaving process is performed. This calculation of the read address is a feature of this embodiment.

  Here, in the present embodiment, the calculation is performed as follows as means for calculating the interleave read address.

  First, the calculation of (f1 × i) is performed as the first calculation. The circuit that executes the first calculation includes an f1 adder 601 and an f1 comparison subtractor 602.

  First, the value of f1 is added in the f1 adder 601 for each information bit.

  Then, the f1 comparison subtracter 602 compares the value after the addition by the f1 adder 601 with the block size K. As a result of the comparison, if the value after addition by the f1 adder 601 is equal to or larger than the block size K, the f1 comparison subtracter 602 makes the value after addition by the f1 adder 601 less than the block size K value. In addition, a value obtained by subtracting the block size K from the value after the addition by the f1 adder 601 is output. On the other hand, if the value after the addition by the f1 adder 601 is less than the value of the block size K, the f1 comparison subtracter 602 outputs the value after the addition by the f1 adder 601 as it is.

  Thus, in this embodiment, subtraction is performed every time the integrated value exceeds the block size K in the first calculation stage. Therefore, it is possible to reduce the number of times the block size K is subtracted when the f1, f2 comparison subtractor 608 calculates mod K after adding the first calculation result and the second calculation result. That is, it is possible to reduce the number of comparison subtractors as a whole circuit.

  This point will be specifically described. First, the f1 comparison subtracter 602 included in the first calculation unit outputs a value obtained by subtracting the block size K every time the block size K is exceeded. For this reason, the output of the f1 adder 601 is less than the maximum value 6144 of the block size K, and is 6143 at the maximum. Therefore, the output of the f1 adder 601 does not exceed 13 bits necessary to represent the maximum value 6143 of the block size K. For example, taking the case of the block size K = 6144 described in Table 1 as an example, the maximum output of the ROM 606 is 6122 when i = 70.

On the other hand, the output of the ROM 606 is a value representing (f2 × i ² ) mod K, but since this value also includes the calculation of mod K, the value is smaller than the maximum value 6144 of the block size K. To 6143 at the maximum. Therefore, the output of the ROM 606 does not exceed 13 bits necessary to represent the maximum value 6143 of the block size K. For example, taking the case of block size K = 6144 described in Table 1 as an example, the maximum output of ROM 606 is 5856 when i = 5 or the like.

  Therefore, the value after addition in the f1, f2 comparison subtractor 608 is 122886 at the maximum because the value before the addition is 6143 + 6143 at the maximum. Further, the maximum value 122886 after the addition in the f1, f2 comparison subtractor 608 can be expressed by 14 bits.

  The necessary number of comparison subtraction elements required when the f1, f2 comparison subtractor 608 calculates mod K is calculated from the number of bits necessary to represent the value after addition in the f1, f2 comparison subtractor 608. Since this is a number obtained by adding 1 to the difference in the number of bits necessary to represent the block size K, 14-13 + 1 = 2.

  The necessary number of comparison subtraction elements of the f1 comparison subtracter 602 will also be described. In this regard, since the value output from the f1 comparison subtracter 602 is less than the block size K, it is 6143 at the maximum. The value of f1 is 477 at the maximum. Therefore, the output of the f1 adder 601 is 6143 + 477 = 6620 at the maximum and can be expressed in 13 bits.

  Then, the necessary number of comparison subtraction elements required when the f1 comparison subtractor 602 calculates mod K is obtained by calculating the block size K from the number of bits necessary to represent the value after addition in the f1 comparison subtractor 602. Since 13 is a number obtained by adding 1 to the difference in the number of bits necessary for the expression, 13−13 + 1 = 1.

  Thus, in this embodiment, it is sufficient that there are at most three comparison subtraction elements in the entire circuit. In this regard, in the example described in the column of the problem to be solved by the invention, the required number of comparison subtraction elements is 16, and thus the number of comparison subtraction elements required in this embodiment can be greatly reduced. .

Next, (f2 × i ² ) is calculated as the ^second calculation. Here, the circuit that executes the second calculation includes a comparator 603, an f2 calculation counter 604, an offset adder 605, and a ROM 606.

  The f2 calculation counter 604 increments the counter value for each information bit. The comparator 603 compares the counter value with the set K / GCD value for the corresponding block size K value.

  The comparator 603 resets the f2 calculation counter 604 if the counter value of the f2 calculation counter 604 is the same value as the set value K / GCD as a result of the comparison. On the other hand, if the counter value of the f2 calculation counter 604 is a value other than the set value K / GCD, the comparator 603 increments without resetting the f2 calculation counter 604. Since the comparator 603 operates in this way, the counter value of the f2 calculation counter 604 increases one by one, and when the counter value becomes the value of K / GCD, it is counted again from 0. It will change periodically.

  The offset adder 605 adds the offset value corresponding to the head address corresponding to the corresponding block size K in the ROM 606 to the counter value of the f2 calculation counter 604. For example, if data is stored in the ROM 606 according to Table 2, if the block size K is 40, the offset value is zero. The addition result of the offset adder 605 is input to the ROM 606 as an address. The ROM 606 outputs stored data corresponding to the input address.

  This point will be described with reference to FIG. FIG. 9 is an image diagram showing a data structure of data stored in the ROM 606.

The ROM 606 stores all (f2 × i ² ) mod K values for each of the values that the block size K can take. The possible values of K this time are K = 40, 48, 56. For example, when K = 40, K / GCD = 4. That is, when K = 40, four (f2 × i ² ) mod K values become one cycle, and (f2 × i ² ) mod K changes to a data series that circulates in this cycle. Similarly, when K = 48, K / GCD = 4.

  Here, for example, it is assumed that K = 48 this time and the counter value of the f2 calculation counter 604 is 2. In this case, the offset value is 4. With this offset value 4, an offset is made up to address 4, which is the head address of the address where data corresponding to K = 48 is stored.

The offset adder 605 adds the count value 2 to the offset value 4 and inputs the addition value 6 to the ROM 606 as an address. As a result, the ROM 606 outputs the third value of (f2 × i ² ) mod K stored at address 6 when K = 48, as stored data corresponding to the input address.

As described above, the counter value of the f2 calculation counter 604 periodically circulates in the range of 0 to 3 by repeating reset and increment. As a result, (f2 × ⁱ 2) in the case of ^{K = 48 (f2 × i 2} ) when the first value ~K = 48 of the mod K fourth value of mod K is cyclically outputted. This output value becomes the calculation result of the second calculation.

  Further, for example, it is assumed that K = 6144 and the counter value of the f2 calculation counter 604 is 63 as in the example of Table 1 described in FIGS. 7-1 to 7-6. In this case, the offset value is 3239. By this offset value 3239, an offset is made up to the address 3239 which is the head address of the address where the data corresponding to K = 6144 is stored.

The offset adder 605 adds the count value 63 to the offset value 3239 and inputs the added value 3303 as an address to the ROM 606. As a result, the ROM 606 outputs the 64th value of (f2 × i ² ) mod K when K = 6144 stored in the address 3303 as stored data corresponding to the input address.

  The values obtained by the first calculation and the second calculation are added by the f1, f2 adder 607, and the value after the addition is input to the f1, f2 comparison subtracter 608.

  Then, the f1 and f2 comparison subtractor 608 compares the value input from the f1 and f2 adder 607 with the block size K. As a result of comparison, the value input from the f1 and f2 adder 607 is the block. If the size is greater than or equal to the size K, a value obtained by subtracting the block size K from the value input from the f1, f2 adder 607 is output as a read address of the Dual Port ROM 610. On the other hand, if the value input from the f1, f2 adder 607 is less than the block size K value, the value input from the f1, f2 adder 607 is output as it is as the read address of the Dual Port ROM 610.

  As a result, a read address on the interleave side is generated, and the interleave operation is performed by reading the data stored in the corresponding address for the block size.

  Here, the above description is a case where the present embodiment is applied to an interleave circuit. However, this embodiment can also be applied to a deinterleave circuit used in a turbo decoder by generating a write address and a read address generation method with a configuration opposite to that of an interleave circuit.

  Thus, the case where this embodiment is applied to a deinterleave circuit will be described with reference to FIG. Here, this deinterleave circuit can be used as, for example, the interleave circuit 203 shown in FIG.

  Referring to FIG. 10, this interleave circuit includes an f1 adder 701, an f1 comparison subtractor 702, a comparator 703, an f2 calculation counter 704, an offset adder 705, a ROM 706, an f1, f2 adder 707, and an f1, f2 comparison subtractor. 708, a read counter 709, and a dual port RAM 710.

These f1 adder 701, f1 comparison subtractor 702, comparator 703, f2 calculation counter 704, offset adder 705, ROM 706, f1, f2 adder 707 and f1, f2 comparison subtractor 708 are the above-described f1 adder. 601, f1 comparison subtractor 602, comparator 603, f2 calculation counter 604, offset adder 605, ROM 606, f1, f2 adder 607 and f1, f2 comparison subtractor 608 are processed, and the designated block size An address according to the generation formula (f1 × i + f2 × i ² ) mod K corresponding to K is generated.

  Then, using the generated address as a write address, data writing for the block size is executed in the Dual Port RAM 710. Then, after the writing is completed, a read counter 709 that is an address counter that increments a value for each read data executes reading. This makes it possible to implement deinterleaving processing.

  The interleave circuit shown in FIG. 6 and the deinterleave circuit shown in FIG. 10 according to the present embodiment described above can reduce the amount of data stored in the ROM in advance, so that processing is performed with a ROM having a small storage capacity. It is possible to achieve the effect. Furthermore, the interleave circuit shown in FIG. 6 and the deinterleave circuit shown in FIG. 10 according to the present embodiment described above do not require a large-scale modulo arithmetic circuit, and the scale of the calculation circuit can be greatly reduced. It has the effect of becoming.

  The reason is that the value to be stored is reduced by using the periodicity of {f2 × i ^ 2mod (K / GCD)}, so that it is not necessary to store all the indexes i. It is. On the other hand, a value having no periodicity, f1 × i mod K, is calculated step by step. This is because the modular circuit becomes unnecessary by adding these.

  A part of each of the interleave circuit shown in FIG. 6 and the deinterleave circuit shown in FIG. 10 corresponds to the “address generation circuit” of the present invention.

  Moreover, although the above-described embodiment is a preferred embodiment of the present invention, the scope of the present invention is not limited only to the above-described embodiment, and various modifications are made without departing from the gist of the present invention. Implementation in the form is possible.

  For example, in the above description of the embodiment, the description has been made on the assumption that data having a pattern of all block sizes is written in the ROM. For this reason, in the above-described embodiment, as described with reference to FIG. 9, an operation of shifting to the head address of the data storage unit in the corresponding block size is performed by adding and adding an offset value. However, it is also conceivable to modify this as in the following first and second modifications.

First, as a first modification, the offset value and offset adder 605 may not be used. In this case, the value of (f2 × i ² ) mod K corresponding to the corresponding block size K is written in the ROM for only one cycle before the start of communication. That is, the value of (f2 × i ² ) mod K corresponding to the corresponding block size K is written for one cycle from the head address of the ROM. This eliminates the need to use the offset value and offset adder 605.

  Subsequently, as a second modified example, an operation in which the data is held only for the communication period by a flip-flop (FF) instead of the ROM, and selected according to the count value of the write counter 609 is the same treatment.

  In the above description, the interleaving process and the deinterleaving process in turbo encoding and turbo decoding compliant with the LTE standard have been described as examples. However, even standards other than LTE can be applied to standards other than LTE as long as they do not depart from the spirit of the present invention.

  Furthermore, the interleaving circuit and the deinterleaving circuit described above can be realized by hardware, software, or a combination thereof. In addition, the interleaving-related processing method performed by the above interleaving circuit and deinterleaving circuit can also be realized by hardware, software, or a combination thereof. Here, “realized by software” means realized by a computer reading and executing a program.

  The program may be stored using various types of non-transitory computer readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD- R, CD-R / W, and semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (random access memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A remainder obtained by dividing the sum of the first result obtained by multiplying the ordinal by the first constant and the result obtained by multiplying the square of the ordinal by the second constant by a predetermined divisor is generated as an address. An address generator,
First computing means for obtaining a first intermediate remainder by dividing the first result by the divisor;
Second computing means for obtaining a second intermediate remainder by dividing the predetermined function of the ordinal by the divisor;
Third arithmetic means for dividing the sum of the first intermediate remainder and the second intermediate remainder by the divisor to obtain a final remainder;
With
An address generation apparatus characterized in that the final remainder is the address.

(Appendix 2)
The address generation device according to attachment 1, wherein
The second calculation means includes
Means for obtaining a third intermediate remainder by dividing the ordinal number by a predetermined numerical value determined by the second constant and the divisor;
Storage means for holding a correspondence relationship between the third intermediate residue and the second intermediate residue;
An address generation apparatus characterized in that the second intermediate residue is obtained by referring to the storage means using the third intermediate residue as a key.

(Appendix 3)
The address generation device according to attachment 2, wherein
The means for obtaining the third intermediate remainder is
A counter that counts the ordinal number and outputs a count value as the third intermediate remainder;
Means for resetting the counter when the third intermediate remainder reaches the predetermined value;
An address generation device comprising:

(Appendix 4)
The address generation device according to appendix 2 or 3,
The address generation apparatus according to claim 1, wherein the predetermined numerical value is a quotient obtained by dividing the divisor by a greatest common divisor of the second constant and the divisor.

(Appendix 5)
The address generation device according to any one of appendices 2 to 4,
The second calculation means moves the reference position to a position where the second intermediate remainder corresponding to the predetermined divisor in the storage means is stored, and then stores the storage using the third intermediate remainder as a key. An address generation apparatus characterized in that the second intermediate remainder is obtained by referring to means.

(Appendix 6)
The address generation device according to any one of appendices 1 to 5,
The first calculation means includes
An adder that adds the first constant to the first intermediate residue obtained by the comparison subtractor and outputs the resulting sum to the comparison subtractor;
The comparison subtractor for obtaining the first intermediate remainder by performing a comparison subtraction on the sum input from the adder and the first constant;
An address generation device comprising:

(Appendix 7)
The address generation device according to any one of appendices 1 to 6,
Storage means for storing input data in accordance with a write address, reading out and outputting the stored data in accordance with a read address, wherein the ordinal number is used as one of the write address and the read address, and the address generation device Storing means for using the address generated by the second address as the other of the write address and the read address;
A data rearrangement device comprising:

(Appendix 8)
A remainder obtained by dividing the sum of the first result obtained by multiplying the ordinal by the first constant and the result obtained by multiplying the square of the ordinal by the second constant by a predetermined divisor is generated as an address. An address generation method,
A first calculation step of obtaining a first intermediate remainder by dividing the first result by the divisor;
A second calculation step of obtaining a second intermediate remainder by dividing the predetermined function of the ordinal number by the divisor;
A third calculation step of obtaining a final remainder by dividing the sum of the first intermediate remainder and the second intermediate remainder by the divisor;
Have
An address generation method, wherein the final remainder is the address.

(Appendix 9)
The address generation method according to attachment 8, wherein
The second calculation step includes:
Obtaining a third intermediate remainder by dividing the ordinal by a predetermined numerical value determined by the second constant and the divisor;
Including a step of referring to storage means holding a correspondence relationship between the third intermediate residue and the second intermediate residue;
An address generation method characterized in that the second intermediate residue is obtained by referring to the storage means using the third intermediate residue as a key.

(Appendix 10)
The address generation method according to attachment 9, wherein
The step of obtaining the third intermediate remainder includes
A counter that counts the ordinal number and outputs a count value as the third intermediate remainder;
Resetting the counter when the third intermediate remainder reaches the predetermined value;
An address generation method comprising:

(Appendix 11)
The address generation method according to appendix 9 or 10,
The address generation method characterized in that the predetermined numerical value is a quotient obtained by dividing the divisor by a greatest common divisor of the second constant and the divisor.

(Appendix 12)
The address generation method according to any one of appendices 9 to 11,
In the second calculation step, the reference position is moved to a position where the second intermediate remainder corresponding to the predetermined divisor in the storage means is stored, and the storage is performed using the third intermediate remainder as a key. An address generation method characterized in that the second intermediate remainder is obtained by referring to a step.

(Appendix 13)
The address generation method according to any one of appendices 8 to 12,
The first calculation step includes:
Adding the first constant to the first intermediate residue obtained by the comparison subtractor and outputting the resulting sum to the comparison subtractor using an adder;
The comparison subtractor obtains the first intermediate remainder by performing a comparison subtraction on the sum input from the adder and the first constant;
An address generation method comprising:

(Appendix 14)
In addition to the address generation method described in any one of appendices 8 to 13,
A storage step of storing input data according to a write address, reading out the stored data according to a read address and outputting the same, wherein the ordinal number is used as one of the write address and the read address, and the address generation method A storage step of using the generated address as the other of the write address and the read address;
A data rearrangement method comprising:

(Appendix 15)
A dual port RAM used for interleaving using a cyclic data sequence obtained by using GCD (greatest common divisor) in an interleaving circuit for turbo coding and decoding used in LTE (Long Term Evolution 3GPP TS 36.212) An interleave circuit that generates addresses.

(Appendix 16)
The interleave circuit according to appendix 15, wherein the cyclic data is stored in a ROM and read from an information bit i (an arbitrary value of 0, 1, 2, ... K-1) to generate an interleave address Interleave circuit that performs.

  The present invention is suitable for interleaving and deinterleaving.

101 turbo encoder 102 encoding circuit 1
103 Coding circuit 2
104 Interleave circuit 105 Transmitter 201 Receiver 202 Turbo decoder 203 Deinterleave circuit 204 First decode circuit 205 Interleave circuit 206 Second decode circuit 207 Demultiplexer 300 Interleave circuit 301 Write counter 302 Read counter 303 f1 multiplier 304 i ² multiplier 305 f2 multiplier 306 adder 307 modulo arithmetic circuit 308 Dual Port RAM
400 Deinterleave circuit 401 Write counter 402 Read counter 403 f1 multiplier 404 i ² multiplier 405 f2 multiplier 406 adder 407 Modulo operation circuit 408 Dual Port RAM
501 Modulo operation comparison subtraction element 601 f1 adder 602 f1 comparison subtractor 603 comparator 604 f2 calculation counter 605 offset adder 606 ROM
607 f1, f2 adder 608 f1, f2 comparison subtractor 609 Write counter 610 Dual Port RAM
701 f1 adder 702 f1 comparison subtractor 703 comparator 704 f2 calculation counter 705 offset adder 706 ROM
707 f1, f2 adder 708 f1, f2 comparison subtractor 709 Read counter 710 Dual Port RAM

Claims (8)

A remainder obtained by dividing the sum of the first result obtained by multiplying the ordinal by the first constant and the result obtained by multiplying the square of the ordinal by the second constant by a predetermined divisor is generated as an address. An address generator,
First computing means for obtaining a first intermediate remainder by dividing the first result by the divisor;
Second computing means for obtaining a second intermediate remainder by dividing the predetermined function of the ordinal by the divisor;
Third arithmetic means for dividing the sum of the first intermediate remainder and the second intermediate remainder by the divisor to obtain a final remainder;
With
An address generation apparatus characterized in that the final remainder is the address. The address generation device according to claim 1,
The second calculation means includes
Means for obtaining a third intermediate remainder by dividing the ordinal number by a predetermined numerical value determined by the second constant and the divisor;
Storage means for holding a correspondence relationship between the third intermediate residue and the second intermediate residue;
An address generation apparatus characterized in that the second intermediate residue is obtained by referring to the storage means using the third intermediate residue as a key. The address generation device according to claim 2,
The means for obtaining the third intermediate remainder is
A counter that counts the ordinal number and outputs a count value as the third intermediate remainder;
Means for resetting the counter when the third intermediate remainder reaches the predetermined value;
An address generation device comprising: The address generation device according to claim 2 or 3,
The address generation apparatus according to claim 1, wherein the predetermined numerical value is a quotient obtained by dividing the divisor by a greatest common divisor of the second constant and the divisor. The address generation device according to any one of claims 2 to 4,
The second calculation means moves the reference position to a position where the second intermediate remainder corresponding to the predetermined divisor in the storage means is stored, and then stores the storage using the third intermediate remainder as a key. An address generation apparatus characterized in that the second intermediate remainder is obtained by referring to means. The address generation device according to any one of claims 1 to 5,
The first calculation means includes
An adder that adds the first constant to the first intermediate residue obtained by the comparison subtractor and outputs the resulting sum to the comparison subtractor;
The comparison subtractor for obtaining the first intermediate remainder by performing a comparison subtraction on the sum input from the adder and the first constant;
An address generation device comprising: The address generation device according to any one of claims 1 to 6,
Storage means for storing input data in accordance with a write address, reading out and outputting the stored data in accordance with a read address, wherein the ordinal number is used as one of the write address and the read address, and the address generation device Storing means for using the address generated by the second address as the other of the write address and the read address;
A data rearrangement device comprising: A remainder obtained by dividing the sum of the first result obtained by multiplying the ordinal by the first constant and the result obtained by multiplying the square of the ordinal by the second constant by a predetermined divisor is generated as an address. An address generation method,
A first calculation step of obtaining a first intermediate remainder by dividing the first result by the divisor;
A second calculation step of obtaining a second intermediate remainder by dividing the predetermined function of the ordinal number by the divisor;
A third calculation step of obtaining a final remainder by dividing the sum of the first intermediate remainder and the second intermediate remainder by the divisor;
Have
An address generation method, wherein the final remainder is the address.

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