JP2015035484A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device having a magnetic memory element.SOLUTION: A magnetic memory element comprises: a lamination part L1 of a domain wall displacement layer WDL and a cap layer CL on the domain wall displacement layer WDL; and a lamination part L2 which is arranged on the lamination part L1 in a central part and in which a magnetization reversal layer MRL, a tunnel barrier layer TBL and a magnetization fixed layer MFL are sequentially laminated from the bottom. With this configuration, a ferromagnetic film which can ensure a large MR ratio can be selected as the magnetization reversal layer, thereby increasing a sensing margin at the time of reading. In addition, a ferromagnetic film which requires a small writing current can be selected as the domain wall displacement layer WDL, thereby achieving reduction in writing current. In this way, characteristics of the magnetic memory element can be improved.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. For example, the present invention can be suitably used for a semiconductor device having a magnetic memory and a method for manufacturing the semiconductor device.

  In recent years, an MRAM using a ferromagnetic film having a magnetoresistive effect has been proposed as one of nonvolatile memories, and its development is progressing.

  For example, Patent Document 1 (Japanese Patent Laid-Open No. 2005-191032) and Patent Document 2 (Japanese Patent Laid-Open No. 2006-73930) disclose a domain wall motion type magnetic memory.

  Patent Document 3 (International Publication No. 2009/060749) discloses a first magnetization free layer having magnetic anisotropy in the film thickness direction, and a second magnetization free layer having magnetic anisotropy in the in-plane direction. There is disclosed a domain wall motion type magnetic memory including:

JP 2005-191032 A JP 2006-73930 A International Publication No. 2009/060749

  The present inventor is engaged in the research and development of the MRAM as described above, and is examining the improvement of the performance. In the process, in order to improve the performance of the MRAM, in particular, the domain wall motion type magnetic memory element, it has been found that there is room for further improvement with respect to its structure and manufacturing method.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device shown in an embodiment disclosed in the present application includes a first stacked unit having a first ferromagnetic film and a nonmagnetic conductive film, a second ferromagnetic film, an insulating film, and a third layer. And a magnetic memory element having a second stacked portion having a ferromagnetic film. The second stacked unit is disposed above or below a partial region of the first stacked unit, and the first to fifth ferromagnetic films have perpendicular magnetic anisotropy.

  A manufacturing method of a semiconductor device shown in an embodiment disclosed in the present application includes a step of forming a laminated film of a first ferromagnetic film and a nonmagnetic conductive film above a semiconductor substrate, And sequentially depositing a second ferromagnetic film, an insulating film, and a third ferromagnetic film. Then, there is a step of selectively etching the second ferromagnetic film, the insulating film, and the third ferromagnetic film until the nonmagnetic conductive film is exposed.

  According to the semiconductor device shown in the following representative embodiments disclosed in the present application, the characteristics of the semiconductor device can be improved.

  According to the method for manufacturing a semiconductor device shown in the following representative embodiment disclosed in the present application, a semiconductor device having good characteristics can be manufactured.

FIG. 3 is a cross-sectional view showing a magnetic memory element of the semiconductor device of First Embodiment. 4 is a plan view showing a magnetic memory element of the semiconductor device of First Embodiment; FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment. 1 is a circuit diagram showing a configuration of a semiconductor device according to a first embodiment. FIG. 3 is a diagram illustrating the magnetization direction of each layer (ferromagnetic film) of the magnetic memory element according to the first embodiment. It is sectional drawing which shows the structure of the magnetic memory element of a comparative example, and its current pathway. FIG. 3 is a cross-sectional view showing a current path of the magnetic memory element in the first embodiment. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device of First Embodiment; FIG. FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 14; It is sectional drawing which shows the manufacturing process of the semiconductor device of a comparative example. FIG. 17 is a cross-sectional view showing a manufacturing process of the semiconductor device of the comparative example, and is a cross-sectional view showing a manufacturing process following FIG. 16. FIG. 18 is a cross-sectional view showing a manufacturing process of the semiconductor device of the comparative example, and is a cross-sectional view showing a manufacturing process following FIG. 17. FIG. 19 is a cross-sectional view showing a manufacturing process of the semiconductor device of the comparative example, and is a cross-sectional view showing a manufacturing process following FIG. 18. It is a graph which shows the relationship between MTJ resistance (R0, R1) and MR ratio. It is a graph which shows the relationship between MTJ resistance (R0, R1) and variation (σ). 11 is a cross-sectional view showing a manufacturing step of the semiconductor device of Second Embodiment; FIG. FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 22; FIG. 24 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 23. FIG. 25 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and showing the manufacturing step following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 25. FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 26. FIG. 28 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment, and showing a manufacturing step following FIG. 27; 11 is a cross-sectional view showing a manufacturing step of the semiconductor device of Embodiment 3; FIG. FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 29. FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 30. FIG. 32 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 31. FIG. 33 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 32. FIG. 34 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 33. FIG. 35 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 34. FIG. 36 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment, and is a cross-sectional view showing a manufacturing step following FIG. 35. FIG. 10 is a cross-sectional view showing a magnetic memory element of a semiconductor device according to a fourth embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In addition, when there are a plurality of similar members (parts), a symbol may be added to the generic symbol to indicate an individual or specific part. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  In the cross-sectional view and the plan view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large for easy understanding of the drawing. Even when the cross-sectional view and the plan view correspond to each other, a specific part may be displayed relatively large in order to make the drawing easy to understand.

(Embodiment 1)
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings.

[Description of structure]
FIG. 1 is a cross-sectional view showing a magnetic memory element of the semiconductor device of the present embodiment. FIG. 2 is a plan view showing a magnetic memory element of the semiconductor device of the present embodiment. For example, FIG. 1 corresponds to the AA cross section of FIG. FIG. 3 is a cross-sectional view showing the configuration of the semiconductor device of the present embodiment. FIG. 4 is a circuit diagram showing a configuration of the semiconductor device of the present embodiment. FIG. 5 is a diagram showing the magnetization direction of each layer (ferromagnetic film) of the magnetic memory element of this embodiment. FIG. 6 is a cross-sectional view showing a configuration of a magnetic memory element of a comparative example and its current path. FIG. 7 is a diagram showing a current path of the magnetic memory element of the present embodiment.

  The magnetic memory element MM in FIG. 1 is a magnetic memory. The magnetic memory is a kind of nonvolatile memory and is also called MRAM (Magnetic Random Access Memory). The magnetic memory is a magnetic memory element (also referred to as a magnetoresistive effect element) using a ferromagnetic film having a magnetoresistive effect.

  The magnetic memory element MM shown in FIG. 1 is connected in series between two selection transistors (TR1, TR2), for example, as shown in FIGS. Such a configuration is referred to as a 2T-1MTJ (2 Transistors-1 Magnetic Tunnel Junction) configuration. As shown in FIG. 4, the magnetic memory element MM has three terminals (terminal a, terminal b, and terminal c). The terminal c is connected to the ground potential line GNL, the terminal a is connected to the bit line BL1 via the selection transistor TR1, and the terminal b is connected to the bit line BL2 via the selection transistor TR2. The terminal a corresponds to a hard layer HL1 described later, and the terminal b corresponds to a hard layer HL2 described later. The terminal c corresponds to a magnetization fixed layer MFL described later.

  The gate electrodes (GE) of the selection transistors TR1 and TR1 are each connected to the word line WL.

  A plurality of such magnetic memory elements MM are arranged at the intersections between the bit line pairs (BL1, BL2) and the word lines WL to constitute a memory cell array.

  Next, each part of the selection transistors (TR1, TR2) and the magnetic memory element MM will be described in detail with reference to FIGS.

<Selection transistor>
As shown in FIG. 3, the selection transistors (TR1, TR2) are formed in a region partitioned by an element isolation region STI on the main surface of a substrate (p-type well PW) S made of a semiconductor. The selection transistors (TR1, TR2) are formed on the substrate (p-type well PW) S through the gate insulating film GI and in the substrate (p-type well PW) S on both sides of the gate electrode GE. Have a source / drain region SD. A sidewall film SW is disposed on the side wall of the gate electrode GE, and the source and drain regions SD have a so-called LDD (Lightly doped Drain) structure.

  The selection transistors (TR1, TR2) and the magnetic memory element MM are connected via a plurality of plugs (P1 to P4) and wirings (M1 to M3). And each plug (P1-P4) is arrange | positioned in the interlayer insulation film (IL1-IL4). Specifically, one source / drain region SD of the selection transistor TR1 is connected to the hard layer HL1 of the magnetic memory element MM via a plurality of plugs (P1 to P4) and wirings (M1 to M3). One source / drain region SD of the transistor for transistor TR2 is connected to the hard layer HL2 of the magnetic memory element MM via a plurality of plugs (P1 to P4) and wirings (M1 to M3). The other source / drain region SD of the selection transistor TR1 is connected to the wiring M1 to be the bit line BL1 via the plug P1, and the other source / drain region SD of the selection transistor TR2 is connected to the plug P1. And connected to the wiring M1 to be the bit line BL2.

<Magnetic memory element>
As shown in FIG. 1, the magnetic memory element MM has a stacked portion L1 including a domain wall motion layer WDL and an upper cap layer CL. A laminated portion L2 in which a magnetization switching layer MRL, a tunnel barrier layer TBL, and a magnetization fixed layer MFL are laminated in this order from the bottom is disposed above the central portion of the laminated portion L1. Hard layers HL1 and HL2 are disposed below the both ends of the stacked portion L1, respectively. A magnetic tunnel junction is formed by the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL of the stacked portion L2.

  As shown in FIG. 2, the shape in plan view (also referred to as a planar shape) from the upper surface of the stacked portion L1 is a substantially rectangular shape having long sides in the X direction. The planar shape of the stacked portion L2 is a substantially rectangular shape having long sides in the Y direction. The stacked portion L1 and the stacked portion L2 extend in a direction crossing each other and have an overlapping region.

  Here, a central region of the laminated portion L1 (domain wall moving layer WDL) is a region 1A, and regions on both sides of the region 1A are regions 1B and 2B, respectively (see FIGS. 1 and 2). The region 1B is an overlapping region between the stacked portion L1 and the hard layer HL1, and the region 2B is an overlapping region between the stacked portion L2 and the hard layer HL2. The region 1A is a region that does not overlap with the hard layers HL1 and HL2 in the stacked portion L1. In other words, the region 1A is a formation region of the stacked portion L1 located between the hard layers HL1 and HL2. At least a part of the region 1A is an overlapping region of the stacked portion L1 and the stacked portion L2. Here, the overlapping region of the stacked portion L1 and the stacked portion L2 is arranged on the central region of the region 1A. Further, the stacked portion L2 is arranged so as to cross the stacked portion L1. The stacked portion L2 only needs to be formed in at least the region 1A, and it is not necessary to extend the stacked portion L2 so as to cross the stacked portion L1.

  The domain wall motion layer WDL, the magnetization switching layer MRL, and the magnetization fixed layer MFL are made of a ferromagnetic film (ferromagnetic material). This ferromagnetic film has a perpendicular magnetic anisotropy (PMA). That is, the magnetization direction of the domain wall motion layer WDL, the magnetization switching layer MRL, and the magnetization fixed layer MFL is the film thickness direction.

  The ferromagnetic film used as the domain wall motion layer WDL, the magnetization switching layer MRL, and the magnetization fixed layer MFL is, for example, a metal selected from Fe (iron), Co (cobalt), and Ni (nickel) or two or more kinds of metals. A film made of an alloy. Further, Pt (platinum) or Pd (palladium) may be included in the film. By including Pt or Pd in the film, the perpendicular magnetic anisotropy can be stabilized.

  Furthermore, B, C, N, O, Al, Si, P, Ti, V, Cr, Mn, Cu, Zn, Zr, Nb, Mo, Tc, Ru, Rh, Ag, Hf, Ta, W, Re, Magnetic properties can be adjusted by adding various elements such as Os, Ir, Au, and Sm.

  As the ferromagnetic film, specifically, Co, Co—Pt, Co—Pd, Co—Cr, Co—Pt—Cr, Co—Cr—Ta, Co—Cr—B, Co—Cr—Pt—B, Co-Cr-Ta-B, Co-V, Co-Mo, Co-W, Co-Ti, Co-Ru, Co-Rh, Fe-Pt, Fe-Pd, Fe-Co-Pt, Fe-Co- A material (alloy film, mixed film) such as Pd or Sm—Co can be used.

  Further, the ferromagnetic film may be a laminated film of films made of the above materials. For example, a laminated film of two or more metal films selected from Fe, Co, and Ni may be used. Specifically, a multilayer film such as Co / Ni, Co / Pd, Co / Pt, or Fe / Au can be used as the ferromagnetic film.

  Of the domain wall motion layer WDL, the magnetization switching layer MRL, and the magnetization fixed layer MFL, the magnetization fixed layer MFL preferably has a laminated structure in which ferromagnetic films are stacked so as to sandwich a nonmagnetic film. For example, various material films of the ferromagnetic film are stacked so as to sandwich a nonmagnetic film made of a Ru (ruthenium) film or the like. Thereby, the magnetic coupling force in the magnetization fixed layer MFL can be increased, and the effect of increasing the coercive force of the film (antiferromagnetic coupling effect) is achieved. Further, in this laminated structure, the state in which the two ferromagnetic films are oriented in opposite directions of magnetization is maintained, so that the leakage magnetic field from each other is cancelled. Thereby, the influence of the leakage magnetic field from the magnetization fixed layer MFL can be reduced.

  The hard layers HL1 and HL2 are made of a ferromagnetic film (ferromagnetic material). This ferromagnetic film has perpendicular magnetic anisotropy. That is, the magnetization direction of the hard layers HL1 and HL2 is the film thickness direction. As the ferromagnetic films constituting the hard layers HL1 and HL2, the same films as the ferromagnetic films used as the domain wall motion layer WDL, the magnetization switching layer MRL, and the magnetization fixed layer MFL described above can be used. For example, the ferromagnetic film used as the hard layers HL1 and HL2 is a film made of a metal selected from, for example, Fe (iron), Co (cobalt), and Ni (nickel) or an alloy of two or more metals. is there. Further, Pt (platinum) or Pd (palladium) may be included in the film. By including Pt or Pd in the film, the perpendicular magnetic anisotropy can be stabilized.

  Furthermore, B, C, N, O, Al, Si, P, Ti, V, Cr, Mn, Cu, Zn, Zr, Nb, Mo, Tc, Ru, Rh, Ag, Hf, Ta, W, Re, Magnetic properties can be adjusted by adding various elements such as Os, Ir, Au, and Sm.

  As the ferromagnetic film, specifically, Co, Co—Pt, Co—Pd, Co—Cr, Co—Pt—Cr, Co—Cr—Ta, Co—Cr—B, Co—Cr—Pt—B, Co-Cr-Ta-B, Co-V, Co-Mo, Co-W, Co-Ti, Co-Ru, Co-Rh, Fe-Pt, Fe-Pd, Fe-Co-Pt, Fe-Co- A material (alloy film, mixed film) such as Pd or Sm—Co can be used.

  Further, the ferromagnetic film may be a laminated film of films made of the above materials. For example, a laminated film of two or more metal films selected from Fe, Co, and Ni may be used. Specifically, a multilayer film such as Co / Ni, Co / Pd, Co / Pt, or Fe / Au can be used as the ferromagnetic film.

  Moreover, the same material may be used for the ferromagnetic film which comprises the hard layers HL1 and HL2, and different materials may be used. Furthermore, the hard layers HL1 and HL2 may have the same planar shape or may have different planar shapes. The magnetization directions of the hard layers HL1 and HL2 are formed so as to be antiparallel to each other (see FIG. 5).

  The cap layer CL is disposed between the domain wall motion layer WDL and the magnetization switching layer MRL. The cap layer CL is made of a nonmagnetic conductive film, such as a Ta (tantalum) film.

  The tunnel barrier layer TBL is made of an insulating film, and for example, an aluminum oxide (AlOx) film or a magnesium oxide (MgO) film is used.

  For example, the following may be mentioned as examples of the combination of materials of each layer used in the magnetic memory element of the present embodiment. For example, a Co—Pt alloy film with a thickness of about 20 to 30 nm can be used as the magnetization fixed layer MFL and the hard layers HL1 and HL2.

  As the magnetization switching layer MRL, for example, a Co / Ni laminated film of about 3 to 5 nm can be used.

  As the domain wall motion layer WDL, a Co—Fe—B alloy film of about 3 to 5 nm can be used.

  As the cap layer CL, a Ta film of about 5 to 10 nm can be used.

  As the tunnel barrier layer TBL, an aluminum oxide film or a magnesium oxide film having a thickness of about 1 to 2 nm can be used.

  Note that a Co—Fe—B alloy film may be used as the magnetization switching layer MRL. That is, the domain wall motion layer WDL and the magnetization switching layer MRL may be made of the same constituent element. As will be described later, these films preferably have characteristics corresponding to their respective roles. However, even if the films are composed of the same constituent elements, by adjusting the film thickness, composition, etc., the ferromagnetic films Characteristics (MR ratio, coercive force, write current, etc.) can be adjusted.

  Here, the direction of magnetization of each layer (ferromagnetic film) of the semiconductor device of the present embodiment will be described with reference to FIG. As shown in FIG. 5, for example, the magnetization of the magnetization fixed layer MFL is fixed in the + z direction. Also, the magnetization of the domain wall motion layer WDL region (also referred to as a magnetization fixed region) 1B is fixed in the + z direction by the hard layer HL1, and the domain wall motion layer WDL region (also referred to as a magnetization fixed region) 2B is fixed by the hard layer HL2. The magnetization of is fixed in the -z direction. Thus, the region 1B and the region 2B of the domain wall motion layer WDL are opposite in direction and have parallel magnetization (also referred to as antiparallel). On the other hand, the region 1A (also referred to as a magnetization free region) 1A of the domain wall motion layer WDL has magnetization that can be reversed between the + z direction and the −z direction. Further, the magnetization direction of the magnetization switching layer MRL becomes the same as the magnetization direction of the region 1A of the domain wall motion layer WDL due to the leakage magnetic field from the region 1A of the domain wall motion layer WDL. That is, the magnetization of the magnetization reversal layer MRL corresponds to the magnetization direction of the region 1A of the domain wall motion layer WDL and has the same direction as that of the magnetization fixed layer MFL and is parallel (also simply referred to as “parallel”) or opposite in direction. Parallel (also called antiparallel).

  Next, a write (rewrite) operation of the magnetic memory element MM will be described. Here, the magnetization of the magnetization fixed layer MFL is in the + z direction, the magnetization of the magnetization switching layer MRL and the region (magnetization free region) 1A is in the −z direction, and the boundary between the region 1B and the region 1A (the end of the hard layer HL1) ) A state where a domain wall is formed in B1 is defined as data “1”. The magnetization of the magnetization fixed layer MFL is in the + z direction, the magnetization of the magnetization switching layer MRL and the region (magnetization free region) 1A is in the + z direction, and the boundary between the region 2B and the region 1A (end of the hard layer HL2) B2 The state in which the domain wall is formed in the data is defined as data “0”. The correspondence between the magnetization direction and the data value may be reversed.

  When data “1” is written in the magnetic memory element in which data “0” is written, a write current is passed from the hard layer HL1 to the hard layer HL2 via the domain wall motion layer WDL. With this write current, spin-polarized electrons are injected from the region 2B into the region 1A. At this time, the domain wall moves from the boundary B2 toward the boundary B1 due to the spin transfer effect.

  That is, the magnetization direction of the region 1A changes from the + z direction to the -z direction. Thereby, the direction of the leakage magnetic field from the region 1A also changes from the + z direction to the −z direction, and accordingly, the magnetization direction of the magnetization switching layer MRL also changes from the + z direction to the −z direction.

  When data “0” is written in a state where data “1” is written, a write current is passed from the hard layer HL2 to the hard layer HL1 through the domain wall motion layer WDL. With this write current, spin-polarized electrons are injected from the region 1B to the region 1A. At this time, the domain wall moves from the boundary B1 toward the boundary B2 due to the spin transfer effect.

  That is, the magnetization direction of the region 1A changes from the −z direction to the + z direction. As a result, the direction of the leakage magnetic field from the region 1A also changes from the -z direction to the + z direction, and accordingly, the magnetization direction of the magnetization switching layer MRL also changes from the -z direction to the + z direction.

  Next, a read operation of the magnetic memory element MM will be described. Reading is determined by whether the magnetic memory element MM is in a low resistance state or a high resistance state. For example, in the state of the data “1”, that is, when the magnetization of the magnetization fixed layer MFL is in the + z direction and the magnetization of the magnetization switching layer MRL and the region (magnetization free region) 1A is in the −z direction (antiparallel) ), The region from the magnetization fixed layer MFL to the region (magnetization free region) 1A is in a high resistance state. In the state of the data “0”, that is, the magnetization of the magnetization fixed layer MFL is in the + z direction, and the magnetization of the magnetization switching layer MRL and the region (magnetization free region) 1A is in the + z direction (when parallel). In this case, the region between the magnetization fixed layer MFL and the region (magnetization free region) 1A is in a low resistance state. Therefore, for example, a read current is passed between the magnetization fixed layer MFL and the hard layer HL2, and the resistance value is detected by the current value flowing between them. For example, when the value is higher than the reference resistance value, the data “1” is read, and when the value is lower than the reference resistance value, for example, the data “0” is read. In other words, the data written in the magnetic memory element MM can be determined.

  Note that a read current may flow between the magnetization fixed layer MFL and the hard layer HL1. Further, the read current may flow from the magnetization fixed layer MFL to the hard layer (HL1 or HL2), or may flow from the hard layer (HL1 or HL2) to the magnetization fixed layer MFL. .

  Thus, it is preferable that the ferromagnetic films constituting the domain wall motion layer WDL, the magnetization switching layer MRL, the magnetization fixed layer MFL, and the hard layers HL1 and HL2 have the following characteristics according to their roles.

  As the ferromagnetic film constituting the magnetization fixed layer MFL and the hard layers HL1 and HL2, it is preferable to use a film having a higher coercive force than the magnetization switching layer MRL. The coercive force refers to energy necessary for reversing the magnetization direction. Among the ferromagnetic films described above, examples of the film having a relatively high coercive force include Co / Pt and Co / Pd.

  Further, as the ferromagnetic film constituting the magnetization switching layer MRL, it is preferable to use a film having a relatively low coercive force. As described above, it is preferable to use a film having a coercive force lower than that of the magnetization fixed layer MFL and the hard layers HL1 and HL2. Moreover, it is preferable to use a film having a coercive force lower than that of the domain wall motion layer WDL. Among the ferromagnetic films described above, examples of the film having a relatively low coercive force include Co / Ni.

  As the ferromagnetic film constituting the domain wall motion layer WDL, it is preferable to use a film having a write current (threshold current) smaller than that of the magnetization switching layer MRL.

  Here, in the present embodiment, the magnetic memory element MM is disposed on the laminated portion L1 of the domain wall motion layer WDL and the cap layer CL above the magnetic wall moving layer WDL, and on the upper portion of the central portion of the laminated portion L1, Since the MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL have the stacked portion L2 stacked in order from the bottom, the characteristics of the magnetic memory element MM can be improved. Specifically, the MR ratio can be improved. In addition, the write current value can be reduced. The MR ratio is the resistance when the magnetization of the magnetization fixed layer MFL is in the + z direction and the magnetization inversion layer MRL is in the −z direction (when antiparallel), and the resistance of the magnetization fixed layer MFL is + z. R0 × R1 / (R0 + R1) where the resistance is R0 when the magnetization of the magnetization switching layer MRL is in the + z direction (when parallel). As the MR ratio increases, the difference between the high resistance value R1 and the low resistance value R0 increases, and the sensing margin during reading increases.

  In other words, since the ferromagnetic films constituting the magnetization switching layer MRL and the domain wall motion layer WDL can be selected independently, the MR ratio can be improved and the write current value can be reduced. it can.

  That is, it is not necessary to search for a material that satisfies the characteristics required for each of the domain wall motion layer and the magnetization switching layer, and it is possible to independently use a film that can make maximum use of each characteristic.

  For example, in the configuration of the magnetic memory element of the comparative example shown in FIG. 6, it is difficult to reduce the write current value while improving the MR ratio. FIG. 6 is a cross-sectional view showing a configuration of a magnetic memory element of a comparative example.

  In the magnetic memory element of the comparative example shown in FIG. 6, the magnetization fixed layer MFL is disposed on the stacked portion L0 of the domain wall motion layer WDL and the tunnel barrier layer TBL. In this case, by flowing a write current from the hard layer HL1 to the hard layer HL2 via the domain wall moving layer WDL, the domain wall can be moved from the boundary B2 toward the boundary B1, and data “1” can be written. . In addition, by passing a write current from the hard layer HL2 to the hard layer HL1 via the domain wall moving layer WDL, the domain wall can be moved from the boundary B1 toward the boundary B2, and data “0” can be written. Further, a read current is passed between the magnetization fixed layer MFL and the hard layer HL2, and the resistance value is detected from the current value flowing between them. In the case of high resistance, data “1” is read and low resistance In this case, data “0” can be read.

  However, even if the material can be written (rewritten) with a small current, a large current is required for writing even if the MR ratio (resistance difference due to change in magnetization direction) is small or a material with a large MR ratio. In many cases, it is difficult to optimize the characteristics of both the MR ratio and the write current, such as reducing the write current while increasing the MR ratio. Therefore, when the domain wall motion layer WDL is included in both the current path WC at the time of writing and the current path RC at the time of reading, as in the comparative example shown in FIG. 6, the domain wall motion layer WDL is written as Even if a ferromagnetic film having a small current (current density necessary for domain wall motion) is selected, the MR ratio may be small. Conversely, when a ferromagnetic film having a large MR ratio is selected, the write current (current density necessary for domain wall motion) may not be reduced.

  In contrast, in the present embodiment, as shown in FIG. 7, the current path WC at the time of writing mainly includes the domain wall motion layer WDL, and the current path RC at the time of reading includes the magnetization switching layer MRL. included. Therefore, even if a ferromagnetic film having a large MR ratio is selected as the magnetization switching layer MRL and the sensing margin at the time of reading is ensured to be large, the magnetization switching layer MRL is not included in the current path WC at the time of writing. Can be suppressed. On the other hand, even if a ferromagnetic film having a small write current is selected as the domain wall motion layer WDL and the write current is reduced, the domain wall motion layer WDL has a small influence on the read current path RC. The influence of the MR ratio can be reduced, and a large sensing margin during reading can be secured by the high MR ratio of the magnetization switching layer MRL. In addition, the reading speed can be improved.

  As described above, by adopting the configuration of the present embodiment, a film configuration that can maximize the MR ratio can be used as the magnetization switching layer MRL regardless of the magnitude of the write current, and the domain wall motion layer WDL. As the ferromagnetic film constituting the film, a film structure capable of minimizing the write current (threshold current) can be used regardless of the MR ratio, thereby widening the range of material selection.

  Furthermore, in the structure of the present embodiment, the magnetization fixed layer MFL, the tunnel barrier layer TBL, and the magnetization switching layer MRL are processed, so that the tunnel barrier layer is etched as in the comparative example (see FIGS. 16 to 19). There is no need to stop, and the manufacturing margin can be greatly increased. The manufacturing method of this embodiment will be described in detail below.

[Product description]
Next, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 8 to 15 and the configuration of the semiconductor device will be further clarified. 8 to 15 are cross-sectional views showing the manufacturing steps of the semiconductor device of the present embodiment. 8 to 15, FIG. 8 is a cross-sectional view showing a process for forming a selection transistor and wiring thereon, and FIGS. 9 to 15 are cross-sectional views showing a process for forming a magnetic memory element.

  First, as shown in FIG. 8, two selection transistors (TR1, TR2) are formed on the main surface of a substrate (semiconductor substrate) S made of a semiconductor, and further, interlayer insulating films (IL1 to IL4) are formed thereon. ) To form a plurality of wirings (M1 to M3). Although there is no restriction | limiting in these formation methods, For example, it can form by the following processes.

  First, the substrate S is prepared. As the substrate S, for example, a substrate made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm can be used.

  Next, an element isolation region STI is formed on the main surface of the substrate S. The element isolation region STI can be formed by, for example, an STI (Shallow Trench Isolation) method. In this case, an element isolation region STI is formed by etching the element isolation region of the substrate S to form a groove and embedding an insulating film such as a silicon oxide film in the groove. For example, an insulating film such as a silicon oxide film is deposited on a substrate including the inside of the groove, and the insulating film other than the groove is removed by using a CMP (Chemical Mechanical Polishing) method or the like. An insulating film can be embedded in the trench.

  An active region is defined by the element isolation region STI, and semiconductor elements such as selection transistors (TR1, TR2) are formed in the active region. The transistor is also called a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Here, an n-channel type MISFET is described as an example. However, a p-channel type MISFET having a reversed conductivity type may be formed as a semiconductor element, and an n-channel type MISFET and a p-channel type MISFET may be formed. Both MISFETs may be formed.

  Next, a p-type well PW is formed in the active region of the substrate S. The p-type well PW is formed, for example, by ion-implanting p-type impurities into the substrate S. Thereby, a p-type well PW which is a p-type semiconductor region from the main surface of the substrate S to a predetermined depth can be formed.

  Next, the gate electrode GE is formed on the main surface of the substrate (p-type well PW) S via the gate insulating film GI. First, a gate insulating film GI made of an insulating film is formed on the main surface of the substrate S. For example, the gate insulating film GI made of a silicon oxide film or the like is formed using a thermal oxidation method or the like. Next, a gate electrode material made of, for example, a polycrystalline silicon film is deposited on the gate insulating film GI by using a CVD (Chemical Vapor Deposition) method or the like, and this polycrystalline silicon film is patterned into a desired shape. Then, the gate electrode GE is formed. With patterning, a photoresist film having a desired shape is formed on a film such as a polycrystalline silicon film by using a photolithography technique, and the film is selectively etched using the photoresist film as a mask. Processing the film into a desired shape.

Next, source and drain regions SD are formed in the substrate S on both sides of the gate electrode GE. First, an n ⁻ type semiconductor region having a low impurity concentration is formed by ion implantation using the gate electrode GE as a mask (ion implantation blocking mask). Next, an insulating film made of a silicon oxide film or the like is formed on the substrate S including the gate electrode GE and anisotropically etched to form the sidewall film SW on the side wall of the gate electrode GE. Next, an n ⁺ type semiconductor region having a high impurity concentration is formed by ion implantation using the gate electrode GE and the sidewall film SW as a mask. As a result, it is possible to form an LDD source / drain region SD composed of an n ⁻ type semiconductor region having a low impurity concentration and an n ⁺ type semiconductor region having a higher impurity concentration and a deep junction depth.

  Next, annealing treatment (heat treatment) is performed to activate the impurities introduced by the conventional ion implantation.

  Through the above steps, a semiconductor element such as a selection transistor (TR1, TR2) can be formed on the main surface of the substrate S.

Thereafter, a metal silicide film (not shown) may be formed on the gate electrode GE and the n ⁺ type semiconductor region by using a salicide technique. With this metal silicide layer, diffusion resistance, contact resistance, and the like can be reduced.

  Next, an interlayer insulating film IL1 is formed on the main surface of the substrate S. For example, an insulating film such as a silicon oxide film is deposited using a CVD method or the like. Thereafter, the surface of the insulating film is planarized using a CMP method or the like as necessary.

  Next, a plug (connection portion) P1 is formed in the interlayer insulating film IL1. First, a contact hole is formed by etching the interlayer insulating film IL1, and a plug (connection portion) P1 is formed by embedding a conductive film therein. For example, a laminated film of a barrier conductor film (not shown) and a main conductor film is formed on the interlayer insulating film IL1 including the inside of the contact hole, and an unnecessary film on the interlayer insulating film IL1 is subjected to a CMP method or an etch back method. To remove.

  Next, the wiring M1 is formed on the interlayer insulating film IL1 in which the plug P1 is embedded. For example, a conductive film is deposited on the interlayer insulating film IL1 and patterned to form the wiring M1. Note that the wiring M1 may be formed using damascene technology (here, single damascene technology). In this case, a groove insulating film is formed on the interlayer insulating film IL1, a wiring groove is formed in the groove insulating film, and then a conductive film is embedded in the wiring groove to form the wiring M1.

  Thereafter, an interlayer insulating film IL2 is formed over the wiring M1, then a plug P2 is formed in the interlayer insulating film IL2, and further a wiring M2 is formed over the interlayer insulating film IL2. The interlayer insulating film IL2, the plug P2, and the wiring M2 can be formed in the same manner as the interlayer insulating film IL1, the plug P1, and the wiring M1, respectively. Next, similarly, an interlayer insulating film IL3, a plug P3, and a wiring M3 are formed. Further, similarly, an interlayer insulating film IL4 and a plug P4 are formed. Note that a dual damascene method may be used in forming the second and subsequent wirings. That is, the plug and the wiring may be integrally formed by simultaneously burying the contact hole and the wiring groove formed in each of the interlayer insulating film and the groove insulating film with the conductive film.

  Through the above steps, the selection transistors (TR1, TR2), the interlayer insulating films (IL1 to IL4), the wirings (M1 to M3), and the like can be formed (see FIG. 8).

  Next, the magnetic memory element MM is formed on the interlayer insulating film IL4 in which the plug P4 is embedded.

  First, as shown in FIG. 9, the hard layers HL1 and HL2 are formed on the interlayer insulating film IL4 in which the plug P4 is embedded. For example, a ferromagnetic film is deposited on the plug P4 and the interlayer insulating film IL4 by a sputtering method or the like. Next, an insulating film such as a silicon oxide film is formed as a hard mask HM1 on the ferromagnetic film by a CVD method. This insulating film (hard mask HM1) is patterned to remain only in the formation regions (regions 1B and 2B) of the hard layers HL1 and HL2. Next, the hard layers HL1 and HL2 are formed by etching the ferromagnetic film using the hard mask HM1 as a mask. Note that the hard mask HM1 may be formed of a stacked film of a silicon nitride film and a silicon oxide film thereabove.

  The hard layers HL1 and HL2 are each formed on the plug P4. The plug P4 electrically connected to the hard layer HL1 is electrically connected to one of the source and drain regions SD of the selection transistor TR1. The plug P4 electrically connected to the hard layer HL2 is electrically connected to one of the source and drain regions SD of the selection transistor TR2 (see FIG. 3). The ferromagnetic films used as the hard layers HL1 and HL2 are as described in the “magnetic memory element” column.

  Next, after removing the hard mask HM1, an interlayer insulating film IL5 is formed on the hard layers HL1 and HL2. For example, an insulating film such as a silicon oxide film is deposited as the interlayer insulating film IL5 on the hard layers HL1 and HL2 and the interlayer insulating film IL4 by a CVD method or the like. Thereafter, the surface portion of the interlayer insulating film IL5 is removed using a CMP method, an etch back method, or the like until the surfaces of the hard layers HL1 and HL2 are exposed. As a result, as shown in FIG. 10, the hard layers HL1 and HL2 are embedded in the interlayer insulating film IL5, and the surfaces of the hard layers HL1 and HL2 are exposed from the surface of the interlayer insulating film IL5.

  Next, as shown in FIG. 11, a laminated portion of the domain wall motion layer WDL and the cap layer CL thereabove is formed on the interlayer insulating film IL5 in which the hard layers HL1 and HL2 are embedded. For example, a ferromagnetic film is deposited as the domain wall motion layer WDL on the hard layers HL1 and HL2 and the interlayer insulating film IL5 by sputtering or the like. Next, a conductive film is deposited as a cap layer CL on the ferromagnetic film by a sputtering method or the like. The ferromagnetic film used as the domain wall motion layer WDL and the conductive film used as the cap layer CL are as described in the “magnetic memory element” column.

  Next, an insulating film such as a silicon oxide film is formed as a hard mask HM2 on the cap layer CL by a CVD method. The insulating film (hard mask HM2) is patterned to remain in the regions 1B, 1A, and 2B. Next, as shown in FIG. 12, by using the hard mask HM2 as a mask, the laminated film of the domain wall motion layer WDL and the cap layer CL is etched, so that the laminate portion comprising the domain wall motion layer WDL and the cap layer CL on the upper side thereof. L1 is formed. Note that the hard mask HM2 may be formed of a stacked film of a silicon nitride film and a silicon oxide film thereabove.

  Next, after removing the hard mask HM2, an interlayer insulating film IL6 is formed on the stacked portion L1. For example, an insulating film such as a silicon oxide film is deposited as the interlayer insulating film IL6 on the stacked portion L1 and the interlayer insulating film IL5 by a CVD method or the like. Thereafter, the surface portion of the interlayer insulating film IL6 is removed using a CMP method, an etch back method, or the like until the surface of the stacked portion L1 is exposed. As a result, as shown in FIG. 13, the laminated portion L1 is embedded in the interlayer insulating film IL6, and the surface of the cap layer CL of the laminated portion L1 is exposed from the surface of the interlayer insulating film IL6.

  Next, as shown in FIG. 14, on the interlayer insulating film IL6 in which the laminated portion L1 is embedded, a laminated film of the magnetization switching layer MRL, the upper tunnel barrier layer TBL, and the upper magnetization fixed layer MFL is formed. Form. For example, a ferromagnetic film is deposited as the magnetization reversal layer MRL on the stacked portion L1 and the interlayer insulating film IL6 by a sputtering method or the like. Next, an insulating film is deposited as a tunnel barrier layer TBL on the ferromagnetic film by a CVD method, a sputtering method, or the like. Next, for example, a ferromagnetic film is deposited on the insulating film as the magnetization fixed layer MFL by a sputtering method or the like. The ferromagnetic film used as the magnetization switching layer MRL and the magnetization fixed layer MFL and the insulating film used as the tunnel barrier layer TBL are as described in the “magnetic memory element” column.

  Next, an insulating film such as a silicon oxide film is formed as a hard mask HM3 on the magnetization fixed layer MFL by a CVD method. The insulating film (hard mask HM3) is patterned to remain in the central portion of the region 1A. Next, as shown in FIG. 15, by using the hard mask HM3 as a mask, the laminated film of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched (selectively etched), thereby from these layers. A stacked portion L2 is formed. Note that the hard mask HM3 may be formed of a stacked film of a silicon nitride film and a silicon oxide film thereabove.

  Next, after removing the hard mask HM3, an interlayer insulating film IL7 is formed on the stacked portion L2 (see FIG. 3). For example, an insulating film such as a silicon oxide film is deposited as the interlayer insulating film IL7 on the stacked portions L1 and L2 and the interlayer insulating film IL6 by a CVD method or the like. Thereafter, a plug (not shown) and a wiring (not shown) are formed on the magnetization fixed layer MFL of the stacked portion L2.

  Through the above steps, the selection transistors (TR1, TR2) and the magnetic memory element MM electrically connected thereto via the plugs (P1 to P4) and the wirings (M1 to M3) can be formed. (See FIG. 3).

  Here, in the present embodiment, the cap layer CL is used as an etching stopper when the stacked layer of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched when the stacked portion L2 is formed. Therefore, the characteristics of the magnetic memory element can be improved.

  For example, in the manufacturing process of the magnetic memory element of the semiconductor device of the comparative example, since the tunnel barrier layer TBL serves as an etching stopper, the etching control becomes difficult and the variation of the MTJ resistance (R0, R1) increases. 16 to 19 are cross-sectional views showing manufacturing steps of the semiconductor device of the comparative example.

  First, the manufacturing process of the magnetic memory element of the semiconductor device of the comparative example will be described. In the manufacturing process of the semiconductor device of the comparative example, as shown in FIG. 16, the domain wall motion layer WDL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL are sequentially formed on the interlayer insulating film IL5 in which the hard layers HL1 and HL2 are embedded. accumulate. Next, using the hard mask HM52 in the regions 1A, 1B, and 2B as a mask, the laminated film of the domain wall motion layer WDL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched (FIG. 17).

  Next, after removing the hard mask HM52, an interlayer insulating film IL6 is formed on the laminated film, and a surface portion of the interlayer insulating film IL6 is formed on the surface of the magnetization fixed layer MFL by using a CMP method, an etch back method, or the like. Remove until is exposed.

  Next, as shown in FIG. 18, a hard mask HM53 is formed on the interlayer insulating film IL6 in which the stacked film is embedded. Next, as shown in FIG. 19, the magnetization fixed layer MFL is etched using the hard mask HM53 at the center of the region 1A as a mask. At this time, it is preferable to use the tunnel barrier layer TBL as an etching stopper and finish the etching on the surface of the tunnel barrier layer TBL. However, since the tunnel barrier layer TBL is a thin film (for example, about 1 to 2 nm), it is difficult to etch the magnetization fixed layer MFL with good controllability. For this reason, the magnetization fixed layer MFL remains on the tunnel barrier layer TBL. Further, the thickness of the tunnel barrier layer TBL varies. Furthermore, the tunnel barrier layer TBL is etched, and the underlying domain wall motion layer WDL may be exposed or the film may be reduced. Such residues of the magnetization fixed layer MFL, variations in the thickness of the tunnel barrier layer TBL, variations in the thickness of the domain wall motion layer WDL, and the like greatly affect the MTJ resistance (R0, R1). For this reason, variation in MTJ resistance (R0, R1) increases, and as a result, it becomes difficult to ensure the MR ratio.

  FIG. 20 is a graph showing the relationship between the MTJ resistance (R0, R1) and the MR ratio. As shown in FIG. 20, if the difference between the resistor R0 and the resistor R1 is large, a large MR ratio can be ensured. However, if the variation between the resistor R0 and the resistor R1 increases, these differences, that is, the sensing margin becomes small. .

  FIG. 21 is a graph showing the relationship between MTJ resistance (R0, R1) and variation (σ). The horizontal axis is resistance [kΩ], and the vertical axis is variation (σ). As shown in FIG. 21, before the magnetization fixed layer MFL is etched (see the left figure, FIG. 6, and FIG. 18), the MTJ resistance (R0, R1) varies within 2%, whereas the comparative example In other words, after the etching of the magnetization fixed layer MFL (see the right figure, FIG. 6 and FIG. 19), the MTJ resistance (R0, R1) has a small variation within 4% and a large variation is 7 % Can be confirmed.

  On the other hand, in the present embodiment (see FIGS. 7, 14, and 15), since the cap layer CL having a small contribution to the MTJ resistance (R0, R1) can be used as an etching stopper, the MTJ resistance ( Variations in R0, R1) can be reduced. Further, the cap layer CL can be made thicker than the tunnel barrier layer TBL, and the controllability of etching of the laminated film of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL can be improved. it can. In other words, it becomes easy to adjust the etching conditions so that the cap layer CL remains on the domain wall motion layer WDL.

  Thus, in the present embodiment, since the cap layer CL can be used as an etching stopper, variation in MTJ resistance (R0, R1) can be reduced, and the MR ratio can be increased. Therefore, the characteristics of the magnetic memory element can be improved, such as increasing the sensing margin during reading.

  Although a magnetic memory element having a structure in which the magnetization fixed layer MFL is left above the hard layers HL1 and HL2 as shown in the left diagram of FIG. 21 can be considered, the magnetic memory element having such a structure has an MTJ resistance ( Although the variation of R0, R1) can be reduced, the MR ratio becomes extremely small. That is, in this case, since the magnetization fixed layer MFL is provided not only in the region 1A but also in the regions 1B and 2B, the magnetization of the regions 1B and 2B is caused by the magnetization fixed layer MFL and the hard layers HL1 and HL2. This portion is fixed and does not contribute to the change in MTJ resistance (R0, R1) accompanying the magnetization reversal. In other words, the fixed extra resistance is connected in parallel between the magnetization fixed layer MFL and the hard layers (HL1, HL2). Therefore, since the MR ratio is lowered and the sensing margin at the time of reading is lowered, the characteristics of the magnetic memory element having the structure in which the magnetization fixed layer MFL is left above the hard layers HL1 and HL2 are not preferable.

(Embodiment 2)
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings. In the first embodiment, the laminated film of the domain wall motion layer WDL and the cap layer CL is etched to form the laminated portion L1, and then the laminated film of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched. Although the laminated portion L2 is formed, etching may be performed after forming a laminated film of five layers of the domain wall motion layer WDL, the cap layer CL, the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL.

[Description of structure]
Since the configuration of the semiconductor device (magnetic memory element, selection transistor, etc.) of the present embodiment is the same as that of the first embodiment, description thereof is omitted (see FIGS. 1 to 7). Here, also in the present embodiment, the magnetic memory element MM is disposed on the laminated portion L1 of the domain wall motion layer WDL and the cap layer CL above the magnetic wall moving layer WDL, and on the upper portion of the central portion of the laminated portion L1. Since the MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL have the stacked portion L2 stacked in order from the bottom, the characteristics of the magnetic memory element MM can be improved. Specifically, as described in detail in Embodiment 1, the MR ratio can be improved. In addition, the write current value can be reduced.

[Product description]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 22 to 28 are cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. Note that the process for forming the selection transistor and the wiring over the selection transistor is the same as that in Embodiment 1, and thus detailed description thereof is omitted (see FIG. 8). Therefore, the process of forming the magnetic memory element will be described in detail with reference to FIGS.

  First, similarly to the first embodiment, two selection transistors (TR1, TR2) are formed on the main surface of the substrate S, and a plurality of selection transistors (IL1 to IL4) are formed on the upper surface thereof via interlayer insulating films (IL1 to IL4). Wirings (M1 to M3) are formed (see FIG. 8).

  Next, the magnetic memory element MM is formed on the interlayer insulating film IL4 in which the plug P4 is embedded.

  First, as shown in FIG. 22, the hard layers HL1 and HL2 are formed on the interlayer insulating film IL4 in which the plug P4 is embedded. As in the case of the first embodiment, the hard layers HL1 and HL2 can be formed by etching the ferromagnetic film using the hard mask HM1 as a mask.

  Next, as shown in FIG. 23, in the same manner as in the first embodiment, an interlayer insulating film IL5 is formed on the hard layers HL1 and HL2, and the interlayer insulating film IL5 is formed by using a CMP method, an etch back method, or the like. The surface portion is removed until the surfaces of the hard layers HL1 and HL2 are exposed. Thereby, the hard layers HL1 and HL2 are embedded in the interlayer insulating film IL5, and the surfaces of the hard layers HL1 and HL2 are exposed from the surface of the interlayer insulating film IL5.

  Next, as shown in FIG. 24, the domain wall motion layer WDL, the cap layer CL, the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL are formed on the interlayer insulating film IL5 in which the hard layers HL1 and HL2 are embedded. Forming in order from the side, a five-layer film is formed. For example, a ferromagnetic film is deposited as the domain wall motion layer WDL on the hard layers HL1 and HL2 and the interlayer insulating film IL5 by sputtering or the like. Next, a conductive film is deposited as a cap layer CL on the ferromagnetic film by a sputtering method or the like. Next, a ferromagnetic film is deposited as a magnetization switching layer MRL on the conductive film by a sputtering method or the like. Next, an insulating film is deposited as a tunnel barrier layer TBL on the ferromagnetic film by a CVD method, a sputtering method, or the like. Next, for example, a ferromagnetic film is deposited on the insulating film as the magnetization fixed layer MFL by a sputtering method or the like. As the material of each of these five layers, the materials described in the “magnetic memory element” column of the first embodiment can be used.

  Next, an insulating film such as a silicon oxide film is formed as a hard mask HM22 on the magnetization fixed layer MFL by a CVD method. This insulating film (hard mask HM22) is left in the regions 1B, 1A, and 2B by patterning. Next, as shown in FIG. 25, using the hard mask HM2 as a mask, the five-layered film composed of the domain wall motion layer WDL, the cap layer CL, the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched. Thus, the laminated portion L1 made of these layers is formed. Note that the hard mask HM22 may be formed of a laminated film of a silicon nitride film and a silicon oxide film thereabove.

  Next, after removing the hard mask HM22, an interlayer insulating film IL6 is formed on the stacked portion L1. For example, an insulating film such as a silicon oxide film is deposited as the interlayer insulating film IL6 on the stacked portion L1 and the interlayer insulating film IL5 by a CVD method or the like. Next, the surface portion of the interlayer insulating film IL6 is removed using a CMP method, an etch back method, or the like until the surface of the magnetization fixed layer MFL is exposed (FIG. 26).

  Next, an insulating film such as a silicon oxide film is formed as a hard mask HM23 on the magnetization fixed layer MFL and the interlayer insulating film IL6 by a CVD method. This insulating film (hard mask HM23) is patterned to remain in the center of the region 1A (FIG. 27).

  Next, as shown in FIG. 28, by using the hard mask HM23 as a mask, the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL are etched to form a stacked portion L2 made of these layers. By this step, the laminated portion L2 composed of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is formed, and the laminated portion L1 composed of the domain wall motion layer WDL and the cap layer CL remains below the laminated portion L2. Note that the hard mask HM23 may be formed of a stacked film of a silicon nitride film and a silicon oxide film thereabove.

  Next, after removing the hard mask HM23, an interlayer insulating film IL7 is formed on the stacked portion L2 (see FIG. 3). For example, an insulating film such as a silicon oxide film is deposited as the interlayer insulating film IL7 on the stacked portions L1 and L2 and the interlayer insulating film IL6 by a CVD method or the like. Thereafter, a plug (not shown) and a wiring (not shown) are formed on the magnetization fixed layer MFL of the stacked portion L2.

  Through the above steps, the selection transistors (TR1, TR2) and the magnetic memory element MM electrically connected thereto via the plugs (P1 to P4) and the wirings (M1 to M3) can be formed. (See FIG. 3).

  Here, also in the present embodiment, the cap layer CL is used as an etching stopper when the laminated film of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched when forming the laminated portion L2. Therefore, as described in detail in Embodiment 1, the characteristics of the magnetic memory element can be improved.

(Embodiment 3)
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings. In the first embodiment, the laminated film of the domain wall motion layer WDL and the cap layer CL is etched to form the laminated portion L1, and then the laminated film of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched. The laminated portion L2 is formed. On the other hand, in the present embodiment, after forming the five-layered film as in the second embodiment, first, the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL are etched, Thereafter, the domain wall motion layer WDL and the cap layer CL are etched.

[Description of structure]
Since the configuration of the semiconductor device (magnetic memory element, selection transistor, etc.) of the present embodiment is the same as that of the first embodiment, description thereof is omitted (see FIGS. 1 to 7). Here, also in the present embodiment, the magnetic memory element MM is disposed on the laminated portion L1 of the domain wall motion layer WDL and the cap layer CL above the magnetic wall moving layer WDL, and on the upper portion of the central portion of the laminated portion L1. Since the MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL have the stacked portion L2 stacked in order from the bottom, the characteristics of the magnetic memory element MM can be improved. Specifically, as described in detail in Embodiment 1, the MR ratio can be improved. In addition, the write current value can be reduced.

[Product description]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 29 to 36 are cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. Note that the process for forming the selection transistor and the wiring over the selection transistor is the same as that in Embodiment 1, and thus detailed description thereof is omitted (see FIG. 8). Therefore, the process of forming the magnetic memory element will be described in detail with reference to FIGS.

  First, similarly to the first embodiment, two selection transistors (TR1, TR2) are formed on the main surface of the substrate S, and a plurality of selection transistors (IL1 to IL4) are formed on the upper surface thereof via interlayer insulating films (IL1 to IL4). Wirings (M1 to M3) are formed (see FIG. 8).

  Next, the magnetic memory element MM is formed on the interlayer insulating film IL4 in which the plug P4 is embedded.

  First, as shown in FIG. 29, hard layers HL1 and HL2 are formed on the interlayer insulating film IL4 in which the plug P4 is embedded. As in the case of the first embodiment, the hard layers HL1 and HL2 can be formed by etching the ferromagnetic film using the hard mask HM1 as a mask.

  Next, as shown in FIG. 30, an interlayer insulating film IL5 is formed on the hard layers HL1 and HL2 in the same manner as in the first embodiment, and the interlayer insulating film IL5 is formed using a CMP method, an etch back method, or the like. The surface portion is removed until the surfaces of the hard layers HL1 and HL2 are exposed. Thereby, the hard layers HL1 and HL2 are embedded in the interlayer insulating film IL5, and the surfaces of the hard layers HL1 and HL2 are exposed from the surface of the interlayer insulating film IL5.

  Next, as shown in FIG. 31, the domain wall motion layer WDL, the cap layer CL, the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL are formed on the interlayer insulating film IL5 in which the hard layers HL1 and HL2 are embedded. Forming in order from the side, a five-layer film is formed. For example, a ferromagnetic film is deposited as the domain wall motion layer WDL on the hard layers HL1 and HL2 and the interlayer insulating film IL5 by sputtering or the like. Next, a conductive film is deposited as a cap layer CL on the ferromagnetic film by a sputtering method or the like. Next, a ferromagnetic film is deposited as a magnetization switching layer MRL on the conductive film by a sputtering method or the like. Next, an insulating film is deposited as a tunnel barrier layer TBL on the ferromagnetic film by a CVD method, a sputtering method, or the like. Next, for example, a ferromagnetic film is deposited on the insulating film as the magnetization fixed layer MFL by a sputtering method or the like. As the material of each of these five layers, the materials described in the “magnetic memory element” column of the first embodiment can be used.

  Next, an insulating film such as a silicon oxide film is formed on the magnetization fixed layer MFL as a hard mask HM32 by a CVD method. This insulating film (hard mask HM32) is patterned to remain in the center of the region 1A. Next, as shown in FIG. 32, by using the hard mask HM32 as a mask, the top three layers of the magnetization reversal layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL are etched to form a stacked layer composed of these layers. Part L2 is formed. Note that the hard mask HM32 may be formed of a stacked film of a silicon nitride film and a silicon oxide film thereabove.

  Next, after removing the hard mask HM32, as shown in FIG. 33, an insulating film such as a silicon oxide film is formed as a hard mask HM33 on the stacked portion L2 and the cap layer CL by the CVD method. This insulating film (hard mask HM33) is patterned to remain in the regions 1B, 1A, and 2B (FIG. 34). Next, as shown in FIG. 35, by using the hard mask HM33 as a mask, the laminated film of the domain wall motion layer WDL and the cap layer CL is etched to form a laminated portion L1 composed of these layers. Note that the hard mask HM33 may be formed of a stacked film of a silicon nitride film and a silicon oxide film thereabove.

  Next, after removing the hard mask HM33, an interlayer insulating film IL36 is formed on the interlayer insulating film IL5 and the stacked portions L1 and L2, as shown in FIG. For example, an insulating film such as a silicon oxide film is deposited as the interlayer insulating film IL36 on the interlayer insulating film IL5 and the stacked portions L1 and L2 by a CVD method or the like. The interlayer insulating film IL36 corresponds to the interlayer insulating films IL6 and IL7 in FIG. Thereafter, a plug (not shown) and a wiring (not shown) are formed on the magnetization fixed layer MFL of the stacked portion L2.

  Through the above steps, the selection transistors (TR1, TR2) and the magnetic memory element MM electrically connected thereto via the plugs (P1 to P4) and the wirings (M1 to M3) can be formed. (See FIG. 3).

  Here, also in the present embodiment, the cap layer CL is used as an etching stopper when the laminated film of the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL is etched when forming the laminated portion L2. Therefore, as described in detail in Embodiment 1, the characteristics of the magnetic memory element can be improved.

  In addition, since the film to be etched is formed on the entire surface of the substrate S during the etching of the magnetization switching layer MRL (laminated portion L2), the change in the signal waveform for detecting the etching end point (S / N ratio) (Also called) increases. This improves the controllability of etching.

(Embodiment 4)
Hereinafter, the semiconductor device of the present embodiment will be described in detail with reference to the drawings. In the first to third embodiments, the stacked portion L1 and the stacked portion L2 are formed on the hard layers HL1 and HL2. However, the stacked portion L1 is formed on the stacked portion L2, and the hard layers HL1 and HL2 are further formed. It may be formed.

[Description of structure]
FIG. 37 is a cross-sectional view showing the magnetic memory element of the semiconductor device of the present embodiment. The magnetic memory element MM of the present embodiment has a stacked portion L1 of a domain wall motion layer WDL and a cap layer CL below it. A laminated part L2 in which a magnetization switching layer MRL, a tunnel barrier layer TBL, and a magnetization fixed layer MFL are arranged in order from the top is arranged below the central part of the laminated part L1. Hard layers HL1 and HL2 are arranged on the upper ends of both ends of the laminated portion L1, respectively. A magnetic tunnel junction is formed by the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL of the stacked portion L2.

  As described above, the magnetic memory element MM of the present embodiment has a configuration in which the magnetic memory element of the first embodiment (FIG. 1) is turned upside down.

  The magnetic memory element MM of the present embodiment is also connected in series between the two selection transistors (TR1, TR2) (see FIG. 4). Also in this case, as shown in FIG. 4, the magnetic memory element MM has three terminals (terminal a, terminal b, and terminal c). The terminal c is connected to the ground potential line GNL, the terminal a is connected to the bit line BL1 via the selection transistor TR1, and the terminal b is connected to the bit line BL2 via the selection transistor TR2. The terminal a corresponds to the hard layer HL1, and the terminal b corresponds to the hard layer HL2. The terminal c corresponds to the magnetization fixed layer MFL.

  Note that as the materials of the domain wall motion layer WDL, the cap layer CL, the magnetization switching layer MRL, the tunnel barrier layer TBL, and the magnetization fixed layer MFL, the materials described in the “magnetic memory element” column of the first embodiment are used. it can. The magnetic memory element operation (write operation, read operation) of the present embodiment is the same as that of the first embodiment.

  Here, also in the present embodiment, the magnetic memory element MM is disposed at the lower portion of the laminated portion L1 of the domain wall motion layer WDL and the cap layer CL, and the central portion of the laminated portion L1, and includes the magnetization switching layer MRL, the tunnel Since the configuration includes the stacked portion L2 including the barrier layer TBL and the magnetization fixed layer MFL, the characteristics of the magnetic memory element MM can be improved. Specifically, as described in detail in Embodiment 1, the MR ratio can be improved. In addition, the write current value can be reduced.

[Product description]
Next, a method for manufacturing the semiconductor device of this embodiment will be described. Although there is no limitation on the method for manufacturing the semiconductor device of the present embodiment, the semiconductor device of the present embodiment can be formed by the following method, for example.

  First, similarly to the first embodiment, two selection transistors (TR1, TR2) are formed on the main surface of the substrate S, and a plurality of selection transistors (IL1 to IL4) are formed on the upper surface thereof via interlayer insulating films (IL1 to IL4). Wirings (M1 to M3) are formed (see FIG. 8).

  Next, the magnetic memory element MM is formed on the interlayer insulating film IL4 in which the plug P4 is embedded.

  First, the stacked portion L2 is formed on the interlayer insulating film IL4 in which the plug P4 is embedded. For example, the magnetization fixed layer MFL, the tunnel barrier layer TBL, and the magnetization switching layer MRL are formed in this order from the lower side on the interlayer insulating film IL4 in which the plug P4 is embedded, thereby forming a three-layered film. Next, a hard mask (not shown) is formed in the central portion of the region 1A, and the three-layer laminated film is etched using the hard mask as a mask. Thereby, the laminated portion L2 can be formed.

  Next, after removing the hard mask, an interlayer insulating film IL15 made of a silicon oxide film or the like is formed on the interlayer insulating film IL4 and the stacked portion L2. Thereafter, the surface portion of the interlayer insulating film IL15 is removed using a CMP method, an etch back method, or the like until the surface of the stacked portion L2 is exposed.

  Next, the stacked portion L1 is formed on the interlayer insulating film IL15 in which the stacked portion L2 is embedded. For example, the cap layer CL and the domain wall motion layer WDL are sequentially formed from the lower side on the interlayer insulating film IL15 in which the stacked portion L1 is embedded, thereby forming a two-layered film. Next, a hard mask (not shown) is formed in the regions 1A, 1B, and 2B, and the two-layer laminated film is etched using the hard mask as a mask. Thereby, the laminated portion L1 can be formed.

  Next, after removing the hard mask, an interlayer insulating film IL16 made of a silicon oxide film or the like is formed over the interlayer insulating film IL15 and the stacked portion L1. Thereafter, the surface portion of the interlayer insulating film IL16 is removed using a CMP method, an etch back method, or the like until the surface of the stacked portion L1 is exposed.

  Next, hard layers HL1 and HL2 are formed on the interlayer insulating film IL16 in which the stacked portion L1 is embedded. For example, a ferromagnetic film is deposited by sputtering or the like on the interlayer insulating film IL16 in which the stacked portion L1 is embedded. Next, a hard mask (not shown) is formed in the regions 1B and 2B on the ferromagnetic film, and the ferromagnetic film is etched using the hard mask as a mask. Thereby, the hard layers HL1 and HL2 can be formed.

  Next, after removing the hard mask, an interlayer insulating film IL17 made of a silicon oxide film or the like is formed on the interlayer insulating film IL16 and the hard layers HL1 and HL2. Thereafter, the surface portion of the interlayer insulating film IL17 is removed using a CMP method, an etch back method, or the like until the surfaces of the hard layers HL1 and HL2 are exposed.

  Thereafter, after removing the hard mask, an interlayer insulating film IL18 is formed on the interlayer insulating film IL17 and the hard layers HL1 and HL2, and a plug P5 is formed in the interlayer insulating film IL18 on the hard layers HL1 and HL2. To do.

  Through the above steps, the selection transistors (TR1, TR2) and the magnetic memory element MM electrically connected thereto via the plugs (P1 to P4) and the wirings (M1 to M3) can be formed. (See FIG. 3).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1A region 1B region 2B region a terminal b terminal B1 boundary B2 boundary BL1 bit line BL2 bit line c terminal CL cap layer GE gate electrode GI gate insulating film GNL ground potential line HL1 hard layer HL2 hard layer HM1 hard mask HM2 hard mask HM22 hard Mask HM23 Hard mask HM3 Hard mask HM32 Hard mask HM33 Hard mask HM52 Hard mask HM53 Hard mask IL1 Interlayer insulating film IL2 Interlayer insulating film IL3 Interlayer insulating film IL4 Interlayer insulating film IL5 Interlayer insulating film IL6 Interlayer insulating film IL7 Interlayer insulating film IL15 Interlayer insulating Film IL16 Interlayer insulating film IL17 Interlayer insulating film IL18 Interlayer insulating film IL36 Interlayer insulating film L0 Laminating portion L1 Laminating portion L2 Laminating portion M1 Wiring M2 Wiring M3 Wiring MFL Magnetization fixed layer MM Magnetic memory element MRL Magnetization reversal layer P1 Plug P2 Plug P3 Plug P4 Plug P5 Plug PW p-type well R0 Resistor R1 Resistor RC Current path S Substrate SD Source, drain region STI Element isolation region SW Side wall film TBL Tunnel barrier layer TR1 Select transistor TR2 Select Transistor WC current path WDL domain wall motion layer WL word line

Claims (20)

A semiconductor device having a magnetic memory element,
The magnetic memory element is:
A first region, and a second region and a third region located on both sides of the first region, each including a first ferromagnetic film and a nonmagnetic conductive film formed on the first ferromagnetic film A first laminated portion having:
A second ferromagnetic film; an insulating film formed on the second ferromagnetic film; and a third ferromagnetic film formed on the insulating film; A second stacked portion disposed on one region;
A fourth ferromagnetic film disposed under the second region of the first stacked unit;
A fifth ferromagnetic film disposed under the third region of the first stacked unit;
Have
The first to fifth ferromagnetic films are semiconductor devices having perpendicular magnetic anisotropy. The semiconductor device according to claim 1,
The first stacked portion is arranged to extend in the first direction,
The second stacked unit is a semiconductor device arranged to extend in a second direction intersecting the first direction. The semiconductor device according to claim 1,
The magnetization direction of the first ferromagnetic film in the second region is fixed to the first magnetization direction by the fourth ferromagnetic film,
The first ferromagnetic film in the third region is fixed in a second magnetization direction antiparallel to the first magnetization direction by the fifth ferromagnetic film,
The semiconductor device, wherein the first ferromagnetic film in the first region has reversible magnetization. The semiconductor device according to claim 1,
The semiconductor device, wherein the magnetization direction of the second ferromagnetic film is the same as the magnetization direction of the first ferromagnetic film in the first region. The semiconductor device according to claim 1,
The first ferromagnetic film has a write current smaller than that of the second ferromagnetic film. The semiconductor device according to claim 1,
The second ferromagnetic film has a smaller coercive force than the first ferromagnetic film. The semiconductor device according to claim 1,
A semiconductor device that changes the magnetization direction of the first region of the first ferromagnetic film by causing a current to flow from the fourth ferromagnetic film to the fifth ferromagnetic film via the first ferromagnetic film. The semiconductor device according to claim 1,
The resistance of the first ferromagnetic film is determined by the resistance between the third ferromagnetic film and the fourth ferromagnetic film or the resistance between the third ferromagnetic film and the fifth ferromagnetic film. A semiconductor device for determining the magnetization direction of one region. The semiconductor device according to claim 1,
The magnetic memory element is formed above a semiconductor substrate,
A semiconductor device, wherein a field effect transistor electrically connected to the magnetic memory element is formed on the semiconductor substrate. The semiconductor device according to claim 9.
A first field effect transistor and a second field effect transistor on the semiconductor substrate;
The first field effect transistor is electrically connected to the fourth ferromagnetic film,
The second field effect transistor is a semiconductor device electrically connected to the fifth ferromagnetic film. A semiconductor device having a magnetic memory element,
The magnetic memory element is:
A first region, and a second region and a third region located on both sides of the first region, the first ferromagnetic film and a nonmagnetic conductive film formed under the first ferromagnetic film. A first laminated portion having:
A second ferromagnetic film; an insulating film formed under the second ferromagnetic film; and a third ferromagnetic film formed under the insulating film; A second laminate disposed below one region;
A fourth ferromagnetic film disposed on the second region of the first stacked unit;
A fifth ferromagnetic film disposed on the third region of the first stacked unit;
Have
The first to fifth ferromagnetic films are semiconductor devices having perpendicular magnetic anisotropy. A method of manufacturing a semiconductor device having a magnetic memory element,
(A) forming a laminated film of a first ferromagnetic film and a nonmagnetic conductive film on the first ferromagnetic film above the semiconductor substrate;
(B) a step of sequentially depositing a second ferromagnetic film, an insulating film, and a third ferromagnetic film on the laminated film;
(C) selectively etching the second ferromagnetic film, the insulating film, and the third ferromagnetic film until the nonmagnetic conductive film is exposed;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 12,
Before the step (a),
(D) forming a fourth ferromagnetic film and a fifth ferromagnetic film in the second region and the third region on both sides of the first region of the semiconductor substrate,
A method for manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 13,
A step of forming a field effect transistor on the main surface of the semiconductor substrate before the step (d);
A method for manufacturing a semiconductor device, comprising: 14. The method of manufacturing a semiconductor device according to claim 13,
Before the step (d), forming a first field effect transistor and a second field effect transistor on the main surface of the semiconductor substrate;
The first field effect transistor is electrically connected to the fourth ferromagnetic film,
The method of manufacturing a semiconductor device, wherein the second field effect transistor is electrically connected to the fifth ferromagnetic film. 14. The method of manufacturing a semiconductor device according to claim 13,
The step (a) is a step of leaving the stacked film in the first region, the second region, and the third region,
The step (c) is a method for manufacturing a semiconductor device, wherein the second ferromagnetic film, the insulating film, and the third ferromagnetic film are left in the first region. 14. The method of manufacturing a semiconductor device according to claim 13,
After the step (b) and before the step (c),
(E) etching the laminated film, the second ferromagnetic film, the insulating film, and the third ferromagnetic film to form the laminated film in the first region, the second region, and the third region; Leaving the second ferromagnetic film, the insulating film and the third ferromagnetic film;
Have
The step (c) is a method for manufacturing a semiconductor device, wherein the second ferromagnetic film, the insulating film, and the third ferromagnetic film are left in the first region. 14. The method of manufacturing a semiconductor device according to claim 13,
In the step (c), the second ferromagnetic film, the insulating film, and the third ferromagnetic film among the stacked film, the second ferromagnetic film, the insulating film, and the third ferromagnetic film are etched. This is a step of leaving the second ferromagnetic film, the insulating film, and the third ferromagnetic film in the first region,
After the step (c),
(F) leaving the laminated film in the first region, the second region, and the third region;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 16,
In the step (a), the laminated film is disposed so as to extend in the first direction,
In the step (c), the second ferromagnetic film, the insulating film, and the third ferromagnetic film are disposed so as to extend in a second direction intersecting the first direction. Method. In the manufacturing method of the semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, wherein the first ferromagnetic film has a write current smaller than that of the second ferromagnetic film.

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