JP2015032338A - Memory device and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device capable of increasing a reading speed, and suppressing the increase of power consumption.SOLUTION: A memory device includes read assist circuits (109, 110) for, when the read request of a first address and the read request of a second address are input, and when the row address of the first address is different from the row address of the second address, supplying a ground potential to the reference potential node of a memory cell corresponding to the first address and the reference potential node of the memory cell corresponding to the second address, and for, when the row address of the first address is the same as the row address of the second address, supplying a negative potential to the reference potential node of the memory cell corresponding to the first address and the reference potential node of the memory cell corresponding to the second address.

Description

  The present invention relates to a memory device and a control method thereof.

  2. Description of the Related Art A semiconductor memory device having a plurality of static memory cells arranged in a matrix and each accessible via a plurality of ports is known (for example, see Patent Document 1). The plurality of first power supply lines are arranged corresponding to each memory cell column, and each is coupled to the first power supply node of the memory cell in the corresponding column. The plurality of second power supply lines are arranged corresponding to each memory cell column, and each is coupled to the second power supply node of the memory cell in the corresponding column. The plurality of power supply control circuits are arranged corresponding to each column, and each sets the voltage level of the first and second power supply lines in the corresponding column in accordance with the operation mode and access port instruction information.

  In addition, a semiconductor device is known that can improve the read margin, prevent the reading speed from decreasing, and prevent the writing margin from decreasing (see, for example, Patent Document 2). The power supply voltage controller supplies the first power supply voltage and a second power supply voltage having a level lower than the first power supply voltage to the memory cell, and sets the level of the first power supply voltage when reading data from the memory cell Setting the level of the first power supply voltage higher when writing data to the memory cell, and setting the level of the second power supply voltage lower than the second power supply voltage when writing data to the memory cell. Do at least one of

  There is also known a semiconductor memory device having word lines and bit lines arranged in a matrix and a plurality of memory cells arranged at intersections between the word lines and the bit lines (see, for example, Patent Document 3). . The row data holding power supply control circuit controls the potential of the row data holding power supply supplied to the memory cells arranged on the same bit line. Each of the plurality of memory cells has two inverter circuits that are cross-coupled and hold high data and low data in pairs. During the write operation, the row data holding power supply control circuit sets the potential of the row data holding power supply of the memory cell corresponding to the selected bit line to a potential higher than that of the row data holding power supply of the memory cell corresponding to the non-selected bit line. To control.

JP 2008-47180 A JP 2010-287287 A Japanese Patent Laid-Open No. 2007-193928

  In Patent Document 2, the first power supply voltage level is set higher than the first power supply voltage level when data is read from the memory cell, and the second power supply voltage is set. Is set to be lower than the second power supply voltage at the time of data writing to the memory cell. Thereby, it is possible to improve the read margin and prevent the reading speed from being lowered. However, there is a problem that power consumption increases due to this power supply voltage control.

  An object of the present invention is to provide a memory device and a control method thereof that can increase the reading speed and suppress an increase in power consumption.

  The memory device is arranged in a matrix and is provided for each of a plurality of memory cells for storing data and for each column of the plurality of memory cells, and a plurality of first cells for inputting / outputting data to / from the memory cells. A bit line, provided for each column of the plurality of memory cells, a plurality of second bit lines for inputting / outputting data to / from the memory cells, and provided for each row of the plurality of memory cells; A plurality of first word lines connecting the memory cells to the first bit line; and a plurality of first word lines provided for each row of the plurality of memory cells and connecting the memory cells to the second bit line. Two word lines and a first address and a second address each including a row address and a column address are input, and the plurality of word lines are based on the row address of the first address. A decoder that supplies a voltage to one word line and supplies a voltage to the plurality of second word lines based on a row address of the second address; and a plurality of the plurality of pixels based on a column address of the first address. A column selector that selectively outputs data of the first bit line and selectively outputs data of the plurality of second bit lines based on a column address of the second address; When an address read request and a read request for the second address are input, if the row address of the first address is different from the row address of the second address, it corresponds to the first address. A ground potential is supplied to the reference potential node of the memory cell and the reference potential node of the memory cell corresponding to the second address, and the row address of the first address is supplied. If the second address and the row address of the second address are the same, a negative potential is supplied to the reference potential node of the memory cell corresponding to the first address and the reference potential node of the memory cell corresponding to the second address. A read assist circuit.

  When the row address is the same, a current flows from both the first and second bit lines to the reference potential node of the same memory cell. Therefore, by supplying a negative potential to the reference potential node of the memory cell, the read speed is increased. Can be fast. In addition, when the row address is different, no current flows from both the first and second bit lines to the reference potential node of the same memory cell, and the reading speed does not decrease, so the reference potential node of the memory cell By supplying a ground potential to the power supply, an increase in power consumption can be suppressed.

FIG. 1 is a block diagram illustrating a configuration example of the memory device according to the present embodiment. 2A and 2B are circuit diagrams illustrating a configuration example of a part of the memory device in FIG. 3A to 3C are diagrams illustrating operations of the read assist circuit and the write assist circuit. 4A to 4C are diagrams showing a read assist signal for the A port and a read assist signal for the B port. 5A and 5B are diagrams illustrating a configuration example of a circuit for generating a read assist signal in the address comparator. FIG. 6A is a diagram illustrating a configuration example of the boost control circuit, and FIG. 6B is a timing chart illustrating an operation example of the boost control circuit. FIG. 7 is a timing chart showing a read operation of the memory device. FIG. 8 is a timing chart showing the write operation of the memory device.

  FIG. 1 is a block diagram illustrating a configuration example of the memory device according to the present embodiment. The memory device is, for example, a 2-port static random access memory (SRAM). The two ports have an A port and a B port.

  The plurality of memory cells MC11 to MC32 are static memory cells, which are arranged in a matrix in the row direction and the column direction, and store data. Memory cells MC11 are arranged in the first row and the first column. The memory cells MC12 are arranged in the first row and the second column. Memory cells MC21 are arranged in the second row and the first column. The memory cell MC22 is arranged in the second row and the second column. The memory cell MC31 is arranged in the third row and the first column. The memory cells MC32 are arranged in the third row and the second column. For simplicity, an example of memory cells MC11 to MC32 of 3 rows and 2 columns is shown, but more memory cells are actually arranged.

  The reference potential nodes MVSS1 and MVSS2 of the memory cells in the same column among the memory cells MC11 to MC32 are connected to each other. The reference potential nodes MVSS1 of the memory cells MC11, MC21, MC31 in the first column are connected to each other. The reference potential nodes MVSS2 of the memory cells MC12, MC22, and MC32 in the second column are connected to each other.

  The plurality of first bit lines BLA1, BAX1, BLA2, and BAX2 are A-port bit lines and are provided for each column of the plurality of memory cells MC11 to MC32, and input / output data to / from the memory cells MC11 to MC32. can do. The bit lines BLA1 and BAX1 are connected to the memory cells MC11, MC21, MC31 in the first column, and mutually complementary data are input / output. The bit lines BLA2 and BAX2 are connected to the memory cells MC12, MC22, MC32 in the second column, and complementary data are input / output.

  The plurality of second bit lines BLB1, BLBX1, BLB2, and BLBX2 are bit lines of the B port and are provided for each column of the plurality of memory cells MC11 to MC32, and input / output data to / from the memory cells MC11 to MC32. can do. The bit lines BLB1 and BLBX1 are connected to the memory cells MC11, MC21, MC31 in the first column, and mutually complementary data are input / output. The bit lines BLB2 and BLBX2 are connected to the memory cells MC12, MC22, MC32 in the second column, and mutually complementary data are input / output.

  The plurality of first word lines WLA1, WLA2, and WLA3 are A port word lines and are provided for each row of the plurality of memory cells MC11 to MC32, and the memory cells MC11 to MC32 are respectively connected to the first bit lines BLA1, This is a line for connecting to BAX1, BLA2, and BAX2. The word line WLA1 is connected to the memory cells MC11 and MC12 in the first row. When the word line WLA1 is at a high level, the memory cell MC11 is connected to the bit lines BLA1 and BAX1, and the memory cell MC12 is connected to the bit lines BLA2 and BAX2. The word line WLA2 is connected to the memory cells MC21 and MC22 in the second row. When the word line WLA2 becomes high level, the memory cell MC21 is connected to the bit lines BLA1 and BAX1, and the memory cell MC22 is connected to the bit lines BLA2 and BAX2. The word line WLA3 is connected to the memory cells MC31 and MC32 in the third row. When the word line WLA3 goes high, the memory cell MC31 is connected to the bit lines BLA1 and BAX1, and the memory cell MC32 is connected to the bit lines BLA2 and BAX2.

  The plurality of second word lines WLB1, WLB2, and WLB3 are B port word lines and are provided for each row of the plurality of memory cells MC11 to MC32, and the memory cells MC11 to MC32 are connected to the second bit lines BLB1, BLB1, respectively. This is a line for connecting to BLBX1, BLB2, and BLBX2. The word line WLB1 is connected to the memory cells MC11 and MC12 in the first row. When the word line WLB1 becomes high level, the memory cell MC11 is connected to the bit lines BLB1 and BLBX1, and the memory cell MC12 is connected to the bit lines BLB2 and BLBX2. The word line WLB2 is connected to the memory cells MC21 and MC22 in the second row. When the word line WLB2 becomes high level, the memory cell MC21 is connected to the bit lines BLB1 and BLBX1, and the memory cell MC22 is connected to the bit lines BLB2 and BLBX2. The word line WLB3 is connected to the memory cells MC31 and MC32 in the third row. When the word line WLB3 becomes high level, the memory cell MC31 is connected to the bit lines BLB1 and BLBX1, and the memory cell MC32 is connected to the bit lines BLB2 and BLBX2.

  The decoder 101 inputs the clock signal CLK, the first write enable signal WEA, the second write enable signal WEB, the first address AA, the second address AB, the first word lines WLA1 to WLA3, and the second Voltage is supplied to the first word line WLB1 to WLB3, the first sense amplifier enable signal SAEA, the second sense amplifier enable signal SAEB, the first column address COLA, the second column address COLB, and the first write assist signal. WENA and the second write assist signal WENB are output.

  The first address AA is the address of the A port, the upper plural bits are row addresses, and the lower plural addresses are column addresses. The second address AB is an address of the B port, the upper plural bits are row addresses, and the lower plural addresses are column addresses. The first write enable signal WEA is an A port write enable signal, and the second write enable signal WEB is a B port write enable signal. In the write enable signals WEA and WEB, a high level indicates a write request, and a low level indicates a read request.

  The first sense amplifier enable signal SAEA is a sense amplifier enable signal for the A port, and is an enable signal for the first sense amplifier 104. The second sense amplifier enable signal SAEB is a B port sense amplifier enable signal and is an enable signal for the second sense amplifier 105. The first column address COLA is a column address of the A port, and is a column address of lower multiple bits of the first address AA. The second column address COLB is a column address of the B port, and is a column address of a plurality of lower bits of the second address AB. The first write assist signal WENA is a write assist signal for the A port, and becomes a high level pulse synchronized with the clock signal CLK when the first write enable signal WEA indicates a write request. The second write assist signal WENB is a B port write assist signal and becomes a high level pulse synchronized with the clock signal CLK when the second write enable signal WEB indicates a write request.

  The first word line WLA1 goes high when the row address of the first address AA indicates the first row. In this case, the memory cells MC11 and MC12 in the first row are connected to the first bit lines BLA1, BAX1, BLA2, and BAX2, respectively. The first word line WLA2 goes high when the row address of the first address AA indicates the second row. In this case, the memory cells MC21 and MC22 in the second row are connected to the first bit lines BLA1, BAX1, and BLA2, BAX2, respectively. The first word line WLA3 goes high when the row address of the first address AA indicates a third row. In this case, the memory cells MC31 and MC32 in the third row are connected to the first bit lines BLA1, BAX1, and BLA2, BAX2, respectively.

  The second word line WLB1 goes high when the row address of the second address AB indicates the first row. In that case, the memory cells MC11 and MC12 in the first row are connected to the second bit lines BLB1, BLBX1, and BLB2, BLBX2, respectively. The second word line WLB2 goes high when the row address of the second address AB indicates the second row. In that case, the memory cells MC21 and MC22 in the second row are connected to the second bit lines BLB1, BLBX1, and BLB2, BLBX2, respectively. The second word line WLB3 goes high when the row address of the second address AB indicates the third row. In that case, the memory cells MC31 and MC32 in the third row are connected to the second bit lines BLB1, BLBX1, and BLB2, BLBX2, respectively. As described above, the decoder 101 supplies a voltage to the plurality of first word lines WLA1 to WLA3 based on the row address of the first address AA, and the plurality of second addresses based on the row address of the second address AB. A voltage is supplied to the two word lines WLB1 to WLB3.

  First, the case where the first write enable signal WEA indicates a read request will be described. When the first word line WLA1 is at a high level, the data stored in the memory cell MC11 is output to the first bit lines BLA1 and BAX1, and the data stored in the memory cell MC12 is the first Are output to the bit lines BLA2 and BAX2. When the first word line WLA2 is at a high level, the data stored in the memory cell MC21 is output to the first bit lines BLA1 and BAX1, and the data stored in the memory cell MC22 is the first Are output to the bit lines BLA2 and BAX2. When the first word line WLA3 is at a high level, the data stored in the memory cell MC31 is output to the first bit lines BLA1 and BAX1, and the data stored in the memory cell MC32 is the first Are output to the bit lines BLA2 and BAX2.

  When the first column address COLA indicates the first column, the first column selector 102 selects the data of the first bit lines BLA1 and BAX1 and outputs the selected data to the first sense amplifier 104. Further, the first column selector 102 selects the data of the first bit lines BLA2 and BAX2 and outputs it to the first sense amplifier 104 when the first column address COLA indicates the second column. . The first sense amplifier 104 is activated when the first sense amplifier enable signal SAEA is at a high level, depending on the magnitude relationship between the first bit lines BLA1 and BAX1, or the magnitude relationship between the first bit lines BLA2 and BAX2. The first read data RDA of the A port is output. Note that the first sense amplifier enable signal SAEA is at a high level when the first write enable signal WEA indicates a read request.

  Next, a case where the second write enable signal WEB indicates a read request will be described. When the second word line WLB1 is at a high level, the data stored in the memory cell MC11 is output to the second bit lines BLB1 and BLBX1, and the data stored in the memory cell MC12 is the second To the bit lines BLB2 and BLBX2. When the second word line WLB2 is at a high level, the data stored in the memory cell MC21 is output to the second bit lines BLB1 and BLBX1, and the data stored in the memory cell MC22 is the second To the bit lines BLB2 and BLBX2. When the second word line WLB3 is at a high level, the data stored in the memory cell MC31 is output to the second bit lines BLB1 and BLBX1, and the data stored in the memory cell MC32 is the second To the bit lines BLB2 and BLBX2.

  When the second column address COLB indicates the first column, the second column selector 103 selects the data of the second bit lines BLB1 and BLBX1 and outputs the selected data to the second sense amplifier 105. Further, the second column selector 103 selects the data of the second bit lines BLB2 and BLBX2 and outputs the selected data to the second sense amplifier 105 when the second column address COLB indicates the second column. . The second sense amplifier 105 is activated when the second sense amplifier enable signal SAEB is at a high level, depending on the magnitude relationship between the second bit lines BLB1 and BLBX1 or the magnitude relationship between the second bit lines BLB2 and BLBX2. Then, the second read data RDB of the B port is output. The second sense amplifier enable signal SAEB is at a high level when the second write enable signal WEB indicates a read request.

  Next, a case where the first write enable signal WEA indicates a write request will be described. Similarly to the above, one of the first word lines WLA1 to WLA3 becomes high level in accordance with the row address of the first address AA. The read / write assist circuit 109 outputs the first write data of the A port to the first bit lines BLA1 and BAX1 when the first column address COLA indicates the first column. The data of the first bit lines BLA1 and BAX1 is written into the memory cell selected by one of the first word lines WLA1 to WLA3. When the first column address COLA indicates the second column, the read / write assist circuit 110 outputs the first write data of the A port to the first bit lines BLA2 and BAX2. The data of the first bit lines BLA2 and BAX2 are written into the memory cell selected by any one of the first word lines WLA1 to WLA3.

  Next, a case where the second write enable signal WEB indicates a write request will be described. Similarly to the above, one of the second word lines WLB1 to WLB3 becomes high level according to the row address of the second address AB. The read / write assist circuit 109 outputs the second write data of the B port to the second bit lines BLB1 and BLBX1 when the second column address COLB indicates the first column. The data of the second bit lines BLB1 and BLBX1 is written into the memory cell selected by any one of the second word lines WLB1 to WLB3. When the second column address COLB indicates the second column, the read / write assist circuit 110 outputs the second write data of the B port to the second bit lines BLB2 and BLBX2. The data of the second bit lines BLB2 and BLBX2 is written into the memory cell selected by any one of the second word lines WLB1 to WLB3.

  The address comparator 106 receives the clock signal CLK, the write enable signals WEA and WEB, and the addresses AA and AB, and according to the comparison result of the first address AA and the second address AB, the first read assist signal RENA and The second read assist signal RENB is output. The boost control circuit 107 receives the clock signal CLK, the write enable signals WEA and WEB, and the read assist signals RENA and RENB, and outputs the first boost signal BSTAX and the second boost signal BSTBX.

  The negative potential generation circuit 108 includes n-channel field effect transistors 111 and 112 and capacitors 113 and 114. N-channel field effect transistor 112 has a drain connected to node NVSSA, a gate connected to the node of boost signal BSTAX, and a source connected to the ground potential node. The capacitor 114 is connected between the drain and gate of the transistor 112. When the boost signal BSTAX becomes high level, the transistor 112 is turned on and the node NVSSA becomes the ground potential. Thereafter, when the boost signal BSTAX is set to the low level, the transistor 112 is turned off, and the node NVSSA coupled by the capacitor 114 becomes a negative potential.

  The n-channel field effect transistor 111 has a drain connected to the node NVSSB, a gate connected to the node of the boost signal BSTBX, and a source connected to the ground potential node. The capacitor 113 is connected between the drain and gate of the transistor 111. When the boost signal BSTBX goes high, the transistor 111 is turned on and the node NVSSB becomes the ground potential. After that, when the boost signal BSTBX is set to a low level, the transistor 111 is turned off and the node NVSSB coupled by the capacitor 113 becomes a negative potential.

  The read / write assist circuit 109 receives the read assist signals RENA and RENB, controls the potential of the reference potential node MVSS1 of the memory cells MC11, MC21, and MC31 in the first column, and bit lines BLA1, BLAX1, BLB1, BLBX1. To control the potential. The read assist circuit 109 supplies the ground potential to the reference potential node MVSS1 of the memory cells MC11, MC21, MC31 in the first column, thereby controlling the read speed of the memory cells MC11, MC21, MC31 to the normal speed. By using the negative potential of NVSSA or NVSSB to supply a negative potential to the reference potential node MVSS1 of the memory cells MC11, MC21, MC31 in the first column, the reading speed of the memory cells MC11, MC21, MC31 is increased. Can be controlled. The write assist circuit 109 can improve the write margin of the memory cells MC11, MC21, and MC31 by using the negative potential of the node NVSSA or NVSSB to supply a negative potential to the bit lines BLA1, BAX1, BLB1, or BLBX1. it can.

  The read / write assist circuit 110 receives the read assist signals RENA and RENB, controls the potential of the reference potential node MVSS2 of the memory cells MC12, MC22, MC32 in the second column, and the bit lines BLA1, BLAX1, BLB1, BLBX1. To control the potential. The read assist circuit 110 controls the read speed to the normal speed by supplying the ground potential to the reference potential node MVSS2 of the memory cells MC12, MC22, MC32 in the second column, and uses the negative potential of the node NVSSA or NVSSB. By supplying a negative potential to the reference potential node MVSS2 of the memory cells MC12, MC22, and MC32 in the second column, the reading speed of the memory cells MC12, MC22, and MC32 can be controlled to a high speed. The write assist circuit 110 can improve the write margin of the memory cells MC12, MC22, and MC32 by supplying a negative potential to the bit lines BLA2, BAX2, BLB2, or BLBX2 using the negative potential of the node NVSSA or NVSSB. it can.

  2A is a circuit diagram illustrating a configuration example of part of the memory device in FIG. Memory cell MC11 includes n-channel field effect transistors 221 to 226 and p-channel field effect transistors 227 and 228. The transistor 221 has a drain connected to the first bit line BLA1, a gate connected to the first word line WLA1, and a source connected to the node N1. The transistor 222 has a drain connected to the second bit line BLB1, a gate connected to the second word line WLB1, and a source connected to the node N1. The transistor 225 has a drain connected to the first bit line BAX1, a gate connected to the first word line WLA1, and a source connected to the node N2. The transistor 226 has a drain connected to the second bit line BLBX1, a gate connected to the second word line WLB1, and a source connected to the node N2. Transistor 227 has a source connected to the power supply potential node, a gate connected to node N2, and a drain connected to node N1. Transistor 228 has a source connected to the power supply potential node, a gate connected to node N1, and a drain connected to node N2. The transistor 223 has a drain connected to the node N1, a gate connected to the node N2, and a source connected to the reference potential node MVSS1. The transistor 224 has a drain connected to the node N2, a gate connected to the node N1, and a source connected to the reference potential node MVSS1. The memory cells MC12 to MC32 have the same configuration as the memory cell MC11.

  Transistors 227 and 223 are inverters, and output logically inverted data of the data of node N2 to node N1. Transistors 228 and 224 are inverters that output logically inverted data of the data at node N1 to node N2. Thereby, the memory cell MC11 can store complementary data in the nodes N1 and N2. The data stored in the nodes N1 and N2 are data logically inverted from each other.

  When the first word line WLA1 goes high, the transistors 221 and 225 are turned on, the node N1 is connected to the first bit line BLA1, and the node N2 is connected to the first bit line BAX1. When the second word line WLB1 becomes high level, the transistors 222 and 226 are turned on, the node N1 is connected to the second bit line BLB1, and the node N2 is connected to the second bit line BLBX1.

  The read assist circuit 201, the A port write assist circuit 211, and the B port write assist circuit 212 correspond to the read / write assist circuit 109 of FIG. The read assist circuit 202, the A port write assist circuit 213, and the B port write assist circuit 214 correspond to the read / write assist circuit 110 of FIG.

  In recent years, low power consumption of memory devices has been demanded. In order to reduce the power consumption of the memory device, it is important to reduce the voltage of the memory device. However, when the power supply voltage is lowered, the influence of random variations of transistors increases, and the operation margin of the memory device decreases. In particular, when the power supply voltage is low, the write margin of the memory device decreases, a write failure occurs, and the read speed decreases.

  The read assist circuit 201 supplies the ground potential to the reference potential node MVSS1 of the memory cells MC11MC21 and MC31 of the first column when the read request of the first column is requested, thereby increasing the read speed of the memory cells MC11, MC21, and MC31. Normal speed can be achieved. On the other hand, the read assist circuit 201 supplies a negative potential to the reference potential node MVSS1 of the memory cells MC11, MC21, MC31 of the first column at the time of a read request for the first column, thereby causing an n-channel field effect transistor. The driving capability of 221 to 226 can be increased, and the reading speed of the memory cells MC11, MC21, MC31 can be increased.

  Similarly, the read assist circuit 202 supplies a ground potential to the reference potential node MVSS2 of the memory cells MC12, MC22, and MC32 of the second column when a read request for the second column is requested, thereby causing the memory cells MC12, MC22, The reading speed of the MC 32 can be set to the normal speed. On the other hand, the read assist circuit 202 supplies a negative potential to the reference potential node MVSS2 of the memory cells MC12, MC22, MC32 of the second column at the time of a read request for the second column, whereby the memory cells MC12, MC22. , MC32 can be read at a high speed.

  The write assist circuit 211 of the A port has an n channel compared to the case where the ground potential is supplied by supplying a negative potential to the first bit line BLA1 or BAX1 at the time of a write request for the first column of the A port. The drive capability of the field effect transistor 221 or 225 can be increased, and the write margin of the memory cells MC11, MC21, MC31 can be improved.

  Similarly, the A port write assist circuit 213 supplies a negative potential to the first bit line BLA2 or BAX2 at the time of a write request for the second column of the A port, compared to a case where a ground potential is supplied. The write margin of the memory cells MC12, MC22, MC32 can be improved.

  The B port write assist circuit 212 supplies a negative potential to the second bit line BLB1 or BLBX1 at the time of a write request for the first column of the B port, so that an n channel is provided. The driving capability of the field effect transistor 222 or 226 can be increased, and the write margin of the memory cells MC11, MC21, MC31 can be improved.

  Similarly, the B port write assist circuit 214 supplies a negative potential to the second bit line BLB2 or BLBX2 at the time of a write request for the second column of the B port, compared to a case where a ground potential is supplied. The write margin of the memory cells MC12, MC22, MC32 can be improved.

  Next, the worst case of the read operation of the memory device will be described. The worst case is when the read row address of the A port and the read row address of the B port are the same. For example, the A port reads the memory cell MC11 and the B port reads the memory cell MC12. In this case, the first word line WLA1 is set to the high level by the first address AA of the A port, and the second word line WLB1 is set to the high level by the second address AB of the B port. Then, the transistors 211, 222, 225, and 226 in the memory cells MC11 and MC12 are simultaneously turned on. For example, when the node N2 is at a high level, the transistor 223 is turned on. In that case, a current flowing from the first bit line BLA1 to the reference potential node MVSS1 via the transistors 221 and 223 and a current flowing from the second bit line BLB1 to the reference potential node MVSS1 via the transistors 222 and 223 are generated. Therefore, the transition speed from the high level to the low level of the bit lines BLA1 and BLB1 becomes slow, and the reading speed becomes slow. In this case, the read assist circuits 201 and 202 increase the read speed by setting the reference potential nodes MVSS1 and MVSS2 to a negative potential.

  On the other hand, when the read row address of the A port and the read row address of the B port are different, there is no decrease in read speed. For example, the A port reads the memory cell MC11 and the B port reads the memory cell MC22. In this case, the first word line WLA1 is set to the high level by the first address AA of the A port, and the second word line WLB2 is set to the high level by the second address AB of the B port. Then, the word line WLA1 is at a high level, but the word line WLB1 is at a low level, so that the transistor 221 is turned on and the transistor 222 is turned off. As a result, there is no decrease in reading speed. In this case, since it is not necessary to increase the reading speed, the read assist circuits 201 and 202 set the reference potential nodes MVSS1 and MVSS2 to the ground potential. In this case, the read assist circuits 201 and 202 can further increase the reading speed by setting the reference potential nodes MVSS1 and MVSS2 to a negative potential. However, when the read assist circuits 201 and 202 make the reference potential nodes MVSS1 and MVSS2 negative potentials, the power consumption increases. Therefore, in this case, the read assist circuits 201 and 202 can reduce power consumption by setting the reference potential nodes MVSS1 and MVSS2 to the ground potential.

  Further, when the write column address of the A port and the read column address of the B port are the same, there is a problem that the write margin of the A port is deteriorated. For example, in the A port, the memory cell MC11 is written, and in the B port, the memory cell MC21 is read. In this case, as described above, the read assist circuit 201 can set the reference potential node MVSS1 of the memory cell MC21 to a negative potential in order to read the memory cell MC21 at high speed. However, since the reference potential node MVSS1 of the memory cells MC11 and MC21 in the same column is connected to each other, the reference potential node MVSS1 of the memory cell MC11 also becomes a negative potential. For example, when the node N2 is at a high level, the transistor 223 is turned on, and the node N1 and the gate of the transistor 228 are at a negative potential, so that the operation margin of the memory cell MC11 deteriorates and a write error occurs. There is a case. Similarly, when the node N1 is at a high level, the transistor 224 is turned on and the node N2 and the gate of the transistor 227 are at a negative potential, so that the operation margin of the memory cell MC11 deteriorates and a write error occurs. There is a case. In this case, as described above, the memory cell MC21 does not have a decrease in reading speed, and it is not necessary to increase the reading speed. Therefore, in this case, the read assist circuit 201 sets the reference potential node MVSS1 of the memory cell MC21 to the ground potential node. Thereby, it is possible to prevent the write margin of the memory cell MC11 from deteriorating and a write error.

  FIG. 3A is a diagram showing operations of the read assist circuits 201 and 202 and the write assist circuits 211 to 214 when accessing different row addresses in the A port and the B port.

  First, the case where the A port performs a write operation and the B port performs a write operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  Next, the case where the A port performs a read operation and the B port performs a write operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. The non-selected column of the A port excludes the selected column of the B port. The same applies hereinafter. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. Note that the non-selected column of the B port excludes the selected column of the A port. The same applies hereinafter.

  Next, a case where the A port is a write operation and the B port is a read operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  Next, the case where the A port performs a read operation and the B port performs a read operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  As described above, the read assist circuits 201 and 202 correspond to the first address AA when the row address of the first address AA of the A port is different from the row address of the second address AB of the B port. A ground potential is supplied to the reference potential node MVSS1 or MVSS2 of the memory cell and the reference potential node MVSS1 or MVSS2 of the memory cell corresponding to the second address AB. In this case, as described above, since the reading speed is not reduced, the read assist circuits 201 and 202 can reduce the power consumption by supplying the ground potential to the reference potential node MVSS1 or MVSS2. Thereby, as described above, it is possible to prevent the deterioration of the write margin and the write error.

  FIG. 3B is a diagram illustrating operations of the read assist circuits 201 and 202 and the write assist circuits 211 to 214 when accessing the same row address and different column addresses in the A port and the B port.

  First, the case where the A port performs a write operation and the B port performs a write operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. The non-selected column of the A port excludes the selected column of the B port. The same applies hereinafter. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. Note that the non-selected column of the B port excludes the selected column of the A port. The same applies hereinafter.

  Next, the case where the A port performs a read operation and the B port performs a write operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies a negative potential to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  Next, a case where the A port is a write operation and the B port is a read operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies a negative potential to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  Next, the case where the A port performs a read operation and the B port performs a read operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies a negative potential to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies a negative potential to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  As described above, in the read assist circuits 201 and 202, when the read row addresses of the A port and the B port are the same and the read column addresses are different, the reference potential node of the memory cell corresponding to the first address AA. A negative potential is supplied to the reference potential node MVSS1 or MVSS2 of the memory cell corresponding to MVSS1 or MVSS2 and the second address AB. Thereby, the reading speed can be increased.

  The write assist circuits 211 to 214 supply a negative potential to the bit line of the selected column for the write operation. At this time, the read assist circuits 201 and 202 set the reference potential node MVSS1 or MVSS2 of the selected column of the write operation to the ground potential (0 V). As a result, deterioration of the write margin and write error can be prevented.

  FIG. 3C is a diagram illustrating operations of the read assist circuits 201 and 202 and the write assist circuits 211 to 214 when accessing the same row address and the same column address in the A port and the B port. Here, simultaneous write operations on both the A port and the B port are prohibited.

  First, the case where the A port performs a read operation and the B port performs a write operation will be described. In this case, it is specified that only the write operation is guaranteed and the read operation is not guaranteed. Since the read operation is not guaranteed in the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. Thereby, power consumption can be reduced. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  Next, a case where the A port is a write operation and the B port is a read operation will be described. In this case, it is specified that only the write operation is guaranteed and the read operation is not guaranteed. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2, and the write assist circuits 211 to 214 apply a negative potential to the bit line. Supply. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. Since the read operation is not guaranteed in the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. Thereby, power consumption can be reduced. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  Next, the case where the A port performs a read operation and the B port performs a read operation will be described. In the column selected by the column address of the A port, the read assist circuit 201 or 202 supplies a negative potential to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the A port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2. In the column selected by the column address of the B port, the read assist circuit 201 or 202 supplies a negative potential to the reference potential node MVSS1 or MVSS2. In a column not selected by the column address of the B port, the read assist circuit 201 or 202 supplies the ground potential (0 V) to the reference potential node MVSS1 or MVSS2.

  FIG. 4A corresponds to FIG. 3A and shows a read assist signal RENA for the A port and a read assist signal RENB for the B port. Since all the reference potential nodes MVSS (MVSS1 or MVSS2) in the selected column of the A port in FIG. 3A are 0V, all the read assist signals RENA of the A port in FIG. Further, since all the reference potential nodes MVSS (MVSS1 or MVSS2) in the selection column of the B port in FIG. 3A are 0V, the read assist signals RENB in the B port in FIG. .

  FIG. 4B corresponds to FIG. 3B and shows a read assist signal RENA for the A port and a read assist signal RENB for the B port. When the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the A port in FIG. 3B is 0V, the read assist signal RENA of the A port in FIG. On the other hand, when the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the A port in FIG. 3B is a negative potential, the read assist signal RENA of the A port in FIG. H. When the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the B port in FIG. 3B is 0V, the read assist signal RENB of the B port in FIG. . On the other hand, when the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the B port in FIG. 3B is a negative potential, the read assist signal RENB of the B port in FIG. H.

  FIG. 4C corresponds to FIG. 3C and shows a read assist signal RENA for the A port and a read assist signal RENB for the B port. When the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the A port in FIG. 3C is 0V, the read assist signal RENA of the A port in FIG. On the other hand, when the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the A port in FIG. 3C is a negative potential, the read assist signal RENA of the A port in FIG. H. When the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the B port in FIG. 3C is 0V, the read assist signal RENB of the B port in FIG. . On the other hand, when the reference potential node MVSS (MVSS1 or MVSS2) of the selected column of the B port in FIG. 3C is a negative potential, the read assist signal RENB of the B port in FIG. H.

  However, when both the lowermost A port and B port in FIG. 4C are in the read operation, the same memory cell is read, so the negative potential of the node NVSSA and the node NVSSB in FIG. Need not be supplied to the same node MVSS1. In order to reduce power consumption, it is preferable to supply only one of the negative potentials to the node MVSS1. Therefore, the read assist signal RENA is set to the high level H, and the read assist signal RENB is set to the low level L. Accordingly, the transistor 236 is turned on and the transistor 237 is turned off, so that only the negative potential of the node NVSSA is supplied to the node MVSS1. Note that the read assist signal RENA may be set to the low level L and the read assist signal RENB may be set to the high level H.

  The address comparator 106 in FIG. 1 includes a circuit that generates the read assist signal RENA in FIG. 5A and a circuit that generates the read assist signal RENB in FIG. 5B.

  FIG. 5A is a diagram illustrating a configuration example of a circuit for generating the read assist signal RENA in FIGS. 4A to 4C in the address comparator 106. The first address AA of the A port has lower n + 1 bit column addresses AA <0> to AA <n> and upper m bit row addresses AA <n + 1> to AA <n + m>. The second address AB of the B port has lower n + 1 bit column addresses AB <0> to AB <n> and upper m bit row addresses AB <n + 1> to AB <n + m>.

  The n + 1 negative exclusive OR circuits 501 respectively perform exclusive OR logic of the A port column addresses AA <0> to AA <n> and the B port column addresses AB <0> to AB <n>. Output the inverted value bit by bit. The negative exclusive OR circuit 501 outputs 1 when the two input values are the same, and outputs 0 when they are different. A logical product (AND) circuit 503 outputs a logical product of output values of n + 1 negative exclusive OR circuits 501. That is, the AND circuit 503 outputs 1 when the column addresses AA <0> to AA <n> of the A port and the column addresses AB <0> to AB <n> of the B port are the same, and when they are different. Outputs 0. A negative logical product (NAND) circuit 505 outputs a negative logical product of the output value of the logical product circuit 503 and the write enable signal WEB.

  The m negative exclusive OR circuits 502 respectively perform exclusive OR logic of row addresses AA <n + 1> to AA <n + m> of the A port and row addresses AB <n + 1> to AB <n + m> of the B port. Output the inverted value bit by bit. The negative exclusive OR circuit 502 outputs 1 when the two input values are the same value, and outputs 0 when they are different. The logical product circuit 504 outputs a logical product of the output values of the m negative exclusive OR circuits 502. That is, the AND circuit 504 outputs 1 when the row address AA <n + 1> to AA <n + m> of the A port and the row address AB <n + 1> to AB <n + m> of the B port are the same, and when they are different Outputs 0. The AND circuit 506 outputs a logical product of the output value of the AND circuit 504 and the logical inversion value of the write enable signal WEA. The logical product circuit 507 outputs the logical product of the clock signal CLK, the output value of the logical product circuit 506, and the output value of the negative logical product circuit 505 as the read assist signal RENA. The address comparator 106 can generate the read assist signal RENA shown in FIGS. 4A to 4C by the circuit shown in FIG.

  FIG. 5B is a diagram illustrating a configuration example of a circuit for generating the read assist signal RENB in FIGS. 4A to 4C in the address comparator 106. Hereinafter, points where the circuit in FIG. 5B is different from the circuit in FIG. The logical product circuit 506 in FIG. 5B inputs a logical inversion value of the write enable signal WEB instead of a logical inversion value of the write enable signal WEA. Further, the NAND circuit 505 in FIG. 5B inputs a high-level power supply potential VDD indicating a value “1” instead of the write enable signal WEB. As a result, the read assist signal RENB is at a low level L in the lowermost stage of FIG. The address comparator 106 can generate the read assist signal RENB shown in FIGS. 4A to 4C by the circuit shown in FIG.

  6A is a diagram illustrating a configuration example of the boost control circuit 107 in FIG. 1, and FIG. 6B is a timing chart illustrating an operation example of the boost control circuit 107. The delay circuit 601 outputs a signal N11 obtained by delaying the clock signal CLK. The AND circuit 603 outputs a logical product signal N13 of the clock signal CLK and the signal N11. The AND circuit 602 outputs a logical product signal N12 of the read assist signal RENA and the clock signal CLK. The selector 604 selects the signal N13 when the write enable signal WEA is high level, selects the signal N12 when the write enable signal WEA is low level, and outputs the signal N14. Inverter 605 outputs a logic inversion signal of signal N14 as boost signal BSTAX. By lowering the boost signal BSTAX from the high level to the low level, the write assist circuits 211 to 214 can supply a negative potential to the bit line, thereby preventing a write margin deterioration and a write error.

  The boost control circuit 107 generates the boost signal BSTBX by a circuit similar to that shown in FIG. In this case, the boost signal BSTBX can be generated instead of the boost signal BSTAX by using the read assist signal RENB instead of the read assist signal RENA and using the write enable signal WEB instead of the write enable signal WEA.

  Next, the structure of the read assist circuit 201 in FIG. The negative logical product circuit 231 outputs a negative logical product signal of the read assist signal RENA and the column address signal COLA1. The column address signal COLA1 is at a high level when the column address of the first address AA indicates the first column, and is at a low level otherwise. The inverter 233 outputs a logical inversion signal of the output signal of the negative logical product circuit 231. The NAND circuit 232 outputs a NAND signal of the read assist signal RENB and the column address signal COLB1. The column address signal COLB1 becomes a high level when the column address of the second address AB indicates the first column, and becomes a low level otherwise. The inverter 234 outputs a logical inversion signal of the output signal of the NAND circuit 232.

  The n-channel field effect transistor 235 has a source connected to the ground potential node and a gate connected to the output node of the NAND circuit 232. The n-channel field effect transistor 238 has a source connected to the drain of the transistor 235, a gate connected to the output node of the NAND circuit 231, and a drain connected to the reference potential node MVSS1. The n-channel field effect transistor 236 has a source connected to the node NVSSA, a gate connected to the output node of the inverter 233, and a drain connected to the reference potential node MVSS1. The n-channel field effect transistor 237 has a source connected to the node NVSSB, a gate connected to the output node of the inverter 234, and a drain connected to the reference potential node MVSS1.

  As shown in FIGS. 3A to 3C and FIGS. 4A to 4C, when the read assist signal RENA or RENB is at the low level L, the transistors 236 and 237 are turned off and the transistor 235 is turned off. And 238 are turned on, and the ground potential node is connected to the reference potential node MVSS1. When the read assist signal RENA is at the high level H, the transistor 236 is turned on, and the negative potential node NVSSA is connected to the reference potential node MVSS1. When the read assist signal RENB is at the high level H, the transistor 237 is turned on, and the negative potential node NVSSB is connected to the reference potential node MVSS1. A negative potential is supplied to the nodes NVSSA and NVSSB by the negative potential generation circuit 108 of FIG. The read assist circuit 202 has the same configuration as the read assist circuit 201.

  FIG. 2B is a diagram illustrating a configuration example of the write assist circuit 211 in FIG. Similarly to FIG. 1, the negative potential generation circuit 108 includes a transistor 112 and a capacitor 114, and supplies a negative potential to the node NVSSA. The n-channel field effect transistor 112 has a source connected to the ground potential node, a gate connected to the node of the boost signal BSTAX, and a drain connected to the node NVSSA. The capacitor 114 is connected between the gate of the transistor 112 and the node NVSSA. The read assist circuits 201 and 202 and the write assist circuits 211 to 214 share the negative potential generated by the negative potential generation circuit 108. Thereby, the memory device can be reduced in size.

  The AND circuit 241 outputs a logical product signal WD of the write assist signal WENA, the column address signal COLA1, and the logical inversion value of the write data D. The AND circuit 242 outputs a logical product signal WDX of the write assist signal WENA, the column address signal COLA1, and the write data D. The n-channel field effect transistor 243 has a source connected to the node NVSSA, a gate connected to the node of the signal WD, and a drain connected to the bit line BLA1. The n-channel field effect transistor 244 has a source connected to the node NVSSA, a gate connected to the node of the signal WDX, and a drain connected to the bit line BAX1. In the p-channel field effect transistor 245, the source is connected to the power supply potential node, the gate is connected to the node of the column address signal COLA1, and the drain is connected to the bit line BLA1. In the p-channel field effect transistor 246, the source is connected to the power supply potential node, the gate is connected to the node of the column address signal COLA1, and the drain is connected to the bit line BAX1.

  The B port write assist circuit 212 has the same configuration as the A port write assist circuit 211 of FIG. Bit lines BLB1 and BLBX1 are connected instead of bit lines BLA1 and BLAX1. A column address signal COLB1 is input instead of the column address signal COLA1. A write assist signal WENB is input instead of the write assist signal WENA. Node NVSSB is connected instead of node NVSSA. A boost signal BSTBX is input instead of the boost signal BSTAX.

  The A port write assist circuit 213 has the same configuration as the A port write assist circuit 211, and is connected to the memory cell MC 12 and the like of the second column and the read assist circuit 202. The B port write assist circuit 214 has the same configuration as the B port write assist circuit 212 and is connected to the memory cell MC12 and the like of the second column and the read assist circuit 202.

  FIG. 7 is a timing chart showing a read operation of the memory device. In the period TR1, the A port and the B port have the same row address and different column addresses, and both the A port and the B port perform a read operation. The first word line WLA1 and the second word line WLB1 are at a high level, and the first column signal COLA1 and the second column signal COLB2 are at a high level. In this case, the read assist signals RENA and RENB become high level, and the boost signals BSTAX and BSTBX change from high level to low level. Then, the nodes MVSS1 and MVSS2 become negative potentials. As a result, the potential change speed of the bit lines BLA1 and BLB2 is increased, and the reading speed is increased.

  In the period TR2, the A port and the B port have the same row address and the same column address, and both the A port and the B port perform a read operation. The first word line WLA1 and the second word line WLB1 are at a high level, and the first column signal COLA1 and the second column signal COLB1 are at a high level. In this case, the read assist signal RENA goes high, and the boost signal BSTAX goes from high level to low level. Then, the node MVSS1 becomes a negative potential. Thereby, the potential change speed of the bit lines BLA1 and BLB1 is increased, and the reading speed is increased.

  In the period TR3, the A port and the B port have different row addresses and different column addresses, and both the A port and the B port perform a read operation. The first word line WLA1 and the second word line WLB2 are at a high level, and the first column signal COLA1 and the second column signal COLB2 are at a high level. In this case, the read assist signals RENA and RENB are at a low level, and the boost signals BSTAX and BSTBX are maintained at a high level. Then, the nodes MVSS1 and MVSS2 become the ground potential. In this case, read assist is not performed because there is no decrease in reading speed. Thereby, power consumption can be reduced.

  In the period TR4, only the A port performs a read operation. The first word line WLA1 is at a high level, and the first column signal COLA1 is at a high level. In this case, the read assist signals RENA and RENB are at a low level, and the boost signals BSTAX and BSTBX are maintained at a high level. Then, the nodes MVSS1 and MVSS2 become the ground potential. In this case, read assist is not performed because there is no decrease in reading speed. Thereby, power consumption can be reduced.

  FIG. 8 is a timing chart showing the write operation of the memory device. In the period TW1, the A port and the B port have the same row address and different column addresses, and both the A port and the B port perform a write operation. The first word line WLA1 and the second word line WLB1 are at a high level, and the first column signal COLA1 and the second column signal COLB2 are at a high level. In this case, the write assist signals WENA and WENB become high level. Then, the bit lines BLA1 and BLB2 change from the high level to the ground potential. Thereafter, the boost signals BSTAX and BSTBX change from the high level to the low level. Then, the bit lines BLA1 and BLB2 change from the ground potential to the negative potential. As a result, deterioration of the write margin and write error can be prevented.

  In the period TW2, the A port and the B port have the same row address and the same column address, the A port performs a write operation, and the B port performs a read operation. The first word line WLA1 and the second word line WLB1 are at a high level, and the first column signal COLA1 and the second column signal COLB1 are at a high level. In this case, the write assist signal WENA goes high. Since the read operation is not guaranteed, the read assist signals RENA and RENB become low level. Then, the bit line BLA1 changes from the high level to the ground potential. Thereafter, the boost signal BSTAX changes from the high level to the low level. Then, the bit line BLA1 is changed from the ground potential to the negative potential. As a result, deterioration of the write margin and write error can be prevented.

  In the period TW3, the A port and the B port have the same row address and different column addresses, the A port performs a write operation, and the B port performs a read operation. The first word line WLA1 and the second word line WLB1 are at a high level, and the first column signal COLA1 and the second column signal COLB2 are at a high level. In this case, the write assist signal WENA goes high and the read assist signal RENB goes high. Further, the boost signal BSTBX changes from the high level to the low level. Then, the node MVSS2 becomes a negative potential, and the reading speed is increased. Further, the bit line BLA1 changes from the high level to the ground potential. Thereafter, the boost signal BSTAX changes from the high level to the low level. Then, the bit line BLA1 is changed from the ground potential to the negative potential. As a result, deterioration of the write margin and write error can be prevented.

  In the period TW4, only the A port performs a write operation. The first word line WLA1 is at a high level, and the first column signal COLA1 is at a high level. In this case, the write assist signal WENA goes high. Then, the bit line BLA1 changes from the high level to the ground potential. Thereafter, the boost signal BSTAX changes from the high level to the low level. Then, the bit line BLA1 is changed from the ground potential to the negative potential. As a result, deterioration of the write margin and write error can be prevented.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

101 Decoder 102, 103 Column selector 104, 105 Sense amplifier 106 Address comparator 107 Boost control circuit 108 Negative potential generation circuit 109, 110 Read / write assist circuit

Claims (6)

A plurality of memory cells arranged in a matrix and storing data;
A plurality of first bit lines provided for each column of the plurality of memory cells for inputting / outputting data to / from the memory cells;
A plurality of second bit lines provided for each column of the plurality of memory cells, for inputting / outputting data to / from the memory cells;
A plurality of first word lines provided for each row of the plurality of memory cells and connecting the memory cells to the first bit line;
A plurality of second word lines provided for each row of the plurality of memory cells and connecting the memory cells to the second bit line;
A first address and a second address each including a row address and a column address are input, and a voltage is supplied to the plurality of first word lines based on the row address of the first address, and the second address A decoder for supplying a voltage to the plurality of second word lines based on a row address of
The data of the plurality of first bit lines is selectively output based on the column address of the first address, and the data of the plurality of second bit lines is selectively output based on the column address of the second address. A column selector to selectively output,
When the read request for the first address and the read request for the second address are input, the row address of the first address and the row address of the second address are different from each other. A ground potential is supplied to the reference potential node of the memory cell corresponding to the address and the reference potential node of the memory cell corresponding to the second address, and the row address of the first address and the row address of the second address are In the same case, a read assist circuit for supplying a negative potential to a reference potential node of the memory cell corresponding to the first address and a reference potential node of the memory cell corresponding to the second address is provided. Memory device.   Further, when a write request for the first address is input, a negative potential is supplied to the first bit line corresponding to the column address of the first address, and the write request for the second address is supplied. 2. The memory device according to claim 1, further comprising: a write assist circuit that supplies a negative potential to the second bit line corresponding to the column address of the second address when the is input. Furthermore, it has a negative potential generation circuit for generating a negative potential,
3. The memory device according to claim 2, wherein the read assist circuit and the write assist circuit share a negative potential generated by the negative potential generation circuit.   The read assist circuit, when there is an access request for the first address and the second address, and when the row address of the first address and the row address of the second address are different, 4. The ground potential is supplied to a reference potential node of a memory cell corresponding to one address and a reference potential node of a memory cell corresponding to the second address. Memory device.   5. The memory device according to claim 1, wherein reference potential nodes of memory cells in the same column among the plurality of memory cells are connected to each other. A plurality of memory cells arranged in a matrix and storing data;
A plurality of first bit lines provided for each column of the plurality of memory cells for inputting / outputting data to / from the memory cells;
A plurality of second bit lines provided for each column of the plurality of memory cells, for inputting / outputting data to / from the memory cells;
A plurality of first word lines provided for each row of the plurality of memory cells and connecting the memory cells to the first bit line;
A plurality of second word lines provided for each row of the plurality of memory cells and connecting the memory cells to the second bit line;
A first address and a second address each including a row address and a column address are input, and a voltage is supplied to the plurality of first word lines based on the row address of the first address, and the second address A decoder for supplying a voltage to the plurality of second word lines based on a row address of
The data of the plurality of first bit lines is selectively output based on the column address of the first address, and the data of the plurality of second bit lines is selectively output based on the column address of the second address. A control method of a memory device having a column selector for selectively outputting,
When the read request for the first address and the read request for the second address are input, the row address of the first address and the row address of the second address are different from each other. A ground potential is supplied to the reference potential node of the memory cell corresponding to the address and the reference potential node of the memory cell corresponding to the second address, and the row address of the first address and the row address of the second address are In the same case, a negative potential is supplied to the reference potential node of the memory cell corresponding to the first address and the reference potential node of the memory cell corresponding to the second address. .

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