JP2015026296A - Design method and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform simulation for noise analysis for a semiconductor device, which has a high-breakdown voltage transistor and normal-breakdown voltage transistor integrated on a single chip, in a practical calculation processing time period.SOLUTION: In a design method, a first circuit simulation is performed using an LSI net list and a test bench including the same and thereby a negative potential node that can be at a lower negative potential level than a ground potential in the net list is extracted. A parasitic bipolar transistor, which uses the extracted negative potential node as an emitter, an LSI substrate as a base, and a back gate of a MOSFET included in the net list as a collector, is added to the net list and a second circuit simulation using the test bench is performed. In the second circuit simulation, whether or not the net list including the extracted parasitic bipolar satisfies a predetermined signal specification is determined.

Description

  The present invention relates to a semiconductor device design method and program, and is particularly suitable for noise analysis of a semiconductor device in which a high voltage transistor and a normal voltage transistor are integrated on a single chip.

  In a large scale integrated circuit (LSI), a pn junction formed between a semiconductor substrate and an element is placed in a reverse bias state to electrically isolate the elements from each other. When a current flows in a state, there is a problem that a parasitic bipolar transistor including the pn junction operates to form a noise propagation path. This is particularly a problem in a semiconductor device in which a high voltage transistor and a normal voltage transistor are integrated on a single chip, such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) embedded LSI. In general, a circuit simulation using a net list in which parasitic elements such as parasitic bipolar transistors are added as an equivalent circuit to a net list describing an original circuit is used for noise analysis.

  In recent years, there has been an increasing demand for LSIs in which a power MOSFET and a normal voltage transistor are mounted together, such as a hard disk motor driver LSI. An analog / digital conversion circuit and an analog amplifier, which are usually composed of a withstand voltage transistor, handle small signals and are therefore strongly affected by noise. Therefore, the need for noise analysis as described above is high.

  Patent Document 1 discloses a method for extracting an element from a layout pattern and a method for verifying circuit characteristics. Based on the layout pattern, when two or more semiconductor regions having the opposite conductivity type are in contact with the target semiconductor region, the target conductor is regarded as an operation region, a bipolar transistor is extracted, and circuit simulation is performed.

  Patent Document 2 discloses a back annotation device that extracts parasitic circuit information such as a parasitic transistor and a parasitic resistance by a parasitic circuit extraction rule. The extracted parasitic circuit information is associated with logic circuit data to generate equivalent circuit data.

  Patent Document 3 discloses a design method for predicting the occurrence of a malfunction or the like by circuit operation analysis incorporating a parasitic transistor. Parasitic bipolar transistors other than semiconductor elements are extracted from the layout diagram. The circuit parameters of the extracted parasitic bipolar transistor are extracted by a device simulator. A parasitic bipolar transistor is incorporated into an integrated circuit, and a circuit operation analysis is performed by a circuit simulator (SPICE).

Japanese Patent Laid-Open No. 03-266448 Japanese Patent Application Laid-Open No. 07-129650 JP 2006-134955 A

  As a result of examination of Patent Documents 1, 2, and 3, the present inventors have found that there are the following new problems.

  When the circuit scale is increased as in an LSI, parasitic elements such as a parasitic bipolar transistor are spread over the entire LSI, and the number and types of the elements become enormous. Therefore, it is difficult to solve in a practical computer processing time. In general, circuit simulation requires a netlist that describes the connection relationship of elements in a circuit to be simulated and a model parameter that describes the operating characteristics of the elements. The number of parasitic elements including parasitic bipolar transistors affects the scale and complexity of the netlist in circuit simulation. As the number of parasitic bipolar transistors increases, the same number of model parameters are required. If the structural size of the transistor, that is, the width, length, spacing, etc. of each electrode is different, the operating characteristics will be different, so that different model parameters are required. This is because the parasitic bipolar transistor is not intentionally formed, and its structure is diverse.

  The technique described in Patent Document 1 provides rules for extracting bipolar transistors from a layout pattern, and bipolar transistors that satisfy the rules can be extracted comprehensively. At this time, for the parasitic transistor, prepare multiple models with different characteristics according to the shape, size, and overlapping method, and select the closest element model from the extracted characteristics of the parasitic transistor for simulation. Use.

  Since the technology described in Patent Document 2 is a back annotation device including a rule for extracting a parasitic bipolar transistor from a layout pattern and a rule for extracting a parasitic resistance, a parasitic circuit due to a parasitic element is accurately extracted, For this reason, the equivalent circuit is accurately extracted. Model parameters for simulation execution are given, and no extraction method is mentioned.

  When the techniques described in Patent Document 1 and Patent Document 2 are applied to an LSI having a large circuit scale, a bipolar transistor that satisfies the rules is exhaustively extracted, so that the netlist to be simulated becomes large and complicated. The number of model parameters to be prepared is enormous.

  In the technique described in Patent Document 3, after extracting a parasitic bipolar transistor from a layout pattern, model parameters of the extracted parasitic bipolar transistor are extracted by device simulation. The model parameters for any extracted parasitic bipolar shapes are available for circuit simulation. When this technology is applied to an LSI with a large circuit scale, the simulation target netlist becomes large and complex, and the computer processing time for device simulation for extracting model parameters becomes enormous. Since the device simulation is a simulation performed by expressing the device structure with a three-dimensional model, since the computer processing time per one type of device structure is long, the computer processing time becomes enormous when executed for many types of device structures. .

  In either case, the computer processing time increases exponentially with respect to the circuit scale and becomes enormous, and cannot be practically used for an LSI with a large circuit scale.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, by performing a first circuit simulation using a netlist of a semiconductor device and a test bench including the netlist, a negative potential node that can be a negative potential level lower than the ground potential is extracted from the netlist. A parasitic bipolar transistor based on the extracted negative potential node as the emitter, the substrate of the semiconductor device as a base, and the back gate of the MOSFET included in the netlist as a collector is added to the netlist, and a second test bench is used. Perform circuit simulation. By the second circuit simulation, it is determined whether or not the extracted net list including the parasitic bipolar satisfies a predetermined signal specification.

  The effect obtained by the one embodiment will be briefly described as follows.

  That is, the number of parasitic bipolar transistors to be simulated is limited, and the simulation can be executed in a practical calculation processing time.

FIG. 1 is a flowchart showing a design method according to the first embodiment. FIG. 2 is a flowchart showing a design method according to the second embodiment. FIG. 3 is a flowchart illustrating a design method according to the third embodiment. FIG. 4 is a circuit diagram illustrating an example of a circuit mounted on a semiconductor device that is an object of noise analysis. FIG. 5 is a waveform diagram showing the waveform of the negative potential node. FIG. 6 is a circuit diagram showing an example of a simulation target net list in the damaged element node specifying step. FIG. 7 is a circuit diagram illustrating an example of a simulation target netlist for noise analysis. FIG. 8 is a circuit diagram showing another example of a simulation target netlist for noise analysis. FIG. 9 is an explanatory diagram illustrating an example of a method for deriving a current amplification factor calculation formula for a parasitic bipolar transistor. FIG. 10 is an explanatory diagram showing an example of a method for creating an equivalent circuit of a parasitic bipolar transistor using a parasitic diode and a substrate resistance element. FIG. 11 is a flowchart illustrating a design method according to the fourth embodiment.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Addition of parasitic bipolar with the harming node limited to a negative potential node>
A method for designing a semiconductor device (10) in which a plurality of MOSFETs (TrH, TrL, M1, M2, M3) are formed on an n-type semiconductor substrate, including a negative potential node extraction step (S1) and addition of a parasitic bipolar transistor The program includes a step (S2) and a determination step (S3, S4), and is executed by a program operating on the electronic computer.

  The negative potential node extracting step performs a first circuit simulation using a netlist (1) of the semiconductor device and a test bench (2) including the netlist, thereby lowering the ground potential in the netlist. A negative potential node that can be a negative potential level is extracted.

  In the step of adding the parasitic bipolar transistor, a parasitic bipolar transistor (Bip) having the negative potential node as an emitter, the substrate of the semiconductor device as a base, and a back gate of a MOSFET included in the netlist as a collector is added to the netlist. To do.

  The determination step determines whether or not a predetermined signal specification is satisfied by performing a second circuit simulation (S3) using the test bench on the netlist to which the parasitic bipolar transistor is added. I do.

  As a result, the number of parasitic bipolar transistors to be simulated is limited, and the simulation can be executed in a practical calculation processing time.

[2] <Damage element node identification step>
In item 1, the design method further includes the following damaged element node specifying step (S6).

  In the damaged element node specifying step, a noise current source (15) is connected to a node to which the back gate of the MOSFET included in the netlist is connected, and a third circuit simulation (S6) using the test bench is performed. . As a result, the node that cannot satisfy the signal specification is identified as a damaged element node, and the current amount of the noise current source when the signal specification cannot be satisfied is extracted as a criterion (S6).

  In the determining step, a parasitic bipolar transistor (Bip) having the negative potential node as an emitter, the substrate of the semiconductor device as a base, and the damaged element node as a collector is added to the netlist, and a test bench is used. By performing the circuit simulation of No. 2 (S3), it is determined whether or not the amount of current at the damaged element node exceeds the criteria (S4).

  As a result, the damaged element nodes can be narrowed down, and the computer processing time (simulation time) for noise analysis time can be further suppressed.

[3] <Simplified model of parasitic bipolar transistor>
Item 2. The current-controlled current source according to Item 1 or 2, wherein, in the second circuit simulation, the parasitic bipolar transistor has a current amplification factor calculated based on a well layer pattern in the layout (4) of the semiconductor device. Modeling is performed in (16) (S7, S8).

  This eliminates the need for device simulation for extracting model parameters suitable for each of a large number of parasitic bipolar transistors, and reduces computer processing time (simulation time) for noise analysis time.

[4] <Calculation of base current of parasitic bipolar transistor>
In Item 3, in the second circuit simulation, the base current of the parasitic bipolar transistor uses a parasitic diode (Ds) and a substrate resistance element (Rs) including the negative potential node and the base of the parasitic bipolar transistor. Obtained based on the equivalent circuit.

  Thus, the base current of the parasitic bipolar transistor can be calculated without using device simulation, and the computer processing time (simulation time) for noise analysis time can be further suppressed.

[5] <Calculation of base current of parasitic bipolar transistor by static circuit analysis>
In item 1 or item 2, the base-emitter of the parasitic bipolar transistor is modeled by an equivalent circuit using a parasitic diode (Ds) and a substrate resistance element (Rs). In the second circuit simulation, the base current of the parasitic bipolar transistor is calculated by static circuit analysis for the equivalent circuit. The collector current of the parasitic bipolar transistor is modeled by a current control current source (16) having the calculated base current as input and having a current amplification factor calculated based on a well layer pattern in the layout of the semiconductor device. To do.

  As a result, the base current of the parasitic bipolar transistor can be calculated by static circuit analysis regardless of transient analysis, and the computer processing time (simulation time) for noise analysis time can be further suppressed.

[6] <Addition of parasitic bipolar with the harm node limited to a negative potential node (program)>
A program operating on an electronic computer for noise analysis in a semiconductor device (10) in which a plurality of MOSFETs (TrH, TrL, M1, M2, M3) are formed on an n-type semiconductor substrate, and extracting a negative potential node It includes a step (S1), a parasitic bipolar transistor addition step (S2), and a determination step (S3, S4).

  The negative potential node extracting step performs a first circuit simulation using a netlist (1) of the semiconductor device and a test bench (2) including the netlist, thereby lowering the ground potential in the netlist. A negative potential node that can be a negative potential level is extracted.

  In the step of adding the parasitic bipolar transistor, a parasitic bipolar transistor (Bip) having the negative potential node as an emitter, the substrate of the semiconductor device as a base, and a back gate of a MOSFET included in the netlist as a collector is added to the netlist. To do.

  The determination step determines whether or not a predetermined signal specification is satisfied by performing a second circuit simulation (S3) using the test bench on the netlist to which the parasitic bipolar transistor is added. I do.

  As a result, the number of parasitic bipolar transistors to be simulated is limited, and the simulation can be executed in a practical calculation processing time.

[7] <Damage element node identification step (program)>
In item 6, the program further includes a damaged element node specifying step (S6).

  In the damage element node specifying step, a noise current source (15) is connected to a node to which the back gate of the MOSFET included in the netlist is connected, and a third circuit simulation (S6) using the test bench is performed. Do. Thus, a node that cannot satisfy the signal specification is identified as a damaged element node, and the current amount of the noise current source when the signal specification cannot be satisfied is extracted as a criterion.

  In the determining step, a parasitic bipolar transistor (Bip) having the negative potential node as an emitter, the substrate of the semiconductor device as a base, and the damaged element node as a collector is added to the netlist, and a test bench is used. By performing the circuit simulation of No. 2 (S3), it is determined whether or not the amount of current at the damaged element node exceeds the criteria.

  As a result, the damaged element nodes can be narrowed down, and the computer processing time (simulation time) for noise analysis time can be further suppressed.

[8] <Simplified model of parasitic bipolar transistor (program)>
Item 6. The current-controlled current source (16) according to Item 6 or 7, wherein, in the second circuit simulation, the parasitic bipolar transistor has a current amplification factor calculated based on a well layer pattern in the layout of the semiconductor device. (S7, S8).

  This eliminates the need for device simulation for extracting model parameters suitable for each of a large number of parasitic bipolar transistors, and reduces computer processing time (simulation time) for noise analysis time.

[9] <Calculation of base current of parasitic bipolar transistor (program)>
In item 8, in the second circuit simulation, the base current of the parasitic bipolar transistor uses a parasitic diode (Ds) and a substrate resistance element (Rs) including the negative potential node and the base of the parasitic bipolar transistor. Obtained based on the equivalent circuit.

  Thus, the base current of the parasitic bipolar transistor can be calculated without using device simulation, and the computer processing time (simulation time) for noise analysis time can be further suppressed.

[10] <Calculation of parasitic bipolar Ib by static circuit analysis (program)>
In item 6 or 7, the base-emitter of the parasitic bipolar transistor is modeled by an equivalent circuit using a parasitic diode (Ds) and a substrate resistance element (Rs). In the second circuit simulation, the base current of the parasitic bipolar transistor is calculated by static circuit analysis for the equivalent circuit. The collector current of the parasitic bipolar transistor is modeled by a current control current source (16) having the calculated base current as input and having a current amplification factor calculated based on a well layer pattern in the layout of the semiconductor device. To do.

  As a result, the base current of the parasitic bipolar transistor can be calculated by static circuit analysis regardless of transient analysis, and the computer processing time (simulation time) for noise analysis time can be further suppressed.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 is a flowchart showing a design method according to the outline of the embodiment. Although not particularly limited, it is a program that operates on an electronic computer such as EWS (Engineering Work Station). In the negative potential node extraction step S1, a negative potential node that can be at a negative potential level lower than the ground potential by performing a first circuit simulation using the netlist 1 of the semiconductor device to be analyzed and the test bench 2 including the same. To extract. The net list 1 and the test bench 2 may be a net list and a test bench used for normal circuit design. In order to confirm that the netlist 1 designed under various conditions satisfies a predetermined specification, the test bench 2 has many test items with different input signal waveforms, connected circuit conditions, operating conditions, etc. A probe description for determining whether or not a predetermined specification is satisfied is included.

  In the parasitic bipolar transistor adding step S2, a parasitic bipolar transistor Bip having the extracted negative potential node as an emitter, a substrate as a base, and a back gate of a MOSFET included in the netlist 1 as a collector is added to the netlist 1. A second circuit simulation is performed on the netlist to which the parasitic bipolar transistor Bip is added (step S3). In the determination step S4, it is determined whether or not a predetermined signal specification is satisfied as a result of the simulation.

  As a result, the number of parasitic bipolar transistors to be simulated is limited, and the simulation can be executed in a practical calculation processing time.

  Note that the countermeasure step S5 is a layout design change or a circuit design change, and may be included in the same program, or the program outputs that it does not satisfy the specifications and ends, and the countermeasure is given to the designer. You can leave it to me. When measures are automatically taken by the same program, for example, in layout design, it is possible to make changes such as increasing the number of substrate contacts around the negative potential node and increasing the load capacitance of the negative potential node. Further, for example, in circuit design, a change is made such as inserting a resistor between the high voltage power MOSFET and the negative potential node, increasing the value of the inserted resistor, or dulling the drive waveform by the drive circuits 11 and 12. Can do.

  FIG. 4 is a circuit diagram illustrating an example of a circuit mounted on a semiconductor device that is an object of noise analysis. The LSI 10 includes a circuit for driving an external inductive load 13 by high voltage power MOSFETs (TrH, TrL) vertically stacked in two stages, and an analog circuit by normal voltage MOSFETs (M1, M2, M3), It is mounted on the same chip. The high breakdown voltage power MOSFETs (TrH, TrL) stacked vertically in two stages are driven by the drive circuits 11 and 12, respectively. The drain of the high voltage power MOSFET (TrH) is connected to the high voltage power supply VDH, and the source of the other high voltage power MOSFET (TrL) is grounded. The source of the high breakdown voltage power MOSFET (TrH) and the drain of the other high breakdown voltage power MOSFET (TrL) are connected to each other and connected to the external inductive load 13 via the terminal OUT. The drive circuit 11 operates with the power supply VD, and the drive circuit 12 operates with the power supply VL. A capacitor C1 is connected between one terminal of the external inductive load 13 and the VD terminal, and a capacitor C2 connected to the resistor RL and the ground is connected to the other terminal. The input signals of the drive circuits 11 and 12 (not shown) are amplified and the inductive load 13 is driven via the terminal OUT. The analog circuit is a differential circuit that operates with the power source VA, and load resistors R1 and R2 are connected to the MOSFETs (M1, M2) to form a differential pair, and are connected to the current source MOSFET (M3) in common Has been. Differential outputs OT1 and OT2 corresponding to input signals IN1 and IN2 (not shown) are output. The internal circuit of the LSI 10 is described in the netlist 1, and the circuit connected to the outside is described in the test bench 2. FIG. 4 illustrates a very simple circuit example for the sake of explanation. A circuit that may be damaged by noise is not limited to an analog circuit.

  FIG. 5 is a waveform diagram showing the waveform of the negative potential node. A circuit simulation is executed using the netlist 1 and the test bench 2 shown in FIG. 4, and the terminal OUT is observed. Since the inductive load 13 is connected to the terminal OUT, when driven alternately by TrH and TrL, which are high breakdown voltage power MOSFETs vertically stacked in two stages, a damping waveform is observed due to the back electromotive force. Is done. The damping on the ground side becomes a negative potential lower than the ground potential. In the negative potential node extraction step S1, such a node is extracted as a negative potential node.

  FIG. 7 is a circuit diagram illustrating an example of a simulation target netlist for noise analysis. A parasitic bipolar transistor Bip having the extracted negative potential node OUT as the emitter, the substrate as the base, and the collector of the back gate of the normal voltage MOSFET (M2) of the analog circuit, for example, is added to the netlist 1 (step S2). A second circuit simulation is performed on the netlist 1 to which the parasitic bipolar transistor Bip is added (step S3). The model parameters for the parasitic bipolar transistor Bip may be extracted using a device simulator or the like. Since the parasitic bipolar transistor Bip to be added to the netlist 1 has been specified, the parasitic bipolar transistor is comprehensively extracted, and the device simulation is obtained by performing device simulation for all necessary model parameters. Can greatly reduce the computer load.

  In the determination step S4, it is determined whether or not a predetermined signal specification is satisfied as a result of the simulation. The determination as to whether or not a predetermined signal specification is satisfied may be the same as a determination criterion for normal design. Evaluating how the influence of the parasitic bipolar affects the predetermined signal specifications, and if the predetermined specifications are satisfied even if there is an influence, the noise is allowed to be sufficiently small.

  The circuit illustrated in FIG. 7 is an example of noise analysis in which the MOSFET (M2) is viewed as a damaged element node. Noise analysis may be performed for a netlist in which a parasitic bipolar transistor Bip is connected to other MOSFETs at the same time, or a plurality of simulations may be performed by sequentially connecting one by one. If noise analysis is performed with a plurality of MOSFETs simultaneously viewed as a damaged element node, the complex influence can be evaluated, but the netlist to be simulated becomes large and complex, and the computer processing per simulation The time will be longer.

  Compared to the conventional noise analysis that extracts all parasitic bipolar elements and adds them to the netlist, the analysis target parasitic bipolar elements can be limited to only the parasitic bipolar transistors connected to the negative potential node. The number of parasitic bipolar elements added to the netlist 1 can be greatly reduced. Thus, the scale and complexity of the netlist being simulated is significantly reduced.

  The reason why it can be limited only to the parasitic bipolar transistor connected to the negative potential node will be described. In a semiconductor device (LSI) 10 in which a high voltage transistor and a normal voltage transistor are integrated on a single chip, the drain or source of the high voltage transistor is used as an emitter, the substrate is used as a base, and the drain or source of the normal voltage transistor is used as a collector. An npn type bipolar transistor is formed as a parasitic bipolar transistor. Usually, since the p-type semiconductor substrate is grounded, the pn junction is always reverse-biased. As long as the pn junction is not forward-biased, the npn-type bipolar transistor does not perform an amplification operation. Therefore, the parasitic bipolar transistor only needs to be considered when the pn junction is forward-biased. Since the p substrate is normally grounded, the pn junction is not forward-biased unless the drain or source of the high breakdown voltage transistor has a negative potential. Therefore, it is only necessary to consider the case where the drain or source of the high voltage transistor has a negative potential. Note that the drain or the source of the high voltage transistor is not limited as long as a negative potential can be generated. Further, when formed on an n-type substrate, the parasitic bipolar transistor is a pnp type, and the parasitic bipolar transistor operates only when the potential of the n substrate is higher than the potential at which the potential is fixed.

[Embodiment 2]
FIG. 2 is a flowchart showing a design method according to the second embodiment. The damage element node specifying step (S6) is further included in the flowchart representing the design method according to the first embodiment. FIG. 6 is a circuit diagram showing an example of a simulation target net list in the damaged element node specifying step.

  In the damage element node specifying step S6, for example, as shown in FIG. 6, the noise current sources (15_1, 15_2, 15_3) are connected to the nodes to which the back gates of the MOSFETs (M1, M2, M3) included in the netlist 1 are connected. The third circuit simulation (S6) using the test bench is performed by connecting. Thereby, the node that cannot satisfy the signal specification is identified as the damaged element node, and the current amount of the noise current source when the signal specification cannot be satisfied is extracted as the criterion (S6).

  In the determination step S4, as in the first embodiment, a parasitic bipolar transistor (Bip) having a negative potential node as an emitter, a base of the semiconductor device substrate as a base, and a damaged element node as a collector is added to the netlist 1, A second circuit simulation using the test bench 2 is performed (S3). In the present embodiment, in the determination step S4, it is determined whether or not the current amount in the damaged element node specified in step S6 satisfies the criteria.

  The circuit illustrated in FIG. 6 is a differential amplifier circuit. The difference between the differential input signals input to IN1 and IN2 is differentially output to outputs OT1 and OT2. VREF is a reference voltage that gives the current value of the constant current source by M3. In the test bench, for example, it is assumed that a satisfactory signal specification is given to the linearity of gain (OT2-OT1) / (IN2-IN1). As shown in FIG. 6, noise current sources (15_1, 15_2, 15_3) are connected to nodes to which back gates of MOSFETs (M1, M2, M3) included in the netlist 1 are connected, and a test bench is used. A third circuit simulation (S6) is performed. An index of how much noise is given to each of the noise current sources (15_1, 15_2, 15_3) when the signal specification of the linearity of the gain cannot be satisfied is previously set in the third circuit. It is obtained by simulation (S6). This indicator is a criterion. In the determination step S4, it is determined whether the noise amount is within an allowable range based on the obtained criteria. The criteria can be automatically obtained by a program executed on a computer. For example, a description for determining whether or not the signal specification is satisfied is included in the test bench 2, and the current amount of the noise current source (15_1, 15_2, 15_3) is gradually increased to obtain the signal specification. The amount of current at the time when it is no longer satisfied can be used as the criterion.

  Thereby, the damage element node can be narrowed down, and the simulation time can be further suppressed.

[Embodiment 3] <Calculation of base current of parasitic bipolar transistor>
FIG. 3 is a flowchart showing a design method according to the second embodiment. The second embodiment further includes a step (S7) of reading the current amplification factor h _FE calculation formula of the parasitic bipolar element and a step (S8) of calculating the base current and collector current of the parasitic bipolar element. The parasitic bipolar transistor Bip used in the circuit simulation (S3) is modeled by the current control current source 16 having the current amplification factor _hFE calculated based on the pattern of the well layer in the layout 4 of the semiconductor device 10 (S7, S7). S8). In step S2, the parasitic bipolar transistor Bip is replaced with a high-accuracy device model similar to a normal bipolar transistor, and when a base current is input, a collector current proportional to the current amplification factor _hFE is output as a proportional constant. It can be modeled by a current controlled current source.

FIG. 8 is a circuit diagram showing another example of a simulation target netlist for noise analysis. A space between the substrate of the LSI 10 and the negative potential node is described by an equivalent circuit including a parasitic diode Ds and a substrate resistance Rs. The base current Ib of the parasitic bipolar transistor Bip can be obtained as a current flowing through the parasitic diode Ds and the substrate resistance Rs. The collector current Ic of the parasitic bipolar transistor Bip can be modeled by a current controlled current source 16 whose current value is controlled by the formula Ic = h _FE Ib.

  This eliminates the need for device simulation for extracting model parameters suitable for each of a large number of parasitic bipolar transistors, and reduces computer processing time for noise analysis time.

  FIG. 9 is an explanatory diagram illustrating an example of a method for deriving a current amplification factor calculation formula for a parasitic bipolar transistor. A top view is shown on the upper side, and a cross-sectional view is shown on the lower side. As shown in the cross-sectional view, the parasitic bipolar transistor Bip is based on a P-type epitaxial substrate 30 and has an N-type buried layer 31_1 on the high breakdown voltage transistor side and an n-type epitaxial growth layer 33_1 as an emitter, and an N type on the normal breakdown voltage MOSFET side. The buried layer 31_2 and the N-type epitaxial growth layer 33_2 are formed as a collector. Looking at the top view, this is a place where a P well layer (P well pattern) 42 is sandwiched between two N well layers (N well patterns) 41_1 and 41_2.

In general, the current amplification factor h _FE of a bipolar transistor can be approximately expressed by the following equation.
h _FE = (Ln · dn) / (We · Wb)
Here, Wb is the base width, We is the emitter width, and Ln and dn are the carrier diffusion length and depth, respectively. Wb corresponds to an interval between the N well layers Nwell / Epi 41_1 and 41_2. We correspond to the cell width of the damaged MOSFET. The damaged MOSFET is formed with a P-type diffusion layer 36 sandwiching the gate 37. The diffusion length Ln and the depth dn can be obtained based on the doping profile of the substrate and the well by device simulation or the like in advance. Device simulation is required to obtain the diffusion length Ln and the depth dn, but these parameters are uniquely determined based on the doping profile of the substrate and the well, and do not depend on the transistor shape. There should be only one type of parameter for the semiconductor manufacturing process.

According to the equation shown above, of the parameters that determine the current amplification factor h _FE, base width Wb and the emitter width We is the negative potential node and victim element node is determined, is calculated based on the layout pattern therebetween well Recalculation is required for each noise analysis. On the other hand, since the diffusion length Ln and the depth dn are parameters inherent to the semiconductor manufacturing process, it is not necessary to recalculate each time noise analysis is performed.

  As a result, the base current of the parasitic bipolar transistor can be calculated without using device simulation for each noise analysis, and the computer processing time for noise analysis time can be further suppressed.

[Embodiment 4] <Calculation of base current of parasitic bipolar transistor by static circuit analysis>
FIG. 10 is an explanatory diagram showing an example of a method for creating an equivalent circuit of a parasitic bipolar transistor using a parasitic diode and a substrate resistance element.

  On the P-type epitaxial substrate 30, N-type epitaxial growth layers 33_1 to 33_7 that are N-wells and P-type epitaxial growth layers 34_1 to 34_8 that are P-wells are formed. The N-type buried layer 31 and the P-type buried layer 32 are not shown. High breakdown voltage transistors TrL and TrH are formed in N wells (N type epitaxial growth layers) 33_2 and 33_4, respectively, and normal breakdown voltage MOSFETs M1 and M3 are formed in N wells (N type epitaxial growth layers) 33_6 and 33_7, respectively. Has been.

  Similar to the circuit example shown in FIG. 4, a node where the drain of the high voltage transistor TrL and the source of TrH are connected to each other is defined as a negative potential node. The drains of the high breakdown voltage transistor TrL are N-type diffusion layers 35_2 and 35_4, which are formed in an N-well (N-type epitaxial growth layer) 33_2, and a PN junction is formed between the P-type substrate 30 and a parasitic bipolar transistor. It functions as the emitter of the transistor Bip. The P-type substrate 30 is a base. If M1 which is a normal withstand voltage MOSFET is a damaged element, an N well (N type epitaxial growth layer) 33_7 is connected to the back gate of M1. The N well (N type epitaxial growth layer) 33_7 has a PN junction formed with the P type substrate 30, and functions as a collector of the parasitic bipolar transistor Bip.

  An equivalent circuit is extracted using the substrate 30 between the electrodes (base-emitter, base-collector) of the parasitic bipolar transistor Bip as a grid-like RC network. The substrate 30 is grounded through P-type epitaxial growth layers 34_3 to 34_8 which are the same layer as the P well. This is a so-called substrate contact. The vertical resistances of the P-type epitaxial growth layers 34_3 to 34_8 and the substrate 30 are modeled as Rs_2, Rs_4, Rs_7, Rs_9, Rs_13, and Rs_16. Since the drain of the high breakdown voltage transistor TrH in which the PN junction is formed is connected to the high voltage power supply VDH, it is modeled as a parasitic diode Ds_2. Since the parasitic diode Ds_2 is reverse-biased, it functions as a capacitor. The well of the normal voltage transistor M3 in which the PN junction is formed is modeled as a parasitic diode Ds_3. A current source 15 that functions as a noise generation source is connected to the negative potential node, and a current source 16 is also connected to the back gate of the SFET M1 for the normal breakdown voltage that is a damaged element.

FIG. 11 is a flowchart illustrating a design method according to the fourth embodiment. As described above, modeling is performed with an equivalent circuit using the parasitic diode Ds and the substrate resistance element Rs. Compared to the third embodiment, the extraction of the lattice RC network (S9) and the circuit between the damage element node and criteria identification step (S6) and the reading step (S7) of the current amplification factor _hFE calculation formula of the parasitic bipolar element A simulation (S10) is performed. In the extraction of the lattice RC network (S9), as described above, the equivalent circuit is extracted using the substrate 30 between the electrodes of the parasitic bipolar transistor Bip (base-emitter, base-collector) as the lattice RC network. . The grid-like RC network has been described as a grid-like RC network that shows a cross-sectional view in FIG. 10 and spreads two-dimensionally in the depth direction and the inter-electrode direction, but also spreads in a direction parallel to the substrate surface. It may be modeled as a dimensional grid RC network. A current source 15 that functions as a noise generation source is connected to the negative potential node, and a current source 16 that also functions as a collector current of the parasitic bipolar transistor Bip is connected to the back gate of the SFET M1, which is a damaged element. .

  The circuit simulation S10 may be a static circuit analysis such as an AC analysis or a DC analysis, not a transient analysis. Since the current source 15 that functions as a noise generation source, the grid RC network, and the current source 16 that functions as a collector current of the parasitic bipolar transistor Bip are all linear elements, static circuits such as AC analysis and DC analysis are used. The result of the analysis agrees with the result of the transient analysis. Since it is sufficient to perform static circuit analysis with a small load on the computer, it is possible to further reduce the computer processing time for noise analysis time.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the embodiment has been disclosed as a design support system that performs noise analysis by software on an electronic computer. However, the electronic computer can be applied to any electronic computer such as a large supercomputer, an engineering workstation, and a personal computer. . Further, the software may be application software that operates independently, or may be a single function incorporated as a subprogram or the like in a larger design tool.

1 Netlist 2 Test bench 3 Bipolar transistor current amplification factor h _FE calculation formula 4 Layout data S1 Negative potential node extraction step S2 Add parasitic bipolar transistor to netlist S3 Circuit simulation S4 Judgment step S5 Countermeasure (Layout design change, circuit design Change)
S6 Step of identifying damaged element node and criteria S7 Reading of current amplification factor h _{FE of} parasitic bipolar element S8 Calculation of base current and collector current of parasitic bipolar element S9 Extraction of lattice RC network S10 Static circuit analysis TrH, TrL High voltage transistor M1, M2, M3 Normal voltage MOSFET
Bip Parasitic bipolar transistor Ds Parasitic diode Rs Substrate resistance Cs Parasitic capacitance R Resistance C Capacitance VH, VL, VA Power supply 10 LSI
11 and 12 Drive circuit 13 Inductive load 14 Diode 15 Noise current source 16 Current source (Ic)
30 Substrate 31 N-type buried layer 32 P-type buried layer 33 N-type epitaxial growth layer 34 P-type epitaxial growth layer 35 N-type diffusion layer 36 P-type diffusion layer 37 Gate 41 N-well layer 42 P-well layer

Claims (10)

A method for designing a semiconductor device in which a plurality of MOSFETs are formed on an n-type semiconductor substrate, comprising a negative potential node extraction step, a parasitic bipolar transistor addition step, and a determination step, and according to a program operating on an electronic computer Executed,
The negative potential node extracting step performs a first circuit simulation using a netlist of the semiconductor device and a test bench including the netlist, so that a negative potential level lower than a ground potential in the netlist can be obtained. Extract potential nodes,
The parasitic bipolar transistor adding step adds a parasitic bipolar transistor having the negative potential node as an emitter, a substrate of the semiconductor device as a base, and a back gate of a MOSFET included in the netlist as a collector, to the netlist,
The determination step determines whether or not a predetermined signal specification is satisfied by performing a second circuit simulation using the test bench on the netlist to which the parasitic bipolar transistor is added. Design method. 2. The signal specification is satisfied by performing a third circuit simulation using the test bench by connecting a noise current source to a node to which a back gate of the MOSFET included in the netlist is connected. Further including a damaged element node identifying step of identifying a node that cannot be performed as a damaged element node, and extracting a current amount of the noise current source when the signal specification cannot be satisfied as a criterion;
The determination step includes adding a parasitic bipolar transistor having the negative potential node as an emitter, the substrate of the semiconductor device as a base, and the damaged element node as a collector to the netlist, and a second circuit using a test bench. A design method for determining whether or not an amount of current in the damaged element node exceeds the criterion by performing a simulation.   In Claim 1, in the second circuit simulation, the parasitic bipolar transistor is modeled by a current control current source having a current amplification factor calculated based on a pattern of a well layer in the layout of the semiconductor device. Design method.   4. The base circuit according to claim 3, wherein in the second circuit simulation, the base current of the parasitic bipolar transistor is based on an equivalent circuit using a parasitic diode and a substrate resistance element including the negative potential node and the base of the parasitic bipolar transistor. The design method you want.   2. The base-emitter of the parasitic bipolar transistor according to claim 1 is modeled by an equivalent circuit using a parasitic diode and a substrate resistance element, and in the second circuit simulation, the base current of the parasitic bipolar transistor is the equivalent current. Calculated by static circuit analysis for a circuit, the collector current of the parasitic bipolar transistor has the calculated base current as an input, and has a current amplification factor calculated based on a well layer pattern in the layout of the semiconductor device. A design method that models with a current-controlled current source. A program that operates on an electronic computer, including a negative potential node extraction step, a parasitic bipolar transistor addition step, and a determination step, for noise analysis in a semiconductor device in which a plurality of MOSFETs are formed on an n-type semiconductor substrate. And
The negative potential node extracting step performs a first circuit simulation using a netlist of the semiconductor device and a test bench including the netlist, so that a negative potential level lower than a ground potential in the netlist can be obtained. Extract potential nodes,
The parasitic bipolar transistor adding step adds a parasitic bipolar transistor having the negative potential node as an emitter, a substrate of the semiconductor device as a base, and a back gate of a MOSFET included in the netlist as a collector, to the netlist,
The determination step determines whether or not a predetermined signal specification is satisfied by performing a second circuit simulation using the test bench on the netlist to which the parasitic bipolar transistor is added. program. The program according to claim 6, further comprising a victim element node specifying step,
In the damage element node specifying step, a noise current source is connected to a node to which a back gate of a MOSFET included in the netlist is connected, and a third circuit simulation using the test bench is performed, whereby the signal The node that cannot satisfy the specification is identified as a damaged element node, and the current amount of the noise current source when the signal specification cannot be satisfied is extracted as a criterion.
The determination step includes adding a parasitic bipolar transistor having the negative potential node as an emitter, the substrate of the semiconductor device as a base, and the damaged element node as a collector to the netlist, and a second circuit using a test bench. A program for determining whether or not the amount of current at the damaged element node exceeds the criteria by performing a simulation.   7. The second circuit simulation according to claim 6, wherein the parasitic bipolar transistor is modeled by a current control current source having a current amplification factor calculated based on a pattern of a well layer in the layout of the semiconductor device. program.   9. The base circuit according to claim 8, wherein, in the second circuit simulation, the base current of the parasitic bipolar transistor is based on an equivalent circuit using a parasitic diode and a substrate resistance element including the negative potential node and the base of the parasitic bipolar transistor. The program you want.   7. The base-emitter between the parasitic bipolar transistors according to claim 6 is modeled by an equivalent circuit using a parasitic diode and a substrate resistance element. In the second circuit simulation, the base current of the parasitic bipolar transistor is the equivalent current. Calculated by static circuit analysis for a circuit, the collector current of the parasitic bipolar transistor has the calculated base current as an input, and has a current amplification factor calculated based on a well layer pattern in the layout of the semiconductor device. A program that models with a current-controlled current source.

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