JP2015022556A - Processor system and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently suppress the power consumption of a system.SOLUTION: A processor 101 executes an executable task 110 registered in a ready queue 103. If the executable task 110 is not registered in the ready queue 103, the processor 101 shifts into a first power saving state. On the other hand, a controller 102 receives timer interrupts at predetermined intervals and updates the ready queue 103. If the executable task 110 is registered in the ready queue 103, the controller 102 transmits a processor start interrupt to the processor 101. Upon receiving the processor start interrupt, the processor 101 transitions to a first activation state to execute the executable tasks 110 registered in the ready queue.

Description

  The present invention relates to a processor system and a semiconductor integrated circuit.

  In a portable information terminal that operates with electric power charged in a battery such as a smartphone, a mobile phone, and a tablet PC (Personal Computer), it is important to suppress power consumption during standby time in order to increase the driving time. . As a technique for reducing the power consumption during the standby time, for example, when there is no process to be executed, there is a technique for shifting to a power saving state with less power consumption.

  Related prior art includes, for example, stopping the supply of a clock signal to the processor or reducing the frequency by a program running at the lowest priority under a multitasking operating system. In addition, there is a technique in which a standby task for stopping clock supply is prepared as a task with the lowest priority, and the standby task is executed after the other task processing is completed.

JP-A-4-278612 Japanese Patent Laid-Open No. 11-212661

  However, according to the prior art, it is difficult to achieve sufficient power saving of the system. For example, in order to reduce the power consumption of the system, even if the frequency of the clock signal supplied to the processor is decreased when there is no task to be executed, a timer interrupt periodically enters the processor. For this reason, each time a timer interrupt occurs, the processor is started and the power saving state is interrupted, making it difficult to achieve sufficient power saving.

  In addition, when there is a task waiting to be executed after a certain time, if the frequency of the clock signal supplied to the processor is lowered, a timer interrupt may not be output to the processor at a specified time. In this case, the task waiting for execution is not executed after a certain time, and the real-time property of the system cannot be guaranteed.

  In one aspect, an object of the present invention is to provide a processor system and a semiconductor integrated circuit capable of efficiently suppressing power consumption of the system.

  According to one aspect of the present invention, a storage device having a ready queue for registering an executable task in a state where execution can be started, and when the executable task is not registered in the ready queue, A processor that transitions to a first power saving state that consumes less power than a first startup state that executes an executable task, an update process that updates the ready queue when a timer interrupt is received, and A processor system comprising: a controller that executes a transition process for causing the processor to transition to the first activation state when an executable task is registered; and a clock signal control circuit that outputs the timer interrupt to the controller at a predetermined cycle And semiconductor integrated circuits are proposed.

  According to one aspect of the present invention, there is an effect that the power consumption of the system can be efficiently suppressed.

FIG. 1 is an explanatory diagram of an example of the processor system 100 according to the first embodiment. FIG. 2 is a block diagram illustrating a hardware configuration example of the processor system 100. FIG. 3 is an explanatory diagram illustrating an example of the ready queue 103. FIG. 4 is a block diagram illustrating a functional configuration example of the controller 102. FIG. 5 is a flowchart of an example of a task processing procedure of the processor system 100 according to the first embodiment. FIG. 6 is an explanatory diagram of an example of the processor system 100 according to the second embodiment. FIG. 7 is an explanatory diagram showing an example of the timer queue 601. FIG. 8 is a flowchart of an example of a task processing procedure of the processor system 100 according to the second embodiment. FIG. 9 is a flowchart illustrating an example of an update process procedure of the timer queue 601 and the ready queue 103.

  Embodiments of a processor system and a semiconductor integrated circuit according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
(One Example of Processor System 100)
FIG. 1 is an explanatory diagram of an example of the processor system 100 according to the first embodiment. The processor system 100 is hardware that executes an OS (Operating System) and application processing in a computer. In FIG. 1, the processor system 100 includes a processor 101, a controller 102, a ready queue 103, and a clock signal control circuit 104.

  The processor 101 is a processor that executes high-load processing such as application tasks. For example, the processor 101 is a processor that has a higher processing capability than the controller 102 and consumes more power than the controller 102 that does not execute a task. When there is no task to be executed, the processor 101 uses a first power saving state (hereinafter simply referred to as “power saving”) that consumes less power than a first activation state in which the task is executed (hereinafter simply referred to as “activation state”). It is possible to transition to a “state”. For example, the processor 101 transitions to a power saving state by reducing the supplied voltage or reducing the frequency at which the processor 101 operates. The processor 101 can also shift to a power saving state by stopping the supply of a clock signal to a circuit for executing a task, or by cutting off power to the circuit for executing a task. Note that a clock signal is a signal that periodically takes a high voltage state and a low voltage condition, and is supplied to synchronize the timing of a plurality of circuits when the digital circuit operates.

  The controller 102 is a processor that executes low-load processing such as an OS interrupt response. Note that an interrupt is to cause a processor to interrupt a process that is currently being executed and to forcibly specify a process, and an interrupt response is a process that is forcibly specified. The controller 102 can communicate with the processor 101 and has a mechanism for causing an interrupt between the processors. Using this mechanism, the controller 102 can transmit to the processor 101 a processor activation interrupt that causes the processor 101 to transition from the power saving state to the activation state.

  The ready queue 103 is OS data for registering the executable tasks 110 that can be executed by the processor 101 in order of priority. The priority is an index for the processor 101 to select the executable task 110, and the processor 101 executes from the executable task 110 having a high priority. By referring to the ready queue 103, the processor 101 can confirm whether there is a task to be executed next. When the executable task 110 is registered in the ready queue 103, the processor 101 extracts the executable task 110 from the ready queue 103 and performs a dispatch process for executing the extracted task.

  The clock signal control circuit 104 is a device that supplies a clock signal to the processor 101 and the controller 102. The clock signal control circuit 104 is also a device that transmits a timer interrupt to the controller 102 at a predetermined cycle.

  In this embodiment, the processor 101 executes the executable task 110 registered in the ready queue 103. When the executable task 110 is not registered in the ready queue 103, the processor 101 shifts to the power saving state. On the other hand, the controller 102 receives a timer interrupt at a predetermined cycle and updates the ready queue 103. When the executable task 110 is registered in the ready queue 103, the controller 102 transmits a processor activation interrupt to the processor 101. The processor 101 that has received the processor activation interrupt makes a transition to the activation state and executes the executable task 110 registered in the ready queue 103. Hereinafter, a task processing procedure of the processor system 100 will be described in detail.

  (1) The processor 101 executes the executable task 110 registered in the ready queue 103. In the example of FIG. 1, the processor 101 extracts the executable task 110 registered in the ready queue 103 and executes the executable task 110.

  (2) When the executable task 110 is not registered in the ready queue 103, the processor 101 shifts to the power saving state. After completing the execution process, the processor 101 checks whether the executable task 110 is registered in the ready queue 103. In the example of FIG. 1, the executable task 110 is not registered, and the processor 101 transitions from the activated state to the power saving state.

  (3) The controller 102 receives a timer interrupt at a predetermined cycle and updates the ready queue 103. The controller 102 receives a timer interrupt from the clock signal control circuit 104 at a predetermined cycle. The controller 102 that has received the timer interrupt confirms whether the executable task 110 exists. If not, the controller 102 waits for the next timer interrupt.

  (4) When the executable task 110 is registered in the ready queue 103, the controller 102 transmits a processor activation interrupt to the processor 101. The controller 102 that has received the timer interrupt registers the executable task 110 in the ready queue 103 when the executable task 110 exists. Next, the controller 102 transmits a processor start interrupt to the processor 101 and waits for the next timer interrupt.

  (5) The processor 101 that has received the processor activation interrupt makes a transition to the activation state and executes the executable task 110 registered in the ready queue 103. In the example of FIG. 1, the processor 101 transitions from the power saving state to the activated state, extracts the executable task 110 registered in the ready queue 103, and executes the executable task 110.

  As described above, the processor system 100 includes the ready queue 103 that registers the executable task 110 in a state where the execution can be started. When the executable task 110 is not registered in the ready queue 103, the processor 101 shifts to a power saving state in which the power consumption is lower than the activation state in which the executable task 110 is executed. The controller 102 updates the ready queue 103 when a timer interrupt is accepted. Here, when the executable task 110 is registered in the ready queue 103, the controller 102 causes the processor 101 to transition to an activated state. The clock signal control circuit 104 outputs a timer interrupt to the controller 102 at a predetermined cycle.

  As a result, the controller 102 updates the ready queue 103, and the processor 101 does not update the ready queue 103. Therefore, even when there is an execution waiting task, the processor system 100 can transition to the power saving state when the executable task 110 does not exist, and suppress the power consumption of the entire system.

  Further, since the clock signal control circuit 104 does not output a timer interrupt to the processor 101, the processor 101 does not transit from the power saving state to the activated state at a predetermined cycle in order to process the timer interrupt. Therefore, the processor 101 can maintain the power saving state continuously for a long time and suppress the power consumption of the entire system.

(Hardware configuration example of the processor system 100)
FIG. 2 is a block diagram illustrating a hardware configuration example of the processor system 100. In FIG. 2, a processor system 100 includes a processor 101, a controller 102, a clock signal control circuit 104, a clock signal generation circuit 201, a memory 202, and an I / O (Input / Output) interface 203. Each component is connected by a bus 200.

  Here, the processor 101 and the controller 102 control the entire processor system 100. The memory 202 can store the ready queue 103. The memory 202 includes, for example, a ROM (Read Only Memory), a RAM (Random Access Memory), a flash ROM, and the like. Specifically, for example, a flash ROM or ROM stores various programs, and the RAM is used as a work area for the processor 101 and the controller 102. The program stored in the memory 202 is loaded into the processor 101 and the controller 102 to cause the processor 101 and the controller 102 to execute the coded processing.

  The clock signal generation circuit 201 supplies a clock signal having a predetermined cycle to the clock signal control circuit 104. The clock signal control circuit 104 is a device that supplies a clock signal to the processor 101 and the controller 102. The clock signal control circuit 104 can reduce the frequency of the clock signal supplied to the processor 101 and the controller 102 by changing the setting value, and can save power in the processor 101 and the controller 102. The clock signal control circuit 104 is also a device that transmits a timer interrupt to the controller 102 at a predetermined cycle.

  The memory 202 can also be a shared memory that can be accessed from both the processor 101 and the controller 102. The memory 202 can also be a distributed memory that is divided into a part that can be accessed from the processor 101 and a part that can be accessed from the controller 102. In this case, the processor system 100 includes a DMAC (Direct Memory Access Controller) (not shown) that performs data transfer without passing through the processor 101 and the controller 102. The DMAC transfers data used by both the processor 101 such as the ready queue 103 and the controller 102.

  The I / O interface 203 is connected to an input / output device such as a magnetic disk drive. The magnetic disk drive controls reading / writing of data with respect to the magnetic disk according to the control of the processor 101 and the controller 102. The magnetic disk stores data written under the control of the magnetic disk drive.

  The processor system 100 may include, for example, an SSD (Solid State Drive) in addition to the components described above.

(An example of the ready queue 103)
FIG. 3 is an explanatory diagram illustrating an example of the ready queue 103. The ready queue 103 can have a plurality of priority queues. In the example of FIG. 3, the ready queue 103 has three queues: a priority 1 queue 301, a priority 2 queue 302, and a priority 3 queue 303. The priority is highest in the priority 1 queue 301, next in the priority 2 queue 302, and lowest in the priority 3 queue 303. The executable task 311 is registered in the priority 1 queue 301, the executable task is not registered in the priority 2 queue 302, and the executable tasks 321, 322, and 323 are registered in the priority 3 queue 303. Is done. The processor 101 first executes the executable task 311 according to the priority.

(Functional configuration example of the controller 102)
FIG. 4 is a block diagram illustrating a functional configuration example of the controller 102. In FIG. 4, the controller 102 includes a reception unit 401, an update unit 402, a determination unit 403, and an output unit 404. Specifically, each function unit realizes its function by causing the controller 102 to execute a program stored in a storage device such as the memory 202 illustrated in FIG. 2, for example. The processing result of each functional unit is stored in, for example, a storage device such as the memory 202 illustrated in FIG. Each functional unit may be realized by hardware, for example. Specifically, for example, each functional unit includes AND as a logical product circuit, INVERTER as a negative logical circuit, OR as a logical sum circuit, NOR as a logical sum negation circuit, and FF (Flip Flop) as a latch circuit. ) Or the like.

  The accepting unit 401 has a function of accepting a timer interrupt transmitted from the clock signal control circuit 104. After accepting the timer interrupt, the accepting unit 401 causes the updating unit 402 to execute an update process.

  The update unit 402 has a function of updating the ready queue 103. The update unit 402 registers the executable task 110 in the ready queue 103 when the executable task 110 exists. Thereafter, the update unit 402 causes the determination unit 403 to execute determination processing.

  The determination unit 403 has a function of determining whether or not the executable task 110 is registered in the ready queue 103. When the executable task 110 is registered in the ready queue 103, the determination unit 403 causes the output unit 404 to execute output processing. If not registered, the determination unit 403 causes the reception unit 401 to execute a next timer interrupt reception process.

  The output unit 404 has a function of outputting a processor activation interrupt to the processor 101. After the processor activation interrupt is output, the output unit 404 causes the reception unit 401 to execute a next timer interrupt reception process.

  FIG. 5 is a flowchart of an example of a task processing procedure of the processor system 100 according to the first embodiment. The flowchart on the left side is executed by the processor 101, and the flowchart on the right side is executed by the controller 102.

  In the flowchart of FIG. 5, first, the processor 101 confirms whether or not the executable task 110 is registered in the ready queue 103 (step S501). When the executable task 110 is not registered (step S502: No), the processor 101 shifts to a power saving state (step S503).

  Next, the controller 102 receives a timer interrupt from the clock signal control circuit 104 at a predetermined cycle, and checks whether there is an executable task 110. If the executable task 110 exists, the controller 102 registers the executable task 110 in the ready queue 103 (step S511). Next, the controller 102 checks whether or not the executable task 110 is registered in the ready queue 103 (step S512). When the executable task 110 is not registered in the ready queue 103 (step S512: No), the controller 102 waits for reception of the next timer interrupt.

  When the executable task 110 is registered in the ready queue 103 (step S512: Yes), the controller 102 transmits a processor activation interrupt to the processor 101 (step S513). After transmitting the processor activation interrupt, the controller 102 waits for acceptance of the next timer interrupt.

  When the processor activation interrupt is received from the controller 102, the processor 101 transitions to the activation state (step S504). After that, the processor 101 moves to step S501.

  If the executable task 110 exists in the ready queue 103 (step S502: Yes), the processor 101 takes out the executable task 110 from the ready queue 103 and performs a dispatch process for executing the extracted task (step S505). ). Thereby, a series of processing by this flowchart is complete | finished. By executing this flowchart, the processor 101 executes the executable task 110 when the executable task 110 exists in the ready queue 103, and enters the power saving state when the executable task 110 does not exist.

  As described above, in the processor system 100 according to the first embodiment, the processor 101 shifts to the power saving state when the executable task 110 is not registered in the ready queue 103. In addition, the controller 102 updates the ready queue 103 when a timer interrupt is received, and transitions the processor 101 to an activated state when an executable task is registered in the ready queue 103. As a result, even when there is an execution waiting task, the processor 101 can be shifted to the power saving state when the executable task 110 does not exist, thereby reducing the power consumption of the entire system.

  Further, since the clock signal control circuit 104 does not output a timer interrupt to the processor 101, the processor 101 does not transit from the power saving state to the activated state at a predetermined cycle in order to process the timer interrupt. Therefore, the processor 101 can maintain the power saving state continuously for a long time and suppress the power consumption of the entire system.

  Further, when the executable task is registered in the ready queue 103, the controller 102 can transition the processor 101 from the power saving state to the activated state by transmitting a processor activation interrupt to the processor 101.

  In other words, the processor system 100 according to the first embodiment can keep the processor 101 in the power saving state for a long time, and the ready queue 103 is managed by the controller 102 with a small amount of power consumption. It can be suppressed efficiently.

(Embodiment 2)
FIG. 6 is an explanatory diagram of an example of the processor system 100 according to the second embodiment. In FIG. 6, the processor system 100 further includes a timer queue 601. Note that illustration and description of the same portions as those described in Embodiment 1 are omitted.

  The processor 101 can receive an input / output interrupt in a power saving state. The input / output interrupt is an interrupt transmitted to the processor 101 when an input / output device such as a magnetic disk drive ends input / output processing. Due to the input / output interrupt, the execution waiting task 111 waiting for the end of the input / output processing can become the executable task 110.

  When there is no process to be executed, the controller 102 uses a second power saving state (hereinafter simply referred to as “power saving”) that consumes less power than a second activation state during processing (hereinafter simply referred to as “activation state”). It is possible to transition to a “power state”. The process executed by the controller 102 is, for example, a process for updating the ready queue 103 and the timer queue 601 executed when a timer interrupt is received, and a process for causing the processor 101 to transition from the power saving state to the activated state. For example, the controller 102 can transition to the power saving state in the same manner as the processor 101.

  Even when the controller 102 is in the power saving state, the clock signal control circuit 104 transmits a timer interrupt to the controller 102 at the same predetermined cycle as in the activated state.

  The timer queue 601 is OS data for registering an execution waiting task 111 that is ready to start execution after a predetermined time has elapsed. The timer queue 601 can be stored in the memory 202. The timer queue 601 manages the execution waiting tasks 111 by arranging them in the order of a predetermined time. The waiting task 111 becomes an executable task 110 after a predetermined time elapses, is deleted from the timer queue 601, and is registered in the ready queue 103. In addition, the task being executed in the processor 101 issues an API (Application Program Interface) that waits for a predetermined time, whereby the task being executed becomes the execution waiting task 111 and is registered in the timer queue 601. Here, the API is a procedure for an application to use a function provided by the OS.

  In this embodiment, the processor 101 executes the executable task 110 registered in the ready queue 103. When the executable task 110 is not registered in the ready queue 103, the processor 101 shifts to the power saving state. On the other hand, the controller 102 receives a timer interrupt at a predetermined cycle, and updates the timer queue 601 and the ready queue 103. When the executable task 110 is registered in the ready queue 103, the controller 102 transmits a processor activation interrupt to the processor 101. The processor 101 that has received the processor activation interrupt makes a transition to the activation state and executes the executable task 110 registered in the ready queue 103. Hereinafter, a task processing procedure of the processor system 100 will be described in detail.

  (1) The processor 101 executes the executable task 110 registered in the ready queue 103. In the example of FIG. 6, the processor 101 extracts the executable task 110 registered in the ready queue 103 and executes the executable task 110.

  (2) When the executable task 110 is not registered in the ready queue 103, the processor 101 shifts to the power saving state. In the example of FIG. 6, the task being executed by the processor 101 executes an API that waits for a predetermined time (10 msec). As a result, the task is registered in the timer queue 601 as the execution waiting task 111. Thereafter, the processor 101 confirms whether the executable task 110 is registered in the ready queue 103. In the example of FIG. 6, the executable task 110 is not registered, and the processor 101 transitions from the activated state to the power saving state.

  (3) The controller 102 receives a timer interrupt at a predetermined cycle, and updates the timer queue 601 and the ready queue 103. The controller 102 receives a timer interrupt at a predetermined cycle, and transitions to an activated state. The controller 102 subtracts a predetermined period from a predetermined time of the execution waiting task 111 registered in the timer queue 601. In the example of FIG. 6, the controller 102 receives a timer interrupt at a predetermined period of 1 msec. In this case, the predetermined time of the execution waiting task 111 is 9 msec by subtraction. The controller 102 confirms whether the executable task 110 exists. If not, the controller 102 transitions to a power saving state and waits for the next timer interrupt.

  (4) When the executable task 110 is registered in the ready queue 103, the controller 102 transmits a processor activation interrupt to the processor 101. In the example of FIG. 6, when the controller 102 receives the timer interrupt 10 times, the predetermined time of the execution waiting task 111 is 0 msec. Since the predetermined time of the execution waiting task 111 has elapsed, the controller 102 deletes the execution waiting task 111 from the timer queue 601 and registers it as the executable task 110 in the ready queue 103. Next, the controller 102 transmits a processor activation interrupt to the processor 101. The controller 102 transitions to the power saving state and waits for the next timer interrupt.

  (5) The processor 101 that has received the processor activation interrupt makes a transition to the activation state and executes the executable task 110 registered in the ready queue 103. The processor 101 transitions from the power saving state to the activated state, extracts the executable task 110 registered in the ready queue 103, and executes the executable task 110.

  As described above, the processor system 100 includes the ready queue 103 that registers the executable task 110 in a state where the execution can be started. Furthermore, the processor system 100 has a timer queue 601 for registering an execution waiting task 111 that is ready to start execution after a predetermined time has elapsed. When the executable task 110 is not registered in the ready queue 103, the processor 101 shifts to a power saving state in which the power consumption is lower than the activation state in which the executable task 110 is executed. The controller 102 updates the ready queue 103 and the timer queue 601 when a timer interrupt is accepted. The controller 102 registers, in the ready queue 103, an execution waiting task 111 that has been in a state where a predetermined time has elapsed and can start execution as an executable task 110. Here, when the executable task 110 is registered in the ready queue 103, the controller 102 causes the processor 101 to transition to an activated state. The clock signal control circuit 104 causes the controller 102 to output a timer interrupt generated at a predetermined cycle.

  As a result, the controller 102 updates the timer queue 601 and the processor 101 does not update the timer queue 601. Therefore, the processor system 100 shifts to the power saving state when the executable task 110 does not exist even when there is an execution waiting task 111 in which the execution can be started after a predetermined time has elapsed. Power consumption can be reduced.

  Further, the clock signal control circuit 104 transmits a timer interrupt to the controller 102 at the same predetermined cycle as that in the activated state even when the controller 102 is in the power saving state. For this reason, the controller 102 can start the execution waiting task 111 registered in the timer queue 601 after a predetermined time even in the power saving state. Therefore, the processor system 100 can maintain real-time characteristics.

  The controller 102 can transition to the power saving state until the next timer interrupt is received after the update process of the ready queue 103 and the timer queue 601 and the transition process of the processor 101. Therefore, the processor system 100 can further save power.

(Example of timer queue 601)
FIG. 7 is an explanatory diagram showing an example of the timer queue 601. The timer queue 601 registers an execution waiting task 111 that is ready to start execution after a predetermined time has elapsed. The execution waiting task 111 stores a predetermined time. In the example of FIG. 7, the timer queue 601 registers waiting tasks 711, 712, and 713. For example, the execution waiting task 711 stores 5 msec as the predetermined time. The waiting task 711 becomes an executable task 110 after 5 msec and is registered in the ready queue 103.

  FIG. 8 is a flowchart of an example of a task processing procedure of the processor system 100 according to the second embodiment. The flowchart on the left side is executed by the processor 101, and the flowchart on the right side is executed by the controller 102.

  In the flowchart of FIG. 8, first, the processor 101 confirms whether or not the executable task 110 is registered in the ready queue 103 (step S801). When the executable task 110 is not registered (step S802: No), the processor 101 shifts to the power saving state (step S803).

  Next, the controller 102 receives a timer interrupt from the clock signal control circuit 104 at a predetermined cycle, and transitions to an activated state (step S811). Next, the controller 102 updates the timer queue 601 and the ready queue 103 (step S812). The update processing procedure of the timer queue 601 and the ready queue 103 will be described in detail with reference to FIG. Next, the controller 102 checks whether or not the executable task 110 is registered in the ready queue 103 (step S813). When the executable task 110 is not registered in the ready queue 103 (step S813: No), the controller 102 proceeds to step S815.

  When the executable task 110 is registered in the ready queue 103 (step S813: Yes), the controller 102 transmits a processor activation interrupt to the processor 101 (step S814). After transmitting the processor activation interrupt, the controller 102 transitions to a power saving state (step S815) and waits for acceptance of the next timer interrupt.

  When a processor activation interrupt is received from the controller 102 or when an input / output interrupt is received, the processor 101 transitions to an activation state (step S804). After that, the processor 101 moves to step S801.

  If the executable task 110 exists in the ready queue 103 (step S802: Yes), the processor 101 takes out the executable task 110 from the ready queue 103 and performs a dispatch process for executing the extracted task (step S805). ). Thereby, a series of processing by this flowchart is complete | finished. By executing this flowchart, the processor 101 executes the executable task 110 when the executable task 110 exists in the ready queue 103, and enters the power saving state when the executable task 110 does not exist.

  FIG. 9 is a flowchart illustrating an example of an update process procedure of the timer queue 601 and the ready queue 103.

  In the flowchart of FIG. 9, first, the controller 102 checks whether or not the execution waiting task 111 is registered in the timer queue 601 (step S901). If not registered (step S901: No), the controller 102 ends the update processing of the timer queue 601 and the ready queue 103. If registered (step S901: Yes), the controller 102 subtracts the timer interrupt period from the predetermined time of the execution waiting task 111 registered in the timer queue 601 (step S902).

  Next, the controller 102 checks whether or not the predetermined time of the execution waiting task 111 has become 0 (step S903). When it becomes 0 (step S903: Yes), the predetermined time of the execution waiting task 111 has elapsed. Therefore, the controller 102 deletes the execution waiting task 111 from the timer queue 601 and registers it as the executable task 110 in the ready queue 103 (step S904). If it is not 0 (step S903: No), the controller 102 proceeds to step S905.

  The controller 102 confirms whether the next task is registered in the timer queue 601 (step S905). When registered (step S905: Yes), the controller 102 returns to step S902 and subtracts a predetermined time of the next task. When not registered (step S905: No), the controller 102 ends the update process of the timer queue 601 and the ready queue 103. Thereby, a series of processing by this flowchart is complete | finished. By executing this flowchart, the controller 102 updates the timer queue 601 and the ready queue 103 and registers the executable task 110 in the ready queue 103.

  The timer queue 601 can be updated by the following procedure. The controller 102 stores the number of timer interruptions after the execution waiting task 111 is registered in the timer queue 601. After receiving the timer interrupt, the controller 102 compares the product of the number of timer interrupts and the timer interrupt period with a predetermined time. When the product is large, since the predetermined time of the waiting task 111 has elapsed, the controller 102 deletes the waiting task 111 from the timer queue 601 and registers it as the executable task 110 in the ready queue 103.

  As described above, in the processor system 100 according to the second embodiment, the controller 102 updates the timer queue 601 and the processor 101 does not update the timer queue 601. Therefore, the processor system 100 shifts to the power saving state when the executable task 110 does not exist even when there is an execution waiting task 111 in which the execution can be started after a predetermined time has elapsed. Power consumption can be reduced.

  The clock signal control circuit 104 also transmits a timer interrupt to the controller 102 at the same predetermined cycle as that in the activated state even when the controller 102 is in the power saving state. For this reason, the controller 102 can start the execution waiting task 111 registered in the timer queue 601 after a predetermined time even in the power saving state. Therefore, the processor system 100 can maintain real-time characteristics.

  The controller 102 can transition to the power saving state until the next timer interrupt is received after the update process of the ready queue 103 and the timer queue 601 and the transition process of the processor 101. Therefore, the processor system 100 can further save power.

  Further, the processor 101 can receive an input / output interrupt in a power saving state. As a result, the processor 101 can execute the executable task 110 registered in the ready queue 103 without passing through the controller 102 when the input / output processing ends.

  That is, the processor system 100 of this embodiment can leave the processor 101 in a power saving state for a long time. In addition, since the processor system 100 according to the present embodiment manages the timer queue 601 and the ready queue 103 by the controller 102 with a small amount of power consumption, the power consumption of the entire system can be reduced. In addition, since the controller 102 manages the timer queue 601, the processor system 100 can maintain real-time characteristics.

  For these reasons, according to the processor system 100 according to the second embodiment, it is possible to achieve power saving of the entire system while guaranteeing real-time performance.

(Embodiment 3)
In the first and second embodiments, the case where one processor 101 exists in the processor system 100 has been described. In the third embodiment, a case where a plurality of processors 101 exist in the processor system 100 will be described.

  Here, as a form of the processor system 100 having the plurality of processors 101, there is a form in which the processor system 100 executes one OS. In this embodiment, there is one ready queue 103 for the OS, which is shared by a plurality of processors 101. Further, when the executable task 110 is registered in the ready queue 103, the controller 102 causes the plurality of processors 101 to transition to the activated state. As a result, one processor 101 executes the executable task 110, and the remaining processors 101 shift to the power saving state.

  Further, as a form of the processor system 100 having the plurality of processors 101, there is a form in which the processor system 100 executes a plurality of OSs. In this embodiment, there are a plurality of ready queues 103 for the OS, and each of the plurality of processors 101 has a corresponding ready queue 103. Further, when the executable task 110 is registered in one ready queue 103, the controller 102 causes the processor 101 corresponding to the ready queue 103 in which the executable task 110 is registered to transition to an activated state. As a result, one processor 101 executes the executable task 110, and the remaining processors 101 remain in the power saving state.

  It should be noted that the processor system 100 having a plurality of processors 101 executes a plurality of OSs, and there may be one controller 102 or a plurality corresponding to the number of processors 101. When there is one controller 102, the controller 102 updates the plurality of ready queues 103. When there are a plurality of controllers 102, the controller 102 updates the corresponding ready queue 103.

  As described above, according to the processor system 100 according to the third embodiment, even when there are a plurality of processors 101, it is possible to achieve power saving of the entire system while guaranteeing real-time performance.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary note 1) a storage device having a ready queue for registering an executable task in a state where execution can be started;
A processor that transitions to a first power saving state that consumes less power than a first activation state that executes the executable task when the executable task is not registered in the ready queue;
A controller for executing an update process for updating the ready queue when a timer interrupt is received, and a transition process for causing the processor to transition to the first activation state when the executable task is registered in the ready queue; ,
A clock signal control circuit for outputting the timer interrupt to the controller at a predetermined cycle;
A processor system comprising:

(Supplementary Note 2) The storage device further includes a timer queue for registering an execution waiting task that is in a state where the execution can be started after a predetermined time has elapsed.
When the controller accepts the timer interrupt, the controller registers the waiting task that has been in a state where the predetermined time has passed and can start execution as the executable task in the ready queue. The processor system according to appendix 1, characterized by:

(Additional remark 3) When the said update process and the said transition process are performed, the said controller changes to the 2nd power saving state with less power consumption than the 2nd starting state which performs the said update process and the said transition process, The processor system according to appendix 1 or 2, wherein when the timer interrupt is accepted, the state transits to the second activation state.

(Supplementary note 4) The processor according to any one of supplementary notes 1 to 3, wherein the controller causes the processor to transition to the first activation state by outputting an interprocessor interrupt to the processor. system.

(Supplementary Note 5) The processor system according to any one of Supplementary Notes 1 to 4, wherein the processor transitions to the first activation state when an input / output interrupt is received.

(Supplementary Note 6) When there are a plurality of the processors and the plurality of processors share the ready queue, the controller moves the plurality of processors to the first processor when the executable task is registered in the ready queue. The processor system according to any one of appendices 1 to 5, wherein the processor system is shifted to an activated state.

(Supplementary note 7) When the controller has a plurality of processors and each of the processors has the corresponding ready queue, the executable task is registered when the executable task is registered in the ready queue. The processor system according to any one of appendices 1 to 5, wherein a processor corresponding to the ready queue is shifted to the first activation state.

(Supplementary note 8) a storage unit having a ready queue for registering an executable task in a state where execution can be started;
A first control unit that transitions to a first power saving state that consumes less power than a first activation state that executes the executable task when the executable task is not registered in the ready queue;
An update process for updating the ready queue when a timer interrupt is received, and a transition process for transitioning the first control unit to the first activation state when the executable task is registered in the ready queue. A second control unit to execute;
A clock signal control unit that outputs the timer interrupt to the second control unit at a predetermined cycle;
A semiconductor integrated circuit comprising:

(Supplementary Note 9) The storage unit further includes a timer queue for registering an execution waiting task that is in a state where execution can be started after a predetermined time has elapsed,
When the second control unit receives the timer interrupt, the second control unit further sets the ready queue as the executable task after the predetermined time has passed and is ready to start execution. 9. The semiconductor integrated circuit according to appendix 8, wherein

(Additional remark 10) When the said 2nd control part performs the said update process and the said transition process, the 2nd power saving state with less power consumption than the 2nd starting state which performs the said update process and the said transition process 10. The semiconductor integrated circuit according to appendix 8 or 9, wherein when the timer interrupt is accepted, the transition to the second activation state is made.

(Supplementary Note 11) The second control unit causes the first control unit to transition to the first activation state by outputting an interrupt to the first control unit. 10. The semiconductor integrated circuit according to claim 10.

DESCRIPTION OF SYMBOLS 100 Processor system 101 Processor 102 Controller 103 Ready queue 104 Clock signal control circuit 201 Clock signal generation circuit 202 Memory 203 I / O interface 401 Reception part 402 Update part 403 Determination part 404 Output part 601 Timer queue

Claims (11)

A storage device having a ready queue for registering an executable task in a state where execution can be started;
A processor that transitions to a first power saving state that consumes less power than a first activation state that executes the executable task when the executable task is not registered in the ready queue;
A controller for executing an update process for updating the ready queue when a timer interrupt is received, and a transition process for causing the processor to transition to the first activation state when the executable task is registered in the ready queue; ,
A clock signal control circuit for outputting the timer interrupt to the controller at a predetermined cycle;
A processor system comprising: The storage device further includes a timer queue for registering a task waiting to be executed in a state where execution can be started after a predetermined time has elapsed,
When the controller accepts the timer interrupt, the controller registers the waiting task that has been in a state where the predetermined time has passed and can start execution as the executable task in the ready queue. The processor system according to claim 1.   When the controller executes the update process and the transition process, the controller makes a transition to a second power saving state that consumes less power than a second startup state that executes the update process and the transition process, and 3. The processor system according to claim 1, wherein the processor system shifts to the second activation state when the reception is accepted. 4.   The processor system according to claim 1, wherein the controller causes the processor to transition to the first activation state by outputting an inter-processor interrupt to the processor.   5. The processor system according to claim 1, wherein, when an input / output interrupt is received, the processor transitions to the first activation state. 6.   The controller transitions the plurality of processors to the first activation state when the executable task is registered in the ready queue when the plurality of processors exist and the plurality of processors share the ready queue. The processor system according to any one of claims 1 to 5, wherein:   The controller includes the ready queue in which the executable task is registered when the executable task is registered in the ready queue when the plurality of processors are present and the plurality of processors have the corresponding ready queues. The processor system according to claim 1, wherein a processor corresponding to is transitioned to the first activation state. A storage unit having a ready queue for registering an executable task in a state where execution can be started;
A first control unit that transitions to a first power saving state that consumes less power than a first activation state that executes the executable task when the executable task is not registered in the ready queue;
An update process for updating the ready queue when a timer interrupt is received, and a transition process for transitioning the first control unit to the first activation state when the executable task is registered in the ready queue. A second control unit to execute;
A clock signal control unit that outputs the timer interrupt to the second control unit at a predetermined cycle;
A semiconductor integrated circuit comprising: The storage unit further includes a timer queue for registering a task waiting to be executed in a state where execution can be started after a predetermined time has elapsed,
When the second control unit receives the timer interrupt, the second control unit further sets the ready queue as the executable task after the predetermined time has passed and is ready to start execution. 9. The semiconductor integrated circuit according to claim 8, wherein the semiconductor integrated circuit is registered.   When the second control unit executes the update process and the transition process, the second control unit transitions to a second power saving state that consumes less power than a second startup state that executes the update process and the transition process. 10. The semiconductor integrated circuit according to claim 8, wherein when the timer interrupt is accepted, the state transits to the second activation state.   The said 2nd control part makes the said 1st control part change to the said 1st starting state by outputting interruption to the said 1st control part, The any one of Claims 8-10 characterized by the above-mentioned. A semiconductor integrated circuit according to any one of the above.

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