JP2015008423A - Differential receiver, electronic apparatus using the same, and industrial equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a large differential amplitude at input ends of a comparator.SOLUTION: A differential receiver comprises: a comparator 10 which has a first terminal + and a second terminal -, and compares respective voltages of the first terminal + and the second terminal -; first input resistance Ri1 which has one end connected to a first input terminal INP and the other end connected to the first terminal + of the comparator 10; second input resistance Ri2 which has one end connected to a second input terminal INN and the other end connected to the second terminal - of the comparator 10; first divided resistance Rd1 which has one end connected to the first terminal of the comparator 10 and the other end connected to a termination node 12; second divided resistance Rd2 which has one end connected to the second terminal of the comparator 10 and the other end connected to the termination node 12; and a termination voltage adjustment part 30 which adjusts a termination voltage Vof the termination node 12 in such a manner that a midpoint voltage Vbetween a voltage Vof the first terminal and a voltage Vof the second terminal of the comparator 10 coincides with a reference voltage V.

Description

  The present invention relates to a differential receiver.

As a standard for high-speed serial transmission of a digital signal, a communication method using a differential signal such as RS485 standard, RS422, or LVDS (Low Voltage Differential Signaling) standard has been proposed. FIG. 1 is a circuit diagram of a differential receiver investigated by the present inventors. The differential receiver 2r receives the differential signals S _{IN +} and S _IN− input to the input terminals INP and INN, and corresponds to the magnitude relationship between the differential amplitude ΔV = S _{IN +} −S _IN− and a predetermined threshold value. An output signal S _OUT is generated.

Differential receiver 2r, while operated by receiving a predetermined power supply voltage _{V DD} and ground voltage _{V SS,} input terminal INP, the common voltage of the differential signal input to the INN (called input common _{voltage), V DD} A level outside the range of ~ V _SS may be taken.

For example, when V _DD = 5 V and the ground voltage V _SS = 0 V, the common voltage of the differential signal can vary within a range of −7 V to +12 V. In this case, if the differential signals S _{IN +} and S _IN− are directly input to the comparator 10, their voltage levels can be outside the input voltage range of the comparator 10, and thus voltage comparison cannot be performed correctly. Therefore, the differential receiver 2 r includes a resistance network 120 in front of the comparator 10. The resistor network 120 includes input resistors R1 _P and R1 _N , pull-up resistors Ru _P and Ru _N , and pull-down resistors Rd _P and Rd _N.

According to the differential receiver 2r of FIG. 1, the differential signals S _{IN +} and S _IN− are compressed within the input voltage range of the comparator 10 by appropriately setting the voltage dividing ratio of the resistor network 120, and the difference is _detected by the comparator 10. The motion signals S _{IN +} and S _IN− can be compared.

In the differential receiver 2r of FIG. 1, the voltage division ratio to be set in the resistor network 120 is determined based on the relationship between the input voltage range of the comparator 10 and the common voltage fluctuation range (input common voltage range) of the differential input signal. . Specifically, when the input voltage range of the comparator 10 is narrow, in other words, when the power supply voltage V _DD is low, the voltage division ratio increases, and when the common voltage fluctuation range is large, the voltage division ratio also increases.

Here, when the voltage dividing ratio increases, not only the common voltage of the differential signals S _{IN +} and S _IN− but also the differential amplitude is compressed. Since the differential amplitude is on the order of several hundred mV, for example, about 200 mV, when it is compressed by the partial pressure, the comparator 10 has a differential signal S _{IN +} ′, S having a small differential amplitude of several tens mV. _IN- 'is input. That is, there is a problem that the degree required for the comparator 10 becomes high.

  The present invention has been made in view of such circumstances, and one of the exemplary purposes of an aspect thereof is to provide a differential receiver capable of ensuring a large differential amplitude at the input end of a comparator.

  One embodiment of the present invention relates to a differential receiver. The differential receiver has a first input terminal and a second input terminal to which a differential signal is input, a first terminal and a second terminal, and a comparator for comparing voltages of the first terminal and the second terminal, The terminal node, one end connected to the first input terminal, the other end connected to the first terminal of the comparator, one end connected to the second input terminal, the other end connected to the second terminal of the comparator A second input resistor connected to the first terminal, one end connected to the first terminal of the comparator, the other end connected to the termination node, one end connected to the second terminal of the comparator, the other end Is connected to the termination node, a reference voltage source that generates a reference voltage, a voltage at the first terminal of the comparator, and a midpoint voltage of the voltage at the second terminal to match the reference voltage, Termination voltage adjustment to adjust termination voltage of termination node It comprises a part, a.

  According to this aspect, the voltage dividing ratio can be increased by dynamically controlling the termination voltage of the termination node in accordance with the common voltage of the differential signal, and thereby a large differential at the input terminal of the comparator. Amplitude can be secured. In addition, when common mode noise is input, the termination voltage is adjusted by the termination voltage adjustment unit following the common mode noise, so the common mode noise can be canceled and the noise immunity can be improved. Can do.

  The termination voltage adjusting unit may include an error amplifier in which the reference voltage is input to the first terminal, the midpoint voltage is input to the second terminal, and the output terminal is connected to the termination node.

  The termination voltage adjusting unit may further include a voltage dividing circuit that divides voltages of the first terminal and the second terminal of the comparator to generate a midpoint voltage.

  The voltage dividing circuit includes a third voltage dividing resistor and a fourth voltage dividing resistor provided in series between the first terminal and the second terminal of the comparator, and a connection point between the third voltage dividing resistor and the fourth voltage dividing resistor. May be a midpoint voltage.

The voltage dividing circuit includes a first buffer including a first transistor having a control terminal connected to the first terminal of the comparator, a second buffer including a second transistor having a control terminal connected to the second terminal of the comparator, And a third voltage dividing resistor and a fourth voltage dividing resistor provided in series between the emitter / source of one transistor and the emitter / source of the second transistor, the third voltage dividing resistor and the fourth voltage dividing resistor. The potential at the connection point may be a midpoint voltage.
According to this aspect, the first transistor and the second transistor can increase the impedance when the terminal voltage adjusting unit side is viewed from the input terminal of the comparator. Thereby, the resistance values of the third voltage dividing resistor and the fourth voltage dividing resistor can be reduced.

  The termination voltage adjusting unit may further include a capacitor connected to the termination node.

  Another embodiment of the present invention relates to an electronic device. The electronic device may include any of the above-described differential receivers.

  Another aspect of the present invention relates to industrial equipment. The industrial device may include any of the differential receivers described above.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the differential amplitude of a large differential signal can be ensured at the input end of the comparator.

It is a circuit diagram of a differential receiver examined by the present inventors. It is a circuit diagram of the differential receiver which concerns on embodiment. 3 is a level diagram of the differential receiver of FIG. 4A and 4B are block diagrams of an electronic device and an industrial device including the differential receiver according to the embodiment. It is a circuit diagram of the differential receiver which concerns on a 1st modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

FIG. 2 is a circuit diagram of the differential receiver 2 according to the embodiment. The differential receiver 2 includes a first input terminal INP, a second input terminal INN, a comparator 10, a termination node 12, a first input resistor Ri1, a second input resistor Ri2, a first voltage dividing resistor Rd1, and a second voltage dividing resistor Rd2. A reference voltage source 20 and a termination voltage adjusting unit 30. The differential receiver 2 operates by receiving the power supply voltages V _DD and V _SS . Hereinafter, it is assumed that the upper power supply voltage V _DD = 5V and the lower power supply voltage V _SS = 0V.

Differential signals S _{IN +} and S _IN− transmitted from a differential transmitter (not shown) and transmitted via a differential transmission path are input to the first input terminal INP and the second input terminal INN. The comparator 10 has a first terminal (non-inverting input terminal +) and a second terminal (inverting input terminal −), compares the voltage S _{IN +} ′ of the first terminal with the voltage S _IN− ′ of the second terminal, An output signal S _OUT indicating the comparison result is generated.

  One end of the first input resistor Ri1 is connected to the first input terminal INP, and the other end is connected to the non-inverting input terminal + of the comparator 10. One end of the second input resistor Ri2 is connected to the second input terminal INN, and the other end is connected to the inverting input terminal − of the comparator 10.

  One end of the first voltage dividing resistor Rd1 is connected to the non-inverting input terminal + of the comparator 10, and the other end is connected to the termination node 12. One end of the second voltage dividing resistor Rd2 is connected to the inverting input terminal − of the comparator 10, and the other end is connected to the termination node 12.

The reference voltage source 20 generates a reference voltage _VREF .

The termination voltage adjusting unit 30 terminates the termination node 12 so that the midpoint voltage V _COM of the voltage V _{IN +} of the non-inverting input terminal + and the voltage of the inverting input terminal V _IN− of the comparator 10 matches the reference voltage V _REF. adjusting the voltage _{V T.}

The termination voltage adjusting unit 30 includes an error amplifier 32, a voltage dividing circuit 34, and a capacitor C1. The voltage dividing circuit 34 divides the input voltages V _{IN +} and V _IN− of the comparator 10 to generate a midpoint voltage V _COM at the input end of the comparator 10. For example voltage divider circuit 34 includes a third divider resistor Rd3 and fourth divider resistor Rd4 resistance values are equal, may the voltage of their connecting point as the midpoint voltage V _COM. The resistance values of the third voltage dividing resistor Rd3 and the fourth voltage dividing resistor Rd4 are preferably determined so that the impedance when the terminal voltage adjusting unit 30 side is viewed from the input end of the comparator 10 is sufficiently high.

The reference voltage V _REF is input to the first terminal (non-inverting input terminal +) of the error amplifier 32, the midpoint voltage V _COM is input to the second terminal (inverting input terminal −), and the output terminal is Connected to the end node 12. The error amplifier 32 amplifies an error between the reference voltage V _REF and the midpoint voltage V _COM and applies a termination voltage V _T corresponding to the error to the termination node 12.

Capacitor C1 is connected to termination node 12 and stabilizes termination voltage V _T.

The reference voltage V _REF is preferably set within the input voltage range of the comparator 10.
When the comparator 10 operates in response to the power supply voltages V _DD = 5V and V _SS = 0V, the input voltage range of the comparator 10, that is, the voltage range in which voltage comparison is possible is slightly smaller than the range of V _{SS to} V _DD. Narrow range V _SS + V _{FR to} V _DD −V _HR . V _FR is a footroom, and V _HR is a headroom, which are about several hundred mV to 1 V, for example. When V _FR = V _HR = 1V, the input voltage range of the comparator 10 is 1 to 4V, and therefore it is desirable to set the reference voltage V _REF within this range.

More preferably, the reference voltage V _REF is set to a voltage range in which the gain of the comparator 10 is increased. The input voltage at which the comparator 10 has the highest gain is, for example, around the midpoint voltage (V _DD + V _SS ) / 2 of V _DD and V _SS , depending on the configuration. In this case, the reference voltage V _REF may be a voltage near (V _DD + V _SS ) / 2.

In the differential receiver 2, when the power supply voltages V _DD and V _SS can fluctuate, it is desirable that the reference voltage V _REF works with the power supply voltages V _DD and V _SS of the comparator 10. In this case, the reference voltage source 20 may generate the reference voltage V _REF by dividing the power supply voltages V _DD and V _SS . For example, the reference voltage source 20 may include resistors Rd5 and Rd6 provided in series between two power supply lines. If the resistance value of the resistor Rd5, Rd6 are equal, the reference voltage _{V REF,} the two of the power supply voltage _{V DD,} the midpoint of _{V SS.}

The above is the configuration of the differential receiver 2. Next, the operation will be described.
The termination voltage adjusting unit 30 forms a feedback loop, and adjusts the termination voltage V _T of the termination node 12 so that the common voltage V _COM matches the reference voltage V _REF .

That is, even _if the common voltage V _COM ′ of the differential signals S _{IN +} and S _IN− changes, the common voltage V _COM at the input terminal of the comparator 10 is stabilized to the reference voltage V _REF .

According to the differential receiver 2, the following effects can be obtained.
FIG. 3 is a level diagram of the differential receiver 2 of FIG. The horizontal axis represents the partial pressure ratio α = Rd1 / (Ri1 + Rd1) = Rd2 / (Ri2 + Rd2). α = 100% indicates a voltage level at the first input terminal INP and the second input terminal INN. α = 0% corresponds to the termination voltage V _T at the termination node 12.

  The input voltage range of the comparator 10 is 1V to 4V, and the input common voltage range is -7 to 12V.

For First comparison, a case which is fixed to 2.5V which is the midpoint of the input common voltage range -7~12V a termination voltage _{V T.} This is equivalent to the operation of the comparative technique shown in FIG. In this case, in order to compress all the input common voltage range −7 to 12V to the input voltage range 1 to 4V of the comparator 10, it is understood that the voltage division ratio α may be set to 15.7%. In this case, the differential amplitude is also compressed to 15.7%. When the original differential amplitude is 200 mV, the compressed differential amplitude is about 31 mV.

Next, the case where the termination voltage V _T is variable in the range of 0 to 5 V in the differential receiver 2 of FIG. 2 will be described. In this case, in order to compress all the input common voltage range −7 to 12V to the input voltage range 1 to 4V of the comparator 10, it is understood that the voltage dividing ratio α may be 33.3%. In this case, the differential amplitude is compressed to 33.3%, and when the original differential amplitude is 200 mV, the compressed differential amplitude is about 62 mV.

Thus, according to the differential receiver 2 according to the embodiment, ₊ differential signal S _IN, in accordance with the common voltage of the S _IN- (input common voltage), dynamically termination voltage V _T of the terminal nodes 12 By controlling, the partial pressure ratio α can be increased as compared with the comparative technique. Thereby, a large differential amplitude can be secured at the input terminal of the comparator 10.

  Or, from the opposite viewpoint, when the same differential amplitude as that of the comparison technique is obtained at the input terminal of the comparator 10, the range of the input common voltage can be expanded as compared with the comparison technique.

In addition, when common mode noise is input to the first input terminal INP and the second input terminal INN, the termination voltage adjusting unit 30 adjusts the termination voltage V _T following the common mode noise. Thereby, common mode noise can be canceled and the noise tolerance of the differential receiver 2 can be improved.

Also the provision of the capacitor C1, can stabilize the termination voltage V _T, thereby preventing a decrease in the reception rate caused by the fluctuation of the terminal voltage V _T.

When the power supply voltages V _DD and V _SS change, the input voltage range of the comparator 10 changes accordingly. In the differential receiver 2 of FIG. 2, since the reference voltage source 20 is configured by a voltage dividing circuit, the reference voltage V _REF, that is, the termination voltage V _T follows the power supply voltages V _DD and V _SS , so that the power supply voltage V _DD , regardless of the level of V _SS, the input common voltage range, it can be compressed into the input voltage range of the comparator 10.

  Next, the application of the differential receiver 2 will be described. 4A and 4B are block diagrams of an electronic device and an industrial device including the differential receiver according to the embodiment.

  The electronic device 500 in FIG. 4A includes an interface that conforms to the LVDS standard or the DisplayPort standard. For example, the electronic device 500 is a notebook PC (Personal Computer), a smartphone, or a tablet terminal that includes a liquid crystal display.

  The electronic device 500 includes a liquid crystal panel 502, a driver IC 504, a timing controller IC 506, and an image processing IC 508. The image processing IC 508 generates image data to be displayed on the liquid crystal panel 502 and transmits it to the timing controller IC 506. The timing controller IC 506 receives the image data from the image processing IC 508, optimizes the timing for each line and each pixel with respect to the liquid crystal panel 502, and transmits it to the driver IC 504. The driver IC 504 drives the liquid crystal panel 502 based on the image data from the timing controller IC 506.

  In such an electronic device 500, differential signals are used for data transmission between the image processing IC 508 and the timing controller IC 506 and between the timing controller IC 506 and the driver IC 504. Therefore, the differential receiver 2 according to the embodiment can be mounted on the reception interface of the driver IC 504 and the reception interface of the timing controller IC 506.

  4B constitutes a network system 600 formed in a relatively wide range such as a factory. The network system 600 includes a plurality of industrial devices 602 and a host device 604. The industrial device 602 and the host device 604 comply with the RS-422 and RS-485 standards, and they transmit / receive data to / from each other. The type of the industrial device 602 is not particularly limited.

  The differential receiver 2 according to the embodiment can be suitably used for such a network system 600. The host device 604 includes a differential transmitter 606. The industrial device 602 includes the differential receiver 2 according to the embodiment. The plurality of differential receivers 2 and the differential transmitter 606 are connected via a common bus 608.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

(First modification)
FIG. 5 is a circuit diagram of the differential receiver 2a according to the first modification.
The differential receiver 2a of FIG. 5 differs from the differential receiver 2 of FIG. 2 in the configuration of the termination voltage adjusting unit 30a. The termination voltage adjusting unit 30a includes a first buffer B1 and a second buffer B2 in addition to the third voltage dividing resistor Rd3 and the fourth voltage dividing resistor Rd4.

The first buffer B1 and the second buffer B2 are source followers or emitter followers, and each include a first transistor Q1 and a second transistor Q2 that are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or bipolar transistors.
The first buffer B1 includes a first transistor Q1 having a control terminal, that is, a gate (base) connected to the first terminal (non-inverting input terminal +) of the comparator 10. A first current source CS1 that is a load is connected to a source (emitter) of the first transistor Q1. The second buffer B2 includes a second transistor Q2 and a second current source CS2, and is configured in the same manner as the first buffer B1. A resistive load may be connected instead of the first current source CS1 and the second current source CS2, and the configurations of the first buffer B1 and the second buffer B2 are not particularly limited.

  The third voltage dividing resistor Rd3 and the fourth voltage dividing resistor Rd4 are provided between the output terminal of the first buffer B1 and the output terminal of the second buffer B2, in other words, the emitter (source) of the first transistor Q1 and the second transistor. It is provided in series between the emitters (sources) of Q2.

A third dividing resistor Rd3 potential at the connection point of the fourth divider resistor Rd4 is the midpoint voltage _{V COM.}

  According to this modification, the first buffer B1 and the second buffer B2 can increase the impedance when the termination voltage adjusting unit 30a side is viewed from the input end of the comparator 10. As a result, the resistance values of the third voltage dividing resistor Rd3 and the fourth voltage dividing resistor Rd4 can be reduced.

(Second modification)
In the embodiment, the case where the reference voltage source 20 is configured by a voltage dividing circuit has been described, but the present invention is not limited thereto. In the differential receiver 2, when the power supply voltages V _DD and V _SS are stabilized at a predetermined level, the voltage level of the reference voltage V _REF is a predetermined value (for example, 2.5 V) that does not depend on the power supply voltages V _DD and V _SS. It may be fixed to. In this case, the reference voltage source 20 can be configured by a combination of a bandgap reference circuit and a linear regulator.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 2 ... Differential receiver, INP ... 1st input terminal, INN ... 2nd input terminal, 10 ... Comparator, 12 ... Termination node, Ri1 ... 1st input resistance, Ri2 ... 2nd input resistance, Rd1 ... 1st voltage dividing resistance , Rd2 ... second voltage dividing resistor, Rd3 ... third voltage dividing resistor, Rd4 ... fourth voltage dividing resistor, 20 ... reference voltage source, 30 ... termination voltage adjusting unit, 32 ... error amplifier, 34 ... voltage dividing circuit, B1 ... first buffer, B2 ... second buffer, C1 ... capacitor, Q1 ... first transistor, Q2 ... second transistor, CS1 ... first current source, CS2 ... second current source, 500 ... electronic device, 502 ... liquid crystal panel 504: Driver IC, 506 Timing controller IC, 508 Image processing IC, 600 Network system, 602 Industrial equipment, 604 Host equipment, 606 Differential transmitter, 08 ... bus.

Claims (11)

A first input terminal and a second input terminal to which a differential signal is input;
A comparator having a first terminal and a second terminal for comparing voltages of the first terminal and the second terminal;
A terminal node;
A first input resistor having one end connected to the first input terminal and the other end connected to the first terminal of the comparator;
A second input resistor having one end connected to the second input terminal and the other end connected to the second terminal of the comparator;
A first voltage dividing resistor having one end connected to the first terminal of the comparator and the other end connected to the termination node;
A second voltage dividing resistor having one end connected to the second terminal of the comparator and the other end connected to the termination node;
A reference voltage source for generating a reference voltage;
A termination voltage adjusting unit that adjusts a termination voltage of the termination node such that a midpoint voltage of the voltage of the first terminal and the voltage of the second terminal of the comparator matches the reference voltage;
A differential receiver comprising:   The termination voltage adjusting unit includes an error amplifier in which the reference voltage is input to a first terminal, the midpoint voltage is input to a second terminal, and an output terminal thereof is connected to the termination node. The differential receiver according to claim 1.   3. The voltage termination circuit according to claim 1, further comprising a voltage dividing circuit that divides voltages of the first terminal and the second terminal of the comparator to generate the midpoint voltage. The described differential receiver.   The voltage dividing circuit includes a third voltage dividing resistor and a fourth voltage dividing resistor provided in series between the first terminal and the second terminal of the comparator, and the third voltage dividing resistor and the fourth voltage dividing resistor are provided. The differential receiver according to claim 3, wherein a potential at a connection point of the voltage dividing resistor is the midpoint voltage. The voltage dividing circuit includes:
A first buffer including a first transistor having a control terminal connected to the first terminal of the comparator;
A second buffer including a second transistor having a control terminal connected to the second terminal of the comparator;
A third voltage dividing resistor and a fourth voltage dividing resistor provided in series between the emitter / source of the first transistor and the emitter / source of the second transistor;
The differential receiver according to claim 3, wherein a potential at a connection point between the third voltage dividing resistor and the fourth voltage dividing resistor is the midpoint voltage.   6. The differential receiver according to claim 1, wherein the reference voltage is set to a voltage range in which a gain of the input voltage range of the comparator is increased.   6. The differential receiver according to claim 1, wherein the reference voltage is interlocked with a power supply voltage of the comparator.   The differential receiver according to claim 7, wherein the reference voltage source divides a power supply voltage of the comparator to generate the reference voltage.   The differential receiver according to claim 1, wherein the termination voltage adjusting unit further includes a capacitor connected to the termination node.   An industrial device comprising the differential receiver according to claim 1.   An electronic apparatus comprising the differential receiver according to claim 1.

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