JP2015008330A - Semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element with high efficiency and a low operating voltage.SOLUTION: In a semiconductor light-emitting element 110 including an n-type semiconductor layer, a p-type semiconductor layer 50, a light-emitting part 40, and a p-side electrode, the light-emitting part 40 is provided between the n-type semiconductor layer and the p-type semiconductor layer 50, and includes a plurality of barrier layers and well layers provided between the plurality of barrier layers. The p-type semiconductor layer 50 includes first to fourth p-type layers 51, 52, 53, and 54. The first p-type layer 51 is in contact with the p-side electrode and includes a p-type impurity at a first concentration. The second p-type layer 52 is in contact with the light-emitting part 40 between the first p-type layer 51 and the light-emitting part 40, contains Al, and includes a p-type impurity at a second concentration lower than the first concentration. The third p-type layer 53 is provided between the first p-type layer 51 and the second p-type layer 52 and includes a p-type impurity at a third concentration lower than the second concentration. The fourth p-type layer 54 is provided between the second p-type layer 52 and the third p-type layer 53, and the concentration of a p-type impurity gradually decreases along a direction from the n-type semiconductor layer to the p-type semiconductor layer from the second concentration to the third concentration.

Description

  Embodiments described herein relate generally to a semiconductor light emitting device.

  Application of nitride semiconductors to develop semiconductor light emitting devices such as ultraviolet, blue and green light emitting diodes (LEDs) and blue-violet, blue and green laser diodes (LDs). Has been.

  In order to increase the efficiency of the semiconductor light emitting device, it is important to increase the crystallinity of the semiconductor layer, reduce the non-radiative recombination centers, and increase the internal quantum efficiency. In addition, the activation rate of the p-type impurity in the semiconductor layer is low. For this reason, the density of holes tends to be low. There is a need to improve hole injection efficiency. In addition, a reduction in operating voltage is required for semiconductor light emitting devices.

Japanese Patent No. 3314666

  Embodiments of the present invention provide a semiconductor light emitting device with high efficiency and low operating voltage.

  According to an embodiment of the present invention, a semiconductor light emitting device including an n-type semiconductor layer, a p-type semiconductor layer, a light emitting unit, and a p-side electrode is provided. The light emitting unit is provided between the n-type semiconductor layer and the p-type semiconductor layer. The p-side electrode is provided on the p-type semiconductor layer. The p-type semiconductor layer includes a first p-type layer, a second p-type layer, a third p-type layer, and a fourth p-type layer. The first p-type layer includes a p-type impurity at a first concentration and is provided on the p-side electrode side. The second p-type layer includes Al, includes a p-type impurity at a second concentration lower than the first concentration, and is provided on the light emitting unit side. The third p-type layer is provided between the first p-type layer and the second p-type layer, and includes a p-type impurity at a third concentration lower than the second concentration. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The concentration of the p-type impurity in the fourth p-type layer gradually decreases from the second concentration to the third concentration along a first direction from the n-type semiconductor layer toward the p-type semiconductor layer. The thickness of the third p-type layer is not less than 10 nanometers and not more than 80 nanometers. The third concentration is not less than 0.05 times and not more than 0.8 times the second concentration. As for the third concentration, the p-type impurity concentration in the third p-type layer is constant so that the variation of the third concentration is within ± 20% of the average of the third concentration.

It is a mimetic diagram showing a semiconductor light emitting element concerning an embodiment. It is a typical sectional view showing a semiconductor light emitting element concerning an embodiment. It is a typical sectional view showing some semiconductor light emitting elements concerning an embodiment. It is a typical sectional view showing some semiconductor light emitting elements concerning an embodiment. It is a graph which shows the structure of the semiconductor light-emitting device which concerns on embodiment. FIG. 6A to FIG. 6C are schematic views showing a semiconductor light emitting device of a reference example. FIG. 7A to FIG. 7C are schematic views showing a semiconductor light emitting device of a reference example. FIG. 8A and FIG. 8B are schematic views showing a semiconductor light emitting device of a reference example. It is a graph which shows the characteristic of a semiconductor light-emitting device.

Each embodiment will be described below with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(Embodiment)
FIG. 1 is a schematic view illustrating the configuration of the semiconductor light emitting device according to the embodiment.
FIG. 2 is a schematic cross-sectional view illustrating the configuration of the semiconductor light emitting element according to the embodiment.
FIG. 3 is a schematic cross-sectional view illustrating the configuration of a part of the semiconductor light emitting element according to the embodiment. FIG. 4 is a schematic cross-sectional view illustrating the configuration of a part of the semiconductor light emitting element according to the embodiment. First, the outline of the configuration of the semiconductor light emitting device according to the embodiment will be described with reference to FIG.

As shown in FIG. 2, the semiconductor light emitting device 110 according to the embodiment includes an n-type semiconductor layer 20, a p-type semiconductor layer 50, a light emitting unit 40, and a p-side electrode 80.
The light emitting unit 40 is provided between the n-type semiconductor layer 20 and the p-type semiconductor layer 50. The light emitting unit 40 includes a plurality of barrier layers and a well layer provided between the plurality of barrier layers. An example of the configuration of the light emitting unit 40 will be described later. The p-side electrode 80 is in contact with the p-type semiconductor layer 50.

  Here, the direction from the n-type semiconductor layer 20 toward the p-type semiconductor layer 50 is defined as a + Z direction (first direction).

  The p-type semiconductor layer 50 includes a first p-type layer 51, a second p-type layer 52, a third p-type layer 53, and a fourth p-type layer 54.

  The first p-type layer 51 is in contact with the p-side electrode 80. The second p-type layer 52 is in contact with the light emitting unit 40 between the first p-type layer 51 and the light emitting unit 40. The third p-type layer 53 is provided between the first p-type layer 51 and the second p-type layer 52. The fourth p-type layer 54 is provided between the second p-type layer 52 and the third p-type layer 53.

  The second p-type layer 52 includes Al. For the second p-type layer 52, for example, an AlGaN layer is used. The second p-type layer 52 can function, for example, as an electron overflow suppression layer (electron overflow prevention layer). The first p-type layer 51 functions as a contact layer with the p-side electrode 80. As the first p-type layer 51, the third p-type layer 53, and the fourth p-type layer 54, for example, a GaN layer is used.

  The first p-type layer 51, the second p-type layer 52, the third p-type layer 53, and the fourth p-type layer 54 contain p-type impurities. For example, Mg (magnesium) is used as the p-type impurity. The embodiment is not limited to this, and other elements may be used as the p-type impurity. That is, at least one of Mg, Zn, and C can be used as the p-type impurity.

  The n-type semiconductor layer 20 can include, for example, an n-type guide layer 22 and an n-type contact layer 21. The n-type guide layer 22 is provided between the n-type contact layer 21 and the light emitting unit 40. For the n-type guide layer 22, for example, a GaN layer is used. As the n-type contact layer 21, a GaN layer containing n-type impurities is used. For example, Si (silicon) is used as the n-type impurity. The embodiment is not limited to this, and other elements may be used as the n-type impurity. That is, at least one of Si, Ge, Te, and Sn can be used for the n-type impurity.

  For example, a multilayer stack (not shown) may be further provided between the n-type semiconductor layer 20 and the light emitting unit 40. The multilayer laminate includes a plurality of thick film layers and a plurality of thin film layers that are alternately laminated along the + Z direction. The thin film layer has a thickness that is less than the thickness of the thick film layer. The thin film layer has a composition different from that of the thick film layer. The multilayer laminate has a superlattice structure, for example. The multilayer laminate is provided as necessary and can be omitted in some cases.

  Thus, in the semiconductor light emitting device 110, the stacked structure 10s including the n-type semiconductor layer 20, the light emitting unit 40, and the p-type semiconductor layer 50 is provided. In this example, a part of the laminated structure 10s on the first main surface 10a side is selectively removed. Thereby, a part of the n-type semiconductor layer 20 (specifically, the n-type contact layer 21) is exposed on the first main surface 10a side. An n-side electrode 70 is provided on the exposed portion. The n-side electrode 70 is in contact with the n-type semiconductor layer 20. The embodiment is not limited thereto, and the n-side electrode 70 may be provided on the second main surface 10b side of the n-type semiconductor layer 20. The second main surface 10b is a surface opposite to the first main surface 10a of the laminated structure 10s. As the n-side electrode 70, for example, a composite film of titanium-platinum-gold (Ti / Pt / Au) is used. The thickness of the Ti film is, for example, about 0.05 μm (micrometer). The thickness of the Pt film is about 0.05 μm, for example. The thickness of the Au film is about 1.0 μm, for example.

For the p-side electrode 80, for example, indium tin oxide (ITO) is used. That is, the p-side electrode 80 includes a metal oxide and can transmit light emitted from the light emitting unit 40.
The p-side electrode 80 can be a composite film such as nickel-gold (Ni / Au).

  The semiconductor light emitting device 110 further includes a substrate 10 and a buffer layer 11. The substrate 10 and the buffer layer 11 are provided as necessary and may be omitted.

  For the substrate 10, for example, sapphire, GaN, SiC, Si, and GaAs are used. A buffer layer 11 is formed on the substrate 10. For example, a GaN layer is used for the buffer layer 11. On the buffer layer 11, an n-type semiconductor layer 20, a light emitting unit 40, and a p-type semiconductor layer 50 are sequentially formed. The substrate 10 may be removed after the laminated structure 10s is formed on the buffer layer 11.

FIG. 3 shows an example of the configuration of the light emitting unit 40.
As illustrated in FIG. 3, the light emitting unit 40 includes a plurality of barrier layers BL and a well layer WL provided between the plurality of barrier layers BL.

  In this example, there are four well layers WL. However, the embodiment is not limited to this. The number of well layers WL is two or more and is arbitrary. In this example, a plurality of well layers WL are provided. That is, the light emitting unit 40 in this specific example has a multiple quantum well (MQW) structure.

  The multiple well layers WL include a first well layer WL1 to an nth well layer WLn. Here, “n” is an integer of 2 or more. For example, the (i + 1) th well layer WL (i + 1) is provided between the i-th well layer WLi and the p-type semiconductor layer 50. Here, “i” is an integer of 1 or more.

  The plurality of barrier layers BL include a first barrier layer BL1 to an nth barrier layer BLn. For example, the (i + 1) th barrier layer BL (i + 1) is provided between the i-th barrier layer BLi and the p-type semiconductor layer 50.

  The i-th well layer WLi is provided between the i-th barrier layer BLi and the (i + 1) th barrier layer BL (i + 1). Further, the plurality of barrier layers BL have a (n + 1) th barrier layer BL (n + 1). The (n + 1) th barrier layer BL (n + 1) is, for example, a p-side barrier layer BLP.

  FIG. 4 illustrates the configuration of the light emitting unit 40 in another semiconductor light emitting device 111 according to this embodiment. The configuration of the semiconductor light emitting device 111 other than the light emitting unit 40 is the same as that of the semiconductor light emitting device 110 illustrated in FIG.

As shown in FIG. 4, in the semiconductor light emitting element 111, the light emitting unit 40 includes two barrier layers BL and one well layer WL. As described above, the light emitting unit 40 in the semiconductor light emitting device 111 may have a single quantum well (SQW) structure.
Thus, in the embodiment, the MQW structure or the SQW structure is adopted.

  Hereinafter, the semiconductor light emitting device 110 having the MQW structure will be described. However, the following description is also applied to the semiconductor light emitting device 111 having the SQW structure.

  Nitride semiconductors are used for the n-type semiconductor layer 20, the p-type semiconductor layer 50, and the light emitting unit 40. That is, the n-type semiconductor layer 20, the p-type semiconductor layer 50, and the light emitting unit 40 include a nitride semiconductor.

  The well layer WL can include InGaN, and the barrier layer BL can include GaN. The band gap energy of the barrier layer BL is larger than the band gap energy of the well layer WL.

  The barrier layer BL may not be doped with In. That is, the barrier layer BL does not substantially contain In. The In composition ratio in the group III element of the well layer WL is higher than the In composition ratio in the group III element of the barrier layer BL. That is, even when the barrier layer BL includes In, the In composition ratio of the barrier layer BL is lower than the In composition ratio of the well layer WL.

  The composition ratio of In in the group III element of the well layer WL is, for example, not less than 0.05 and not more than 0.3.

  The peak wavelength of light emitted from the light emitting unit 40 is 380 nanometers (nm) or more and 550 nm or less.

FIG. 1 is a graph illustrating the p-type impurity concentration in the p-type semiconductor layer 50.
In FIG. 1, the horizontal axis is the position Pz along the + Z direction. The vertical axis represents the p-type impurity concentration C (p). The vertical axis is, for example, the logarithm of the p-type impurity concentration C (p).

As shown in FIG. 1, the first p-type layer 51 includes a p-type impurity at the first concentration C1.
The second p-type layer 52 includes a p-type impurity at a second concentration C2 lower than the first concentration C1.
The third p-type layer 53 includes a p-type impurity at a third concentration C3 lower than the second concentration C2.
The p-type impurity concentration C (p) in the fourth p-type layer 54 gradually decreases from the second concentration C2 to the third concentration C3 along the + Z direction (the direction from the n-type semiconductor layer 20 toward the p-type semiconductor layer 50). .

That is, the p-type impurity concentration C (p) in the p-type semiconductor layer 50 gradually decreases in the fourth p-type layer 54 from the second concentration C2 of the second p-type layer 52 along the + Z direction. The third concentration C3 is the lowest in FIG. 2, and the first concentration C1 is the highest in the first p-type layer 51.
This provides a semiconductor light emitting device with high efficiency and low operating voltage.

  Note that the p-type impurity concentration C (p) in the fourth p-type layer 54 can change linearly along the + Z direction. Further, the p-type impurity concentration C (p) in the fourth p-type layer 54 may change in a curved manner. The p-type impurity concentration C (p) in the fourth p-type layer 54 may change stepwise in a plurality of steps along the + Z direction.

  In the above, the p-type impurity is, for example, Mg. That is, the first concentration C <b> 1 is the Mg concentration in the first p-type layer 51. The second concentration C2 is the Mg concentration in the second p-type layer 52. The third concentration C3 is the concentration of Mg in the third p-type layer 53. The p-type impurity concentration C (p) in the fourth p-type layer 54 is the Mg concentration in the fourth p-type layer 54.

  That is, for example, the first p-type layer 51 contains Mg at the first concentration C1. The second p-type layer 52 includes Mg at the second concentration C2. The third p-type layer 53 contains Mg at the third concentration C3. The Mg concentration in the fourth p-type layer 54 gradually decreases from the second concentration C2 to the third concentration C3 along the + Z direction.

The first concentration C1 is, for example, 2 × 10 ²⁰ cm ⁻³ or more. The second concentration C2 is, for example, not less than 2.5 × 10 ¹⁹ cm ^{−3 and} less than 2 × 10 ²⁰ cm ⁻³ . The third concentration C3 is, for example, 1 × 10 ¹⁹ cm ⁻³ or more and less than 2.5 × 10 ¹⁹ cm ⁻³ .
For example, the third concentration C3 is not less than 0.05 times and not more than 0.8 times the second concentration C2.

  In the above, the third p-type layer 53 is a layer having a substantially constant p-type impurity concentration C (p). The variation of the p-type impurity concentration C (p) in the third p-type layer 53 is, for example, within ± 20% of the average value of the third concentration C3.

  The concentration of the p-type impurity contained in each layer of the p-type semiconductor layer 50 can be measured by, for example, the secondary ion mass spectrometry (SIMS) method.

  Hereinafter, the semiconductor light emitting device 110a will be described. The semiconductor light emitting device 110 a is one specific example of the semiconductor light emitting device 110. The semiconductor light emitting device 110a has the configuration illustrated in FIG. The semiconductor light emitting device 110a was manufactured as follows.

First, the buffer layer 11 was formed on the sapphire substrate 10. An n-type GaN layer to be the n-type contact layer 21 was formed on the buffer layer 11. The n-type contact layer 21 has a thickness of about 4 μm. The concentration of the n-type impurity (Si in this specific example) in the n-type contact layer 21 is about 2 × 10 ¹⁸ cm ⁻³ .

A GaN layer to be the n-type guide layer 22 was formed on the n-type contact layer 21. The thickness of the n-type guide layer 22 is about 0.1 μm. The concentration of the n-type impurity in the n-type guide layer 22 is about 1 × 10 ¹⁸ cm ⁻³ .

  The growth temperature of the n-type contact layer 21 and the growth temperature of the n-type guide layer 22 are 1000 ° C. or more and 1100 ° C. or less.

In _0.01 Ga _0.99 N may be used as the n-type guide layer 22. At this time, the thickness of the n-type guide layer 22 is, for example, about 0.1 μm. When In _0.01 Ga _0.99 N is used as the n-type guide layer 22, the growth temperature of the n-type guide layer 22 is 700 ° C. or higher and 800 ° C. or lower.

A light emitting unit 40 was formed on the n-type guide layer 22. That is, an In _0.01 Ga _0.99 N layer serving as the barrier layer BL of the light emitting unit 40 and an In _0.15 Ga _0.85 N layer serving as the well layer WL were alternately formed. The thickness of the barrier layer BL is about 5 nm. The thickness of the well layer WL is about 2.5 nm. The well layer WL is undoped. In this specific example, the number of well layers WL is eight and the number of barrier layers BL is nine. The growth temperature of the barrier layer BL and the well layer WL is 700 ° C. or higher and 800 ° C. or lower. The barrier layer BL is undoped. For example, the barrier layer BL may be doped with an n-type impurity at a concentration of about 1 × 10 ¹⁸ cm ⁻³ .

An Al _0.20 Ga _0.80 N layer to be the second p-type layer 52 was formed on the light emitting unit 40. The thickness of the second p-type layer 52 (second thickness t52) is about 5 nm. The concentration of Mg in the second p-type layer 52 is about 1 × 10 ²⁰ cm ⁻³ .

On the second p-type layer 52, a GaN layer to be the fourth p-type layer 54 was formed. The thickness of the fourth p-type layer 54 (fourth thickness t54) is about 40 nm. In the formation of the fourth p-type layer 54, the Mg concentration in the fourth p-type layer 54 was gradually decreased from 1 × 10 ²⁰ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ . The growth temperature of the fourth p-type layer 54 is 1000 ° C. or higher and 1100 ° C. or lower.

A GaN layer to be the third p-type layer 53 was formed on the fourth p-type layer 54. The thickness of the third p-type layer 53 (third thickness t53) is about 40 nm. The Mg concentration in the third p-type layer 53 is about 2 × 10 ¹⁹ cm ⁻³ . The growth temperature of the third p-type layer 53 is 1000 ° C. or higher and 1100 ° C. or lower.

A GaN layer to be the first p-type layer 51 was formed on the third p-type layer 53. The thickness of the first p-type layer 51 (first thickness t51) is about 5 nm. The Mg concentration in the first p-type layer 51 is about 1 × 10 ²¹ cm ⁻³ .

Thus, the laminated structure 10s is formed.
An ITO film to be the p-side electrode 80 is formed on the first p-type layer 51. Further, a pad electrode (not shown) is formed on the p-side electrode 80. The thickness of the ITO film that becomes the p-side electrode 80 is about 0.2 μm. An Au film having a thickness of about 1.0 μm is used for the pad electrode.

A part of the laminated structure 10 s is dry-etched to expose a part of the n-type contact layer 21. A composite film of titanium-platinum-gold (Ti / Pt / Au) to be the n-side electrode 70 is formed on the exposed n-type contact layer 21.
Thereby, the semiconductor light emitting device 110a is formed. The peak wavelength of light emitted from the light emitting unit 40 of the semiconductor light emitting device 110a is 450 nm. That is, the emission is blue.

FIG. 5 is a graph illustrating the configuration of the semiconductor light emitting element according to the embodiment.
That is, the figure shows the elemental analysis result by the SIMS method of the p-type semiconductor layer 50 of the semiconductor light emitting device 110a. The horizontal axis of the figure is the position Pz in the + Z direction. The left vertical axis represents the Mg concentration C (Mg). The vertical axis on the right is the secondary ion intensity I (Al) of Al. The solid line indicates the Mg concentration C (Mg). The broken line indicates the secondary ion intensity I (Al) of Al.

  As shown in FIG. 5, the secondary ion intensity I (Al) of Al shows a sharp peak in the second p-type layer 52. As described above, the second p-type layer 52 includes Al.

Furthermore, as shown in FIG. 5, in the first p-type layer 51, the Mg concentration C (Mg) (that is, the first concentration C1) is about 1 × 10 ²¹ cm ⁻³ . The Mg concentration C (Mg) in the third p-type layer 53 (that is, the third concentration C3) is substantially constant at about 2 × 10 ¹⁹ cm ⁻³ . The Mg concentration C (Mg) in the fourth p-type layer 54 increases from 2 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ along the −Z direction. That is, the Mg concentration C (Mg) in the fourth p-type layer 54 gradually decreases from 1 × 10 ²⁰ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ along the + Z direction. The Mg concentration C (Mg) (that is, the second concentration C2) in the second p-type layer 52 is about 1 × 10 ²⁰ cm ⁻³ .

  Thus, the semiconductor light emitting device 110a has the p-type impurity concentration profile (Mg doping profile) illustrated in FIG.

  That is, the Mg concentration C (Mg) gradually decreases in the fourth p-type layer 54 from the second concentration C2 of the second p-type layer 52 along the + Z direction, and becomes the lowest third concentration C3 in the third p-type layer 53. In the first p-type layer 51, the highest first concentration C1 is obtained.

In the semiconductor light emitting device 110 according to the embodiment (110a and 111; the same applies hereinafter), the impurity concentration (second concentration C2) of the second p-type layer 52 is set to an intermediate value. The second concentration C2 is set to, for example, 2.5 × 10 ¹⁹ cm ⁻³ or more and less than 2 × 10 ²⁰ cm ⁻³ . When the second concentration C2 is lower than 2.5 × 10 ¹⁹ cm ⁻³ , the injection of holes into the light emitting unit 40 is reduced. For this reason, luminous efficiency falls. When the second concentration C2 is 2 × 10 ²⁰ cm ⁻³ or more, defects are likely to occur in the crystal. For this reason, luminous efficiency falls. By setting the second concentration C2 to a moderate and appropriate range of 2.5 × 10 ¹⁹ cm ⁻³ or more and less than 2 × 10 ²⁰ cm ⁻³ , high luminous efficiency can be obtained.

On the other hand, the impurity concentration (first concentration C1) in the first p-type layer 51 serving as the p-side contact layer is set to be higher than the second concentration C2. The first concentration C1 is, for example, 2 × 10 ²⁰ cm ⁻³ or more. Thereby, the contact resistance between the p-type semiconductor layer 50 and the p-side electrode 80 can be sufficiently reduced. When the first concentration C1 is lower than 2 × 10 ²⁰ cm ⁻³ , the contact resistance increases and the operating voltage increases.

  Thus, the first concentration C1 in the first p-type layer 51 is set to a very high value. For this reason, when the thickness of the first p-type layer 51 exceeds a certain level, the crystal quality tends to deteriorate. The thickness (first thickness t51) of the first p-type layer 51 is set to be less than 10 nm, for example. Thereby, high crystal quality can be maintained. If the first thickness t51 is thinner than 1 nm, the contact characteristics are likely to deteriorate. For this reason, the first thickness t51 is set to, for example, 1 nm or more and less than 10 nm.

  At this time, if the first p-type layer 51 having a high impurity concentration is formed in contact with the second p-type layer 52 having a medium impurity concentration, the region having a high impurity concentration has a thickness of a certain level or more. It tends to occur. For this reason, in the embodiment, an intermediate layer having a low impurity concentration is provided between the first p-type layer 51 and the second p-type layer 52. This intermediate layer corresponds to the third p-type layer 53 and the fourth p-type layer 54.

  As illustrated in FIG. 1, the change in impurity concentration (change between the first concentration C1 and the third concentration C3) between the first p-type layer 51 and the third p-type layer 53 is stepped. . Thereby, the thickness of the region having a high impurity concentration is reduced. Thereby, generation | occurrence | production of the defect in a crystal | crystallization is suppressed.

  The change in impurity concentration (change between the third concentration C3 and the second concentration C2) between the third p-type layer 53 and the second p-type layer 52 is a slope. A portion where the impurity concentration changes in a slope shape corresponds to the fourth p-type layer 54. Since the second concentration C2 is a medium concentration, even if the change in the impurity concentration between the third concentration C3 and the second concentration C2 is a slope, it is difficult for defects to occur in the crystal.

  Further, the resistance (series resistance) in the fourth p-type layer 54 can be lowered by changing the impurity concentration in the fourth p-type layer 54 between the second p-type layer 52 and the third p-type layer 53 in a slope shape. . This lowers the operating voltage.

  Note that it is difficult in manufacturing to change the impurity concentration between the third concentration C3 and the second concentration C2 in a step shape. From this point of view, in the embodiment, a layer (fourth p-type layer 54) having an inclined impurity concentration is provided between the third p-type layer 53 and the second p-type layer 52. Thereby, a semiconductor light emitting device that is easy to manufacture is obtained.

Thus, according to the embodiment, the hole injection efficiency is improved. Thereby, luminous efficiency becomes high. Then, the resistance (series resistance) in the p-type semiconductor layer 50 can be lowered and the operating voltage can be reduced. Furthermore, it is easy to manufacture.
According to the embodiment, a semiconductor light emitting device with high efficiency and low operating voltage is provided.

FIG. 6A to FIG. 6C are schematic views illustrating the configuration of a semiconductor light emitting element of a reference example. FIG. 7A to FIG. 7C are schematic views illustrating the configuration of the semiconductor light emitting device of the reference example. FIG. 8A and FIG. 8B are schematic views illustrating the configuration of a semiconductor light emitting element of a reference example.
That is, these drawings show the p-type impurity concentration C (p) (for example, Mg concentration C (Mg)) in the p-type semiconductor layer 50 of the semiconductor light emitting device of the reference example.

As shown in FIG. 6A, the first to fourth p-type layers 51 to 54 are also provided in the semiconductor light emitting device 119a of the first reference example, but the first concentration C1 is the second concentration C2. Is equivalent to In such a first reference example, when the first concentration C1 and the second concentration C2 are set to a high value of 2 × 10 ²⁰ cm ⁻³ or higher, the second concentration C2 is too high, so that the crystal quality is degraded. As a result, the luminous efficiency decreases. Further, when the first concentration C1 and the second concentration C2 are set to an intermediate value between 2.5 × 10 ¹⁹ cm ^{−3 and} less than 2 × 10 ²⁰ cm ⁻³ , the contact resistance increases.

  As shown in FIG. 6B, in the semiconductor light emitting device 119 b of the second reference example, an inclined layer 55 is provided between the first p-type layer 51 and the fourth p-type layer 54. The impurity concentration C (p) in the inclined layer 55 gradually increases from the third concentration C3 to the first concentration C1 along the + Z direction. The first concentration C1 is equivalent to the second concentration C2. Also in this case, the crystal quality is lowered when the first concentration C1 and the second concentration C2 are high. When the first concentration C1 and the second concentration C2 are set to intermediate values, the contact resistance increases.

  As shown in FIG. 6C, in the semiconductor light emitting device 119 c of the third reference example, an inclined layer 55 is provided between the first p-type layer 51 and the fourth p-type layer 54. The impurity concentration C (p) in the inclined layer 55 gradually increases from the third concentration C3 to the first concentration C1 along the + Z direction. The first concentration C1 is higher than the second concentration C2. Since the first concentration C1 is high, the contact resistance is considered to be low. Since the second concentration C2 is set to a medium value, it is considered that the hole injection efficiency is high. However, in the inclined layer 55 between the first p-type layer 51 and the fourth p-type layer 54, the impurity concentration changes in a slope shape. For this reason, in the inclined layer 55, the region where the p-type impurity concentration is high exceeds a certain thickness. For this reason, defects tend to occur in the crystal. For this reason, luminous efficiency is low.

  As shown in FIG. 7A, in the semiconductor light emitting device 119d of the fourth reference example, an inclined layer 55 is provided between the first p-type layer 51 and the second p-type layer 52. The fourth p-type layer 54 is not provided. The impurity concentration C (p) in the inclined layer 55 gradually increases from the third concentration C3 to the first concentration C1 along the + Z direction. The first concentration C1 is higher than the second concentration C2. Also in this case, it is considered that the contact resistance is low and the hole injection efficiency is high. However, the impurity concentration in the inclined layer 55 changes in a slope shape. For this reason, in the inclined layer 55, the region where the p-type impurity concentration is high exceeds a certain thickness. For this reason, defects tend to occur in the crystal. For this reason, luminous efficiency is low.

  As illustrated in FIG. 7B, in the semiconductor light emitting device 119 e of the fifth reference example, the inclined layer 56 is provided between the first p-type layer 51 and the second p-type layer 52. The impurity concentration C (p) in the inclined layer 56 gradually decreases from the second concentration C2 to the third concentration C3 along the + Z direction. The first concentration C1 is higher than the second concentration C2. Also in this case, it is considered that the contact resistance is low and the hole injection efficiency is high. However, the impurity concentration in the inclined layer 56 changes in a slope shape. For this reason, defects tend to occur in the crystal.

  As shown in FIG. 7C, in the semiconductor light emitting device 119 f of the sixth reference example, an inclined layer 56 is provided between the first p-type layer 51 and the second p-type layer 52. The impurity concentration C (p) in the inclined layer 56 gradually decreases from the second concentration C2 to the third concentration C3 along the + Z direction. The first concentration C1 is higher than the second concentration C2. In the semiconductor light emitting device 119f, the third concentration C3 is set very low. Also in this case, it is considered that the contact resistance is low and the hole injection efficiency is high. Although the impurity concentration in the inclined layer 56 changes in a slope shape, the generation of crystal defects is suppressed because the third concentration C3 is low. However, since the third concentration C3 is low, the average impurity concentration of the gradient layer 56 is low. For this reason, the resistance (series resistance) of the inclined layer 56 is increased. For this reason, the operating voltage is high.

  As shown in FIG. 8A, in the semiconductor light emitting device 119g of the seventh reference example, the third p-type layer 53 is provided between the first p-type layer 51 and the second p-type layer 52. The fourth p-type layer 54 is not provided. The first concentration C1 is higher than the second concentration C2. Also in this case, it is considered that the contact resistance is low and the hole injection efficiency is high. However, if the third concentration C3 is set high, defects are likely to occur in the crystal. Further, when the third concentration C3 is set low, the resistance (series resistance) increases. Further, since the impurity concentration changes in a step shape between the second p-type layer 52 and the third p-type layer 53, it is difficult to control the manufacturing conditions.

  As shown in FIG. 8B, in the semiconductor light emitting device 119h of the eighth reference example, the second concentration C2 of the second p-type layer 52 is low. The second concentration C2 is approximately the same as the third concentration C3. The fourth p-type layer 54 is not substantially provided. In this example, the energy band in the second p-type layer 52 is relatively lowered, and the quantum confinement effect is lowered. For this reason, luminous efficiency falls. And the injection | pouring of the hole to the light emission part 40 decreases. For this reason, luminous efficiency falls.

  Thus, in the semiconductor light emitting devices 119a to 119h of the first to eighth reference examples, it is difficult to obtain high efficiency and low operating voltage at the same time.

  On the other hand, according to the semiconductor light emitting device according to the embodiment, high efficiency and low operating voltage can be obtained simultaneously. Furthermore, it is easy to manufacture.

The characteristics of the semiconductor light emitting device 110 according to the embodiment and the semiconductor light emitting device of the reference example were simulated.
Hereinafter, simulation results of characteristics of the semiconductor light emitting device 110 according to the embodiment, the semiconductor light emitting device 119a of the first reference example, the semiconductor light emitting device 119e of the fifth reference example, and the semiconductor light emitting device 119h of the eighth reference example will be described. .

In this simulation, the following was performed.
In the semiconductor light emitting device 110, the first concentration C1 (Mg concentration) was 1 × 10 ²¹ cm ⁻³ . The second concentration C2 (Mg concentration) was 1 × 10 ²⁰ cm ⁻³ . The third concentration C3 (Mg concentration) was 2 × 10 ¹⁹ cm ⁻³ . The Mg concentration C (Mg) in the fourth p-type layer 54 is assumed to decrease linearly from 1 × 10 ²⁰ cm ⁻³ to 2 × 10 ¹⁹ cm ⁻³ along the + Z direction. The first thickness t51 and the second thickness t52 were 5 nm. The third thickness t53 and the fourth thickness t54 were 40 nm.

In the semiconductor light emitting device 119a, the first concentration C1 = the second concentration C2 = 1 × 10 ²⁰ cm ⁻³ and the third concentration C3 = 2 × 10 ¹⁹ cm ^−3, and the first thickness t51, the second thickness t52, The third thickness t53 and the fourth thickness t54 were the same as those of the semiconductor light emitting device 110.

In the semiconductor light emitting device 119e, the first concentration C1 = 1 × 10 ²¹ cm ⁻³ , the second concentration C2 = 1 × 10 ²⁰ cm ⁻³ , the third concentration C3 = 1 × 10 ¹⁸ cm ^−3, and the first thickness. The t51 and the second thickness t52 are the same as those of the semiconductor light emitting device 110. And the thickness of the inclination layer 56 was 80 nm.

In the semiconductor light emitting device 119h, the first concentration C1 = 1 × 10 ²¹ cm ⁻³ , the second concentration C2 = third concentration C3 = 1 × 10 ¹⁹ cm ^−3, and the first thickness t51 and the second thickness t52 are: The same as the semiconductor light emitting device 110 was used. The third thickness t53 was set to 80 nm.

FIG. 9 is a graph illustrating characteristics of the semiconductor light emitting device.
That is, the figure shows the simulation result. The horizontal axis of FIG. 9 is the injection current Ic that flows through the semiconductor light emitting element. The vertical axis represents the operating voltage Vf.

  As can be seen from FIG. 9, the operating voltage Vf of the semiconductor light emitting device 110 according to the embodiment is lower than any of the semiconductor light emitting devices 119a, 119e, and 119h of the reference example.

  The effect of reducing the drive voltage Vf according to the embodiment is particularly remarkable in a region where the injection current Ic is large.

In the embodiment, the light output increases.
For example, in the semiconductor light emitting device 110 according to the embodiment, when the injection current Ic is 20 milliamperes (mA), the operating voltage Vf is 2.88 volts (V), and the light output at this time is 28 milliwatts ( mW).

  On the other hand, in the semiconductor light emitting device 119h of the eighth reference example, when the injection current Ic is 20 mA, the operating voltage Vf is 2.94 V, and the light output at this time is estimated to be 24 mW.

  Thus, in the semiconductor light emitting device 110 according to the embodiment, the light output is high and the efficiency is high. The operating voltage Vf is low.

  In the semiconductor light emitting device 110 (including 111) according to the embodiment, the thickness (first thickness t51) along the + Z direction of the first p-type layer 51 is, for example, not less than 1 nm and less than 10 nm. The first thickness t51 is, for example, 5 nm. The thickness (second thickness t52) along the + Z direction of the second p-type layer 52 is, for example, not less than 1 nm and less than 10 nm. The second thickness t52 is, for example, 5 nm. The thickness (third thickness t53) along the + Z direction of the third p-type layer 53 is, for example, not less than 10 nm and not more than 80 nm. The third thickness t53 is, for example, 40 nm. The thickness (fourth thickness t54) along the + Z direction of the fourth p-type layer 54 is, for example, not less than 10 nm and not more than 80 nm. The fourth thickness t54 is, for example, 40 nm.

  The third thickness t53 is substantially equal to the fourth thickness t54. The difference between the third thickness t53 and the fourth thickness t54 is smaller than the difference between the third thickness t53 and the first thickness t51, and smaller than the difference between the third thickness t53 and the second thickness t52. The difference between the third thickness t53 and the fourth thickness t54 is smaller than the difference between the fourth thickness t54 and the first thickness t51, and smaller than the difference between the fourth thickness t54 and the second thickness t52.

  Thus, by setting the third thickness t53 to be substantially equal to the fourth thickness t54, it becomes easy to appropriately control the profile of the p-type impurity concentration.

  The first thickness t51 is thinner than the third thickness t53 and thinner than the fourth thickness t54. The second thickness t52 is thinner than the third thickness t53 and thinner than the fourth thickness t54. By setting the first thickness t51 and the second thickness t52 to be smaller than the third thickness t53 and the fourth thickness t54, it becomes easy to suppress the occurrence of defects in the crystal.

  The first thickness t51 has a value close to the second thickness t52. The difference between the first thickness t51 and the second thickness t52 is smaller than the difference between the first thickness t51 and the third thickness t53, and smaller than the difference between the first thickness t51 and the fourth thickness t54. The difference between the first thickness t51 and the second thickness t52 is smaller than the difference between the second thickness t52 and the third thickness t53, and smaller than the difference between the second thickness t52 and the fourth thickness t54.

  Examples of the method for growing each semiconductor layer in the semiconductor light emitting device according to the embodiment include a metal organic chemical vapor deposition (MOCVD) method and a molecular beam epitaxy (MBE) method. Used.

The following materials can be used as raw materials for forming each semiconductor layer.
For example, TMGa (trimethyl gallium) and TEGa (triethyl gallium) can be used as the Ga raw material. For example, TMIn (trimethylindium), TEIn (triethylindium), or the like can be used as the In material. As a raw material for Al, for example, TMAl (trimethylaluminum) can be used. As a raw material of N, for example, NH ₃ (ammonia), MMHy (monomethylhydrazine), DMHy (dimethylhydrazine) and the like can be used. For example, SiH ₄ (monosilane) can be used as the Si raw material. As a raw material of Mg, for example, Cp ₂ Mg (biscyclopentadienyl magnesium) can be used.

  According to the embodiment, a semiconductor light emitting device with high efficiency and low operating voltage is provided.

In this specification, “nitride semiconductor” means B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) Semiconductors having all compositions in which the composition ratios x, y, and z are changed within the respective ranges are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strict vertical and strict parallel but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. It ’s fine.

The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, a specific configuration of each element such as an n-type semiconductor layer, a p-type semiconductor layer, a light-emitting portion, a well layer, a barrier layer, and an electrode included in the semiconductor light-emitting element is appropriately selected by those skilled in the art from a known range. Thus, the present invention is included in the scope of the present invention as long as the same effects can be obtained and similar effects can be obtained.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor light-emitting elements that can be implemented by those skilled in the art based on the semiconductor light-emitting elements described above as embodiments of the present invention are included in the scope of the present invention as long as they include the gist of the present invention. Belonging to.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Board | substrate, 10a ... 1st main surface, 10b ... 2nd main surface, 10s ... Laminated structure, 11 ... Buffer layer, 20 ... N-type semiconductor layer, 21 ... N-type contact layer, 22 ... N side guide layer, 40 ... Light emitting part, 50 ... p-type semiconductor layer, 51 ... 1st p-type layer, 52 ... 2nd p-type layer, 53 ... 3rd p-type layer, 54 ... 4th p-type layer, 55, 56 ... Gradient layer, 70 ... n Side electrode, 80... P-side electrode, 110, 110a, 111, 119a to 119h... Semiconductor light emitting device, BL1 to BLi... First to i-th barrier layer, BLP. Concentration, C (Mg) ... Mg concentration, C1-C3 ... First to third concentration, I (Al) ... Secondary ion intensity of Al, Ic ... Injection current, Pz ... Position, Vf ... Operating voltage, WL ... Well Layer, WL1 to WLi... 1st to i-th well layer, t 51, t52, t53, t54 ... 1st to 4th thickness

Claims (8)

an n-type semiconductor layer;
a p-type semiconductor layer;
A light emitting part provided between the n-type semiconductor layer and the p-type semiconductor layer;
A p-side electrode provided in the p-type semiconductor layer;
With
The p-type semiconductor layer is
A first p-type layer including a p-type impurity at a first concentration and provided on the p-side electrode side;
A second p-type layer that includes Al and includes a p-type impurity at a second concentration lower than the first concentration and is provided on the light emitting unit side;
A third p-type layer provided between the first p-type layer and the second p-type layer and including a p-type impurity at a third concentration lower than the second concentration;
A p-type impurity concentration is provided between the second p-type layer and the third p-type layer, and the concentration of the p-type impurity in the first direction from the n-type semiconductor layer toward the p-type semiconductor layer is changed from the second concentration to the first concentration. A fourth p-type layer that gradually decreases to three concentrations;
Including
A thickness of the third p-type layer is not less than 10 nanometers and not more than 80 nanometers;
The third concentration is 0.05 times or more and 0.8 times or less of the second concentration,
The semiconductor light emitting device according to claim 3, wherein the third concentration is constant so that a variation of the third concentration is within ± 20% of an average of the third concentration. An AlGaN layer is used for the second p-side layer,
The semiconductor light emitting device according to claim 1, wherein a GaN layer is used for the first p-type layer, the third p-type layer, and the fourth p-type layer. The first p-type layer is thinner than the third p-type layer and thinner than the fourth p-type layer,
3. The semiconductor light emitting device according to claim 1, wherein a thickness of the second p-type layer is thinner than a thickness of the third p-type layer and is thinner than a thickness of the fourth p-type layer. The difference between the thickness of the third p-type layer and the thickness of the fourth p-type layer is:
Less than the difference between the thickness of the third p-type layer and the thickness of the first p-type layer;
4. The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting element is smaller than a difference between a thickness of the third p-type layer and a thickness of the second p-type layer. The semiconductor light emitting element according to claim 1, wherein the first concentration is 2 × 10 ²⁰ cm ⁻³ or more. 6. The semiconductor light emitting element according to claim 1, wherein the second concentration is 2.5 × 10 ¹⁹ cm ⁻³ or more and less than 2 × 10 ²⁰ cm ⁻³ . The first p-type layer has a thickness of 1 nanometer or more and less than 10 nanometers,
A thickness of the second p-type layer is not less than 1 nanometer and less than 10 nanometers;
The third p-type layer has a thickness of 80 nanometers or less;
7. The semiconductor light emitting device according to claim 1, wherein a thickness of the fourth p-type layer is not less than 10 nanometers and not more than 80 nanometers.   The concentration of the p-type impurity in the fourth p-type layer gradually decreases from the second concentration to the third concentration, and the decreasing rate on the second p-type layer side gradually decreases on the third p-type layer side. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is larger than a ratio of the semiconductor light emitting device.

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