JP2015007989A - Semiconductor device, adjusting method for the same, and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly capture a plurality of read data pieces, which are output from a plurality of core chips, in an interface chip.SOLUTION: Each of a plurality of core chips CCi includes: a data output circuit 54o for outputting read data to an interface chip IF in response to a read command; and an output timing adjustment circuit 400 for matching a duration from a time when receiving the read command until the read data is output by the data output circuit 54o between the plurality of core chips. By this, it is possible to sufficiently secure a latch margin of the read data to be input at the side of the interface chip. Output timing is adjusted at the side of each core chip, thereby eliminating the need for providing latch timing control circuits or the like equivalent to the number of core chips on the side of the interface chip.

Description

  The present invention relates to a semiconductor device, an adjustment method thereof, and a data processing system, and more particularly to a semiconductor device including a plurality of core chips and an interface chip for controlling the core chip, an adjustment method thereof, and a data processing system.

  The storage capacity required for semiconductor devices such as DRAM (Dynamic Random Access Memory) is increasing year by year. In order to satisfy this requirement, recently, a memory device called a multichip package in which a plurality of memory chips are stacked has been proposed. However, since the memory chip used in the multi-chip package is a normal memory chip that operates alone, each memory chip has a so-called front-end unit that interfaces with the outside (for example, a memory controller). It is included. Therefore, the occupied area that can be allocated to the memory core in each memory chip is limited to the area obtained by subtracting the occupied area of the front end portion from the total chip area, and the storage capacity per chip (per memory chip) It is difficult to significantly increase

  In addition, although the circuit constituting the front-end unit is a logic circuit, it is difficult to increase the speed of the front-end transistor because it is manufactured at the same time as the back-end unit including the memory core. There was also a problem.

  As a method for solving such a problem, a method has been proposed in which a front-end unit and a back-end unit are integrated on separate chips and stacked to form one semiconductor device (see Patent Document 1). ). According to this method, since the occupied area that can be allocated to the memory core increases for a plurality of core chips each integrated with a back-end unit, the storage capacity per chip (per core chip) can be increased. Is possible. On the other hand, an interface chip having a front end unit integrated and common to a plurality of core chips can be manufactured by a process different from that of the memory core, and thus a circuit can be formed by high-speed transistors. In addition, since a plurality of core chips can be assigned to one interface chip, it is possible to provide a semiconductor device with a very large capacity and high speed as a whole.

  However, since the operating speed of each core chip varies due to manufacturing process conditions, for example, the time from receiving a read command to outputting read data varies from core chip to core chip. For this reason, the latch margin of the read data on the interface chip side is reduced, and there arises a problem that the read data cannot be correctly latched in some cases.

  As a method for solving this problem, the semiconductor device is not a type of semiconductor device in which the front-end unit and the back-end unit are separated. However, Patent Document 2 discloses a device including a memory and an LSI connected thereto. A method of adjusting the latch timing of output data on the LSI side is disclosed.

JP 2004-327474 A JP 2004-185608 A

  However, since the semiconductor device of the type in which the front end portion and the back end portion are separated, a plurality of core chips constituting the back end portion are assigned to one interface chip constituting the front end portion. When the method described in 2 is applied to this type of semiconductor device, the latch timing control circuit in the interface chip is required for the number of core chips. That is, a plurality of latch timing control circuits corresponding to a plurality of core chips are required in the interface chip. This is because each core chip is a separate chip, and variations due to manufacturing process conditions exist between the core chips. That is, even if each of the core chips has the same function and is manufactured with the same manufacturing mask, the plurality of core chips have different characteristics (for example, delay speed per predetermined circuit) depending on the specific manufacturing process conditions. . Therefore, the speeds at which the plurality of core chips operate are different. Moreover, since the number of core chips allocated to the interface chip is not necessarily determined at the time of manufacturing the interface chip, the method described in Patent Document 2 has a plurality of latch timing control circuits corresponding to the maximum number of core chips that can be allocated. It is necessary to prepare for the interface chip, and depending on the chip configuration, significant waste occurs.

  The semiconductor device according to the present invention includes a plurality of core chips each having an output terminal electrically connected in common, one input terminal electrically connected to each output terminal, and each output terminal. A plurality of read data to be input from the input terminal, and an interface chip that issues at least a read command to the plurality of core chips, and each of the plurality of core chips includes: A data output circuit for outputting the read data to the output terminal in response to the read command; and a first time indicating a time from the read command to outputting the read data to the output terminal. And an output timing adjustment circuit that adjusts to a second time to be matched.

  In addition, the semiconductor device adjustment method according to the present invention includes a plurality of core chips each having an output terminal electrically connected in common, and one input terminal electrically connected to each output terminal of the plurality of core chips. A method of adjusting a semiconductor device comprising an interface chip, wherein a difference in operating speed between a first operating speed of each of the plurality of core chips and a second operating speed of the interface chip is detected, respectively. Based on the detection result, the output timing of the read data output from the plurality of core chips to the interface chip in relation to the read command issued by the interface chip to the plurality of core chips is determined between the plurality of core chips. It is characterized by matching.

  A data processing system according to the present invention includes the semiconductor device described above and a controller connected thereto, and the controller issues a command related to the read command to the interface chip, and the command is transmitted from the controller. The received interface chip issues the read command to the plurality of core chips, and one of the plurality of core chips receives the read command and outputs the read data corresponding to the read command to the interface chip. The interface chip that receives the read data from any of the plurality of core chips outputs the read data to the controller.

  In the present invention, “matching” of time does not require that the time is completely the same, but includes a state in which the time difference cannot be further reduced due to the circuit configuration. In the present invention, since the output timing of the read data is adjusted by the output timing adjustment circuit, the output timing of the read data cannot be finely adjusted with an accuracy exceeding the adjustment pitch of the output timing adjustment circuit. In other words, it is impossible to adjust the time smaller than the minimum delay time or the minimum shortening time which is the minimum resolution of time adjustment. Therefore, a state in which the time difference is minimized by the output timing adjustment circuit is a state in which the times are “matched” in the present invention.

  According to the present invention, an output timing adjustment circuit is provided in each core chip, whereby the time from when the core chip receives the read command until the read data is output is matched between the core chips. It becomes possible to secure a sufficient latch margin for a plurality of read data respectively output from each core chip on the chip side (secured by a common latch margin). In addition, since each core chip side adjusts the output timing of the read data, it is not necessary to provide a plurality of latch timing control circuits corresponding to the number of core chips on the interface chip side. This effect is an effect peculiar to the structure in which each output signal (each output circuit) of each core chip is connected to one input circuit of the interface chip.

It is typical sectional drawing for demonstrating the structure of the semiconductor device 10 by preferable embodiment of this invention. It is a figure for demonstrating the kind of TSV provided in the core chip. It is sectional drawing which shows the structure of TSV1 of the type shown to Fig.2 (a). 2 is a block diagram showing a circuit configuration of a semiconductor device 10. FIG. 2 is a circuit diagram of a process monitor circuit 100 and a replica circuit 300. FIG. It is a flowchart for demonstrating the acquisition method of the adjustment code CO. 2 is a block diagram showing a state in which a tester 700 is connected to the semiconductor device 10. FIG. 5 is a flowchart for explaining an operation of writing output timing data to the timing data storage circuit 200. 5 is a flowchart for explaining an operation of transferring output timing data from the timing data storage circuit 200 to the core chips CC0 to CC7. It is a typical block diagram for demonstrating the flow of the whole signal at the time of read-operation. It is a schematic diagram for demonstrating the flow of read data. 3 is a circuit diagram of an output timing adjustment circuit 400. FIG. It is a circuit diagram of a selection signal generation circuit 480 that generates selection signals TCO1 to TCO7. 10 is a table for explaining a relationship between upper 3 bits CO [5: 3] of output timing data and a set delay amount. FIG. 10 is a timing diagram for explaining the effect of adjustment by the output timing adjustment circuit 400. It is a schematic diagram which shows the flow of a read command and read data. 1 is a block diagram showing a configuration of a data processing system 500 using a semiconductor device 10.

  A typical example of a technical idea (concept) for solving the problems of the present invention is shown below. However, it goes without saying that the claimed contents of the present application are not limited to this technical idea, but are the contents described in the claims of the present application. That is, the technical idea of the present invention is to measure the operating speed of each core chip with the interface chip as a reference, and adjust the output timing of read data on each core chip side based on the result. As a result, the time from the interface chip side issuing a read command to each core chip side and the time when each core chip side accepts the read command until the corresponding read data is output is matched between the core chips. It is possible to synchronize the fetch timing of each of a plurality of read data output from each core chip at a common timing. As a result, based on the time from issuing the interface chip read command due to the process conditions of the interface chip to taking in the corresponding read data, the operating speed variations due to the respective process conditions between the core chips are offset. Is done. That is, this technical idea is useful in a unique structure in which each output signal (each output circuit) of each core chip is commonly connected to one input circuit of the interface chip. As a first example of the unique structure, each core chip has the same function and is manufactured with the same manufacturing mask. As a second example, each core chip has a different storage function (the first core chip is a DRAM, the second chip is an SRAM, the third chip is a non-volatile memory, and the fourth chip is a DSP). Manufactured with a production mask.

  The following technical idea is also disclosed. It is meaningful to measure the operating speed of each core chip on the basis of the interface chip and adjust the operating speed of each core chip. This is because the interface chip is manufactured under different manufacturing conditions from the core chip, and the interface chip has a front-end function with the outside, and the core chip has a back-end function. Specifically, the interface chip communicates with the outside, transmits a unique instruction based on the communication result to the back-end core chip, and receives data from the back end related to the unique instruction. In other words, the interface chip is a source (first driver) of a trigger signal for a command (for example, a read command) to the core chip, and a source (first receiver) of data related to the trigger signal. On the other hand, the core chip includes a second receiver that receives the trigger signal output from the first driver of the interface chip, and a second driver that outputs data related to the trigger signal. Therefore, the first predetermined time (first latency) from the first driver circuit to the first receiver circuit in the interface chip, and the second from the second receiver circuit in the core chip to the second driver circuit. The predetermined time (second latency) is in a so-called racing relationship, and it is important that the first latency and the plurality of second latencies are temporally matched. In each chip, the first and second latencies are designed at the same time. Here, the interface chip is manufactured under different manufacturing conditions from the core chip, and each core chip is manufactured under different manufacturing conditions, so that the first latency and the plurality of second latencies are However, they are placed in a plurality of racing relationships that are different in time. The most efficient solution is to measure each time difference from the plurality of second latencies of each core chip based on the first latency produced by the manufacturing conditions of the interface chip that is the front end function. Most preferred. This is because the interface chip is the source of the trigger signal.

Furthermore, the following technical ideas are also disclosed. The measurement is meaningful in that after the interface chip and the plurality of core chips are assembled as one semiconductor device, the operation speed of each core chip is measured with reference to the interface chip, and the operation speed of each core chip is adjusted. This is because the physical distance between the interface chip and the plurality of core chips is different. In particular, in a semiconductor device composed of a plurality of core chips and a single interface chip, the potential of each power supply line from a power supply terminal outside the semiconductor device to the plurality of core chips and the interface chip inside the semiconductor device is a semiconductor. This is because each chip may be different depending on the parasitic resistance in the device. In this case, the first latency is different from the plurality of second latencies. For example, a plurality of core chips and interface chips are stacked on each other to form a single semiconductor device, and a plurality of power supplies in each of the internal chip farthest from the power supply terminal that is the external terminal of the semiconductor device and the closest chip The potential may be different. Furthermore, even when power is supplied from the interface chip to each core chip, the plurality of power supply potentials in the core chips of the core chip farthest from the interface chip and the core chip closest thereto may be different.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device 10 according to the present embodiment has eight core chips CC0 to CC7 each having the same function and structure and manufactured with the same manufacturing mask, and manufactured with a manufacturing mask different from the core chip. It has a structure in which one interface chip IF and one interposer IP are stacked. The core chips CC0 to CC7 and the interface chip IF are semiconductor chips using a silicon substrate, and all of them are electrically connected to adjacent chips vertically by a large number of through silicon vias TSV (Through Silicon Via) penetrating the silicon substrate. . On the other hand, the interposer IP is a circuit board made of resin, and a plurality of external terminals (solder balls) SB are formed on the back surface IPb thereof.

  The core chips CC0 to CC7 are "known and general itself including both a so-called front-end unit that interfaces with the outside via an external terminal, a plurality of memory cells, and a so-called back-end unit that accesses these memory cells. Of the circuit blocks included in the 1 Gb DDR3 (Synchronous Dynamic Random Access Memory) SDRAM, which is a normal memory chip that can operate even with a single chip and can communicate directly with the memory controller, interface with the outside This is a semiconductor chip from which a so-called front end portion (front end function) to be performed is deleted. In other words, in principle, it is a semiconductor chip in which only circuit blocks belonging to the back-end part are integrated. The circuit block included in the front-end unit controls the parallel / serial conversion circuit (data latch circuit) that performs parallel / serial conversion of input / output data between the memory cell array and data input / output terminals, and controls the data input / output timing. For example, a DLL (Delay Locked Loop) circuit may be used. Details will be described later. The interface chip IF is a semiconductor chip in which only the front end portion is integrated. Therefore, the operating frequency of the interface chip is higher than the operating frequency of the core chip. Since the core chips CC0 to CC7 do not include these circuits belonging to the front end unit, the core chips CC0 to CC7 are operated alone in the core chip manufacturing process except during a test operation in which the core chip is performed in a wafer state. It is not possible. An interface chip IF is required to operate the core chips CC0 to CC7. Therefore, the integration degree of the core chip is higher than that of a general single chip. In the semiconductor device 10 according to the present embodiment, the interface chip has a front-end function that communicates with the outside at a first operating frequency, and the plurality of core chips communicate only with the interface chip and have a frequency higher than the first operating frequency. It has a back-end function that communicates at a low second operating frequency. Therefore, each of the plurality of core chips includes a memory cell array that stores a plurality of information, and a plurality of read data per I / O (DQ) supplied in parallel from the plurality of core chips to the interface chip is the interface chip. A plurality of bits related to one read command given to the core chip. The so-called plurality of bits corresponds to a known number of prefetch data.

  The interface chip IF functions as a common front end unit for the eight core chips CC0 to CC7. Therefore, all external accesses are performed via the interface chip IF, and data input / output is also performed via the interface chip IF. In the present embodiment, the interface chip IF is disposed between the interposer IP and the core chips CC0 to CC7. However, the position of the interface chip IF is not particularly limited, and may be disposed above the core chips CC0 to CC7. Alternatively, it may be arranged on the back surface IPb of the interposer IP. When the interface chip IF is arranged face down on the top of the core chips CC0 to CC7 or face up on the back surface IPb of the interposer IP, there is no need to provide a TSV in the interface chip IF. Further, the interface chip IF may be arranged so as to be sandwiched between two interposers IP.

  The interposer IP functions as a rewiring board for ensuring the mechanical strength of the semiconductor device 10 and increasing the electrode pitch. That is, the electrode 91 formed on the upper surface IPa of the interposer IP is drawn out to the back surface IPb by the through-hole electrode 92, and the pitch of the external terminals SB is expanded by the rewiring layer 93 provided on the back surface IPb. Although only two external terminals SB are shown in FIG. 1, a large number of external terminals are actually provided. The layout of the external terminal SB is the same as that in the DDR3-type SDRAM defined by the standard. Therefore, it can be handled as one DDR3-type SDRAM from an external controller.

  As shown in FIG. 1, the upper surface of the uppermost core chip CC0 is covered with an NCF (Non-Conductive Film) 94 and a lead frame 95, and the gaps between the core chips CC0 to CC7 and the interface chip IF are underfilled. 96 and the periphery thereof is covered with a sealing resin 97. Thereby, each chip is physically protected.

  Most of the TSVs provided in the core chips CC0 to CC7 are short-circuited with TSVs of other layers provided at the same position in a plan view seen from the stacking direction, that is, when viewed from the arrow A shown in FIG. Yes. That is, as shown in FIG. 2A, the upper and lower TSV1 provided at the same position in a plan view are short-circuited, and one wiring is constituted by these TSV1. These TSV1 provided in each of the core chips CC0 to CC7 are respectively connected to the internal circuit 4 in the core chip. Therefore, input signals (command signal, address signal, etc.) supplied from the interface chip IF to the TSV1 shown in FIG. 2A are commonly input to the internal circuits 4 of the core chips CC0 to CC7. Further, output signals (data and the like) supplied from the core chips CC0 to CC7 to the TSV1 are wired-or and input to the interface chip IF.

  On the other hand, as shown in FIG. 2B, some TSVs are not directly connected to other layers TSV2 provided at the same position in plan view, but are provided in the core chips CC0 to CC7. Connected through the internal circuit 5. That is, these internal circuits 5 provided in the core chips CC0 to CC7 are cascade-connected via the TSV2. This type of TSV2 is used to sequentially transfer predetermined information to the internal circuit 5 provided in each of the core chips CC0 to CC7. Such information includes layer address information described later.

  Further, some other TSV groups are short-circuited with TSVs of other layers provided at different positions in plan view, as shown in FIG. For this type of TSV group 3, internal circuits 6 of the core chips CC0 to CC7 are connected to a TSV 3a provided at a predetermined position P in plan view. This makes it possible to selectively input information to the internal circuit 6 provided in each core chip. Such information includes defective chip information described later.

  As described above, there are three types (TSV1 to TSV3) of TSVs provided in the core chips CC0 to CC7 shown in FIGS. As described above, most TSVs are of the type shown in FIG. 2A, and address signals, command signals, clock signals, etc. are transferred from the interface chip IF to the core chip CC0 via the TSV1 of the type shown in FIG. To CC7. Also, read data and write data are input / output to / from the interface chip IF via the TSV1 of the type shown in FIG. On the other hand, TSV2 and TSV3 of the types shown in FIGS. 2B and 2C are used to give individual information to the core chips CC0 to CC7 having the same structure.

  FIG. 3 is a cross-sectional view showing the structure of TSV1 of the type shown in FIG.

  As shown in FIG. 3, TSV1 is provided through silicon substrate 80 and interlayer insulating film 81 on the surface thereof. An insulating ring 82 is provided around TSV1, thereby ensuring insulation between TSV1 and the transistor region. In the example shown in FIG. 3, the insulating ring 82 is doubled, and the electrostatic capacity between the TSV 1 and the silicon substrate 80 is reduced.

  The end 83 of the TSV 1 on the back side of the silicon substrate 80 is covered with a back bump 84. The back bump 84 is an electrode in contact with the front bump 85 provided on the lower core chip. The surface bump 85 is connected to the end portion 86 of the TSV1 through pads P0 to P3 provided in the wiring layers L0 to L3 and a plurality of through-hole electrodes TH1 to TH3 connecting the pads. As a result, the front surface bump 85 and the rear surface bump 84 provided at the same position in plan view are short-circuited. Note that connection to an internal circuit (not shown) is made via internal wiring (not shown) drawn from pads P0 to P3 provided in the wiring layers L0 to L3.

  FIG. 4 is a block diagram showing a circuit configuration of the semiconductor device 10.

  As shown in FIG. 4, the external terminals provided in the interposer IP include clock terminals 11a and 11b, a clock enable terminal 11c, command terminals 12a to 12e, an address terminal 13, a data input / output terminal 14, a data strobe terminal 15a, 15b, a calibration terminal 16, and power supply terminals 17a and 17b. These external terminals are all connected to the interface chip IF and are not directly connected to the core chips CC0 to CC7 except for the power supply terminals 17a and 17b.

  First, the connection relationship between these external terminals and the interface chip IF which is a front-end function, and the circuit configuration of the interface chip IF will be described.

  The clock terminals 11a and 11b are terminals to which external clock signals CK and / CK are supplied, respectively, and the clock enable terminal 11c is a terminal to which a clock enable signal CKE is input. The supplied external clock signals CK and / CK and the clock enable signal CKE are supplied to the clock generation circuit 21 provided in the interface chip IF. In this specification, a signal having “/” at the head of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock generation circuit 21 is a circuit that generates an internal clock signal ICLK. The generated internal clock signal ICLK is supplied to various circuit blocks in the interface chip IF and is also common to the core chips CC0 to CC7 via the TSV. To be supplied.

  The interface chip IF includes a DLL circuit 22, and the input / output clock signal LCLK is generated by the DLL circuit 22. The input / output clock signal LCLK is supplied to the input / output buffer circuit 23 included in the interface chip IF. This is because the DLL function controls the front end with the signal LCLK whose synchronization with the outside is matched when the semiconductor device 10 communicates with the outside. Therefore, the DLL function is not required for the core chips CC0 to CC7 which are back ends.

  The command terminals 12a to 12e are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, and an on-die termination signal ODT are supplied, respectively. These command signals are supplied to a command input buffer 31 provided in the interface chip IF. These command signals supplied to the command input buffer 31 are supplied to the command decoder 32. The command decoder 32 is a circuit that generates various internal commands ICMD by holding, decoding, and counting command signals in synchronization with the internal clock ICLK. The generated internal command ICMD is supplied to various circuit blocks in the interface chip IF, and is also commonly supplied to the core chips CC0 to CC7 via the TSV.

  The address terminal 13 is a terminal to which address signals A0 to A15 and BA0 to BA2 are supplied. The supplied address signals A0 to A15 and BA0 to BA2 are supplied to an address input buffer 41 provided in the interface chip IF. The The output of the address input buffer 41 is commonly supplied to the core chips CC0 to CC7 via the TSV. When the mode register set is entered, the address signals A0 to A15 are supplied to the mode register 42 provided in the interface chip IF. The address signals BA0 to BA2 (bank addresses) are decoded by an address decoder (not shown) provided in the interface chip IF, and the bank selection signal B obtained thereby is supplied to the data latch circuit 25. This is because the bank selection of write data is performed in the interface chip IF.

  The data input / output terminal 14 is a terminal for inputting / outputting read data or write data DQ0 to DQ15. The data strobe terminals 15a and 15b are terminals for inputting / outputting strobe signals DQS and / DQS. The data input / output terminal 14 and the data strobe terminals 15a and 15b are connected to an input / output buffer circuit 23 provided in the interface chip IF. The input / output buffer circuit 23 includes an input buffer IB and an output buffer OB. In synchronization with the input / output clock signal LCLK supplied from the DLL circuit 22, read / write data DQ0 to DQ15 and a strobe signal are provided. Input / output DQS and / DQS. Further, when the internal on-die termination signal IODT is supplied from the command decoder 32, the input / output buffer circuit 23 causes the output buffer OB to function as a termination resistor. Further, the impedance code DRZQ is supplied from the calibration circuit 24 to the input / output buffer circuit 23, thereby designating the impedance of the output buffer OB. The input / output buffer circuit 23 includes a well-known FIFO circuit.

  The calibration circuit 24 includes a replica buffer RB having the same circuit configuration as that of the output buffer OB. When a calibration signal ZQ is supplied from the command decoder 32, an external resistor (connected to the calibration terminal 16 ( The calibration operation is performed by referring to the resistance value (not shown). The calibration operation is an operation for matching the impedance of the replica buffer RB with the resistance value of the external resistor, and the obtained impedance code DRZQ is supplied to the input / output buffer circuit 23. Thereby, the impedance of the output buffer OB is adjusted to a desired value.

  The input / output buffer circuit 23 is connected to the data latch circuit 25. The data latch circuit 25 includes a FIFO circuit (not shown) that realizes a FIFO function that operates by latency control that realizes a well-known DDR function, and a multiplexer MUX (not shown), and is supplied in parallel from the core chips CC0 to CC7. This circuit converts the read data into serial data and converts serial write data supplied from the input / output buffer into parallel data. Therefore, the data latch circuit 25 and the input / output buffer circuit 23 are serially connected, and the data latch circuit 25 and the core chips CC0 to CC7 are parallelly connected. In the present embodiment, the core chips CC0 to CC7 are back end portions of the DDR3 type SDRAM, and the prefetch number is 8 bits. The data latch circuit 25 and the core chips CC0 to CC7 are connected to each bank, and the number of banks included in each core chip CC0 to CC7 is eight banks. Therefore, the connection between the data latch circuit 25 and the core chips CC0 to CC7 is 64 bits (8 bits × 8 banks) per 1DQ.

  Thus, parallel data that has not been serially converted is basically input / output between the data latch circuit 25 and the core chips CC0 to CC7. That is, in a normal SDRAM (that is, a front end and a back end are configured by one chip), data is input / output serially to / from the outside of the chip (that is, the data input / output terminals are per 1DQ). On the other hand, in the core chips CC0 to CC7, data is input / output to / from the interface chip IF in parallel. This is an important difference between the normal SDRAM and the core chips CC0 to CC7. However, it is not essential to input / output all prefetched parallel data using different TSVs, and the number of TSVs required per DQ is reduced by performing partial parallel / serial conversion on the core chips CC0 to CC7 side. It doesn't matter. For example, instead of inputting / outputting 64 bits of data per 1DQ using different TSVs, the number of TSVs required per 1DQ is halved by performing 2-bit parallel / serial conversion on the core chips CC0 to CC7. It may be reduced to (32).

  Further, the data latch circuit 25 is added with a function of enabling a test for each interface chip. The interface chip has no back-end part. For this reason, it cannot be operated as a single unit in principle. However, if the single operation is impossible, the operation test of the interface chip in the wafer state cannot be performed. This indicates that the semiconductor device 10 can only be tested after the assembly process of the interface chip and the plurality of core chips, and means that the interface chip is tested by testing the semiconductor device 10. . If the interface chip has a defect that cannot be recovered, the entire semiconductor device 10 is lost. Considering this point, in the present embodiment, the data latch circuit 25 is provided with a part of a pseudo back-end portion for testing, and a simple storage function is possible at the time of testing.

  The power supply terminals 17a and 17b are terminals to which power supply potentials VDD and VSS are supplied, respectively, and connected to the power-on detection circuit 43 provided in the interface chip IF and also connected to the core chips CC0 to CC7 through the TSV. Has been. The power-on detection circuit 43 is a circuit that detects power-on, and activates the layer address control circuit 45 provided in the interface chip IF when power-on is detected.

  The layer address control circuit 45 is a circuit for changing the layer address according to the I / O configuration of the semiconductor device 10 according to the present embodiment. As described above, the semiconductor device 10 according to the present embodiment includes the 16 data input / output terminals 14, which allows the maximum number of I / Os to be set to 16 bits (DQ0 to DQ15). The number of / O is not fixed to this, and can be set to 8 bits (DQ0 to DQ7) or 4 bits (DQ0 to DQ3). The address allocation is changed according to the number of I / Os, and the layer address is also changed. The layer address control circuit 45 is a circuit that controls a change in address allocation according to the number of I / Os, and is commonly connected to each of the core chips CC0 to CC7 via the TSV.

  The interface chip IF is also provided with a layer address setting circuit 44. The layer address setting circuit 44 is connected to the core chips CC0 to CC7 via the TSV. The layer address setting circuit 44 is cascade-connected to the layer address generation circuit 46 of the core chips CC0 to CC7 using the TSV2 of the type shown in FIG. 2B, and the layers set in the core chips CC0 to CC7 at the time of testing. It plays the role of reading the address.

  Further, a defective chip information holding circuit 33 is provided in the interface chip IF. The defective chip information holding circuit 33 is a circuit that holds a chip number when a defective core chip that does not operate normally is found after assembly. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 through the TSV. The defective chip information holding circuit 33 is connected to the core chips CC0 to CC7 while being shifted using the TSV3 of the type shown in FIG.

  Further, a process monitor circuit 100 is provided in the interface chip IF. The process monitor circuit 100 is a circuit that detects an operation speed difference between the interface chip IF and each of the core chips CC0 to CC7 due to process conditions by measuring the operation speed of the replica circuit 300 provided in the core chips CC0 to CC7. is there. The detection result is stored in the timing data storage circuit 200 provided in the interface chip IF, and transferred to the output timing adjustment circuit 400 provided in each of the core chips CC0 to CC7 when the power is turned on. Details of the process monitor circuit 100 and the like will be described later. Note that the timing data storage circuit 200 may be provided in each of the core chips CC0 to CC7.

  The above is the outline of the connection relationship between the external terminal and the interface chip IF and the circuit configuration of the interface chip IF. Next, the circuit configuration of the core chips CC0 to CC7 will be described.

  As shown in FIG. 4, each of the memory cell arrays 50 included in the core chips CC0 to CC7, which are back-end functions, is divided into 8 banks. A bank is a unit that can accept commands individually. In other words, each bank can operate independently by mutually exclusive control. Each bank can be accessed independently from the outside of the semiconductor device 10. For example, the memory cell array 50 of the bank 1 and the memory cell array 50 of the bank 2 are non-exclusive control that can individually control access to the corresponding word line WL, bit line BL, etc. in the same period on the time axis by different commands. It is a relationship. For example, the bank 2 can be controlled to be active while the bank 1 is kept active (the word line and the bit line are active). However, the external terminals (for example, a plurality of control terminals and a plurality of I / O terminals) of the semiconductor device are shared. In the memory cell array 50, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections (in FIG. 4, one word line WL, 1 Only one bit line BL and one memory cell MC are shown). Selection of the word line WL is performed by the row decoder 51. The bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 53. Selection of the sense amplifier SA is performed by the column decoder 52.

  The row decoder 51 is controlled by a row address supplied from the row control circuit 61. The row control circuit 61 includes an address buffer 61 a that receives a row address supplied from the interface chip IF via the TSV, and the row address buffered by the address buffer 61 a is supplied to the row decoder 51. The address signal supplied via the TSV is supplied to the row control circuit 61 and the like via the input buffer B1. The row control circuit 61 also includes a refresh counter 61b. When a refresh signal is issued from the control logic circuit 63, the row address indicated by the refresh counter 61b is supplied to the row decoder 51.

  The column decoder 52 is controlled by a column address supplied from the column control circuit 62. The column control circuit 62 includes an address buffer 62a that receives a column address supplied from the interface chip IF via the TSV, and the column address buffered by the address buffer 62a is supplied to the column decoder 52. The column control circuit 62 also includes a burst counter 62b that counts the burst length.

  The sense amplifier SA selected by the column decoder 52 is further connected to the data control circuit 54 via some amplifiers (such as sub-amplifiers and data amplifiers) not shown. As a result, 8-bit (= prefetch number) read data is output from the data control circuit 54 per I / O (DQ) during the read operation, and 8-bit write data is data during the write operation. Input to the control circuit 54. The data control circuit 54 and the interface chip IF are connected in parallel via the TSV.

  The control logic circuit 63 is a circuit that receives the internal command ICMD supplied from the interface chip IF via the TSV and controls the operations of the row control circuit 61 and the column control circuit 62 based on the internal command ICMD. As shown in FIG. 4, the control logic circuit 63 includes an output timing adjustment circuit 400. The output timing adjustment circuit 400 serves to adjust the output timing of read data based on the output timing data stored in the timing data storage circuit 200 in the interface chip IF. A layer address comparison circuit (chip information comparison circuit) 47 is connected to the control logic circuit 63. The layer address comparison circuit 47 is a circuit that detects whether or not the core chip is an access target. The detection is performed by a part of the address signal SEL (chip selection information) supplied from the interface chip IF via the TSV. And the layer address LID (chip identification information) set in the layer address generation circuit 46 are compared. When a match is detected, the match signal HIT is activated. The coincidence signal HIT is supplied to the replica circuit 300 in addition to the control logic circuit 63.

  In the layer address generation circuit 46, a unique layer address is set to each of the core chips CC0 to CC7 at the time of initialization. The layer address setting method is as follows. First, when the semiconductor device 10 is initialized, a minimum value (0, 0, 0) is set as an initial value in the layer address generation circuit 46 of each of the core chips CC0 to CC7. The layer address generation circuits 46 of the core chips CC0 to CC7 are cascade-connected using the type of TSV shown in FIG. 2B and have an increment circuit therein. The layer address (0, 0, 0) set in the layer address generation circuit 46 of the uppermost core chip CC0 is sent to the layer address generation circuit 46 of the second core chip CC1 via the TSV and incremented. Thus, different layer addresses (0, 0, 1) are generated. Similarly, the generated layer address is transferred to the lower core chip, and the layer address generation circuit 46 in the transferred core chip increments this. In the layer address generation circuit 46 of the lowermost core chip CC7, the maximum value (1, 1, 1) is set as the layer address. Thereby, a unique layer address is set to each of the core chips CC0 to CC7.

  The layer address generation circuit 46 is supplied with a defective chip signal DEF from the defective chip information holding circuit 33 of the interface chip IF through the TSV. Since the defective chip signal DEF is supplied to each of the core chips CC0 to CC7 using the TSV3 of the type shown in FIG. 2C, an individual defective chip signal DEF can be supplied to each of the core chips CC0 to CC7. The defective chip signal DEF is a signal that is activated when the core chip is a defective chip. When the core chip is activated, the layer address generation circuit 46 uses a layer address that is not incremented instead of an incremented layer address. Transfer to the lower core chip. The defective chip signal DEF is also supplied to the control logic circuit 63. When the defective chip signal DEF is activated, the operation of the control logic circuit 63 is completely stopped. As a result, a defective core chip does not perform a read operation or a write operation even if an address signal or a command signal is input from the interface chip IF.

  The output of the control logic circuit 63 is also supplied to the mode register 64. Thereby, when the output of the control logic circuit 63 indicates the mode register set, the set value of the mode register 64 is overwritten by the address signal. Thereby, the operation mode of the core chips CC0 to CC7 is set.

  Furthermore, an internal voltage generation circuit 70 is provided in the core chips CC0 to CC7. The power supply potentials VDD and VSS are supplied to the internal voltage generation circuit, and the internal voltage generation circuit 70 receives these to generate various internal voltages. The internal voltage generated by the internal voltage generation circuit 70 includes an internal voltage VPERI (≈VDD) used as an operation power supply for various peripheral circuits, an internal voltage VARY (<VDD) used as an array voltage of the memory cell array 50, and the word line WL. An internal voltage VPP (> VDD) or the like which is an activation potential is included. In addition, the core chips CC0 to CC7 are also provided with a power-on detection circuit 71. When the power-on is detected, various internal circuits are reset.

  The peripheral circuits included in the core chips CC0 to CC7 operate in synchronization with the internal clock signal ICLK supplied from the interface chip IF via the TSV. The internal clock signal ICLK supplied via the TSV is supplied to various peripheral circuits via the input buffer B2.

  The above is the basic circuit configuration of the core chips CC0 to CC7. The core chips CC0 to CC7 are not provided with a front-end unit for interfacing with the outside, and therefore cannot be operated alone in principle. However, if the single operation is impossible, it becomes impossible to perform the operation test of the core chip in the wafer state. This indicates that the semiconductor device 10 can only be tested after the assembly process of the interface chip and the plurality of core chips, and means that each core chip is tested by testing the semiconductor device 10. To do. If the core chip has a defect that cannot be recovered, the entire semiconductor device 10 is lost. In consideration of this point, in the present embodiment, the core chips CC0 to CC7 include a plurality of test pads TP and a test front end unit of a test command decoder 65 for a pseudo front end unit for testing. Are provided, and an address signal, test data, and a command signal can be input from the test pad TP. It should be noted that the test front-end unit is a circuit having a function that realizes a simple test in the wafer test, and does not have all the front-end functions in the interface chip. For example, since the operating frequency of the core chip is lower than the operating frequency of the front end, it can be simply realized by a test front end circuit for testing at a low frequency.

  The type of the test pad TP is almost the same as that of the external terminal provided in the interposer IP. Specifically, a test pad TP1 to which a clock signal is input, a test pad TP2 to which an address signal is input, a test pad TP3 to which a command signal is input, a test pad TP4 for inputting / outputting test data, a data strobe A test pad TP5 for inputting and outputting signals, a test pad TP6 for supplying power supply potential, and the like are included.

  At the time of testing, a normal external command that has not been decoded is input, so that a test command decoder 65 is also provided in the core chips CC0 to CC7. Further, since serial test data is input / output during the test, the core chips CC0 to CC7 are also provided with a test input / output circuit 55.

  The above is the overall configuration of the semiconductor device 10 according to the present embodiment. As described above, since the semiconductor device 10 according to the present embodiment has a configuration in which eight 1 Gb core chips are stacked, the total memory capacity is 8 Gb. Further, since there is one terminal (chip selection terminal) to which the chip selection signal / CS is input, the controller recognizes it as a single DRAM having a memory capacity of 8 Gb.

  FIG. 5 is a circuit diagram of the process monitor circuit 100 and the replica circuit 300.

  The replica circuit 300 is a circuit provided in each of the core chips CC0 to CC7, and has a configuration in which a selection buffer 310 and a fixed delay circuit 320 are cascade-connected as shown in FIG. The fixed delay circuit 320 has a configuration in which a plurality of delay elements DLY are cascade-connected. The clock signal IN is commonly input from the interface chip IF to the selection buffer 310 of each of the core chips CC0 to CC7 via TSV1. Further, the delay signal PB0 is extracted from the input terminal of the fixed delay circuit 320, and the delay signal PA0 is extracted from the output terminal of the fixed delay circuit 320. Delay signals PB0 and PA0 output from the core chips CC0 to CC7 are supplied to the process monitor circuit 100 of the interface chip IF via the same TSV1. In this embodiment, the clock signal input to the command terminal 12e (terminal to which the on-die termination signal ODT is input during normal operation) is used as the clock signal IN supplied to the replica circuit 300. It is not limited and any signal may be used. Further, the signal is not limited to a signal supplied from the outside, and a signal generated inside the interface chip IF may be used as the clock signal IN.

  The delay amount of the signal path composed of the selection buffer 310 and the fixed delay circuit 320 is designed to match the delay amount of the control logic circuit 63 and the data control circuit 54. That is, the replica circuit 300 is a replica of the control logic circuit 63 and the data control circuit 54. Therefore, when the signal propagation time of the control logic circuit 63 and the data control circuit 54 is slower than the design value due to the process conditions, the delay time of the replica circuit 300 also depends on the result of the manufacturing conditions. Conversely, when the signal propagation time of the control logic circuit 63 and the data control circuit 54 is faster than the design value due to the result of the manufacturing conditions, the delay time of the replica circuit 300 is also the result of the manufacturing conditions. Faster. That is, each replica circuit 300 of each of the core chips CC0 to CC7 has a specific delay amount determined by the corresponding process condition.

  The selection buffer 310 is a circuit that operates when the coincidence signal HIT is activated. The coincidence signal HIT is a signal that becomes effective in one core chip among the core chips CC0 to CC7, for example. Therefore, the clock signal IN supplied from the interface chip IF to each of the core chips CC0 to CC7 is effective in any one of the core chips. That is, the delay signals PB0 and PA0 are supplied from any of the selected core chips to the interface chip IF.

  These delay signals PB0 and PA0 are input to the process monitor circuit 100 in the interface chip IF. As shown in FIG. 5, the process monitor circuit 100 includes a variable delay circuit 110 that can change the delay amount, and a delay control circuit 120 that adjusts the delay amount of the variable delay circuit 110.

  The variable delay circuit 110 is a circuit in which the delay amount of the variable delay circuit 110 can be adjusted based on the adjustment code CO supplied from the delay control circuit 120, and a delay signal PB0 is input to the input end thereof via TSV1. The The delay control circuit 120 includes a counter 121 that generates an adjustment code CO that is a count value, a phase comparison circuit 122 that is connected to the output terminal of the variable delay circuit 110 and the output terminal of the fixed delay circuit 320 via TSV1, and the phase Gate circuits G1 to G3 that control the counter 121 based on the output of the comparison circuit 122 are included. The TSV connecting the process monitor circuit 100 and the replica circuit 300 is preferably a test TSV included in a data I / O TSV group in order to increase the accuracy of monitoring. The test TSV is a concept of safety design used in, for example, an aircraft that physically uses two TSVs for one electrical signal. As a result, even if there is a problem with one TSV, the test is executed without relieving the TSV to another TSV by the redundancy technique.

  More specifically, the variable delay circuit 110 has a configuration in which a plurality of delay elements DLY are cascade-connected, some of which are passed by the adjustment code CO. Note that “path” means that the input signal at the input end is output to the output end without being delayed. Thereby, the delay amount can be changed based on the adjustment code CO. As shown in FIG. 5, the delay signal PB1 is extracted from the input terminal of the last delay element DLYn included in the variable delay circuit 110, and the delay signal PB2 is extracted from the output terminal of the delay element DLYn. These delay signals PB1 and PB2 are supplied to the inverting input terminals (−) of the comparators 122a and 122b included in the phase comparison circuit 122, respectively. The delay signal PA0 output from the fixed delay circuit 320 via TSV1 is commonly input to the non-inverting input terminals (+) of the comparators 122a and 122b.

  With this configuration, the phases of the delay signal PA0 via the signal path PA and the delay signals PB1 and PB2 via the signal path PB shown in FIG. 5 are determined, respectively. The count signal DOWN or the adjustment end flag END is generated by the gate circuits G1 to G3. The outputs of these gate circuits G1 to G3 are supplied to the counter 121, and the count value (that is, the adjustment code CO) is counted up or down. If the adjustment end flag END is activated, the current count value (adjustment code CO) is output to the data latch circuit 25 shown in FIG. The adjustment end flag END is activated when the outputs of the comparators 122a and 122b match, that is, when the delay amount of the variable delay circuit 110 of the interface chip IF matches the delay amount of the fixed delay circuit 320 of the core chip. Therefore, the adjustment code CO finally obtained is information indicating the difference between the operation speed of the selected core chip and the operation speed of the interface chip IF. The adjustment code CO supplied to the data latch circuit 25 is output to the outside of the semiconductor device 10 via the input / output buffer circuit 23 and the data input / output terminal 14.

  As shown in FIG. 5, the process monitor circuit 100 and the replica circuit 300 are provided with several dummy circuits DUM1 to DUM4 so that the comparison conditions are matched. Specifically, the dummy circuits DUM1 and DUM2 are dummy circuits for the comparators 122a and 122b, respectively, and are provided to match the loads of the signal paths PA and PB. The dummy circuits DUM3 and DUM4 are also provided to match the loads of the signal paths PA and PB.

  FIG. 6 is a flowchart for explaining a method of obtaining the adjustment code CO.

  First, by issuing a predetermined test command from the external tester 600 shown in FIG. 7, the semiconductor device 10 is entered into the process monitor test mode (step S11). Such a test mode is performed by setting predetermined values in the mode registers 42 and 64.

  Next, by inputting an address signal from the tester 600, one of the core chips CC0 to CC7 is selected (step S12). That is, the coincidence signal HIT is activated in any one of the core chips CC0 to CC7, and the selection buffer 310 shown in FIG. In this state, by inputting the clock signal IN from the command terminal 12e, the clock signal IN is supplied to the replica circuit 300 of each core chip CC0 to CC7 (step S13). Here, the selection buffer 310 is operating only in one selected core chip. Therefore, the clock signal IN propagates only through the replica circuit 300 in the selected core chip.

  Next, the adjustment code CO is generated by activating the delay control circuit 120 in the process monitor circuit 100 (step S14). That is, the adjustment code CO is counted up or down according to the phases of the delay signal PA0 via the signal path PA and the delay signals PB1 and PB2 via the signal path PB shown in FIG. The process is repeated until the delay amount of the circuit 110 matches the delay amount of the fixed delay circuit 320. When the delay amount of the variable delay circuit 110 matches the delay amount of the fixed delay circuit 320, the adjustment end flag END is activated (step S15), and the adjustment code CO at this time is output to the tester via the data input / output terminal 14. (Step S16).

  The above operation is performed for each of the core chips CC0 to CC7 by switching the layer address. When the test for all the core chips CC0 to CC7 is completed (step S17: YES), the process monitor test mode is exited, and a series of operations are performed. The process ends (step S18).

  When the above processing is completed, the adjustment code CO corresponding to each of the core chips CC0 to CC7 is stored in the table 610 in the tester 600. The adjustment code CO stored in the tester in this way is converted into output timing data as necessary in the tester 600 and then written in the timing data storage circuit 200 in the interface chip IF. However, such conversion is not essential, and the adjustment code CO itself written in the table 610 may be used as output timing data. In the present embodiment, the output timing data and the adjustment code are the same signal, but the adjustment code written in the timing data storage circuit 200 is expressed as output timing data.

  FIG. 8 is a flowchart for explaining an operation of writing output timing data to the timing data storage circuit 200.

  First, by issuing a predetermined test command from the tester 600 shown in FIG. 7, the semiconductor device 10 is entered into the output timing data writing mode (step S21). Such a test mode is performed by setting predetermined values in the mode registers 42 and 64.

  Next, the output timing data stored in the table 610 in the tester 600 is input to the interface chip IF via the data input / output terminal 14 (step S22). The output timing data input to the interface chip IF is supplied to the timing data storage circuit 200. The timing data storage circuit 200 is provided with a plurality of nonvolatile storage elements such as antifuse elements, and output timing data is written to these nonvolatile storage elements (step S23).

  When the writing of the output timing data is completed, the output timing data writing mode is exited, and the series of processing ends (step S24). As described above, in this embodiment, the output timing data corresponding to each of the core chips CC0 to CC7 is not stored in the core chip but is collectively stored in the timing data storage circuit 200 in the interface chip IF. The output timing data stored in the timing data storage circuit 200 in this way is transferred to the corresponding core chips CC0 to CC7 when the power is turned on.

  FIG. 9 is a flowchart for explaining an operation of transferring output timing data from the timing data storage circuit 200 to the core chips CC0 to CC7.

  First, when the semiconductor device 10 is turned on (step S31), a reset signal is generated by the power-on detection circuits 43 and 71 (step S32), and an initialization operation is performed in the interface chip IF and the core chips CC0 to CC7. It starts (step S33).

  In the initialization operation, the control logic circuit 63 included in any of the core chips CC0 to CC7 is activated by inputting an address signal from the interface chip IF to the core chips CC0 to CC7 (step S34). By transferring the output timing data from the timing data storage circuit 200 via the TSV, the output timing data corresponding to the output timing adjustment circuit 400 in the activated control logic circuit 63 is written (step S35). The output timing data may be transferred using a dedicated TSV, or using a TSV that is not currently used (in a series of operations according to the flowchart of FIG. 9 at power-on) (for example, a part of the address TSV). It doesn't matter.

  The above operation is performed for each of the core chips CC0 to CC7 by switching the layer address, and when the transfer of the output timing data to all the core chips CC0 to CC7 is completed (step S36: YES), the initialization operation is performed. The process ends (step S37). As a result, the corresponding output timing data is set in the output timing adjustment circuits 400 of the core chips CC0 to CC7.

  FIG. 10 is a schematic block diagram for explaining the overall signal flow during the read operation.

  As shown in FIG. 10, an address signal ADD and a command signal CMD input to the interface chip IF from the outside are supplied to input buffers 31 and 41 in the interface chip IF. These signals are supplied to the command decoder 32 and the like, and predetermined processing is performed in the address / command control circuits 32a and 32b, the column control circuit 32c, and the input / output control circuit 32e included in the command decoder 32, and the generated control is performed. A signal is supplied to the data latch circuit 25. The data latch circuit 25 includes a TSV buffer 25a and a read / write bus 25b. The control signal generated by the command decoder 32 is supplied to the data latch circuit 25 and the input / output buffer circuit 23, whereby the input / output timing of data is controlled.

  A TSV buffer 32d included in the command decoder 32 is connected to each of the core chips CC0 to CC7 via the TSV. The internal command ICMD supplied from the TSV buffer 32d is received by the TSV buffer 63a included in the control logic circuit 63 in the core chip, and the address / command control circuit 63b, the column control circuit 63c, and the output control circuit 63d Processing is performed. The output control circuit 63d includes an output timing adjustment circuit 400. As described above, the output timing data transferred from the timing data storage circuit 200 in the interface chip IF when power is turned on is set here. .

  The output timing data is supplied to the read / write bus 54a and the TSV buffer 54b included in the data control circuit 54 in the core chip, whereby the output timing of the read data from the core chips CC0 to CC7 to the interface chip IF is controlled. The storage information of a plurality of bits accessed in association with one read command is 8 bits (= prefetch) per I / O (DQ) from the memory cell array 50 via the sense circuit 53 and the column decoder 52. Number) of read data is connected to a data control circuit 54.

  FIG. 11 is a schematic diagram for explaining the flow of read data.

  As shown in FIG. 11, the TSV buffer 54b in the data control circuit 54 in the core chip includes a data output circuit 54o and a data input circuit 54i. The input terminal of the data output circuit 54 o and the output terminal of the data input circuit 54 i are connected to various amplifiers included in the sense circuit 53 and the column decoder 52 via the read / write bus 54 a and finally connected to the memory cell array 50. Has been.

  An output timing signal DRAO_CORE is supplied from the output timing adjusting circuit 400 in the control logic circuit 63 to the data output circuit 54o. That is, the data output circuit 54o is a clocked driver controlled by the output timing signal DRAO_CORE. The output timing signal DRAO_CORE is a signal that specifies the operation timing of the data output circuit 54o (that is, a signal that outputs a read data signal on the read / write bus 54a read from the memory cell array 50 to the TSV), and its activation timing is It is adjusted according to the set output timing data.

  Read data (read data signal) input to the interface chip IF via the TSV is supplied to a data input circuit 25i included in the TSV buffer 25a. The TSV buffer 25a also includes a data output circuit 25o. The input terminal of the data output circuit 25o and the output terminal of the data input circuit 25i are connected to the input / output buffer circuit 23 via the read / write bus 25b.

  An input timing signal DRAO_IF is supplied to the data input circuit 25i from the command decoder 32 of the interface chip IF. That is, the data input circuit 25i is a clocked receiver controlled by the input timing signal DRAO_IF. The input timing signal DRAO_IF is a signal for designating the permission timing (capture timing) of the read data output from the core chip to the interface chip IF via the TSV by the data input circuit 25i. Functions as a circuit. In the present embodiment, the activation timing of the input timing signal DRAO_IF by the command decoder 32 is fixed to a unique timing (first latency) determined by the process conditions (manufacturing conditions) of the interface chip IF. On the other hand, the activation timing (second latency) of each output timing signal DRAO_CORE on each of the core chips CC0 to CC7 is adjusted by the corresponding output timing data that has been tested and adjusted in advance by the process monitor circuit 100 described above. Therefore, the activation timings of the input timing signal DRAO_IF and the output timing signal DRAO_CORE of each of the plurality of core chips are almost the same.

  FIG. 12 is a circuit diagram of the output timing adjustment circuit 400.

  As shown in FIG. 12, the output timing adjustment circuit 400 includes a signal generation circuit 401 that generates an original signal DRAO_COREX from a signal MDRDT_CORE and a plurality of cascaded delay circuits 410 to 470 that transmit the original signal DRAO_COREX. The output from the delay circuit 470 at the final stage is used as the output timing signal DRAO_CORE. Each of the delay circuits 410 to 470 includes delay elements 411 to 471 and multiplexers 421 to 472. Based on the logic levels of the corresponding selection signals TCO1 to TCO7, each of the delay circuits 411 to 471 passes (delays) the delay elements 411 to 471. Or not) is selected. Thus, when all the delay elements 411 to 471 are passed, the delay amount of the output timing adjustment circuit 400 is minimized, and the activation timing of the output timing signal DRAO_CORE is the fastest. On the contrary, when all the delay elements 411 to 471 are passed, the delay amount of the output timing adjustment circuit 400 becomes the maximum, and the activation timing of the output timing signal DRAO_CORE becomes the latest.

  FIG. 13 is a circuit diagram of a selection signal generation circuit 480 that generates selection signals TCO1 to TCO7.

  As shown in FIG. 13, the selection signal generation circuit 480 extracts and outputs the upper 3 bits CO [5: 3] from the set 6-bit output timing data CO [5: 0], and outputs the output circuit 481. And a decoder 482 that decodes the upper 3 bits CO [5: 3] of the output timing data. Of the 8-bit signal obtained by decoding, a 7-bit signal excluding the selection signal TCO0 is used as the selection signals TCO1 to TCO7. Here, among the set 6-bit output timing data CO [5: 0], only the upper 3 bits CO [5: 3] are used because the measurement accuracy of the process monitor circuit 100 is taken into consideration.

  FIG. 14 is a table for explaining the relationship between the upper 3 bits CO [5: 3] of the output timing data and the set delay amount.

  As shown in FIG. 14, the case where the upper 3 bits CO [5: 3] of the output timing data is (0, 1, 1) is the default value. The speed can be reduced. Actually, as the operation speed of the core chip is determined to be faster than the operation speed of the interface chip IF by the process monitor circuit 100, the number of delay elements 411 to 471 through which the original signal DRAO_COREX passes is increased. More delay amount (plus offset) is given to DRAO_COREX to increase the propagation delay amount of the output timing signal DRAO_CORE. Conversely, as the operation speed of the core chip is determined to be slower than the operation speed of the interface chip IF by the process monitor circuit 100, the number of delay elements 411 to 471 through which the original signal DRAO_COREX passes is reduced, thereby reducing the original signal DRAO_COREX. A smaller delay amount (minus offset) is given to reduce the propagation delay amount of the output timing signal DRAO_CORE.

  That is, as shown in FIG. 14, the operation speed of the interface chip is used as a reference (default) based on the test results detected by the process monitor 100 in the interface chip and the replica circuit 300 in each core chip. A plurality of positive offset values (+1 to +4) in four stages different from the default value from the default value and a plurality of negative offsets (−1 to −3) in three stages are disclosed. The delay amount and default of these offsets are given to all the core chips. For example, the timing of the read data output of the core chip whose operation speed is slower than that of the interface chip (= clock timing of the clocked driver) is negative offset, It matches the input timing of the read data of the interface chip (= clock timing of the clocked receiver). The core chip read data output timing (= clocked driver clock timing), which is faster than the interface chip, matches the interface chip read data input timing (= clocked receiver clock timing) due to the plus offset. Is done. When the operating speed of the interface chip and the operating speed of the core chip are the same, a default value is given to the core chip, and the read data output timing (= clock timing of the clocked driver) It matches the timing (= clock timing of the clocked receiver).

  FIG. 15 is a timing diagram for explaining the effect of adjustment by the output timing adjustment circuit 400.

  The waveforms of (a) to (c) shown in FIG. 15 are all signal waveforms on the core chip side, and (a) shows the case where the operating speed of the first core chip is equivalent to that of the interface chip IF. ) Shows the case where the operating speed of the second core chip is faster than the interface chip IF, and (c) shows the case where the operating speed of the third core chip is slower than the interface chip IF. The waveforms (a) to (c) may be considered as a result of the respective manufacturing conditions in one core chip. The lower waveform shown in FIG. 15 is a signal waveform in the interface chip IF.

  In FIG. 15, “_IF”, “_CORE”, and “_TSV” added to each signal described below indicate a signal in the interface chip IF, a signal in the core chip, and a signal in the through silicon via TSV, respectively. Show. In addition, each signal is associated with FIG. The signal MDRDT is a signal for determining an internal read command generated by the address / command control circuit 32a in the command decoder 32 in the interface chip IF based on a read command READ supplied from the outside. The signal MDRDT_IF is an address. A signal that determines an internal read command generated by the command control circuit 32b, and a signal MDRDT_CORE is a signal that determines an internal read command generated by the address / command control circuit 63b from the internal read command transferred to the core chip. The signal DRAE_CORE is a signal generated by the column control circuit 63c and determines the output timing of the read data of the memory cell array to the read / write bus 54a. The signal RWBS_CORE is a signal that determines the read data on the read / write bus 54a. DRAO_CORE is a signal that determines the operation timing (drive timing) of the TSV buffer 54b generated by the output timing adjustment circuit 400, and the signal DATA_TSV is a signal that determines read data read from the memory cell array on the TSV. The signal RWBS_IF is a signal that determines read data on the read / write bus 25b, and the signal DRAO_IF is a signal that determines the operation timing (receive timing or latch timing) of the TSV buffer 25a generated by the input / output control circuit 32e.

  As shown in FIG. 15A, when the operating speed of the core chip is equivalent to that of the interface chip IF, the output timing data is set to the default value shown in FIG. On the other hand, as shown in FIG. 15B, when the operating speed of the core chip is faster than the interface chip IF, the delay amount of the output timing data in the core chip is increased more than the default delay amount. The activation timing of the output timing signal DRAO_CORE is delayed. As a result, the signal DATA_TSV is controlled at the same time as the signal DATA_TSV indicated by (a). Also, as shown in FIG. 15C, when the operating speed of the core chip is slower than the interface chip IF, the output timing signal DRAO_CORE is reduced by reducing the delay amount of the output timing data from the default amount of delay. The activation timing of is accelerated. As a result, the signal DATA_TSV is controlled at the same time as the signal DATA_TSV indicated by (a).

  Thereby, the read timing of the read data (second latency) in the interface chip IF is set to each core chip even though the input timing signal DRAO_IF on the interface chip IF side is fixed to a specific timing (first latency). It becomes possible to synchronize with the output timing of each read data on the CC0 to CC7 side.

  FIG. 16 is a schematic diagram showing the flow of a read command and read data.

  As shown in FIG. 16, the read command MDRDT_TSV output from the TSV buffer 32d of the interface chip IF in relation to the signal MDRDT in the interface chip IF is commonly supplied to the core chips CC0 to CC7. Only one core chip with the matching layer address accepts the read command MDRDT_TSV. The control logic circuit 63 in the core chip that has received the read command MDRDT_TSV generates the read command MDRDT_CORE and the signal DRAO_CORE, and activates the data output circuit 54o based on the delay amount set in the output timing adjustment circuit 400. The data output circuit 54o supplies the read data DATA_TSV to the interface chip IF via the TSV. The TSV to which the read data DATA_TSV is transmitted is shared by the core chips CC0 to CC7. However, as described above, the valid read command MDRDT_CORE is accepted only from one core chip having the same layer address. Read data is output from a plurality of core chips to the same TSV at the same time, and bus fight is not performed.

  The read data DATA_TSV supplied from the core chip to the interface chip IF via the TSV is latched in the data latch circuit 25 in the interface chip IF, but the latch timing (that is, fetching of the read data DATA_TSV into the interface chip IF) Is fixedly determined by the input timing signal DRAO_IF in the interface chip IF. More specifically, the read data output from each core chip arrives at the same time at the point of the data latch circuit 25 of the interface chip. However, in this embodiment, the read data DATA_TSV is output from each core chip in accordance with the activation timing of the input timing signal DRAO_IF, so that the operation speed of the interface chip IF or the core chips CC0 to CC7 depends on the process conditions (manufacturing conditions). Is different from the design value, the data latch circuit 25 in the interface chip IF can correctly latch the read data DATA_TSV at one and the same time.

  FIG. 17 is a block diagram showing a configuration of a data processing system 500 using the semiconductor device 10 according to a preferred embodiment of the present invention.

  A data processing system 500 shown in FIG. 17 has a configuration in which a data processor 520 and the semiconductor device (DRAM) 10 according to the present embodiment are connected to each other via a system bus 510. Examples of the data processor 520 include, but are not limited to, a microprocessor (MPU), a digital signal processor (DSP), and the like. In FIG. 10, for simplicity, the data processor 520 and the DRAM 530 are connected via the system bus 510, but they may be connected via a local bus without passing through the system bus 510. The data processor 520 includes a memory controller that controls the DRAM 10, a read command is issued from the data processor 520 to the DRAM 10, and read data is output from the DRAM 10 to the data processor 520.

  In FIG. 17, only one set of system buses 510 is illustrated for simplicity, but may be provided serially or in parallel via a connector or the like as necessary. In the memory system data processing system shown in FIG. 17, a storage device 540, an I / O device 550, and a ROM 560 are connected to the system bus 510, but these are not necessarily essential components.

  Examples of the storage device 540 include a hard disk drive, an optical disk drive, and a flash memory. Examples of the I / O device 550 include a display device such as a liquid crystal display and an input device such as a keyboard and a mouse.

  Further, the I / O device 550 may be only one of the input device and the output device. Furthermore, although each component shown in FIG. 17 is drawn one by one for simplicity, it is not limited to this, and a plurality of one or more components may be provided.

  In the embodiment of the present invention, the controller issues a command related to the read command to the interface chip. The interface chip that receives the command from the controller issues a read command to a plurality of core chips. Any of the plurality of core chips receives the read command and outputs read data, which is information of the memory cell array corresponding to the read command, to the interface chip. The interface chip that has received the read data from any of the plurality of core chips outputs the read data to the controller. The command issued by the controller is a so-called command (read command as a system) defined by an industry group that controls a known semiconductor device. The read command issued by the interface chip to the core chip is a control signal inside the semiconductor chip. The same applies to the read data.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, a DDR3 type SDRAM is used as a plurality of core chips each having the same function, but the present invention is not limited to this. Therefore, it may be a DRAM other than the DDR3 type, and may be a semiconductor memory other than DRAM (SRAM (Static Random Access Memory), PRAM (Face Change Random Access Memory), MRAM (Magnetic Random Access Memory), Flash Memory, etc.). It does not matter. Further, the core chip may be a plurality of semiconductor chips each having a function other than the semiconductor memory and having the same function or different functions. Further, it is not essential that all the core chips are laminated, and a part or all of the core chips may be arranged in a plane. Further, the number of core chips is not limited to eight.

  In the above embodiment, the output timing data is stored in the timing data storage circuit 200 in the interface chip IF. However, this point is not essential in the present invention, and the output timing data is stored in the individual core chips CC0 to CC7. You may memorize it. Further, it is not essential that the adjustment code obtained by the process monitor circuit 100 is temporarily stored in the table in the tester, and may be directly written in the timing data storage circuit 200, or once stored in the cache in the interface chip IF. The timing data storage circuit 200 may be written.

  Furthermore, in the above embodiment, the replica circuit 300 is provided in each of the core chips CC0 to CC7. However, in the process monitor operation, an actual signal path may be used instead of the replica circuit 300. The actual signal path refers to various signal generation circuits from the address / command control circuit 63b in the core chip to the output timing adjustment circuit 400 in FIG. 10, in other words, from the signal MDRDT_CORE to the signal DRAO_CORE (default value delay amount). It is a signal path to. Further, instead of the variable delay circuit 110, various signal generation circuits from the address / command control circuit 32a to the input / output control circuit 32e in the interface chip IF, in other words, an actual signal path from the signal MDRDT_IF to the signal DRAO_IF is used. It doesn't matter.

  Further, the basic technical idea of the present application is not limited to this. For example, each core chip has been disclosed as a plurality of chips of semiconductor memories each having the same function, but the basic technical idea of the present application is not limited to this. Each of these may be a plurality of core chips having the same function or different functions. That is, each of the IF chip and the core chip may be a silicon chip having a specific function. For example, each of the plurality of core chips may be a DSP chip having the same function, and may include an interface chip (ASIC) common to the plurality of core chips. The core chips preferably have the same function and are manufactured with the same mask. However, due to in-plane distribution within the same wafer, wafer differences, lot differences, and the like, the post-manufacture characteristics may be different. Further, for example, each core chip has a different storage function (the first core chip is a DRAM, the second chip is an SRAM, the third chip is a nonvolatile memory, and the fourth chip is a DSP). An interface chip (ASIC) manufactured by a mask and common to the plurality of core chips may be provided.

  In addition, in the case of a COC (chip on chip) having a structure using TSV, a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an ASSP (Application The present invention can be applied to semiconductor products such as Specific Standard Circuit). The device to which the present application is applied can also be applied to semiconductor devices such as SOC (system on chip), MCP (multichip package), and POP (package on package).

  The transistor may be a field effect transistor (FET) or a bipolar transistor. In addition to MOS (Metal Oxide Semiconductor), the present invention can be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor). It can be applied to various FETs such as transistors. Transistors other than FETs may be used. A part of the bipolar transistor may be included. A P-channel transistor or a PMOS transistor is a typical example of a first conductivity type transistor, and an N-channel transistor or an NMOS transistor is a typical example of a second conductivity type transistor. Furthermore, the semiconductor substrate is not limited to a P-type semiconductor substrate, and may be an N-type semiconductor substrate, a semiconductor substrate having an SOI (Silicon on Insulator) structure, or another semiconductor substrate.

  Furthermore, various test circuits (test circuit in the core chip, test circuit in the interface chip), non-volatile memory circuit, buffer in the core chip, test entry circuit in the interface chip, test signal generation circuit, input external terminals thereof, etc. The circuit format is not limited to the circuit format disclosed in the embodiment.

  Furthermore, the structure of TSV is not ask | required. Further, the circuit format of the TSV buffer (driver, receiver) is not limited.

  Further, various combinations or selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1-3 TSV
4-6 Internal circuit 10 Semiconductor device 11a, 11b Clock terminal 11c Clock enable terminal 12a-12e Command terminal 13 Address terminal 14 Data input / output terminal 15a, 15b Data strobe terminal 16 Calibration terminal 17a, 17b Power supply terminal 21 Clock generation circuit 22 DLL circuit 23 Input / output buffer circuit 24 Calibration circuit 25 Data latch circuit 25a TSV buffer 25b Read / write bus 25i Data input circuit 25o Data output circuit 31 Command input buffer 32 Command decoder 32e Input / output control circuit 33 Defective chip information holding circuit 41 Address Input buffer 42 Mode register 43 Power-on detection circuit 44 Layer address setting circuit 45 Layer address control circuit 46 Layer address generation circuit 46a Layer Address register 46b Increment circuit 46c Transfer circuit 47 Layer address comparison circuit 47a Layer address selection circuit 47x Row address comparison circuit 47y Column address comparison circuit 50 Memory cell array 51 Row decoder 52 Column decoder 53 Sense circuit 54 Data control circuit 54a Read / write bus 54b TSV Buffer 54i Data input circuit 54o Data output circuit 55 Input / output circuit 61 Row control circuit 62 Column control circuit 63 Control logic circuit 63a Latch circuit 63b, 63c Control circuit 63x Row command control circuit 63y Column command control circuit 64 Mode register 63a TSV buffer 63b Address / command control circuit 63c Column control circuit 63d Output control circuit 65 Command decoder 70 Internal voltage generation circuit 1 power-on detecting circuit 80 a silicon substrate 81 interlayer insulating film 82 insulating ring 83 and 86 TSV end 84 rear surface bump 85 surface bump 91 electrode 92 through-hole electrodes 93 rewiring layer 94 NCF
95 Lead frame 96 Underfill 97 Sealing resin 100 Process monitor circuit 110 Variable delay circuit 120 Delay control circuit 121 Counter 122 Phase comparison circuit 122a, 122b Comparator 200 Timing data storage circuit 300 Replica circuit 310 Selection buffer 320 Fixed delay circuit 400 Output timing Adjustment circuit 401 Signal generation circuit 410-470 Delay circuit 411-471 Delay element 421-472 Multiplexer 480 Selection signal generation circuit 481 Output circuit 482 Decoder 500 Data processing system 510 System bus 520 Data processor 540 Storage device 550 Device 600 Tester 610 Table CC0 ~ CC7 Core chip ICCMD Internal column command ICMD Internal command IF Interface Suchippu IP interposer IRCMD internal row command LID layer address (chip identification information)
RCMD Low command SB External terminal SEL Chip selection information TSV Through electrode

Claims (23)

A plurality of core chips each including an output terminal;
An input terminal electrically connected in common to the output terminal; and a data input circuit that receives a plurality of read data supplied from the output terminal via the input terminal, and at least leads to the plurality of core chips. An interface chip for issuing commands,
Each of the plurality of core chips includes a data output circuit that outputs the read data to the output terminal in response to the read command, and an output timing adjustment circuit that adjusts an output period from a first time to a second time. Including
The output period is a time from receiving the read command to outputting the read data from the data output circuit to the output terminal,
The semiconductor device, wherein the second times of the plurality of core chips are substantially the same. The interface chip includes an input timing circuit that controls the data input circuit to take in the read data at a timing after an input period has elapsed from the issue of the read command;
The semiconductor device according to claim 1, wherein the output timing adjustment circuit adjusts the output period based on the input period. The interface chip further includes a process monitor circuit that detects an operation speed difference between a first operation speed of each of the plurality of core chips and a second operation speed of the interface chip;
2. The semiconductor device according to claim 1, wherein the output timing adjustment circuit adjusts the output period so that the first operation speed matches the second operation speed.   The output timing adjustment circuit delays an output timing signal that defines a timing for outputting the read data when the process monitor circuit determines that the first operation speed is faster than the second operation speed. The semiconductor device according to claim 3.   The output timing adjustment circuit accelerates an output timing signal that defines a timing for outputting the read data when the process monitor circuit determines that the first operation speed is slower than the second operation speed. Item 4. The semiconductor device according to Item 3. Each of the plurality of core chips includes a fixed delay circuit having a specific delay amount determined by a process condition of the core chip,
The process monitor circuit includes a variable delay circuit capable of changing a delay amount determined by a process condition and an adjustment code of the interface chip, and a delay amount of the variable delay circuit matches a delay amount of the plurality of fixed delay circuits. A delay control circuit that changes the adjustment code to
The semiconductor device according to claim 3, wherein the output timing adjustment circuit adjusts the output period based on output timing data including the adjustment code or a code generated based on the adjustment code. The interface chip further includes a timing data storage circuit that stores the adjustment code or the output timing data,
The semiconductor device according to claim 6, wherein the adjustment code or the output timing data stored in the timing data storage circuit is supplied to each of the corresponding core chips when power is turned on.   The semiconductor device according to claim 1, wherein the plurality of core chips are stacked. The plurality of core chips each include a plurality of through electrodes penetrating the semiconductor substrate,
The semiconductor device according to claim 8, wherein the through electrodes that transmit the read data are electrically connected to each other between the core chips.   The semiconductor device according to claim 8, wherein the plurality of core chips and the interface chip are stacked. The interface chip has a front-end function for communicating with the outside at a first operating frequency,
2. The semiconductor device according to claim 1, wherein each of the plurality of core chips has a back-end function that communicates with the interface chip at a second operating frequency lower than the first operating frequency.   2. The semiconductor according to claim 1, wherein the number of bits of the plurality of read data simultaneously output from the interface chip to the outside is smaller than the number of bits of the plurality of read data simultaneously output from the plurality of core chips to the interface chip. apparatus.   13. The semiconductor device according to claim 12, wherein the interface chip converts the plurality of read data supplied in parallel from one of the plurality of core chips into serial read data, and outputs the serial read data to the outside. Each of the plurality of core chips further includes a memory cell array that stores a plurality of data,
14. The semiconductor device according to claim 13, wherein each of the plurality of core chips simultaneously outputs the read data including a plurality of prefetch data read from the memory cell array in response to the read command in parallel. Preparing a semiconductor device having a plurality of core chips each including an output terminal and an interface chip including an input terminal electrically connected in common to the output terminals of the plurality of core chips;
Detecting an operating speed difference between a first operating speed of each of the plurality of core chips and a second operating speed of the interface chip;
Based on the corresponding operating speed difference, the output timing from when the plurality of core chips receive the read command issued from the interface chip to when the read data is output to the interface chip is determined between the plurality of core chips. A method for adjusting a semiconductor device to match.   The matching step is performed by adjusting an output period from a first time to a second time, and the output period is a time from when the read command is received until the read data is output to the output terminal. The semiconductor device adjustment method according to claim 15, wherein the second times of the plurality of core chips are substantially the same as each other.   17. The semiconductor device adjustment method according to claim 16, wherein the matching step is performed based on an input period indicating a period from when the read command is issued until the interface chip captures the read data.   16. The semiconductor device according to claim 15, wherein the matching step is performed so as to delay an output timing signal that determines a timing for outputting the read data for a core chip having the first operation speed higher than the second operation speed. Adjustment method.   16. The semiconductor device according to claim 15, wherein the matching step is performed so as to advance an output timing signal that determines a timing for outputting the read data for a core chip having the first operation speed slower than the second operation speed. Adjustment method. Each of the plurality of core chips includes a fixed delay circuit having a specific delay amount determined by a process condition of the core chip,
The interface chip includes a variable delay circuit capable of changing a delay amount determined by a process condition and an adjustment code of the interface chip,
The difference in operating speed between each of the second operating speed and each of the plurality of first operating speeds is such that the delay amount of the variable delay circuit matches the delay amount of the plurality of fixed delay circuits, respectively. The semiconductor device adjustment method according to claim 15, wherein the detection is performed by changing the adjustment code.   21. The semiconductor device adjustment method according to claim 20, wherein output timing data including the adjustment code or a code generated based on the adjustment code is stored in the interface chip.   22. The method of adjusting a semiconductor device according to claim 21, wherein when the power is turned on, the interface chip supplies the adjustment code or the output timing data to the corresponding core chips. A semiconductor device;
A controller connected to the semiconductor device,
The semiconductor device includes:
A plurality of core chips each including an output terminal;
An input terminal electrically connected in common to the output terminal; and a data input circuit that receives a plurality of read data supplied from the output terminal via the input terminal, and at least leads to the plurality of core chips. An interface chip for issuing commands,
Each of the plurality of core chips includes a data output circuit that outputs the read data to the output terminal in response to the read command, and an output timing adjustment circuit that adjusts an output period from a first time to a second time. Including
The output period is a time from receiving the read command to outputting the read data from the data output circuit to the output terminal,
The second times of the plurality of core chips are substantially the same as each other;
The controller issues a command related to the read command to the interface chip;
The interface chip that receives the command from the controller issues the read command to the plurality of core chips,
Any of the plurality of core chips receives the read command and outputs the read data corresponding to the read command to the interface chip,
The data processing system, wherein the interface chip that has received the read data from any of the plurality of core chips outputs the read data to the controller.

Images