JP2015007721A - Display panel and method for manufacturing display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display panel and a method for manufacturing a display panel, in which a polishing amount of an outer edge of an array substrate can be determined in a short time by an easy method.SOLUTION: The display panel includes an array substrate 1, a first inspection terminal and a second inspection terminal, an inspection wiring line, and a counter substrate 2. The array substrate 1 has a planned line e2 of an outer edge. The first inspection terminal and the second inspection terminal are disposed on a normal region of the array substrate 1 and exposed to the outside. The inspection wiring line is disposed on the array substrate 1, located on an end side of the array substrate 1 with respect to the planned line e2 of the outer edge, and connected across the planned line e2 of the outer edge to the first inspection terminal and to the second inspection terminal. The counter substrate 2 has a size smaller than the normal region, and is disposed to oppose to the normal region of the array substrate 1 leaving a space therebetween, located out of the first inspection terminal and the second inspection terminal, and joined to the array substrate 1.

Description

  Embodiments described herein relate generally to a display panel and a method for manufacturing the display panel.

  In general, various products formed by dividing a glass substrate are known. For example, a liquid crystal display panel is known as a display panel. The liquid crystal display panel includes an array substrate, a counter substrate disposed opposite to the array substrate with a gap therebetween, and a liquid crystal layer sandwiched between the two substrates.

  When manufacturing a liquid crystal display panel, first, a liquid crystal display cell having a mother glass having an array pattern larger in size than the array substrate and a counter substrate is prepared. Thereafter, the mother glass is divided along the periphery of the array substrate, and the liquid crystal display panel having the array substrate and the counter substrate is cut out. When the mother glass is divided, it is performed by drawing a scribe line along a planned dividing line that becomes the outer edge of the array substrate in the mother glass.

  From the above, the external accuracy of the liquid crystal display panel depends on the cutting accuracy such as scribe and break. However, the requirements for the external shape accuracy of the liquid crystal display panel are becoming stricter, and the level cannot be absorbed with the cut accuracy. In view of this, a technique has been proposed in which the outer edge of the array substrate (the cut surface of the liquid crystal display panel) is polished and scraped to achieve higher precision of the outer shape.

  However, in this case, it is necessary to inspect (measure) the polishing accuracy of the outer edge of the array substrate. Therefore, as a polishing accuracy inspection method, a method in which the distance from the reference mark to the outer edge (glass edge) of the array substrate is measured can be cited.

JP 2009-122268 A

As described above, it is necessary to add an inspection process for external accuracy as the external shape of the liquid crystal display panel increases. However, the above method has a problem that it takes a very long time to inspect the polishing accuracy of the outer edge of the array substrate. In addition, there is a problem that the inspection is very complicated.
The present invention has been made in view of the above points, and an object of the present invention is to provide a display panel and a display panel manufacturing method capable of determining a polishing amount of an outer edge of an array substrate in a short time by a simple method. There is.

A display panel according to an embodiment is:
An array substrate having an outer edge planned line as an outer edge of the normal region;
A first inspection terminal and a second inspection terminal provided on the regular region of the array substrate and exposed to the outside;
An inspection wiring provided on the array substrate and positioned at an end of the array substrate from the planned outer edge line and connected to the first test terminal and the second test terminal beyond the planned outer edge line;
A counter substrate having a size smaller than that of the normal region and opposed to the normal region with a gap therebetween and positioned away from the first inspection terminal and the second inspection terminal and bonded to the array substrate.

Moreover, the display panel according to an embodiment is
An array substrate having an outer edge planned line as an outer edge of the normal region;
A conductive pattern provided on the regular region of the array substrate and used for driving for image display;
A first inspection terminal and a second inspection terminal provided on the regular region of the array substrate and exposed to the outside;
An inspection wiring provided on the array substrate and located between the conductive pattern and the planned outer edge line and connected to the first inspection terminal and the second inspection terminal;
A counter substrate having a size smaller than that of the normal region and opposed to the normal region with a gap therebetween and positioned away from the first inspection terminal and the second inspection terminal and bonded to the array substrate.

Moreover, the display panel according to an embodiment is
An array substrate having an outer edge planned line as an outer edge of the normal region;
A conductive pattern provided on the regular region of the array substrate and used for driving for image display;
A first inspection terminal, a second inspection terminal, a third inspection terminal, and a fourth inspection terminal that are provided on the regular region of the array substrate and exposed to the outside;
A first inspection wiring provided on the array substrate and located at an end of the array substrate from the planned outer edge line and connected to the first inspection terminal and the second inspection terminal beyond the planned outer edge line;
A second inspection wiring provided on the array substrate with a gap in the first inspection wiring and positioned between the conductive pattern and the predetermined outer edge line and connected to the third inspection terminal and the fourth inspection terminal; ,
A counter substrate having a size smaller than that of the normal region and disposed opposite to the normal region with a gap, and is positioned away from the first to fourth inspection terminals and bonded to the mother substrate.

Moreover, the manufacturing method of the display panel which concerns on one Embodiment is as follows.
An array substrate having an outer edge planned line as an outer edge of the normal region, a first inspection terminal and a second inspection terminal provided on the normal region of the array substrate and exposed to the outside, and provided on the array substrate An inspection wiring which is located at an end of the array substrate from a predetermined outer edge line and is connected to the first inspection terminal and the second inspection terminal beyond the predetermined outer edge line, and has a size smaller than the normal area and the normal area Preparing a display panel comprising a counter substrate disposed opposite to the first test terminal and the second test terminal and spaced from the second test terminal and bonded to the array substrate.
Polishing an outer edge of the array substrate while measuring an electrical property value between the first inspection terminal and the second inspection terminal;
Based on the measured electrical characteristic value, the polishing amount of the outer edge of the array substrate is determined.

Moreover, the manufacturing method of the display panel which concerns on one Embodiment is as follows.
An array substrate having an outer edge planned line as an outer edge of the normal region, a conductive pattern provided on the normal region of the array substrate and used for driving for image display, and provided on the normal region of the array substrate The first inspection terminal and the second inspection terminal that are exposed to the outside and are disposed between the conductive pattern and the outer peripheral line provided on the array substrate and connected to the first inspection terminal and the second inspection terminal. An inspection substrate having a size smaller than that of the normal region and opposed to the normal region with a gap between the inspection wiring and the first substrate and the counter substrate which is positioned away from the first inspection terminal and bonded to the array substrate. Prepare a display panel with
Polishing an outer edge of the array substrate while measuring an electrical characteristic value between the first inspection terminal and the second inspection terminal;
Based on the measured electrical characteristic value, the polishing amount of the outer edge of the array substrate is determined.

Moreover, the manufacturing method of the display panel which concerns on one Embodiment is as follows.
An array substrate having an outer edge planned line as an outer edge of the normal region, a conductive pattern provided on the normal region of the array substrate and used for driving for image display, and provided on the normal region of the array substrate A first inspection terminal, a second inspection terminal, a third inspection terminal, and a fourth inspection terminal that are exposed to the outside, and are provided on the array substrate and positioned at an end of the array substrate from the predetermined outer edge line; A first inspection wiring connected to the first inspection terminal and the second inspection terminal across a line; and the conductive pattern and the predetermined outer edge line provided on the array substrate with a gap in the first inspection wiring. The second inspection wiring, which is located between the third inspection terminal and the fourth inspection terminal, has a size smaller than that of the normal region and is opposed to the normal region with a gap therebetween. 4 inspection terminals A counter substrate positioned out al bonded to the mother substrate, a display panel comprising a prepared,
While measuring the electrical characteristic value between the first inspection terminal and the second inspection terminal and the other electrical characteristic value between the third inspection terminal and the fourth inspection terminal, respectively, Polish the outer edge of the array substrate,
A polishing amount of the outer edge of the array substrate is determined based on the measured electric characteristic value and other electric characteristic values.

FIG. 1 is a perspective view showing a liquid crystal display panel according to the first embodiment. FIG. 2 is a schematic sectional view showing the liquid crystal display panel. FIG. 3 is a schematic plan view showing the liquid crystal display panel, showing a wiring structure. FIG. 4 is a schematic plan view showing a part of the array substrate shown in FIGS. FIG. 5 is an enlarged plan view showing the array substrate, and shows a wiring structure of the array substrate. FIG. 6 is an enlarged cross-sectional view showing the liquid crystal display panel, and shows the structure of the liquid crystal display panel. FIG. 7 is an enlarged cross-sectional view schematically showing a peripheral portion of the liquid crystal display panel taken along line VII-VII in FIG. FIG. 8 is a schematic plan view showing the liquid crystal display panel, and is a diagram showing inspection terminals and inspection wirings formed in a regular region of the array substrate. FIG. 9 is a plan view showing a state in which six array substrates are formed on the mother glass in the manufacturing process of the liquid crystal display panel. FIG. 10 is a plan view showing a state in which six counter substrates are formed on the mother glass in the manufacturing process of the liquid crystal display panel. FIG. 11 is a plan view showing a state in which the two mother glasses shown in FIGS. 9 and 10 are bonded together with a sealing material interposed therebetween. FIG. 12 is a plan view showing a liquid crystal display panel taken out by dividing the mother glass shown in FIG. 11, and shows the inspection terminals and inspection wiring. 13 is a cross-sectional view of the liquid crystal display panel taken along line XIII-XIII in FIG. FIG. 14 is a plan view of the liquid crystal display panel showing a state where the lower side and the upper side of the array substrate shown in FIG. 12 are polished, and shows a state where the inspection wiring is divided. FIG. 15 is a plan view showing a liquid crystal display panel taken out by dividing the mother glass in the second embodiment, and shows the inspection terminals and inspection wiring. 16 is a cross-sectional view showing the liquid crystal display panel taken along line XVI-XVI in FIG. FIG. 17 is a plan view showing a liquid crystal display panel taken out by dividing the mother glass in the third embodiment, and shows the inspection terminals and the inspection wiring.

  Hereinafter, a liquid crystal display panel and a method for manufacturing the liquid crystal display panel according to the first embodiment will be described in detail with reference to the drawings. First, the configuration of the liquid crystal display panel will be described. In this embodiment, the liquid crystal display panel is a counter CF type, and a color filter is formed on the counter substrate side.

  As shown in FIGS. 1 to 6, the liquid crystal display panel includes an array substrate 1, a counter substrate 2 disposed opposite to the array substrate with a predetermined gap, and a liquid crystal layer 3 sandwiched between the two substrates. The color filter 4 is provided. Polarizing plates (not shown) are respectively arranged on the outer surfaces of the array substrate 1 and the counter substrate 2. A backlight unit (not shown) is disposed on the outer surface side of the array substrate 1. The array substrate 1 and the counter substrate 2 have a rectangular display region R1. The color filter 4 is provided in the display area R1 of the array substrate 1.

  The array substrate 1 has a glass substrate 11 as a transparent insulating substrate. In the display region R <b> 1, on the glass substrate 11, a plurality of scanning lines 15 extending in the row direction X and arranged at intervals in a column direction Y orthogonal to the row direction X intersect with the plurality of scanning lines 15. A plurality of signal lines 21 extending in the column direction Y and arranged at intervals in the row direction X are arranged in a lattice pattern.

  On the glass substrate 11, auxiliary capacitance elements 24 are formed, and a plurality of auxiliary capacitance lines 17 that intersect with the plurality of signal lines 21 and extend in the row direction X and are arranged at intervals in the column direction Y are arranged. Is formed. The auxiliary capacitance line 17 extends in parallel with the scanning line 15.

  Here, the array substrate 1 and the counter substrate 2 have a plurality of matrix-like pixels 20 provided so as to overlap with a region surrounded by the plurality of signal lines 21 and the plurality of auxiliary capacitance lines 17. That is, each pixel 20 is provided so as to overlap an area surrounded by two adjacent signal lines 21 and two adjacent auxiliary capacitance lines 17. Each pixel 20 of the array substrate 1 is provided with a TFT (thin film transistor) 19 as a switching element. More specifically, the TFT 19 is provided in the vicinity of each intersection of the scanning line 15 and the signal line 21.

  The TFT 19 includes a semiconductor layer 12 made of amorphous silicon (a-Si) or polysilicon (p-Si) as a semiconductor, and a gate electrode 16 formed by extending a part of the scanning line 15. In the present embodiment, the semiconductor layer 12 and a later-described auxiliary capacitance electrode 13 are formed of p-Si.

  More specifically, in the display region R1, the semiconductor layer 12 and the auxiliary capacitance electrode 13 are formed on the glass substrate 11, and the gate insulating film 14 is formed on the glass substrate including the semiconductor layer and the auxiliary capacitance electrode. It is filmed. A scanning line 15, a gate electrode 16, and an auxiliary capacitance line 17 are disposed on the gate insulating film 14. The auxiliary capacitance line 17 and the auxiliary capacitance electrode 13 are arranged to face each other with the gate insulating film 14 interposed therebetween.

  The scanning line 15, the gate electrode 16, and the auxiliary capacitance line 17 are made of metal. In this embodiment, the scanning line 15, the gate electrode 16 and the auxiliary capacitance line 17 are made of molybdenum / tungsten (MoW). An interlayer insulating film 18 is formed on the gate insulating film 14 including the scanning line 15, the gate electrode 16, and the auxiliary capacitance line 17. In this embodiment, the interlayer insulating film 18 is an inorganic insulating film.

  A signal line 21 and a contact electrode 22 are formed on the interlayer insulating film 18. Each contact electrode 22 is connected to the drain region of the semiconductor layer 12 through a contact hole formed in the gate insulating film 14 and the interlayer insulating film 18. Further, the contact electrode 22 is connected to the auxiliary capacitance electrode 13 through another contact hole formed in the gate insulating film 14 and the interlayer insulating film 18. Here, the auxiliary capacitance line 17 is formed except for the connection portion between the auxiliary capacitance electrode 13 and the contact electrode 22.

  The signal line 21 is connected to the source region of the semiconductor layer 12 through a contact hole formed in the gate insulating film 14 and the interlayer insulating film 18. The signal line 21 and the contact electrode 22 are made of metal. In this embodiment, the signal line 21 and the contact electrode 22 are formed of TAT. Here, TAT is an abbreviation of Ti (titanium) / Al (aluminum) / Ti, and is a metal layer having a three-layer structure. The Al may be an aluminum-based alloy.

  A protective insulating film 23 is formed on the interlayer insulating film 18, the signal line 21, and the contact electrode 22. The protective insulating film 23 also serves as a flattening film for flattening unevenness caused by wiring or the like on the substrate. In this embodiment, the protective insulating film 23 is an organic insulating film. The protective insulating film 23 covers not only the display region R1 but also the frame region R2 surrounding the display region R1. Here, the display region R1 and the frame region R2 are regular regions of the array substrate 1 (glass substrate 11).

  On the protective insulating film 23, pixel electrodes 26 are formed of a transparent conductive film such as ITO (indium tin oxide). A plurality of contact holes 25 are formed in the protective insulating film 23 that overlaps the auxiliary capacitance line 17. These contact holes 25 are provided in the plurality of pixels 20.

  Each pixel electrode 26 is connected to the contact electrode 22 through the contact hole 25. The peripheral edge of each pixel electrode 26 overlaps the auxiliary capacitance line 17 and the signal line 21. The pixel electrodes 26 form the pixels 20 respectively.

  As described above, the array pattern 1 p is formed on the glass substrate 11. In the display region R1, the array pattern 1p is laminated between the glass substrate 11 and the pixel electrode 26. A plurality of columnar spacers 27 as a plurality of spacers are formed on the array pattern 1p. An alignment film 28 is formed on the array pattern 1p (pixel electrode 26 and the like) on which the columnar spacers 27 are formed.

  On the other hand, as shown in FIGS. 3 and 7, an array pattern 1p is formed on the glass substrate 11 in the frame region R2. In the frame region R2, the array pattern 1p includes drive circuits 6a and 6b, a gate insulating film 14, an interlayer insulating film 18, wirings w1, w2, w3, w4, w7, and w8, and a protective insulating film 23. Have.

  The drive circuits 6a and 6b are disposed to face each other in the row direction X with the display region R1 interposed therebetween. The drive circuits 6a and 6b are simultaneously formed of the same material when forming the TFT 19 and the like. The drive circuits 6 a and 6 b are Y drivers connected to the scanning lines 15 and the auxiliary capacitance lines 17.

  Wirings w1, w2, w3, w4, w7, and w8 are provided on the left and right sides of the frame region R2, respectively, to form drive circuits 6a and 6b. The wirings w1, w2, w3, w4, w7, and w8 extend in the column direction Y and are provided at intervals in the row direction X. The wirings w 1, w 2, w 3, w 4, w 7, w 8 are formed on the interlayer insulating film 18 and covered with the protective insulating film 23. The wirings w1, w2, w3, w4, w7, and w8 are part of a conductive pattern used for driving for image display. The wirings w1, w2, w3, and w4 are extended to the end of the glass substrate 11 and connected to pads for outer lead bonding.

  Wirings w1 and w2 are control signal wirings, and wirings w3 and w4 are power supply wirings, respectively. A start pulse signal ST is applied to the wiring w1 through a pad. A clock signal CLK is supplied to the wiring w2 through a pad. A voltage V1 (VDD) is applied to the wiring w3 from a high potential power source (not shown) via a pad. A voltage V2 (VSS) is applied to the wiring w4 from a low potential power source (not shown) via a pad. The wiring w3 and the wiring w4 are power supply wirings having different potentials. For example, the voltage V1 is + 10V and the voltage V2 is −5V.

  Wirings w5 and w6 are connection wirings. In this embodiment, the wirings w5 and w6 extend in the row direction X. The wirings w5 and w6 are formed on at least the gate insulating film 14 in the frame region R2. The wirings w5 and w6 are covered with an interlayer insulating film 18. In this embodiment, the wirings w5 and w6 are formed extending to the display region R1. In the frame region R2, the interlayer insulating film 18 has a through hole facing the wiring w5 and a through hole facing the wiring w6. The wiring w3 is electrically connected to the wiring w5 through the through hole, and the wiring w4 is electrically connected to the wiring w6 through the through hole.

  As shown in FIG. 8, in the frame region R2, the array pattern 1p further includes first to sixth inspection terminals cp1 to cp6 and first to fourth inspection wirings cw1 to cw4.

  The first to sixth inspection terminals cp1 to cp6 are provided on the protective insulating film 23 and exposed to the outside (above the array substrate 1). The first to sixth inspection terminals cp1 to cp6 are made of a conductive material. For example, the first to sixth inspection terminals cp1 to cp6 can be formed of the same material at the same time when the outer lead bonding pads are formed.

  The first to fourth inspection wirings cw1 to cw4 extend to the outer edge of the frame region R2 (regular region) of the array substrate 1 (glass substrate 11). As will be described later, in the manufacturing stage, the first to fourth inspection wirings cw1 to cw4 are formed on a region outside the normal region of the array substrate 1 beyond the outer edge of the frame region R2.

  The first inspection wiring cw1 is connected to the first inspection terminal cp1 and the second inspection terminal cp2. The second inspection wiring cw2 is connected to the third inspection terminal cp3 and the fourth inspection terminal cp4. The first inspection wiring cw1 and the second inspection wiring cw2 are formed of TAT, for example, and can be formed of the same material at the same time when forming the signal line 21 and the like.

  The third inspection wiring cw3 is connected to the fifth inspection terminal cp5. The fourth inspection wiring cw4 is connected to the sixth inspection terminal cp6. The third inspection wiring cw3 and the fourth inspection wiring cw4 are made of, for example, MoW, and can be formed of the same material at the same time when the scanning lines 15 and the like are formed.

  Focusing on the inspection terminals, the first to fourth inspection terminals cp1 to cp4 are connected to the first inspection wiring cw1 and the second inspection wiring cw2 through the contact holes formed in the protective insulating film 23, respectively. The fifth inspection terminal cp5 and the sixth inspection terminal cp6 pass through contact holes formed in the interlayer insulating film 18 and the protective insulating film 23 and are connected to the third inspection wiring cw3 and the fourth inspection wiring cw4.

  As shown in FIGS. 1 to 3 and FIGS. 6 to 8, the counter substrate 2 includes a glass substrate 41 as a transparent insulating substrate. On the glass substrate 41, the color filter 4 is provided. The color filter 4 includes a light shielding part 31, a peripheral light shielding part 32, and a plurality of colored layers. The plurality of colored layers include, for example, a red colored layer 30R, a green colored layer 30G, and a blue colored layer 30B.

  The light shielding part 31 is formed in a lattice shape. The light shielding portion 31 is formed to face the auxiliary capacitance line 17 and the signal line 21. The peripheral light-shielding portion 32 is formed in a rectangular frame shape and is formed over the entire frame region R2. The peripheral light shielding portion 32 contributes to shielding light (backlight) leaking from the outside of the display region R1.

The colored layers 30R, 30G, and 30B are formed on the glass substrate 41 and the light shielding portion 31. The colored layers 30R, 30G, and 30B extend in a strip shape along the column direction Y. The colored layers 30R, 30G, and 30B are adjacent to each other in the row direction X and are alternately arranged. The peripheral portions of the colored layers 30R, 30G, and 30B overlap the light shielding portion 31.
An overcoat layer (not shown) may be disposed on the color filter 4. Thereby, the influence of the unevenness | corrugation on the surface of the light-shielding part 31 and the color filter 4 can be relieved.

On the color filter 4 (overcoat layer), a counter electrode 42 is formed of a transparent conductive film such as ITO. An alignment film 43 is formed on the counter electrode 42. As described above, the opposing pattern 2 p is formed on the glass substrate 41. The counter pattern 2 p includes a color filter 4, a counter electrode 42, and an alignment film 43. The counter pattern 2p may further include an overcoat layer.
The counter substrate 2 has a size smaller than the normal region of the array substrate 1. The counter substrate 2 is located away from the first to sixth inspection terminals cp1 to cp6.

  The array substrate 1 and the counter substrate 2 are arranged to face each other with a predetermined gap by a plurality of columnar spacers 27. The seal material 51 faces the frame region R2, is provided between the array substrate 1 and the counter substrate 2, and is continuously formed in a rectangular frame shape. The array substrate 1 and the counter substrate 2 are bonded to each other by a sealing material 51.

The liquid crystal layer 3 is formed in a space surrounded by the array substrate 1, the counter substrate 2, and the sealing material 51.
A liquid crystal display panel is formed as described above.

Next, a more detailed configuration of the liquid crystal display panel will be described together with its manufacturing method.
As shown in FIG. 1 to FIG. 8 and FIG. 9, first, a mother glass 101 as a first mother substrate having a size larger than that of the array substrate 1 is prepared as a transparent insulating substrate. According to this embodiment, the mother glass 101 has six rectangular divided regions R6 and an ineffective region R7 that is out of the divided region R6 in order to form the array substrate 1.

  The mother glass 101 has a first planned dividing line e1 that overlaps the periphery of the divided region R6. Further, in the divided region R6, the mother glass 101 has a planned outer edge line e2 that is an outer edge of the regular region of the array substrate 1. The first division planned line e1 surrounds the outer edge planned line e2 and is located with a gap in the outer edge planned line e2. The gap between the first planned dividing line e1 and the outer edge planned line e2 is, for example, 200 μm.

  On the prepared mother glass 101, an array pattern 1p including the TFT 19, the auxiliary capacitance element 24, the drive circuits 6a and 6b, the protective insulating film 23, the pixel electrode 26, and the like is formed by a normal manufacturing process such as repeated film formation and patterning. Form. On the mother glass 101, first to sixth inspection terminals cp1 to cp6 and first to fourth inspection wirings cw1 to cw4 are also formed.

  Next, using a spinner, for example, a photosensitive acrylic transparent resin is applied on the entire surface of the mother glass 101. Subsequently, the transparent resin is dried. Next, patterning is exposed to the transparent resin using a predetermined photomask. Next, after developing the exposed transparent resin, it is baked and cured. Thereby, the columnar spacer 27 is formed.

Thereafter, the alignment film material is applied to the entire surface of the mother glass 101 including the display region R1 and patterned to form the alignment film 28. The alignment film 28 is subjected to a predetermined alignment process (rubbing) as necessary.
Thus, six array substrates 1 are completed with one mother glass 101.

  As shown in FIGS. 1 to 3, 6 to 8, and 10, on the other hand, in the manufacturing method of the counter substrate 2, first, a second mother substrate having a size larger than that of the counter substrate 2 as a transparent insulating substrate. A mother glass 102 is prepared. According to this embodiment, the mother glass 102 has six rectangular divided regions R8 and an ineffective region R9 that is out of the divided region R8 in order to form the counter substrate 2. The mother glass 102 has a second planned dividing line e3 that overlaps the periphery of the divided region R8.

On the prepared mother glass 102, the opposing pattern 2p is formed by a normal manufacturing process. The alignment film 43 is subjected to a predetermined alignment process (rubbing) as necessary.
Thus, six counter substrates 2 are completed with one mother glass 102.

  Next, as shown in FIGS. 7, 8, and 11, for example, an ultraviolet curable resin is applied to the frame region R <b> 2 of the array substrate 1 as a material for forming the sealing material 51 by a printing method over the entire circumference. . Thereby, the frame-shaped sealing material 51 is formed. Further, when forming the sealing material 51, an electrode transition material for applying a voltage from the array substrate 1 to the counter substrate 2 can be formed on an electrode transition electrode (not shown) around the sealing material 51.

  Thereafter, a liquid crystal material is dropped into a region surrounded by the sealing material 51. Subsequently, the mother glass 101 and the mother glass 102 are arranged to face each other so that the alignment film 28 and the alignment film 43 face each other, and the array substrate 1 and the counter substrate 2 are arranged to face each other with a plurality of columnar spacers 27 holding a predetermined gap. Then, the peripheral portions of the array substrate 1 and the counter substrate 2 are bonded together with the sealing material 51.

  Next, the sealing material 51 is irradiated with ultraviolet rays from the outside to cure the sealing material 51, and further subjected to a thermosetting treatment to be fully cured. Thereby, the mother glass 101 and the mother glass 102 are joined via the sealing material 51.

  Subsequently, the mother glass 101 is divided along the first planned dividing line e1, and the mother glass 102 is divided along the second planned dividing line e3. When dividing, for example, a scribe line is drawn along the first scheduled dividing line e1 and the second scheduled dividing line e3. Thereby, the array substrate 1 is cut out from the mother glass 101, and the counter substrate 2 is cut out from the mother glass 102.

  The scribing / breaking method is not limited to drawing a scribe line, and various generally known methods can be employed. For example, a laser beam is irradiated using a scribe laser. It may be a technique.

  As shown in FIGS. 12 and 13, thereby, six sets of liquid crystal display panels are taken out from the divided mother glass 101 and mother glass 102. Six sets of liquid crystal display panels can be prepared.

  The counter substrate 2 has a size smaller than the normal region of the array substrate 1, is opposed to the normal region with a gap, is positioned away from the first to sixth inspection terminals cp 1 to cp 6, and is bonded to the array substrate 1. Has been. The first to sixth inspection terminals cp1 to cp6 are provided on the regular region of the array substrate 1 and exposed to the outside.

  The first to fourth inspection wirings cw1 to cw4 are provided on the array substrate 1, are located at the end of the array substrate 1 with respect to the outer edge planned line e2, and extend beyond the outer edge planned line e2 to the first to sixth inspection terminals cp1. To cp6.

  The first inspection wiring cw1 is formed in a strip shape extending in the row direction X along the lower side of the planned outer edge line e2. The first inspection wiring cw1 is located with a gap on the lower side of the planned outer edge line e2.

  The second inspection wiring cw2 is formed in a U shape extending in the row direction X and the column direction Y along the left side, the upper side, and the right side of the planned outer edge line e2. The second inspection wiring cw2 is located with a gap between the left side, the upper side, and the right side of the planned outer edge line e2.

  The third inspection wiring cw3 is formed in a belt shape extending in the column direction Y along the left side of the planned outer edge line e2. The third inspection wiring cw3 is located with a gap on the left side of the planned outer edge line e2. The second inspection wiring cw2 is opposed to the third inspection wiring cw3. The second inspection wiring cw2 is connected to the third inspection wiring cw3 at a plurality of positions through contact holes formed in the interlayer insulating film 18.

  The fourth inspection wiring cw4 is formed in a strip shape extending in the column direction Y along the right side of the planned outer edge line e2. The fourth inspection wiring cw4 is located with a gap on the right side of the planned outer edge line e2. Note that the second inspection wiring cw2 is opposed to the fourth inspection wiring cw4. The second inspection wiring cw2 is connected to the fourth inspection wiring cw4 at a plurality of positions through contact holes formed in the interlayer insulating film 18.

  Here, the line L1 is a line that overlaps the lower side of the planned outer edge line e2, and is a line that points to the lower side that should be reached by polishing (to be cut). The line L2 is a line that overlaps the upper side of the planned outer edge line e2, and is a line that indicates the upper side that should be reached by polishing. The line L3 is a line that overlaps the left side of the planned outer edge line e2, and is a line that indicates the left side that should be reached by polishing. The line L4 is a line that overlaps the right side of the planned outer edge line e2, and is a line that indicates the right side that should be reached by polishing.

After preparing the liquid crystal display panel as described above, the outer edge of the liquid crystal display panel is polished.
First, in this embodiment, the short side of the array substrate 1 is polished.
When polishing the lower side of the array substrate 1, the outer edge on the lower side of the array substrate 1 is polished while measuring the electrical characteristic value between the first inspection terminal cp1 and the second inspection terminal cp2. Here, examples of the electric characteristic value include a current value and an electric resistance value. Then, the polishing amount of the lower side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

  In this embodiment, the first and second inspection terminals cp1 and cp2 energize the first inspection wiring cw1 and measure the current value between the first inspection terminal cp1 and the second inspection terminal cp2, while the array substrate The outer edge of the lower side of 1 is polished. When the current value becomes 0, the lower side of the array substrate 1 is polished to such an extent that the first inspection wiring cw1 is disconnected, and it is determined that the polishing amount has reached a desired amount. Stop. When the polishing of the lower side of the array substrate 1 is completed, the position of the lower side of the array substrate 1 is determined.

  When polishing the upper side of the array substrate 1, the outer edge on the upper side of the array substrate 1 is polished while measuring the electrical characteristic value between the third inspection terminal cp3 and the fourth inspection terminal cp4. Then, the polishing amount of the upper side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

In this embodiment, the array substrate is energized while passing the current from the third inspection terminal cp3 and the fourth inspection terminal cp4 to the second inspection wiring cw2 and measuring the current value between the third inspection terminal cp3 and the fourth inspection terminal cp4. The outer edge of the upper side of 1 is polished. When the current value becomes 0, the upper side of the array substrate 1 is polished to such an extent that the second inspection wiring cw2 is disconnected, and it is determined that the polishing amount has reached a desired amount. Stop. When the polishing of the upper side of the array substrate 1 is completed, the position of the upper side of the array substrate 1 is determined. In addition, in order to improve the external accuracy of the liquid crystal display panel, the upper side of the counter substrate 2 may be polished together with the upper side of the array substrate 1.
As shown in FIG. 14, the short side of the array substrate 1 is thereby polished.

Subsequently, in this embodiment, the long side of the array substrate 1 is polished.
When polishing the left side of the array substrate 1, the outer edge on the left side of the array substrate 1 is polished while measuring the electrical characteristic value between the third inspection terminal cp3 and the fifth inspection terminal cp5. Based on the measured electrical characteristic value, the polishing amount of the left side (outer edge) of the array substrate 1 is determined.

  In this embodiment, a current value is supplied between the third inspection terminal cp3 and the fifth inspection terminal cp5 by energizing the third inspection terminal cp3 and the fifth inspection terminal cp5 between the second inspection wiring cw2 and the third inspection wiring cw3. , The outer edge of the left side of the array substrate 1 is polished. When the current value becomes 0, the left side of the array substrate 1 is polished to such an extent that the second inspection wiring cw2 and the third inspection wiring cw3 are disconnected, and the amount of polishing reaches a desired amount. And the polishing is stopped. When the polishing of the left side of the array substrate 1 is completed, the position of the left side of the array substrate 1 is determined. Note that the left side of the array substrate 1 and the left side of the counter substrate 2 may be polished together in order to increase the external accuracy of the liquid crystal display panel.

  When polishing the right side of the array substrate 1, the outer edge on the right side of the array substrate 1 is polished while measuring the electrical characteristic value between the fourth inspection terminal cp4 and the sixth inspection terminal cp6. Then, the polishing amount of the right side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

In this embodiment, the current value between the fourth inspection terminal cp4 and the sixth inspection terminal cp6 is energized from the fourth inspection terminal cp4 and the sixth inspection terminal cp6 to the second inspection wiring cw2 and the fourth inspection wiring cw4. , The outer edge of the right side of the array substrate 1 is polished. When the current value becomes 0, the right side of the array substrate 1 is polished to such an extent that the second inspection wiring cw2 and the fourth inspection wiring cw4 are disconnected, and the polishing amount reaches a desired amount. And the polishing is stopped. When the polishing of the right side of the array substrate 1 is completed, the position of the right side of the array substrate 1 is determined. Note that the right side of the counter substrate 2 may be polished together with the right side of the array substrate 1 in order to increase the external accuracy of the liquid crystal display panel.
As a result, as shown in FIG. 8, the long side of the array substrate 1 is also polished following the short side of the array substrate 1.

  In addition, when polishing the outer edge (each side) of the array substrate 1, it is possible to control the polishing to continue for a predetermined time after the current value becomes zero. By adjusting (managing) the duration of polishing, the outer edge of the array substrate 1 can be made to coincide with or closer to the outer edge planned line e2.

  As shown in FIG. 3, after that, a polarizing plate is disposed on each of the outer surfaces of the array substrate 1 and the counter substrate 2, or an IC driver is mounted on the frame region R2 of the array substrate 1, whereby the liquid crystal display panel is Complete.

  According to the liquid crystal display panel and the manufacturing method of the liquid crystal display panel according to the first embodiment configured as described above, the liquid crystal display panel in the manufacturing stage includes the array substrate 1 and the first to sixth inspection terminals cp1 to cp1. cp6, first to fourth inspection wirings cw1 to cw4, and a counter substrate 2 are provided.

  The array substrate 1 has a predetermined outer edge line e2 that is an outer edge of the normal region. The first to sixth inspection terminals cp1 to cp6 are provided on the regular region of the array substrate 1 and are exposed to the outside. The first to fourth inspection wirings cw1 to cw4 are provided on the array substrate 1, are located at the end of the array substrate 1 with respect to the outer edge planned line e2, and extend beyond the outer edge planned line e2 to the first to sixth inspection terminals cp1. To cp6. The counter substrate 2 has a size smaller than the normal region of the array substrate 1, is opposed to the normal region with a gap, is positioned away from the first to sixth inspection terminals cp 1 to cp 6, and is bonded to the array substrate 1. Has been.

  When the liquid crystal display panel is completed, after preparing the liquid crystal display panel, the outer edge of the array substrate 1 is polished while measuring the electrical characteristic value between the inspection terminals. Then, the amount of polishing of the outer edge of the array substrate 1 is determined based on the measured electrical characteristic value. That is, it can be determined whether the polishing should be continued or stopped.

  As a comparative example of a method for determining the polishing amount (inspecting polishing accuracy), when measuring the distance from the reference mark to the outer edge of the array substrate 1, it is difficult to polish while performing the above measurement. is there. For this reason, in the case of the comparative example, it is necessary to perform the polishing and the measurement alternately, and the amount of polishing of the outer edge of the array substrate 1 is determined over a long time by a complicated method.

  From the above, it is possible to obtain a liquid crystal display panel and a method for manufacturing the liquid crystal display panel that can determine the polishing amount of the outer edge of the array substrate 1 in a short time by a simple method. And a liquid crystal display panel with a high external precision can be obtained. That is, it is possible to meet the demand for higher accuracy of the outer shape of the liquid crystal display panel.

  Next, a liquid crystal display panel and a method for manufacturing the liquid crystal display panel according to the second embodiment will be described. In the present embodiment, the same functional parts as those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIGS. 15 and 16, the array substrate 1 includes seventh to twelfth inspection terminals cp7 to cp7 instead of the first to sixth inspection terminals cp1 to cp6 and the first to fourth inspection wirings cw1 to cw4. cp12 and fifth to eighth inspection wirings cw5 to cw8 are formed.

  The seventh to twelfth inspection terminals cp7 to cp12 are provided on the protective insulating film 23 and exposed to the outside (above the array substrate 1). The seventh to twelfth inspection terminals cp7 to cp12 are made of a conductive material. For example, the seventh to twelfth inspection terminals cp7 to cp12 can be formed of the same material at the same time when the outer lead bonding pads are formed.

  The fifth to eighth inspection wirings cw5 to cw8 are formed in the frame region R2 (regular region) of the array substrate 1 (glass substrate 11). The ends (side edges) of the fifth to eighth inspection wirings cw5 to cw8 on the display region R1 side are made to coincide with lines that should not be polished (cut).

  The fifth inspection wiring cw5 is connected to the seventh inspection terminal cp7 and the eighth inspection terminal cp8. The sixth inspection wiring cw6 is connected to the ninth inspection terminal cp9 and the tenth inspection terminal cp10. The fifth inspection wiring cw5 and the sixth inspection wiring cw6 are formed of, for example, TAT, and can be formed of the same material simultaneously when forming the signal line 21 and the like.

  The seventh inspection wiring cw7 is connected to the eleventh inspection terminal cp11. The eighth inspection wiring cw8 is connected to the twelfth inspection terminal cp12. The seventh inspection wiring cw7 and the eighth inspection wiring cw8 are formed of, for example, MoW, and can be formed of the same material at the same time when the scanning lines 15 and the like are formed.

  Focusing on the inspection terminals, the seventh to tenth inspection terminals cp7 to cp10 are connected to the fifth inspection wiring cw5 and the sixth inspection wiring cw6 through the contact holes formed in the protective insulating film 23, respectively. The eleventh inspection terminal cp11 and the twelfth inspection terminal cp12 pass through contact holes formed in the interlayer insulating film 18 and the protective insulating film 23 and are connected to the seventh inspection wiring cw7 and the eighth inspection wiring cw8.

The counter substrate 2 is located away from the seventh to twelfth inspection terminals cp7 to cp12.
A liquid crystal display panel is formed as described above.

Next, a more detailed configuration of the liquid crystal display panel will be described together with its manufacturing method.
First, mother glass or the like is prepared, and the liquid crystal display panel is taken out from the mother glass by the same method as in the first embodiment.

  The counter substrate 2 has a size smaller than the normal region of the array substrate 1, is opposed to the normal region with a gap, is positioned away from the seventh to twelfth inspection terminals cp 7 to cp 12, and is bonded to the array substrate 1. Has been. The seventh to twelfth inspection terminals cp7 to cp12 are provided on the regular region of the array substrate 1 and exposed to the outside. Conductive patterns used for driving for image display, such as constituent members of the drive circuits 6 a and 6 b, are provided on the normal region of the array substrate 1.

  The fifth to eighth inspection wirings cw5 to cw8 are provided on the array substrate 1, located between the conductive pattern and the planned outer edge line e2, and connected to the seventh to twelfth inspection terminals cp7 to cp12. .

  The fifth inspection wiring cw5 is formed in a strip shape extending in the row direction X along the lower side of the planned outer edge line e2. The fifth inspection wiring cw5 is located with a gap on the lower side of the planned outer edge line e2.

  The sixth inspection wiring cw6 is formed in a U shape extending in the row direction X and the column direction Y along the left side, the upper side, and the right side of the planned outer edge line e2. The sixth inspection wiring cw6 is located with a gap between the left side, the upper side, and the right side of the planned outer edge line e2.

  The seventh inspection wiring cw7 is formed in a strip shape extending in the column direction Y along the left side of the planned outer edge line e2. The seventh inspection wiring cw7 is located with a gap on the left side of the planned outer edge line e2. The sixth inspection wiring cw6 faces the seventh inspection wiring cw7. The sixth inspection wiring cw6 is connected to the seventh inspection wiring cw7 through a contact hole formed in the interlayer insulating film 18. In this embodiment, the contact hole is located at the upper left corner of the regular region of the array substrate 1.

  The eighth inspection wiring cw8 is formed in a belt shape extending in the column direction Y along the right side of the planned outer edge line e2. The eighth inspection wiring cw8 is located with a gap on the right side of the planned outer edge line e2. The sixth inspection wiring cw6 is opposed to the eighth inspection wiring cw8. The sixth inspection wiring cw6 is connected to the eighth inspection wiring cw8 through a contact hole formed in the interlayer insulating film 18. In this embodiment, the contact hole is located in the upper right corner of the regular region of the array substrate 1.

After preparing the liquid crystal display panel as described above, the outer edge of the liquid crystal display panel is polished.
First, in this embodiment, the short side of the array substrate 1 is polished.
When the lower side of the array substrate 1 is polished, the outer edge on the lower side of the array substrate 1 is polished while measuring the electrical characteristic value between the seventh inspection terminal cp7 and the eighth inspection terminal cp8. Then, the polishing amount of the lower side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

  In this embodiment, the array substrate is measured while energizing the fifth inspection wiring cw5 from the seventh inspection terminal cp7 and the eighth inspection terminal cp8 and measuring the current value between the seventh inspection terminal cp7 and the eighth inspection terminal cp8. The outer edge of the lower side of 1 is polished. If the current value is not 0, it is determined that the position that should not be further polished has not been reached. Thereafter, the polishing of the lower side of the array substrate 1 is completed, whereby the position of the lower side of the array substrate 1 is determined.

  When polishing the upper side of the array substrate 1, the outer edge on the upper side of the array substrate 1 is polished while measuring the electrical characteristic value between the ninth inspection terminal cp9 and the tenth inspection terminal cp10. Then, the polishing amount of the upper side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

In this embodiment, the array substrate is measured while energizing the sixth inspection wiring cw6 from the ninth inspection terminal cp9 and the tenth inspection terminal cp10 and measuring the current value between the ninth inspection terminal cp9 and the tenth inspection terminal cp10. The outer edge of the upper side of 1 is polished. If the current value is not 0, it is determined that the position that should not be further polished has not been reached. Thereafter, the polishing of the upper side of the array substrate 1 is completed, whereby the position of the upper side of the array substrate 1 is determined. In addition, in order to improve the external accuracy of the liquid crystal display panel, the upper side of the counter substrate 2 may be polished together with the upper side of the array substrate 1.
Thereby, the short side of the array substrate 1 is polished.

Subsequently, in this embodiment, the long side of the array substrate 1 is polished.
When polishing the left side of the array substrate 1, the outer edge on the left side of the array substrate 1 is polished while measuring the electrical characteristic value between the ninth inspection terminal cp9 and the eleventh inspection terminal cp11. Based on the measured electrical characteristic value, the polishing amount of the left side (outer edge) of the array substrate 1 is determined.

  In this embodiment, a current is passed between the ninth inspection terminal cp9 and the eleventh inspection terminal cp11 through the sixth inspection wiring cw6 and the seventh inspection wiring cw7 from the ninth inspection terminal cp9 and the eleventh inspection terminal cp11. , The outer edge of the left side of the array substrate 1 is polished. If the current value is not 0, it is determined that the position that should not be further polished has not been reached. Thereafter, the polishing of the left side of the array substrate 1 is completed, whereby the position of the left side of the array substrate 1 is determined. Note that the left side of the array substrate 1 and the left side of the counter substrate 2 may be polished together in order to increase the external accuracy of the liquid crystal display panel.

  When polishing the right side of the array substrate 1, the outer edge of the right side of the array substrate 1 is polished while measuring the electrical characteristic value between the tenth inspection terminal cp10 and the twelfth inspection terminal cp12. Then, the polishing amount of the right side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

In this embodiment, a current value is supplied between the tenth inspection terminal cp10 and the twelfth inspection terminal cp12 by energizing the sixth inspection wiring cw6 and the eighth inspection wiring cw8 from the tenth inspection terminal cp10 and the twelfth inspection terminal cp12. , The outer edge of the right side of the array substrate 1 is polished. If the current value is not 0, it is determined that the position that should not be further polished has not been reached. Thereafter, the polishing of the right side of the array substrate 1 is completed, whereby the position of the right side of the array substrate 1 is determined. Note that the right side of the counter substrate 2 may be polished together with the right side of the array substrate 1 in order to increase the external accuracy of the liquid crystal display panel.
Thus, the long side of the array substrate 1 is also polished following the short side of the array substrate 1.

  As shown in FIG. 3, after that, a polarizing plate is disposed on each of the outer surfaces of the array substrate 1 and the counter substrate 2, or an IC driver is mounted on the frame region R2 of the array substrate 1, whereby the liquid crystal display panel is Complete.

  According to the liquid crystal display panel and the method for manufacturing the liquid crystal display panel according to the second embodiment configured as described above, the liquid crystal display panel at the manufacturing stage includes the array substrate 1, the conductive pattern, and the seventh to twelfth. Inspection terminals cp7 to cp12, fifth to eighth inspection wirings cw5 to cw8, and the counter substrate 2 are provided.

  The array substrate 1 has a predetermined outer edge line e2 that is an outer edge of the normal region. Conductive patterns used for driving for image display, such as constituent members of the drive circuits 6 a and 6 b, are provided on the normal region of the array substrate 1. The seventh to twelfth inspection terminals cp7 to cp12 are provided on the regular region of the array substrate 1 and are exposed to the outside. The fifth to eighth inspection wirings cw5 to cw8 are provided on the array substrate 1, located between the conductive pattern and the planned outer edge line e2, and connected to the seventh to twelfth inspection terminals cp7 to cp12. . The counter substrate 2 has a size smaller than the normal region of the array substrate 1, is opposed to the normal region with a gap, is positioned away from the seventh to twelfth inspection terminals cp 7 to cp 12, and is bonded to the array substrate 1. Has been.

  When the liquid crystal display panel is completed, after preparing the liquid crystal display panel, the outer edge of the array substrate 1 is polished while measuring the electrical characteristic value between the inspection terminals. Then, the amount of polishing of the outer edge of the array substrate 1 is determined based on the measured electrical characteristic value. That is, it is possible to determine whether or not the position that should not be further polished has been reached.

  From the above, it is possible to obtain a liquid crystal display panel and a method for manufacturing the liquid crystal display panel that can determine the polishing amount of the outer edge of the array substrate 1 in a short time by a simple method. And a liquid crystal display panel with a high external precision can be obtained. That is, it is possible to meet the demand for higher accuracy of the outer shape of the liquid crystal display panel.

  Next, a liquid crystal display panel and a method for manufacturing the liquid crystal display panel according to the third embodiment will be described. In the present embodiment, the same functional parts as those in the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 17, on the array substrate 1, first to sixth inspection terminals cp1 to cp6 and first to fourth inspection wirings cw1 to cw4 are formed. Furthermore, the seventh to twelfth inspection terminals cp7 to cp12 and the fifth to eighth inspection wirings cw5 to cw8 shown in the second embodiment are also formed on the array substrate 1.

Next, a more detailed configuration of the liquid crystal display panel will be described together with its manufacturing method.
First, mother glass or the like is prepared, and the liquid crystal display panel is taken out from the mother glass by the same method as in the first embodiment.

  The counter substrate 2 has a size smaller than the normal region of the array substrate 1, is opposed to the normal region with a gap, is positioned away from the first to twelfth inspection terminals cp 1 to cp 12, and is bonded to the array substrate 1. Has been. The first to twelfth inspection terminals cp1 to cp12 are provided on the regular region of the array substrate 1 and exposed to the outside. Conductive patterns used for driving for image display, such as constituent members of the drive circuits 6 a and 6 b, are provided on the normal region of the array substrate 1.

  The first to fourth inspection wirings cw1 to cw4 are provided on the array substrate 1, are located at the end of the array substrate 1 with respect to the outer edge planned line e2, and extend beyond the outer edge planned line e2 to the first to sixth inspection terminals cp1. To cp6.

  The fifth to eighth inspection wirings cw5 to cw8 are provided on the array substrate 1, located between the conductive pattern and the planned outer edge line e2, and connected to the seventh to twelfth inspection terminals cp7 to cp12. .

  In order to obtain a polishing margin, the first to fourth inspection wirings cw1 to cw4 and the fifth to eighth inspection wirings cw5 to cw8 are arranged at a predetermined interval. That is, the first inspection wiring cw1 and the fifth inspection wiring cw5 are arranged at a predetermined interval in the column direction Y. The second inspection wiring cw2 and the sixth inspection wiring cw6 are arranged at a predetermined interval in the column direction Y. The second inspection wiring cw2 and the third inspection wiring cw3, and the sixth inspection wiring cw6 and the seventh inspection wiring cw7 are arranged at a predetermined interval in the row direction X. The second inspection wiring cw2 and the fourth inspection wiring cw4 and the sixth inspection wiring cw6 and the eighth inspection wiring cw8 are arranged at a predetermined interval in the row direction X.

After preparing the liquid crystal display panel as described above, the outer edge of the liquid crystal display panel is polished.
First, in this embodiment, the short side of the array substrate 1 is polished.
When the lower side of the array substrate 1 is polished, the electrical characteristic value between the first inspection terminal cp1 and the second inspection terminal cp2, and the electrical characteristic value between the seventh inspection terminal cp7 and the eighth inspection terminal cp8. , The outer edge on the lower side of the array substrate 1 is polished. Then, the polishing amount of the lower side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

  In this embodiment, the first inspection terminal cp1 and the second inspection terminal cp2 energize the first inspection wiring cw1, the seventh inspection terminal cp7 and the eighth inspection terminal cp8 energize the fifth inspection wiring cw5, and the first inspection While measuring the first current value between the terminal cp1 and the second inspection terminal cp2 and the second current value between the seventh inspection terminal cp7 and the eighth inspection terminal cp8, the lower side of the array substrate 1 The outer edge is polished.

  Then, it can be determined whether the polishing is insufficient from the first current value, and it can be determined from the second current value whether the polishing is excessive. By polishing the lower side of the array substrate 1 just before the first current value becomes 0 and the second current value becomes 0, the position of the lower side of the array substrate 1 is determined. If the interval between the first inspection wiring cw1 and the fifth inspection wiring cw5 is set within the range of the outline accuracy of the liquid crystal display panel, it is possible to ensure the confirmation of the polishing accuracy.

  When the upper side of the array substrate 1 is polished, the electrical characteristic value between the third inspection terminal cp3 and the fourth inspection terminal cp4 and the electrical characteristic value between the ninth inspection terminal cp9 and the tenth inspection terminal cp10. And the outer edge on the upper side of the array substrate 1 is polished. Then, the polishing amount of the upper side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

  In this embodiment, the third inspection terminal cp3 and the fourth inspection terminal cp4 energize the second inspection wiring cw2, the ninth inspection terminal cp9 and the tenth inspection terminal cp10 energize the sixth inspection wiring cw6, and the third inspection While measuring the third current value between the terminal cp3 and the fourth inspection terminal cp4 and the fourth current value between the ninth inspection terminal cp9 and the tenth inspection terminal cp10, respectively, the upper side of the array substrate 1 The outer edge is polished.

Then, it can be determined whether the polishing is insufficient from the third current value, and it can be determined from the fourth current value whether the polishing is excessive. When the polishing of the upper side of the array substrate 1 is completed before the third current value becomes zero and the fourth current value becomes zero, the position of the upper side of the array substrate 1 is determined. If the interval between the second inspection wiring cw2 and the sixth inspection wiring cw6 is set within the range of the outline accuracy of the liquid crystal display panel, it is possible to ensure the confirmation of the polishing accuracy. In addition, in order to improve the external accuracy of the liquid crystal display panel, the upper side of the counter substrate 2 may be polished together with the upper side of the array substrate 1.
Thereby, the short side of the array substrate 1 is polished.

Subsequently, in this embodiment, the long side of the array substrate 1 is polished.
When the left side of the array substrate 1 is polished, the electrical characteristic value between the third inspection terminal cp3 and the fifth inspection terminal cp5 and the electrical characteristic value between the ninth inspection terminal cp9 and the eleventh inspection terminal cp11. , The outer edge on the left side of the array substrate 1 is polished. Based on the measured electrical characteristic value, the polishing amount of the left side (outer edge) of the array substrate 1 is determined.

  In this embodiment, the third inspection terminal cp3 and the fifth inspection terminal cp5 are energized between the second inspection wiring cw2 and the third inspection wiring cw3, and the ninth inspection terminal cp9 and the eleventh inspection terminal cp11 to the sixth inspection wiring cw6. And the seventh inspection wiring cw7, a fifth current value between the third inspection terminal cp3 and the fifth inspection terminal cp5, and a sixth current between the ninth inspection terminal cp9 and the eleventh inspection terminal cp11. The outer edge on the left side of the array substrate 1 is polished while measuring each value.

  Then, it can be determined whether the polishing is insufficient from the fifth current value, and it can be determined from the sixth current value whether the polishing is excessive. By polishing the left side of the array substrate 1 just before the fifth current value becomes 0 and the sixth current value becomes 0, the position of the left side of the array substrate 1 is determined. If the distance between the second inspection wiring cw2 and the third inspection wiring cw3 and the sixth inspection wiring cw6 and the seventh inspection wiring cw7 is set within the range of the outline accuracy of the liquid crystal display panel, the polishing accuracy can be confirmed. It can be guaranteed. Note that the left side of the array substrate 1 and the left side of the counter substrate 2 may be polished together in order to increase the external accuracy of the liquid crystal display panel.

  When polishing the right side of the array substrate 1, the electrical characteristic value between the fourth inspection terminal cp4 and the sixth inspection terminal cp6, and the electrical characteristic value between the tenth inspection terminal cp10 and the twelfth inspection terminal cp12. , The outer edge of the right side of the array substrate 1 is polished. Then, the polishing amount of the right side (outer edge) of the array substrate 1 is determined based on the measured electrical characteristic value.

  In this embodiment, the fourth inspection terminal cp4 and the sixth inspection terminal cp6 are energized between the second inspection wiring cw2 and the fourth inspection wiring cw4, and the tenth inspection terminal cp10 and the twelfth inspection terminal cp12 to the sixth inspection wiring cw6. And the eighth inspection wiring cw8, the seventh current value between the fourth inspection terminal cp4 and the sixth inspection terminal cp6, and the eighth current between the tenth inspection terminal cp10 and the twelfth inspection terminal cp12. The outer edge on the right side of the array substrate 1 is polished while measuring each value.

Then, it can be determined whether the polishing is insufficient from the seventh current value, and it can be determined from the eighth current value whether the polishing is excessive. By polishing the right side of the array substrate 1 just before the seventh current value becomes 0 and the eighth current value becomes 0, the position of the right side of the array substrate 1 is determined. If the interval between the second inspection wiring cw2 and the fourth inspection wiring cw4 and the sixth inspection wiring cw6 and the eighth inspection wiring cw8 is set within the range of the external accuracy of the liquid crystal display panel, the polishing accuracy can be confirmed. It can be guaranteed. Note that the right side of the counter substrate 2 may be polished together with the right side of the array substrate 1 in order to increase the external accuracy of the liquid crystal display panel.
Thus, the long side of the array substrate 1 is also polished following the short side of the array substrate 1.

  As shown in FIG. 3, after that, a polarizing plate is disposed on each of the outer surfaces of the array substrate 1 and the counter substrate 2, or an IC driver is mounted on the frame region R2 of the array substrate 1, whereby the liquid crystal display panel is Complete.

  According to the liquid crystal display panel and the method of manufacturing the liquid crystal display panel according to the third embodiment configured as described above, the liquid crystal display panel at the manufacturing stage includes the array substrate 1, the conductive pattern, and the first to twelfth. Inspection terminals cp1 to cp12, first to eighth inspection wirings cw1 to cw8, and a counter substrate 2 are provided.

  When the liquid crystal display panel is completed, after preparing the liquid crystal display panel, the outer edge of the array substrate 1 is polished while measuring the electrical characteristic value between the inspection terminals. Then, the amount of polishing of the outer edge of the array substrate 1 is determined based on the measured electrical characteristic value. That is, it is possible to determine whether the polishing should be continued or stopped, or whether it has not reached a position where further polishing should not be performed.

  From the above, it is possible to obtain a liquid crystal display panel and a method for manufacturing the liquid crystal display panel that can determine the polishing amount of the outer edge of the array substrate 1 in a short time by a simple method. And a liquid crystal display panel with a high external precision can be obtained. That is, it is possible to meet the demand for higher accuracy of the outer shape of the liquid crystal display panel.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, the first to eighth inspection wirings cw1 to cw8 need only be formed of a conductor. However, in consideration of measuring the electrical characteristic value between the inspection terminals, the first to eighth inspection wirings cw1 to cw8 are preferably formed of a metal such as MoW or TAT.

  Rather than detecting the current value during polishing, for example, polishing is performed for an appropriate time when polishing is estimated to be completed, and then the current value of each terminal is measured to confirm the outer shape (position). Of course, the configuration of the embodiment of the present invention can be used even in such a case.

  Embodiments of the present invention are not limited to the above-described liquid crystal display panel and liquid crystal display panel manufacturing method, and can be applied to various liquid crystal display panels and liquid crystal display panel manufacturing methods. It is also possible to apply to other display panels and methods for manufacturing display panels.

  1 ... Array substrate, 6a. 6b ... Drive circuit, 11 ... Glass substrate, cp1 to cp12 ... First to twelfth inspection terminals, cw1 to cw8 ... First to eighth inspection wirings, 2 ... Counter substrate, 51 ... Seal material, 101,102 ... Mother glass E1... First dividing line, e2. Outer edge planned line, e3. Second dividing line, R1... Display area, R2.

Claims (8)

An array substrate having an outer edge planned line as an outer edge of the normal region;
A first inspection terminal and a second inspection terminal provided on the regular region of the array substrate and exposed to the outside;
An inspection wiring provided on the array substrate and positioned at an end of the array substrate from the planned outer edge line and connected to the first test terminal and the second test terminal beyond the planned outer edge line;
A display panel having a size smaller than the normal region and opposed to the normal region with a gap therebetween and positioned opposite to the first inspection terminal and the second inspection terminal and bonded to the array substrate . An array substrate having an outer edge planned line as an outer edge of the normal region;
A conductive pattern provided on the regular region of the array substrate and used for driving for image display;
A first inspection terminal and a second inspection terminal provided on the regular region of the array substrate and exposed to the outside;
An inspection wiring provided on the array substrate and located between the conductive pattern and the planned outer edge line and connected to the first inspection terminal and the second inspection terminal;
A display panel having a size smaller than the normal region and opposed to the normal region with a gap therebetween and positioned opposite to the first inspection terminal and the second inspection terminal and bonded to the array substrate .   The display panel according to claim 1, wherein the inspection wiring is made of metal. An array substrate having an outer edge planned line as an outer edge of the normal region;
A conductive pattern provided on the regular region of the array substrate and used for driving for image display;
A first inspection terminal, a second inspection terminal, a third inspection terminal, and a fourth inspection terminal that are provided on the regular region of the array substrate and exposed to the outside;
A first inspection wiring provided on the array substrate and located at an end of the array substrate from the planned outer edge line and connected to the first inspection terminal and the second inspection terminal beyond the planned outer edge line;
A second inspection wiring provided on the array substrate with a gap in the first inspection wiring and positioned between the conductive pattern and the predetermined outer edge line and connected to the third inspection terminal and the fourth inspection terminal; ,
And a counter substrate having a size smaller than the normal region and disposed opposite to the normal region with a gap therebetween, and positioned opposite to the first to fourth inspection terminals and joined to the mother substrate.   The display panel according to claim 4, wherein the first inspection wiring and the second inspection wiring are made of metal. An array substrate having an outer edge planned line as an outer edge of the normal region, a first inspection terminal and a second inspection terminal provided on the normal region of the array substrate and exposed to the outside, and provided on the array substrate An inspection wiring which is located at an end of the array substrate from a predetermined outer edge line and is connected to the first inspection terminal and the second inspection terminal beyond the predetermined outer edge line, and has a size smaller than the normal area and the normal area Preparing a display panel comprising a counter substrate disposed opposite to the first test terminal and the second test terminal and spaced from the second test terminal and bonded to the array substrate.
Polishing an outer edge of the array substrate while measuring an electrical property value between the first inspection terminal and the second inspection terminal;
A display panel manufacturing method for determining a polishing amount of an outer edge of the array substrate based on the measured electrical characteristic value. An array substrate having an outer edge planned line as an outer edge of the normal region, a conductive pattern provided on the normal region of the array substrate and used for driving for image display, and provided on the normal region of the array substrate The first inspection terminal and the second inspection terminal that are exposed to the outside and are disposed between the conductive pattern and the outer peripheral line provided on the array substrate and connected to the first inspection terminal and the second inspection terminal. An inspection substrate having a size smaller than that of the normal region and opposed to the normal region with a gap between the inspection wiring and the first substrate and the counter substrate which is positioned away from the first inspection terminal and bonded to the array substrate. Prepare a display panel with
Polishing an outer edge of the array substrate while measuring an electrical characteristic value between the first inspection terminal and the second inspection terminal;
A display panel manufacturing method for determining a polishing amount of an outer edge of the array substrate based on the measured electrical characteristic value. An array substrate having an outer edge planned line as an outer edge of the normal region, a conductive pattern provided on the normal region of the array substrate and used for driving for image display, and provided on the normal region of the array substrate A first inspection terminal, a second inspection terminal, a third inspection terminal, and a fourth inspection terminal that are exposed to the outside, and are provided on the array substrate and positioned at an end of the array substrate from the predetermined outer edge line; A first inspection wiring connected to the first inspection terminal and the second inspection terminal across a line; and the conductive pattern and the predetermined outer edge line provided on the array substrate with a gap in the first inspection wiring. The second inspection wiring, which is located between the third inspection terminal and the fourth inspection terminal, has a size smaller than that of the normal region and is opposed to the normal region with a gap therebetween. 4 inspection terminals A counter substrate positioned out al bonded to the mother substrate, a display panel comprising a prepared,
While measuring the electrical characteristic value between the first inspection terminal and the second inspection terminal and the other electrical characteristic value between the third inspection terminal and the fourth inspection terminal, respectively, Polish the outer edge of the array substrate,
A display panel manufacturing method for determining a polishing amount of an outer edge of the array substrate based on the measured electric characteristic value and other electric characteristic values.

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