JP2015002642A - High voltage generator, high-voltage power supply, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow as much current as possible to flow to a load while avoiding the discharge between circuit patterns on a circuit board in a high-voltage power supply.SOLUTION: A high voltage generator applies, to the gate of an FET (340), a voltage according to the difference between a feedback voltage obtained by stepping down a high-voltage output voltage and a reference voltage corresponding to the target value of the high-voltage output voltage via an auxiliary winding (351) of a transformer (350) and a differential circuit (330), causes the FET (340) to pass a current to a main winding (352) of the transformer, and rectifies a high voltage output from a secondary winding before outputting the voltage. The voltage at the gate of the FET (340) is limited by a voltage clamp circuit (335).

Description

  The present invention relates to a high voltage generator, a high voltage power supply device, and an image forming apparatus.

  As a conventional high-voltage power supply device, for example, as shown in Patent Document 1, a PWM output of a microcomputer (24) is connected to a base of a bipolar transistor via a base winding (20) of a step-up transformer (17), and a DC power supply Is connected to the collector of the bipolar transistor through the primary winding of the step-up transformer (17), and the output winding (25) of the step-up transformer (17) is connected to the load (29) through the rectifier circuit (28). At the same time, it is known to control the output voltage by feeding back the output of the rectifier circuit (28) to the microcomputer (24).

  FIG. 25 shows a high-voltage power supply device that is a more specific example of the above-described high-voltage power supply device. The illustrated high-voltage power supply device includes a transformer drive circuit 705. In the apparatus of FIG. 25, the PWM output of the microcomputer 701 is connected to a 3.3 V power source 702 via a pull-up resistor 707 in the transformer drive circuit 705, and is also a smoothing filter composed of a resistor 711 and a capacitor 712. The circuit 710 is connected to the inverting input (−) of the operational amplifier 721.

  The output of the integrating circuit 720 including the operational amplifier 721, capacitors 722 and 725, and resistors 723, 724, and 726 is connected to one end of the auxiliary winding 751 on the primary side of the step-up transformer 750, and the other end of the auxiliary winding 751. Are connected to the base of an NPN transistor 740.

  One end of the primary winding 752 on the primary side of the step-up transformer 750 is connected to the power source 703 of 24V, and the other end is connected to the collector of the transistor 740. The output from the secondary winding 753 of the step-up transformer 750 is rectified by the rectifier circuit 760 and supplied to the load 785 as a high-voltage output voltage.

  The high-voltage output voltage (the voltage at the node 790A) is also fed back to the non-inverting input (+) of the operational amplifier 721 via the output voltage conversion unit 770 having an output voltage conversion function (step-down function). The rectifier circuit 760 includes diodes 761 and 762 and capacitors 763 and 764. The output voltage converter 770 includes a 50 MΩ resistor 771, a 100 kΩ resistor 772, a 1 MΩ pulldown resistor 773, and a capacitor 774.

  In the initial state, the PWM output of the microcomputer 701 is at the H level and is pulled up by the resistor 707, so that a voltage of 3.3 V from the power supply 702 is applied to the inverting input terminal (−) of the operational amplifier 721 via the filter circuit 710. Is input. Further, since the high voltage output of the node 790A is in an off state, 3.0V which is a value obtained by dividing the output 3.3V of the power supply 702 by the resistor 772 of 100 kΩ and the resistor 773 of 1 MΩ is the non-inverting input of the operational amplifier 721. Input to terminal (+).

  Since the voltage (3.0 V) of the non-inverting input (+) is lower than the voltage (3.3 V) of the inverting input (−), the output of the operational amplifier 721 becomes the lowest voltage (VOL = approximately 0 V). Therefore, no base current flows through the NPN transistor 740 and no current flows through the main winding 752 of the step-up transformer 750. As a result, the output of the node 790A is maintained off.

  Thereafter, the microcomputer 701 starts outputting a PWM signal having a duty corresponding to the target value (target voltage) of the high voltage output from the PWM output port, and the PWM signal is input to the inverting input terminal (−) via the filter circuit 710. Is done. The larger the target voltage is, the smaller the duty of the PWM output is. Therefore, the input voltage of the inverting input terminal (−) of the operational amplifier 721 becomes a smaller value.

  When the input voltage at the inverting input terminal (−) becomes lower than the input at the non-inverting input terminal (+), the output of the integrating circuit 720 gradually increases. As a result, a current flows to the base of the transistor 740 through the auxiliary winding 751 of the step-up transformer 750, and a current flows from the 24 V power source 703 to the collector and emitter of the transistor 740 through the main winding 752. When a current flows through the main winding 752, the potential of the base connected to the auxiliary winding 751 decreases and the current flowing through the main winding 752 is cut off. Thereafter, self-excited oscillation in which the current of the main winding 752 and auxiliary winding 751 is repeatedly turned on and off is started.

  As a result of turning on / off the current of the main winding 752, the boosted AC output is output to the secondary side 753 of the step-up transformer 750, rectified by the rectifier circuit 760, a negative voltage appears at the node 790 A, and the load 785 Supplied.

  The output of the rectifier circuit 760 (the output of the node 790A) is stepped down by the output voltage converter 770 and fed back to the non-inverting input terminal (+) of the operational amplifier 721. Since the output of node 790A is a negative voltage, the value of the feedback voltage decreases as the absolute value increases.

  The base current of the transistor 740 is adjusted in accordance with the voltage difference between the inverting input terminal (−) and the non-inverting input terminal (+) of the operational amplifier 721, and the transistor 740 is driven by the collector current obtained by amplifying the base current. The high voltage output boosted by the oscillation is controlled to a voltage corresponding to the duty of the PWM signal.

  FIG. 26 shows an example of a waveform at the start of output of the circuit of FIG. Symbols D790A, D790B, D790C, and D790D in FIG. 26 indicate changes in potentials of the nodes 790A, 790B, 790C, and 790D in FIG. Reference numerals D790A0, D790B0, D790C0, and D790D0 indicate zero levels of the waveforms D790A, D790B, D790C, and D790D, respectively.

  FIG. 27 shows an example of a circuit (positive / negative bias circuit) that selectively generates positive and negative biases, which is formed by combining circuits similar to the circuit of FIG. The illustrated positive / negative bias circuit includes a positive bias circuit 810 that receives a PWM signal PWMp having a duty corresponding to the positive bias target voltage from the microcomputer 801, and a negative that receives a PWM signal PWMn having a duty corresponding to the negative bias target voltage from the microcomputer 801. And a bias circuit 820.

  The positive bias circuit 810 includes a transformer drive circuit 830, a step-up transformer 835, a rectifier circuit 840, and resistors 857, 858, and 859. The rectifier circuit 840 includes diodes 843 and 844 and capacitors 845 and 846. A step-up mold transformer 837 is configured by the step-up transformer 835, the rectifier circuit 840, and the resistors 857 and 858.

The negative bias circuit 820 includes a transformer drive circuit 860, a step-up transformer 865, a rectifier circuit 870, an oscillation frequency adjustment capacitor 882, and resistors 887, 888, and 889.
The rectifier circuit 870 includes diodes 873 and 874 and capacitors 875 and 876.
Each of the transformer drive circuits 830 and 860 is configured in the same manner as the transformer drive circuit 705 in FIG. 25 and includes a transistor similar to the transistor 740.

  The negative bias is applied to load 890 through resistor 858. For example, the resistance value of the resistor 858 is 100 MΩ. The negative bias output is divided by resistors 887, 888 and 889 and fed back to the transformer drive circuit 860, thereby controlling the negative bias output voltage. For example, the resistor 887 is 5 MΩ, the resistor 888 is 1 MΩ, and the resistor 889 is 5 kΩ.

  At the time of positive bias output, current is supplied through resistors 887 and 889. The voltage divided by the resistors 857 and 859 is fed back to the transformer drive circuit 830, thereby controlling the positive bias output voltage.

Japanese Patent Laid-Open No. 11-341801

  However, the conventional apparatus cannot sufficiently increase the load current when the negative bias is applied. For example, an open type transformer (non-molded transformer) having an EE16 size ferrite core is used as the step-up transformer 865, and the type of the transistor in the transformer driving circuit 860 (having the same role as the transistor 740 in FIG. 25) is When an NPN bipolar transistor with TO-220 and Pc (power loss) of 25 W is used, the rectifier circuit 870 can output only up to about −2700 V and 570 μA, and the current that can flow through the load 890 has a load resistance value. When it is 10 MΩ to 100 MΩ, it is about 25 μA to 14 μA.

  Since a current is supplied through a feedback resistor 887 of 5 MΩ at the time of positive bias output, the potential difference between both ends of the resistor 887 becomes 3000 V when the current flowing through the load is, for example, 600 μA. The potential difference between the circuit patterns exceeds 3000 V, and electric discharge easily occurs between the circuit patterns.

  If the resistance value of the feedback resistor 887 is lowered, the positive bias supply property is improved, but the negative bias supply property is deteriorated as a trade-off. In particular, in recent years, there has been a market demand for various printing media in an intermediate transfer type image forming apparatus. For example, when transferring to a narrow medium such as a postcard or a business card, most of the transfer current is transferred to the transfer roller. A large amount of current must be passed to transfer a high resistance medium such as a film medium because it flows between the intermediate transfer belts, but a conventional high-voltage power supply cannot cope with it.

  In addition, when trying to bring the fixing device and the secondary transfer nip closer to each other in order to cope with a medium shorter in the medium conveyance direction, the temperature of the transfer roller rises due to the heat of the fixing device, and as a result, the resistance value of the transfer roller decreases. As a result, there is a problem that the transfer current increases, so it is difficult to bring the fixing device and the secondary transfer nip close to each other.

  An object of the present invention is to provide a high-voltage power supply apparatus that can flow more current to a load while avoiding discharge between circuit patterns on a circuit board.

The high voltage generator of the present invention is
For applying a DC voltage to the load,
An integrating circuit including an operational amplifier;
The primary side has a main winding and an auxiliary winding, the secondary side has a secondary winding, one end of the main winding is connected to a DC power source, and one end of the auxiliary winding is the integration circuit A transformer connected to the output of
An FET having a drain connected to the other end of the main winding;
A differentiating circuit for coupling the other end of the auxiliary winding to the gate of the FET;
A rectifier circuit that rectifies the output of the secondary winding of the transformer to generate a high voltage output and supplies the output to the load;
An output voltage converter that steps down the high voltage output of the rectifier circuit and outputs it as a feedback voltage;
A reference voltage generator that outputs a voltage having a value equal to the value of the feedback voltage when a voltage applied to the load is equal to a target voltage, as a reference voltage;
The integration circuit outputs a voltage corresponding to the difference between the reference voltage and the feedback voltage,
The output of the integration circuit is supplied to the gate through the auxiliary winding and the differentiation circuit, so that feedback control is performed so that the voltage applied to the load matches the target voltage,
The differentiation circuit is:
A first capacitor connecting the other end of the auxiliary winding and the gate;
A first resistance circuit connected in parallel to the first capacitor;
A second resistance circuit connected between the gate and a ground node;
When the FET is turned on and a current flows from the DC power source to the main winding, a voltage induced in the auxiliary winding is applied to the gate through the differentiation circuit, thereby Causing self-excited oscillation of the transformer,
It further comprises a voltage clamp circuit for limiting the voltage between the gate and the ground node to a predetermined upper limit value or less.

  According to the present invention, a field effect transistor (FET) is used for a self-oscillation circuit of a transformer and is driven by a differentiating circuit, so that the self-oscillation operation and the drain current can be well controlled to increase the output. Is possible. Furthermore, the inrush current at the start of output can be suppressed by clamping the gate voltage with a voltage clamp circuit.

1 is a schematic diagram illustrating an image forming apparatus according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a control system of the image forming apparatus in FIG. 1 together with members to be controlled and sensors. FIG. 3 is a block diagram illustrating a configuration example of a printer engine control unit and a high-voltage power supply device in FIG. 2. The entire block configuration of the secondary transfer bias generator (264) is shown. It is a figure which shows the circuit structure of a negative bias generation part (270). It is a figure which shows the circuit structure of a positive bias generation part (280). (A) And (b) is a figure which shows schematic structure of the step-up transformer in the negative bias generation part of FIG. (A)-(c) is a figure which shows schematic structure of the step-up transformer in the positive bias generation part of FIG. FIG. 6 is a waveform diagram showing an example of voltage and current appearing in each part of the circuit when the high-voltage output voltage is raised by the negative bias generator (270) shown in FIG. FIG. 10 is a waveform diagram schematically showing a gate voltage and a drain current among the waveforms shown in FIG. 9. FIG. 10 is a waveform diagram for comparison, similar to FIG. 9, when no Zener diode is inserted in the negative bias generation unit shown in FIG. 5. FIG. 12 is a waveform diagram schematically showing a gate voltage and a drain current among the waveforms shown in FIG. 11. It is a figure which shows the gate-source voltage (Vgs) and drain current (Id) relation of FET (340). (A) And (b) is a figure which shows the gate voltage of the FET at the time of negative bias generation | occurrence | production with and without the oscillation frequency adjustment capacitor | condenser, drain potential, drain current, and the output voltage of a rectifier circuit. . It is a figure which shows the circuit structure of the transformer drive circuit in Embodiment 2 of this invention. It is a figure which shows the circuit structure of the transformer drive circuit in Embodiment 3 of this invention. It is a figure which shows the circuit structure of the transformer drive circuit in Embodiment 4 of this invention. FIG. 18 is a block diagram corresponding to the circuit configuration of FIG. 17. It is a figure which shows the circuit structure of the transformer drive circuit in Embodiment 5 of this invention. It is a figure which shows the circuit structure of the transformer drive circuit in Embodiment 6 of this invention. 14 is a table showing the relationship between the temperature, resistance value, and clamp voltage of the thermistor used in the sixth embodiment. 10 is a table showing the relationship between the temperature and resistance value of the thermistor used in Embodiment 6. (A)-(c) is a figure which shows the example of arrangement | positioning of the thermistor in Embodiment 6. FIG. It is a figure which shows the relationship between the gate-source voltage Vgs of FET (340), and the drain current Id in different temperature. It is a figure which shows the circuit structure of the apparatus which made an example of the conventional high voltage power supply device more concrete. FIG. 26 is a waveform diagram showing an example of potentials appearing at various parts of the circuit at the start of output of the circuit of FIG. 25. FIG. 26 is a diagram illustrating an example of a circuit (positive / negative bias circuit) that selectively generates positive and negative biases, which is formed by combining circuits similar to the circuit of FIG. 25.

Embodiment 1 FIG.
FIG. 1 shows an image forming apparatus according to Embodiment 1 of the present invention. The illustrated image forming apparatus 100 performs primary transfer in the order of black, yellow, magenta, and cyan, and includes development / transfer units 101K, 101Y, 101M, and 101C for black, yellow, magenta, and cyan.

  The black development / transfer unit 101K includes a developer cartridge 102K, an LED head 103K, a toner container 104K, and a primary transfer roller 105K. The developing device cartridge 102K includes a photosensitive drum 132K, a charging roller 136K, a developing roller 134K, a supply roller 133K, a developing blade 135K, and a cleaning blade 137K. The transfer roller 105K is disposed to face the photosensitive drum 132K.

  Similarly, the yellow developing / transfer unit 101Y includes a developing device cartridge 102Y, an LED head 103Y, a toner container 104Y, and a transfer roller 105Y. The developing device cartridge 102Y includes a photosensitive drum 132Y, a charging roller 136Y, a developing roller 134Y, a supply roller 133Y, a developing blade 135Y, and a cleaning blade 137Y. The transfer roller 105Y is disposed to face the photosensitive drum 132Y.

  Similarly, the magenta development / transfer unit 101M includes a developer cartridge 102M, an LED head 103M, a toner container 104M, and a transfer roller 105M. The developing device cartridge 102M includes a photosensitive drum 132M, a charging roller 136M, a developing roller 134M, a supply roller 133M, a developing blade 135M, and a cleaning blade 137M. The transfer roller 105M is disposed to face the photosensitive drum 132M.

  Similarly, the cyan development / transfer unit 101C includes a developer cartridge 102C, an LED head 103C, a toner container 104C, and a transfer roller 105C. The developing device cartridge 102C includes a photosensitive drum 132C, a charging roller 136C, a developing roller 134C, a supply roller 133C, a developing blade 135C, and a cleaning blade 137C. The transfer roller 105C is disposed to face the photosensitive drum 132C.

  The image forming apparatus 100 further includes an intermediate transfer belt 141, an intermediate transfer belt stretching roller 142, an intermediate transfer belt drive roller 143, a secondary transfer backup roller (intermediate transfer belt backup roller) 144, an intermediate transfer belt tension roller 148, and an intermediate transfer belt. Transfer belt cleaning blade 145, waste toner container 146, paper cassette 151, hopping roller 152, registration roller pair 153 and 154, paper detection sensor 155, secondary transfer roller 156, fixing device 157, conveyance guide 158, and paper discharge tray 159 Is provided. The paper cassette 151 stores printing paper 150 as a recording medium.

  FIG. 2 shows a control system of the image forming apparatus 100 of FIG. 1 together with members to be controlled and sensors. 2, the same reference numerals as those in FIG. 1 denote the same members. The illustrated control system includes a host interface unit 211, a command / image processing unit 212, an LED head interface unit 213, a printer engine control unit 220, a storage unit 230, and a high-voltage power supply device 240.

  The printer engine control unit 220 includes a paper detection sensor 155, a thermistor 265, a fixing device heater 259, a temperature / humidity sensor 290, a hopping motor 254, a registration motor 255, a belt motor 256, a fixing device heater motor 257, and drum motors 258K and 258Y. 258M and 258C are connected. The thermistor 265 detects the temperature of the fixing device heater 259 and outputs a signal indicating the detected temperature.

  As shown in FIG. 3, the high-voltage power supply device 240 includes a microcomputer 260 as a setting signal output unit, charging bias generation units 261K, 261Y, 261M, 261C, development bias generation units 262K, 262Y, 262M, 262C, A secondary transfer bias generator 263K, 263Y, 263M, 263C and a secondary transfer bias generator 264 are provided.

The image forming apparatus 100 receives print data in a predetermined format described in PDL (page description language) or the like from an external device (not shown) via the host interface unit 211.
The input print data is converted into bitmap data by the command / image processing unit 212.
The image forming apparatus 100 controls the fixing device heater 259 according to a signal indicating the detected temperature obtained by the thermistor 265 to set the fixing device 157 to a predetermined temperature, and then performs a printing operation (image forming operation) by an electrophotographic process. Start.

  The paper 150 stored in the paper feed cassette 151 in FIG. 1 is fed by a hopping roller 152. The sheet 150 is conveyed to the nip portion 156N formed by the secondary transfer roller 156 and the secondary transfer backup roller 144 on the intermediate transfer belt 141 by the registration rollers 153 and 154.

  The toner containers 104K, 104Y, 104M, and 104C are detachable from the developing units 102K, 102Y, 102M, and 102C, and have a structure that can supply the internal toner to the developing units.

  In the electrophotographic process, the charging bias generators 261K, 261Y, 261M, and 261C supply charging bias to the developing units 102K, 102Y, 102M, and 102C, respectively, thereby charging the photosensitive drums 132K, 132Y, 132M, and 132C. Let

Thereafter, the light emitting elements of the LED heads 103K, 103Y, 103M, and 103C are selectively turned on according to the bitmap data, and the surface of the photosensitive drums 132K, 132Y, 132M, and 132C is selectively neutralized. Then, electrostatic latent images are formed on the photosensitive drums 132K, 132Y, 132M, and 132C, and toner images are formed on the photosensitive drums 132K, 132Y, 132M, and 132C by development.
For development, the development bias generators 262K, 262Y, 262M, and 262C supply development bias to the developing units 102K, 102Y, 102M, and 102C, respectively.

  The toner images on the photoreceptor developed by the developing units 102K, 102Y, 102M, and 102C are sequentially transferred to the intermediate transfer belt 141 by a bias applied to the transfer rollers 105K, 105Y, 105M, and 105C. For transfer onto the intermediate transfer belt 141, primary transfer bias generators 263K, 263Y, 263M, and 263C supply primary transfer bias to the primary transfer rollers 105K, 105Y, 105M, and 105C, respectively. By sequentially transferring, four color toner images are formed on the intermediate transfer belt 141.

  The sheet 150 is conveyed to the nip portion 156N in synchronization with the timing at which the toner image on the intermediate transfer belt 141 reaches the nip portion 156N. That is, the paper 150 is conveyed so that the paper 150 passes through the nip portion 156N so that the toner image on the intermediate transfer belt 141 passes through the nip portion 156N.

  While the sheet 150 passes through the nip portion 156N, the four-color toner images on the intermediate transfer belt 141 are collectively transferred to the sheet 150 by the secondary transfer high voltage applied to the secondary transfer roller 156.

  For secondary transfer, the secondary transfer bias generator 264 supplies a secondary transfer positive bias to the secondary transfer roller 156. More specifically, the secondary transfer bias generator 264 starts supplying the secondary transfer positive bias to the secondary transfer roller 156 at the same time when the leading edge of the sheet 150 reaches the nip 156N, and the trailing edge of the sheet 150 is The supply of the secondary transfer positive bias is finished at a timing immediately before passing through the nip portion 156N. When the secondary transfer positive bias is not applied to the secondary transfer roller 156, the secondary transfer bias generation unit 264 applies a negative bias, whereby the secondary transfer roller 156 due to residual toner on the intermediate transfer belt 141 is applied. Prevents dirt.

The secondary transfer bias generator 264 is connected to a secondary transfer roller 156 as a load, as schematically shown in FIG. 1, for supplying a bias to the secondary transfer roller 156.
The other bias generators 261K to 261C, 262K to 262C, and 263K to 263C are similarly connected to the respective loads, but are not shown in FIG.

  The toner image transferred to the paper 150 is fixed by the fixing device 157, and then the paper is discharged to a paper discharge tray 159.

  The printer engine control unit 220 sets a target value (target voltage) of the high-voltage output voltage in accordance with a predetermined and stored value (table value), a charging bias generation unit 261K, 261Y, 261M, 261C, a development bias generation unit 262K, 262Y, 262M, 262C, primary transfer bias generators 263K, 263Y, 263M, 263C, and commands for outputting respective target voltages to the secondary transfer bias generator 264 at a predetermined timing.

  FIG. 4 shows a portion related to the secondary transfer bias generation unit 264 of the high-voltage power supply device 240 of FIG. 3 together with the printer engine control unit 220, the microcomputer 260, and the power sources 302 and 303. As shown in FIG. 4, the secondary transfer bias generator 264 includes a negative bias generator (first high voltage generator) 270 and a positive bias generator (second high voltage generator) 280.

  FIG. 5 shows an overall circuit configuration of the negative bias generator 270, and FIG. 6 shows an overall circuit configuration of the positive bias generator 280.

  The microcomputer 260 has an SCI (Serial Communication Interface) port 260a, and is connected to the SCI port 220a of the printer engine control unit 220 as shown in FIG. In response to the command for specifying the target voltage and the command for specifying the target voltage of the positive bias, the PWM signal PWMn having the duty corresponding to the specified target voltage of the negative bias is output from the PWM output port 260n. A PWM signal PWMp having a duty corresponding to the target voltage is output from the PWM output port 260p. The frequency of the PWM signals PWMn and PWMp is 40 kHz, for example.

As shown in FIGS. 4 and 5, the negative bias generator 270 includes a transformer drive circuit 272, a step-up transformer 350, a rectifier circuit 360, and an output voltage converter (step-down circuit) 370.
The transformer drive circuit 272 includes a smoothing filter circuit 310, an integration circuit 320, a differentiation circuit 330, a voltage clamp circuit 335, a field effect transistor (FET) 340, and a capacitor 345. An N channel MOSFET is used as the FET 340.

As shown in FIGS. 4 and 6, the positive bias generator 280 includes a transformer drive circuit 282, a step-up transformer 450, a rectifier circuit 460, and an output voltage converter 470.
The transformer drive circuit 282 includes a smoothing filter circuit 410, an integration circuit 420, a differentiation circuit 430, a voltage clamp circuit 435, a field effect transistor (FET) 440, and a capacitor 445. An N-channel MOSFET is used as the FET 440.

  The power supply 302 is a 3.3V DC power supply, and is connected to the filter circuits 310 and 410 and the output voltage conversion units 370 and 470. The power source 303 is a 24V DC power source and is connected to the integrating circuits 320 and 420 and the step-up transformers 350 and 450.

  As shown in FIG. 5, a capacitor 345 for adjusting the oscillation frequency is connected between the drain and source of the FET 340, and the input side of the filter circuit 310, that is, the PWM output port 260n of the microcomputer 260 has a pull-up resistor. Similarly, as shown in FIG. 6, a capacitor 445 for adjusting the oscillation frequency is connected between the drain and source of the FET 440, and the input side of the filter circuit 410. That is, the PWM output port 260p of the microcomputer 260 is connected to the 3.3V power supply 302 via the pull-up resistor 415, but these elements are not shown in FIG.

  The filter circuit 310 includes a resistor 311 having one end connected to the PWM output port 260n, and a capacitor 312 having one end connected to the other end of the resistor 311 and the other end grounded (connected between ground nodes). Have.

  The PWM signal PWMn output from the PWM output port 260n is smoothed by the filter circuit 310, converted into a DC signal having a voltage value corresponding to the duty of the PWM signal PWMn, and input to the integrating circuit 320 as a reference voltage. .

  The integrating circuit 320 includes an operational amplifier (operational amplifier) 321 whose reference voltage is input to the inverting input terminal (−), a series circuit of a capacitor 322 and a resistor 323 that couple the inverting input terminal and the output terminal of the operational amplifier 321, and the operational amplifier 321. One end of the resistor 324 is connected to one end of the resistor 324, one end is connected to the other end of the resistor 324, the other end is grounded, and the other end of the resistor 323 is connected to the other end. Includes an output terminal of the integration circuit 320 and a 1 kΩ resistor 326.

  The output of the integrating circuit 320 is connected to one end of an auxiliary winding 351 that forms part of the primary side of the step-up transformer 350, and the other end of the auxiliary winding 351 is coupled to the gate of the FET 340 by the differentiating circuit 330. .

  The differentiation circuit 330 has a 2680 pF parallel connection to a resistor 331 and a 56 kΩ resistor (first resistor) 331 having one end connected to the other end of the auxiliary winding 351 and the other end connected to the gate of the FET 340. The capacitor 332 includes a 56 kΩ resistor (second resistor) 333 having one end connected to the gate of the FET 340 and the other end grounded.

  A voltage clamp circuit 335 is provided between the other end of the auxiliary winding 351 and the gate of the FET 340. The voltage clamp circuit 335 limits the potential of the gate of the FET 340 to a predetermined upper limit value or less, and includes a Zener diode 336, for example. In the illustrated example, the cathode of the Zener diode 336 is connected to the other end of the auxiliary winding 351, and the anode is grounded. The Zener voltage of the Zener diode 336 is 12V, for example.

  One end of the main winding 352 constituting another part of the primary side of the step-up transformer 350 is connected to the power source 303 of 24V, and the other end is connected to the drain of the FET 340. The source of the FET 340 is grounded. The capacitor 345 is connected between the drain and source of the FET 340 to adjust the oscillation frequency, and has a capacitance of 0.01 μF, for example. As the step-up transformer 350, for example, one having an EE16 ferrite core is used.

  The rectifier circuit 360 includes a high breakdown voltage diode 361 having a cathode connected to one end of the secondary winding 353, a high breakdown voltage diode 362 having an anode connected to one end of the secondary winding 353, and a cathode grounded. A high voltage capacitor 363 having one end connected to the anode of the diode 361 and the other end connected to the other end of the secondary winding, one end connected to the other end of the secondary winding, and the other end of the diode 362 A high-voltage capacitor 364 connected to the cathode and rectifies the output from the secondary winding 353 of the step-up transformer 350 to generate a high-voltage output. The anode of the diode 361 constitutes the negative output terminal of the rectifier circuit 360, and the cathode of the diode 362 constitutes the positive output terminal.

  The output (high voltage output voltage) of the rectifier circuit 360 is connected as a negative bias output voltage to a load 156 via a resistor 477 (described later) in the positive bias generator 280 as shown in FIG.

  The output voltage conversion unit 370 steps down the high voltage output voltage (the voltage at the node 390C) and supplies it as a feedback voltage to the non-inverting input terminal (+) of the operational amplifier 321. In the illustrated example, the output voltage conversion unit 370 has one end connected to the negative output terminal of the rectifier circuit 360 and a 3 MΩ high withstand voltage resistor 371, and one end connected to the 3.3 V power supply 302. A resistor 372, a 110 kΩ resistor 373 having one end connected to the other end of the resistor 371 and the other end of the resistor 372 and the other end grounded, and a capacitor 374 connected in parallel to the resistor 373, The one end constitutes an output terminal of the output voltage converter 370, and the voltage of the output terminal is supplied as a feedback voltage to the non-inverting input terminal (+) of the operational amplifier 321.

  The microcomputer 260 and the filter circuit 310 constitute a reference voltage generator that generates a reference voltage corresponding to the negative bias target voltage. The reference voltage generated by the reference voltage generator has a value equal to the value of the feedback voltage when the voltage applied to the load is equal to the target voltage.

  The integrating circuit 320 outputs a voltage corresponding to the difference between the reference voltage supplied from the filter circuit 310 and a feedback voltage described later.

  The output of the integrating circuit 320 is supplied to the gate of the FET 340 via the auxiliary winding 351 and the differentiating circuit 330, whereby feedback control is performed so that the voltage applied to the load 156 matches the target voltage. After self-excited oscillation is started by the winding inductance and capacitor, the integration circuit 320 adjusts the gate voltage. The average voltage of the AC voltage due to the oscillation applied to the gate is adjusted by the integrating circuit 320, and as a result, the output voltage is controlled by controlling the drain current. In this manner, self-excited oscillation in which the currents of the main winding 352 and the auxiliary winding 351 are repeatedly turned on / off is started. During oscillation, an AC signal output from the auxiliary winding 351 is applied to the gate of the FET 340 by capacitive coupling by the differentiation circuit 330.

  When the current of the main winding 352 is turned on / off, the boosted AC voltage is output from the secondary winding 353, rectified by the rectifier circuit 360, and a negative voltage appears at the node (output node) 390C, and the resistance (Negative voltage output resistance) 477 is supplied to the load 156 via the 477.

  The frequency of the self-excited oscillation flows to the self-inductance and mutual inductance of the primary and secondary windings of the step-up transformer 350, the parasitic capacitance of each winding, the capacitance of the capacitor of the rectifier circuit 360, and the load 156. Depends on current etc.

  In such an operation, the voltage applied to the gate of the FET 340 by the voltage clamp circuit 335 is limited to a predetermined upper limit value or less, thereby preventing the current flowing through the FET 340 from becoming excessive.

  The filter circuit 410, the pull-up resistor 415, the integration circuit 420, the differentiation circuit 430, the voltage clamp circuit 435, the FET 440, the capacitor 445, the step-up transformer 450, the rectifier circuit 460, and the output voltage conversion unit 470 in the positive bias generation unit 280 , Negative bias generator 270, filter circuit 310, pull-up resistor 315, integrator circuit 320, differentiator circuit 330, voltage clamp circuit 335, FET 340, capacitor 345, step-up transformer 350, rectifier circuit 360, and output voltage converter 370. It is configured in the same way.

In other words, the filter circuit 410 includes a resistor 411 having one end connected to the PWM output port 260p, and a capacitor 412 having one end connected to the other end of the resistor 411 and the other end grounded.
The PWM signal PWMp output from the PWM output port 260p is smoothed by the filter circuit 410, converted into a DC signal having a voltage value corresponding to the duty of the PWM signal PWMp, and input to the integrating circuit 420 as a reference voltage. .

  The integrating circuit 420 includes an operational amplifier (operational amplifier) 421 whose reference voltage is input to the non-inverting input terminal (+), a series circuit of a capacitor 422 and a resistor 423 that couple the inverting input terminal (−) and the output terminal of the operational amplifier 421. A resistor 424 having one end connected to the output terminal of the operational amplifier, a capacitor 425 having one end connected to the other end of the resistor 424 and the other end grounded, and one end connected to the other end of the resistor 424, The other end has a 1 kΩ resistor 426 constituting the output terminal of the integrating circuit 420.

  The output of the integrating circuit 420 is connected to one end of an auxiliary winding 451 that forms part of the primary side of the step-up transformer 450, and the other end of the auxiliary winding 451 is coupled to the gate of the FET 440 by the differentiating circuit 430. .

  The differentiation circuit 430 has a 2680 pF parallel connection to a resistor 431 and a 56 kΩ resistor (first resistor) 431 having one end connected to the other end of the auxiliary winding 451 and the other end connected to the gate of the FET 440. The capacitor 432 has a 56 kΩ resistor (second resistor) 433 having one end connected to the gate of the FET 440 and the other end grounded.

  A voltage clamp circuit 435 is provided between the other end of the auxiliary winding 451 and the gate of the FET 440. The voltage clamp circuit 435 limits the gate potential of the FET 440 to a predetermined upper limit value or less, and includes, for example, a Zener diode 436. In the illustrated example, the cathode of the Zener diode 436 is connected to the other end of the auxiliary winding 451, and the anode is grounded. The Zener voltage of the Zener diode 436 is 12V, for example.

  One end of the main winding 452 constituting another part of the primary side of the step-up transformer 450 is connected to the power source 303 of 24V, and the other end is connected to the drain of the FET 440. The source of the FET 440 is grounded. The capacitor 445 is connected between the drain and source of the FET 440 for adjusting the oscillation frequency, and has a capacitance of 0.01 μF, for example. As the step-up transformer 450, for example, a transformer having a UU type ferrite core is used.

The rectifier circuit 460 includes a high voltage diode 461 whose anode is connected to one end of the secondary winding 453, a high voltage diode 462 whose cathode is connected to one end of the secondary winding 453, and one end of the diode 461. A high voltage capacitor 463 connected to the cathode, the other end connected to the other end of the secondary winding 453, one end connected to the other end of the secondary winding 453, and the other end connected to the anode of the diode 462 The output voltage from the secondary winding 453 of the step-up transformer 450 is rectified to generate a high voltage output. The cathode of the diode 461 constitutes the positive output terminal of the rectifier circuit 460, and the anode of the diode 462 constitutes the negative output terminal of the rectifier circuit 460.
The rectifier circuit 460 is configured in the same manner as the rectifier circuit 360, but the direction of the diode is reversed and generates a positive high voltage output. Further, the negative output terminal of the rectifier circuit 460 is not grounded but is connected to the output node 390C of the negative bias generator 270.

  The output (high voltage output voltage) of the rectifier circuit 460 is supplied to the load 156 as a positive bias output voltage.

  The output voltage conversion unit 470 steps down the high voltage output voltage (the voltage at the node 490C) and supplies it as a feedback voltage to the inverting input terminal (−) of the operational amplifier 421. In the illustrated example, the output voltage converter 470 has a 100 MΩ high withstand voltage resistor 471 connected at one end to the positive output terminal of the rectifier circuit 460 and a 1 MΩ resistor 472 connected at one end to the power supply 302 at 3.3 V. A 51 kΩ resistor 473 having one end connected to the other end of the resistor 471 and the other end of the resistor 472, and the other end grounded, a capacitor 474 connected in parallel to the resistor 473, and a high withstand voltage resistor 477. The one end of the resistor 473 constitutes the output terminal of the output voltage converter 470, and the voltage at the output terminal is supplied as a feedback voltage to the inverting input terminal (−) of the operational amplifier 421. The resistor 477 is connected between the negative output terminal and the positive output terminal of the rectifier circuit 460.

  The step-up transformer 450, the rectifier circuit 460, and the output voltage conversion unit 470 constitute a step-up mold transformer 480 including these as constituent components.

  The microcomputer 260 and the filter circuit 410 constitute a reference voltage generation unit that generates a reference voltage corresponding to the target voltage of the positive bias. The reference voltage generated by the reference voltage generator has a value equal to the value of the feedback voltage when the voltage applied to the load is equal to the target voltage.

  The integration circuit 420 outputs a voltage corresponding to the difference between the reference voltage supplied from the filter circuit 410 and a feedback voltage described later.

  The output of the integrating circuit 420 is supplied to the gate of the FET 440 via the auxiliary winding 451 and the differentiating circuit 430, whereby feedback control is performed so that the voltage applied to the load 156 matches the target voltage. That is, when the output of the integrating circuit 420 rises, the voltage of the gate of the FET 440 rises along with this, and when it exceeds the threshold, the FET 440 is turned on, and the current of the main winding 452 flows from the 24V power source 303. This current induces a voltage having a polarity that lowers the gate voltage of the FET 440 in the auxiliary winding 451. The voltage induced in the auxiliary winding 451 is applied to the gate of the FET 440 via the differentiating circuit 430 to lower the gate voltage below the threshold value, and the FET 440 is turned off. In this manner, self-excited oscillation in which the current of the main winding 452 and the auxiliary winding 451 is repeatedly turned on and off is started. During oscillation, an AC signal output from the auxiliary winding 451 is applied to the gate of the FET 440 by capacitive coupling by the differentiation circuit 430.

  When the current of the main winding 452 is turned on / off, the boosted AC voltage is output from the secondary winding 453, rectified by the rectifier circuit 460, a positive voltage appears at the node (output node) 490C, and the load 156 To be supplied.

  The frequency of the self-excited oscillation flows to the self-inductance and mutual inductance of the primary and secondary windings of the step-up transformer 450, the parasitic capacitance of each winding, the capacitance of the capacitor of the rectifier circuit 460, and the load 156. Depends on current etc.

  In such an operation, the voltage applied to the gate of the FET 440 by the voltage clamp circuit 435 is limited to a predetermined upper limit value or less, thereby preventing the current flowing through the FET 440 from becoming excessive.

7A and 7B show a schematic configuration of the step-up transformer 350 of FIG.
The transformer 350 has a primary side 511 and a secondary side 512.
The transformer 350 includes an auxiliary winding 351, a main winding 352, and a secondary winding 353 wound around a bobbin 502 (shown by a dotted line) provided around an EE16 type ferrite core 501.
The auxiliary winding 351 and the main winding 352 are provided on the primary side 511, and the secondary winding 353 is provided on the secondary side 512.
The auxiliary winding 351 is wound around the bobbin 502 (FIG. 7A), and the main winding 352 is wound around the auxiliary winding 351 (FIG. 7B).

  The auxiliary winding 351 is indicated by reference numerals 503 and 504, respectively, and the main winding 352 is indicated by reference numerals 505 and 506, and the secondary winding 353 is indicated by The winding start and winding end are indicated by reference numerals 507 and 508, respectively.

  The EE type core is a combination of a pair of E type core members, and a spacer gap SGa of 0.04 mm is formed between the core members.

  As the step-up transformer 450 in the positive bias generator 280, a transformer having the UU type ferrite core 521 shown in FIG. 8C in which the core member 522 shown in FIGS. 8A and 8B is assembled is used. . In the example shown in FIG. 8C, a spacer gap SGb of 0.08 mm is formed between the core members.

The printer engine control unit 220 outputs a command specifying a target voltage from the SCI port 220a. This command is received by the SCI port 260a of the microcomputer 260.
In the output off state, a command for setting the target voltage to 0 V is transmitted, and in response to this, the microcomputer 260 outputs a PWM signal (a signal for maintaining the high state) PWMn having a duty of 100% from the PWM port 260n, The PWM port 260p outputs a PWM signal having a duty of 0% (a signal for maintaining the low state) PWMp.

Since the PWM port 260n is connected to the 3.3V power source 302 via the resistor 305, when the output of the PWM port 260n is in a high state, the potential of the PWM port 260n is pulled up to 3.3V.
The voltage of 3.3 V of the PWM port 260 n is input to the inverting input terminal (−) of the operational amplifier 321 as a reference voltage via the filter circuit 310.

In the output off state, 3.3 V supplied from the power supply 302 is divided by the resistor 372 (3.6 kΩ) and the resistor 373 (100 kΩ) of the output voltage conversion unit 370, and 3.2 V obtained as a result of the voltage division is the feedback voltage. Is input to the non-inverting input terminal (+) of the operational amplifier 321.
Since the feedback voltage (input of the non-inverting input terminal (+)) is lower than the reference voltage (input voltage of the inverting input terminal (−)), the output voltage VO of the operational amplifier 321 is the lowest voltage (VOL = approximately 0 V).

  In this state, the gate input voltage of the FET 340 is sufficiently lower than the gate threshold voltage VTH, so the FET 340 is kept off, no current flows through the winding of the step-up transformer, and the high voltage output (node 390C) is kept off. Is done.

Positive bias generation unit 280 operates in the same manner, and maintains the state where the high voltage output (node 490C) is off. That is, the 0 V voltage of the PWM port 260 p is input to the non-inverting input terminal (+) of the operational amplifier 421 as the reference voltage via the filter circuit 410.
In the output off state, 3.3 V supplied from the power supply 302 is divided by the resistor 472 (1 MΩ) and the resistor 473 (51 kΩ) of the output voltage converter 470, and 0.16 V obtained as a result of the voltage division is used as a feedback voltage as an operational amplifier. It is input to the inverting input terminal (−) of 421.
Since the reference voltage (input voltage of the non-inverting input terminal (+)) is lower than the feedback voltage (input voltage of the inverting input terminal (−)), the output voltage VO of the operational amplifier 421 is the lowest voltage (VOL = approximately 0 V). is there.

  In this state, the gate input voltage of the FET 440 is sufficiently lower than the gate threshold voltage VTH, so the FET 440 is kept off, no current flows through the winding of the step-up transformer, and the high voltage output (node 490C) is kept off. Is done.

When the image forming operation is started and the driving of the belt motor 256 is started,
In order to apply a negative bias to the secondary transfer roller 156, the printer engine control unit 220 transmits a command for specifying a target voltage to the microcomputer 260 by serial communication.

  The target voltage of the negative bias of the secondary transfer roller is, for example, −3000V, and the duty of the PWM signal for outputting this voltage is 0%. In this case, the printer engine control unit 220 transmits a command for instructing output of the target voltage of −3000 V to the microcomputer 260.

  When a command for instructing output of −3000 V as a target voltage is transmitted from the printer engine control unit 220 to the microcomputer 260, the microcomputer 260 sets the duty of the PWM signal PWMn output from the PWM port 260n in response to this command. The voltage corresponding to the voltage (−3000V) is changed to 0%.

  The PWM signal PWMn having a duty corresponding to the target voltage is smoothed by the filter circuit 310, converted into a DC voltage (reference voltage) having a value corresponding to the target voltage (target high voltage), and input to the integration circuit 320.

The operational amplifier 321 constitutes an integration circuit 320 having a time constant determined by the capacitor 322 and the resistor 323.
As described above, the integration circuit 320 outputs approximately 0 V, which is VOL in the initial state (negative bias off state), but the PWM signal PWMn corresponding to the target voltage is output from the microcomputer 260, and the DC corresponding to this is output. When a voltage (reference voltage) is input from the filter circuit 310 to the inverting input terminal (−), the reference voltage (0.3 V) of the inverting input terminal is lower than the feedback voltage (3.2 V) of the non-inverting input terminal. Thus, the output voltage is gradually increased with a time constant determined by the capacitor 322 and the resistor 323.

  The increase in the output voltage of the integration circuit 320 increases the input voltage of the differentiation circuit 330 via the auxiliary winding 351 of the step-up transformer 350, and the output voltage of the differentiation circuit 330 is applied to the gate of the FET 340. Accordingly, the output voltage of the integrating circuit 320 is divided by the resistors 324, 326, 331, and 333 and applied to the gate of the FET 340.

  The FET 340 is turned on when the gate voltage exceeds a threshold value due to the rise of the DC voltage input through the differentiating circuit 330, current flows in the main winding 352 of the step-up transformer 350, and oscillation occurs due to LC resonance by the step-up transformer 350. After that, the AC voltage generated in the auxiliary winding 351 is applied to the gate of the FET 340 via the differentiation circuit 330. The input to this gate turns the FET 340 on and off.

  During the above operation, the Zener diode 336 having the anode connected to the end 351b of the auxiliary winding 351 conducts at 12V or higher, and thus the gate voltage is clamped to 6V or lower by the voltage division by the resistors 331 and 333.

  The AC voltage output from the secondary winding 353 of the step-up transformer 350 is rectified by the rectifier circuit 360, stepped down to a low voltage by the output voltage conversion unit 370, and fed back to the integration circuit 320. As the absolute value of the negative bias output voltage output from the rectifier circuit 360 increases, the feedback voltage gradually decreases from 3.3 V and reaches the target voltage of −3000 V, the feedback voltage becomes 0 V, and the negative bias When the absolute value of the output voltage is further increased, the feedback voltage becomes a negative value.

The integration circuit 320 compares the DC voltage (reference voltage) corresponding to the target voltage with the fed back voltage (output of the output voltage conversion unit 370), and if the feedback voltage is higher than the reference voltage (0.3V), the operational amplifier output is As a result, the gate input voltage of the FET 340 increases and the drain current increases.
On the other hand, when the feedback voltage is lower than the reference voltage (0.3 V), the operational amplifier output decreases, and as a result, the gate input voltage of the FET 340 decreases and the drain current decreases.
Such feedback control stabilizes the operational amplifier output when the feedback voltage matches the reference voltage.

The negative bias output from the rectifier circuit 360 is supplied to the load 156 via the resistor 477.
As described above, the voltage equal to the feedback voltage when the voltage applied to the load 156 from the rectifier circuit 360 via the resistor 477 (the voltage at the node 490C) is equal to the target voltage is supplied to the integrating circuit 320 as the reference voltage. Thus, the voltage supplied to the load 156 (the voltage at the node 490C) can be controlled to a value equal to the target voltage.

  By applying a negative bias to the secondary transfer roller 156 as a load, it is possible to prevent the secondary transfer roller 156 from being soiled by residual toner on the intermediate transfer belt 141.

  At the timing when the recording medium 150 reaches the nip portion of the secondary transfer roller 156, the negative bias is turned off, and the positive bias is turned on instead. The printer engine control unit 220 stops the application of the negative bias to the secondary transfer roller 156 and transmits a command specifying the target voltage to the microcomputer 260 by serial communication in order to apply the positive bias to the secondary transfer roller 156. To do.

  The target voltage for the positive bias of the secondary transfer roller is, for example, +2000 V, and the duty of the PWM signal for outputting this voltage is 33.2%. In this case, the printer engine control unit 220 transmits a command to the microcomputer 260 to instruct the output of the target voltage of + 2000V.

  When a command instructing the output of +2000 V as the target voltage is transmitted from the printer engine control unit 220 to the microcomputer 260, the microcomputer 260 sets the duty of the PWM signal PWMp output from the PWM port 260p in accordance with this command to the target voltage. Change to the one corresponding to (+ 2000V), that is, 33.2%.

  The PWM signal PWMp having a duty corresponding to the target voltage is smoothed by the filter circuit 410, converted into a DC voltage (reference voltage) having a value corresponding to the target voltage (target high voltage), and input to the integration circuit 420.

  The operational amplifier 421 constitutes an integration circuit 420 having a time constant determined by the capacitor 422 and the resistor 423. As described above, the integrating circuit 420 outputs approximately 0 V, which is VOL in the initial state (positive bias off state), but the PWM signal PWMp corresponding to the target voltage is output from the microcomputer 260, and the DC corresponding to this is output. When a voltage (reference voltage) is input from the filter circuit 410 to the non-inverting input terminal (+), the reference voltage (about 1.13 V) at the non-inverting input terminal is set to be higher than the feedback voltage (0.16 V) at the inverting input terminal. The output voltage is gradually increased with a high time constant determined by the capacitor 422 and the resistor 423.

  The increase in the output voltage of the integration circuit 420 increases the input voltage of the differentiation circuit 430 through the auxiliary winding 451 of the step-up transformer 450, and the output voltage of the differentiation circuit 430 is applied to the gate of the FET 440. Therefore, the output voltage of the integration circuit 420 is divided by the resistors 424, 426, 431, and 433 and applied to the gate of the FET 440.

  The FET 440 is turned on when the gate voltage exceeds a threshold value due to the rise of the DC voltage input through the differentiating circuit 430, a current flows through the main winding 452 of the step-up transformer 450, and oscillation occurs due to LC resonance by the step-up transformer 450. After that, an AC voltage generated in the auxiliary winding 451 is applied to the gate of the FET 440 via the differentiation circuit 430. The input to this gate turns the FET 440 on and off.

  During the above operation, the Zener diode 436 whose anode is connected to the end 451b of the auxiliary winding 451 conducts at 12V or higher, so that the gate voltage is clamped to 6V or lower by voltage division by the resistors 431 and 433.

  The AC voltage output from the secondary winding 453 of the step-up transformer 450 is rectified by the rectifier circuit 460, stepped down to a low voltage by the output voltage conversion unit 470, and fed back to the integration circuit 420. As the positive bias output voltage output from the rectifier circuit 460 increases, the feedback voltage gradually increases from 0.15 V, and when the target voltage reaches +2000 V, the feedback voltage becomes 1.13 V, and the positive bias output As the voltage is further increased, the feedback voltage is further increased from 1.13V.

The integration circuit 420 compares the DC voltage (reference voltage) corresponding to the target voltage with the fed back voltage (output of the output voltage conversion unit 470). If the feedback voltage is lower than the reference voltage (1.13V), the operational amplifier output is As a result, the gate input voltage of the FET 440 increases and the drain current increases.
On the other hand, when the feedback voltage is higher than the reference voltage (1.13 V), the operational amplifier output decreases, and as a result, the gate input voltage of the FET 440 decreases and the drain current decreases. Such feedback control stabilizes the operational amplifier output when the feedback voltage matches the reference voltage.

  The bias output from the rectifier circuit 460 is supplied to the load 156. As described above, the voltage that is equal to the feedback voltage when the voltage applied to the load 156 from the rectifier circuit 460 (the voltage at the node 490C) is equal to the target voltage is supplied to the integrating circuit 420 as a reference voltage, thereby the load The voltage supplied to 156 (the voltage at node 490C) can be controlled to a value equal to the target voltage.

  By applying a positive bias to the secondary transfer roller 156 as a load, the toner image is transferred from the intermediate transfer belt 141 to the paper 150 as a recording medium.

  When the high voltage is off (when the high voltage output is terminated), the duty of the PWM output PWMn is returned to 100% (a state in which High is maintained), and the duty of the PWM output PWMp is returned to 0% (a state in which Low is maintained).

  FIG. 9 is a waveform diagram showing an example of voltage and current appearing in each part of the circuit when the high-voltage output voltage is raised by the negative bias generator 270 shown in FIG. FIG. 10 is a waveform diagram schematically showing the gate voltage D390B and the drain current D390D among the waveforms shown in FIG. FIG. 11 is a waveform diagram for comparison similar to FIG. 9 when no Zener diode is inserted in the circuit of FIG. FIG. 12 is a waveform diagram schematically showing the gate voltage D390B and the drain current D390D among the waveforms shown in FIG. FIG. 13 shows the relationship between the gate-source voltage Vgs of the FET 340 and the drain current Id.

  A symbol D390B in FIGS. 9 and 11 indicates the potential of the node 390B in FIG. 5, that is, the gate of the FET 340. A symbol D390C indicates the potential of the output of the node 390C, that is, the rectifier circuit 360. Symbol D390A indicates the current of the node 390A, that is, the current of the primary main winding of the step-up transformer 350 (primary current). A symbol D390D indicates the current of the node 390D, that is, the drain current of the FET 340. Reference numerals D390A0, D390B0, D390C0, and D390D0 indicate zero levels of the waveforms D390A, D390B, D390C, and D390D, respectively.

  11 and 12, the gate applied voltage (D390B) remains at 3.2 V until the self-excited oscillation of the step-up transformer 350 starts (until the time indicated by reference sign t22). Increased for a while. When the gate voltage reaches the threshold voltage (t22), a current flows through the FET 340, but there is a delay until the feedback signal voltage level decreases from the output of the transformer 350. As a result, it takes time from when the gate voltage reaches the threshold voltage until the increase in the operational amplifier output starts to decrease (from time t22 to time t23). In FIG. 11, the time points t22 and t23 can be seen substantially simultaneously, but in FIG. 12, the waveform features are exaggerated to make the problem easier to understand. As a result, the gate voltage becomes higher than necessary, and an excessive inrush current (reference numeral Cr in FIG. 12) is generated when the circuit is started.

  In the present embodiment, as shown in FIG. 5, a 12V Zener diode 336 is provided, and the gate voltage is clamped to 6V by dividing by the resistors 331 and 333 of 56 kΩ, and as shown in FIGS. Thus, the necessary drain current (1A) is ensured and the gate voltage is prevented from becoming higher than necessary, thereby preventing an excessive current from flowing.

  For this reason, it is possible to increase the drain current after the rush current flows, increase the output of the step-up transformer, and increase the current output from the rectifier circuit 360.

  In the present embodiment, the Zener voltage is divided by the two 56 kΩ resistors 331 and 333, but the clamp voltage can be set to an arbitrary value by adjusting the resistance values of these resistors. Since the relationship between the gate-source voltage and the drain current differs depending on the type or model of the FET, the clamp voltage may be adjusted so that the drain current is optimal.

  As the FET 340, RCX120N25 manufactured by Rohm Co., Ltd. was used. The gate input capacitance is 1800 pF, and the capacitance of the capacitor 332 is 2680 pF, which is about 1.5 times the capacitance. The reason why the resistance values of the resistors 331 and 333 are 56 kΩ is that the gate voltage can be driven by capacitive coupling of the capacitor and the gate voltage can be feedback controlled using the operational amplifier 321. When the resistance values of the resistors 331 and 333 are lowered, the loss of the FET 340 increases and the temperature of the FET 340 rises. From this viewpoint, the resistance value is desirably 56 kΩ or more and 200 kΩ or less.

  The integrating circuit 320 increases the drain current until the feedback voltage becomes equal to the input voltage (0.3V) from the filter circuit 310. As a result, the high voltage output is increased in absolute value to -3000V and is stabilized in that state.

  The node 390C in FIG. 5 outputs −3000V, and a bias is applied to the secondary transfer roller 156, which is a load, through a 100 MΩ resistor 477 in the positive bias generator 280. Most of the output current flows through a 3 MΩ resistor 371 and a 3.6 kΩ resistor 372 (about 1 mA at −3000 V), and the current flowing through the roller 156 as a load is 30 μA or less.

  Next, the significance of providing a capacitor between the drain and source of the FET 340 will be described with reference to FIGS. FIGS. 14A and 14B show waveforms when −3000 V is output. D390B indicates the gate voltage of the FET 340, D390Dv indicates the potential of the drain of the FET 340, D390D indicates the drain current, and D390C indicates the voltage of the node 390C. The drain current (D390D) is a waveform obtained by measuring the current flowing through the node 390A using a current probe, and the D390C voltage at the node 390C was measured with a high voltage probe. This also applies to FIGS. 9 and 11.

  FIG. 14A shows a waveform of the present embodiment in which a 0.01 μF capacitor 345 is inserted, and FIG. 14B shows a waveform when the capacitor 345 is not inserted. As can be seen by comparing FIG. 14A and FIG. 14B, the insertion of the capacitor decreases the oscillation frequency from about 70 kHz to 64 kHz, and the current peak value from 920 mA to 850 mA. As a result, the surface temperature of the FET decreased by about 10 ° C. As the FET 340, a TO-220 package type was used. A heat sink for cooling the FET 340 was used.

  As the step-up transformer 350 of the negative bias circuit, the one having the configuration shown in FIGS. 7A and 7B was used as described above. The core is a EE16 core 501 of ferrite, and the auxiliary winding 351 is wound on the primary side for 5 turns, and the main winding 352 is wound for 30 turns. The secondary side was divided into four sections by partition plates 513b, 513c, and 513d, and 300 turns were used for a total of 1200 turns. A partition plate 513 a is also provided between the primary side 511 and the secondary side 512. The self-oscillation frequency of the circuit was about 90 kHz at -500 V output and about 64 kHz at -3000 V output. Since the load of the negative bias generator 270 is dominated by the current flowing through the 3 MΩ resistor 371, there is almost no variation in the current flowing through the load 156 via the 100 MΩ resistor 477.

  As described above, as the step-up transformer 450 of the positive bias generator 280, the one having the UU type ferrite core 521 shown in FIG. 8C is used, and the primary side main winding turn number 27T, the auxiliary winding is used. When the number of turns was 5T and the number of secondary turns was 2760T, a voltage applied to the load 156 of 2 kV and a current of 1 mA were obtained. Since 1 mA flows through the 3 MΩ resistor 371 at this time, the anode side potential of the diode 462 becomes −3 kV, and the boosted voltage of the boosting transformer 450 is 5 kV.

  As described above, a field effect transistor (FET) is used as a self-oscillation circuit of a transformer, and its driving is performed by a differentiation circuit, so that the self-oscillation operation and the drain current are well controlled, and an output of about 3 W at maximum It has become possible. Furthermore, by clamping the gate voltage with the voltage clamp circuit 335, it becomes possible to suppress the inrush current at the time of output start-up, and the output of the step-up transformer can be increased. For example, an output of −3000 V / 1 mA is obtained from the EE16 ferrite core. This is possible with an open type transformer (non-molded transformer).

  In addition, the maximum current value of the positive bias output is possible up to 1 mA, and in the intermediate transfer type image forming apparatus, a good transfer of a narrow medium can be performed even in a high temperature environment where the resistance value of the secondary transfer roller is low. It has become possible.

  Further, since the resistance value can be lowered due to the temperature rise of the secondary transfer roller, the fixing device and the secondary transfer roller nip can be brought close to each other, and the lateral feeding of a narrow medium (the direction of the shorter side of the medium is changed). (Feeding that matches the feeding direction) can also be handled, and it is possible to prevent wrinkles from coming to envelopes and the like that are prone to wrinkles when the vertical feed is used.

Embodiment 2. FIG.
FIG. 15 shows a transformer drive circuit of the negative bias generator in the second embodiment together with a step-up transformer. The second embodiment is generally the same as the first embodiment, but the configuration of the integrating circuit 320 is different. That is, in FIG. 15, an NPN bipolar transistor 611 is inserted in the integrating circuit 320, the output of the operational amplifier 321 is connected to the base of the transistor 611 via the resistor 324, and the collector of the transistor 611 is connected to the 24V power source 303. The emitter is connected to one end of a resistor 326 via a resistor 612, and the other end of the resistor 326 is connected to one end of an auxiliary winding 351.

  In the configuration shown in the figure, the base current of the NPN transistor 611 is controlled by the output of the operational amplifier 321, and the current of the NPN transistor 611 is applied to the gate of the FET 340 via the auxiliary winding 351, so that feedback control of the gate voltage is performed. Done. Except for the points described above, the configuration and operation of the second embodiment are the same as those in the example of FIG.

Embodiment 3 FIG.
FIG. 16 shows a transformer drive circuit of the negative bias generator in the third embodiment together with a step-up transformer. The third embodiment is generally the same as the first embodiment, but the configuration of the integrating circuit 320 is different. That is, in FIG. 16, a PNP bipolar transistor 621 is inserted in the integrating circuit 320, the output of the operational amplifier 321 is connected to the base of the transistor 621 through the resistor 324, and the emitter of the transistor 621 is 24V through the resistor 623. The collector is connected to one end of the resistor 326 via the resistor 622, and the other end of the resistor 326 is connected to one end of the auxiliary winding 351. A resistor 624 is connected between the base and emitter of the transistor 621.

  In the operational amplifier 321, the output (reference voltage) of the filter circuit 310 is connected to the non-inverting input terminal (+), and the feedback voltage from the output voltage conversion unit 370 is input to the inverting input terminal (−). When the feedback voltage (inverted input) is lower than the reference voltage (non-inverted input), the output of the operational amplifier 321 is increased, the base current of the transistor 621 is decreased, thereby the collector current is decreased, and the gate voltage of the FET 340 is decreased. Decreases. Conversely, in a state where the feedback voltage (inverted input) is higher than the reference voltage (non-inverted input), the output of the operational amplifier 321 decreases, the base current of the transistor 621 increases, and thereby the collector current also increases. The gate potential of the FET 340 rises via the auxiliary winding 351.

  In this way, the base current of the PNP transistor 621 is controlled by the output of the operational amplifier 321, and the current of the PNP transistor 621 is applied to the gate of the FET 340 via the auxiliary winding 351, thereby performing feedback control of the gate voltage. Is called. In the configuration of FIG. 16, since the transistor 621 has a reverse polarity with respect to the transistor 611 of FIG. 15, the feedback input of the operational amplifier 321 is also reversed. Except for the above, the configuration and operation of the third embodiment are the same as those in the example of FIG.

Embodiment 4 FIG.
FIG. 17 shows a transformer drive circuit of the negative bias generator in the fourth embodiment together with a step-up transformer. The fourth embodiment is generally the same as the first embodiment, but the arrangement of the voltage clamp circuit 335 is different. In FIG. 17, a Zener diode 631 having a Zener voltage of 6.2 V is connected between the gate of the FET 340 and the ground node. That is, in the example of FIG. 5, the Zener diode 336 is connected in parallel to the series circuit of the resistors 331 and 333, but in the example of FIG. 17, the Zener diode 631 is connected in parallel to the resistor 333. Therefore, the gate voltage of the FET 340 is clamped not by a value obtained by dividing the Zener voltage but by the Zener voltage itself.

FIG. 18 shows a block configuration of the negative bias generator 270 together with the power supplies 303 and 303 when the circuit configuration of FIG. 17 is used. The arrangement of the voltage clamp circuit 335 and the differentiation circuit 330 is reversed.
Except for the points described above, the configuration and operation of the fourth embodiment are the same as those in the examples of FIGS.

Embodiment 5 FIG.
FIG. 19 shows a transformer driving circuit of the negative bias generator in the fifth embodiment together with a step-up transformer. The fifth embodiment is generally the same as the fourth embodiment, but the configuration of the voltage clamp circuit 335 is different. In FIG. 19, the voltage clamp circuit 335 of FIG. 17 is configured by a series connection of a plurality of diodes. In the illustrated example, this series connection circuit is composed of ten diodes 640-649. Each of the diodes 640 to 649 has a forward drop voltage VF of 0.6 V, and a clamp voltage of 6 V is realized by connecting 10 diodes in series. The number of diodes is 10 when the forward drop voltage VF is 0.6 V, but may be increased or decreased according to the characteristics of the diode and the value of the required clamp voltage.

  When the circuit configuration of FIG. 19 is used, the block configuration of the negative bias generator 270 is the same as that of FIG. 18, and the arrangement of the voltage clamp circuit 335 and the differentiation circuit 330 is reversed.

  The modifications described with reference to FIGS. 15 to 19 can also be applied to the transformer drive circuit of the positive bias generator 280. In the second to fifth embodiments, the same effect as in the first embodiment can be obtained.

Embodiment 6 FIG.
FIG. 20 shows a transformer drive circuit of the negative bias generator in the sixth embodiment together with a step-up transformer. The sixth embodiment is generally the same as the first embodiment, but the configuration of the voltage clamp circuit is different.

  In FIG. 5, one end of the resistor 333 is connected to the gate of the FET 340 and the other end is grounded. However, in FIG. 20, one end of the resistor circuit 654 formed by connecting the thermistor 651 and the 51 kΩ resistor 333 in series is the FET 340. It is connected to the gate and the other end is grounded. In comparison with FIG. 20, in FIG. 5, it can be seen that one end of a resistor circuit composed of only the resistor 333 is connected to the gate of the FET 340 and the other end is grounded. As the thermistor 651, for example, a thermistor having a negative characteristic whose resistance value decreases as shown in FIGS. In the illustrated example, the resistance value is 5 kΩ at a temperature of 25 ° C.

  The thermistor 651 is provided to compensate for the drain current change due to the temperature change of the FET 340, and is arranged so that the temperature of the thermistor 651 changes according to the temperature of the FET 340.

  For example, when using a surface mount chip thermistor 651, as shown in FIGS. 23A and 23B, the vicinity of the ground pattern 658 on the solder surface 657 connected to the heat sink 655 on the component surface 656. The thermistor 651 is disposed on the FET 340 and the FET 340 receives heat generated by driving.

  As shown in FIG. 23C, when the heat sink 655 is erected with respect to the substrate 659 and an axial type thermistor 651 is used, it is disposed near the heat sink 655 and receives heat. The configuration.

  In the first embodiment, the Zener voltage of the 12V Zener diode 336 is divided by 56 kΩ resistors 331 and 333 to obtain a 6V clamp voltage. In the sixth embodiment, the Zener voltage of the 12V Zener diode 336 is The voltage is divided by a resistor 331 of 56 kΩ, a resistor circuit 654 including a resistor 333 of 51 kΩ and a thermistor 651 (5 kΩ at 25 ° C.), and the gate is clamped by the divided voltage. As a result, at 25 ° C., the gate is clamped at 6V. As shown in the table of FIG. 21, the clamp voltage at other temperatures increases as the temperature decreases.

  The relationship between the gate-source voltage Vgs of the FET 340 and the drain current Id is as shown in FIG. 24, and the current decreases as the temperature decreases. This makes it possible to compensate for the lack of current during startup at low temperatures. By using a thermistor, when starting at a low temperature, the clamp voltage with respect to the gate-source voltage is increased to compensate for the current shortage, and at the same time, after the FET is warmed by driving the FET, the clamp voltage is lowered to reduce the excess. The gate voltage is controlled so that no current flows.

  In the sixth embodiment, the same effect as in the first embodiment can be obtained. Further, the output voltage of the auxiliary winding 651 is clamped to a predetermined voltage by the voltage clamp circuit 335, and further, the voltage is divided by the resistor circuit 654 including the resistor 331 and the thermistor 651 to compensate the gate applied voltage for the temperature characteristics of the FET. The maximum output of the negative bias can be obtained from the start of the low temperature state in the environment of 10 ° C. or less, while the overcurrent can be prevented from flowing through the FET even at a high temperature. Operation is possible over a wide temperature range.

  In the above example, a series circuit of the resistor 333 and the negative thermistor 651 is connected between the gate of the FET 340 and the ground node, but instead, the gate of the FET 340 and the other end of the auxiliary winding 351 (the differential circuit 330). A series circuit of a positive temperature coefficient thermistor and a resistor 331 may be connected between the input terminals), and only the resistor 333 may be connected between the gate of the FET 340 and the ground node. Further, a series circuit of a positive temperature coefficient thermistor and a resistor 331 is connected between the gate of the FET 340 and the other end of the auxiliary winding 351 (input terminal of the differentiation circuit 330), and a resistor 333 is connected between the gate of the FET 340 and the ground node. And a series circuit of a thermistor 651 having a negative characteristic may be connected.

  In short, the first resistance circuit is connected between the gate of the FET 340 and the other end of the auxiliary winding 351 (the input terminal of the differentiation circuit 330), and the second resistance circuit is connected between the gate of the FET 340 and the ground node. The input voltage of the differentiation circuit 330 may be divided by the first resistance circuit and the second resistance circuit and applied to the gate of the FET 340. The configuration of FIG. 5 can be regarded as a first resistor circuit configured by only the resistor 331 in the first resistor circuit.

  The modifications described with reference to the second and third embodiments with respect to the first embodiment can be added to the sixth embodiment. In the second to sixth embodiments, the modification of the transformer drive circuit of the first embodiment has been described with respect to the negative bias generator, but the same modification can be applied to the transformer drive circuit of the positive bias generator.

  As described above, the negative bias is applied when no paper is present in the secondary transfer nip portion. However, the high-voltage power supply device of the present invention is also used for cleaning the toner adhering to the secondary transfer roller. Can do. In the case of cleaning, for example, a positive bias and a negative bias are alternately applied every rotation cycle of the transfer roller 156 after the completion of the secondary transfer, and the toner attached to the secondary transfer roller 156 is reversely transferred to the transfer belt 141. The operation of the secondary transfer bias generator 264 in this case is the same as described above.

  Although the case where the high-voltage power supply device of the present invention is applied to an intermediate transfer type color image forming apparatus has been described above, the present invention can also be applied to a direct transfer color image forming apparatus equipped with a high-voltage power supply. The present invention can also be applied to an image forming apparatus.

  220 Printer engine control unit, 260 microcomputer, 310, 410 filter circuit, 320, 420 integration circuit, 321, 421 operational amplifier, 330, 430 differentiation circuit, 335, 435 voltage clamp circuit, 336, 436, 631 Zener diode, 340, 440 FET, 350, 450 step-up transformer, 360, 460 rectifier circuit, 370, 470 output voltage converter.

Claims (10)

A high voltage generator for applying a DC voltage to a load,
An integrating circuit including an operational amplifier;
The primary side has a main winding and an auxiliary winding, the secondary side has a secondary winding, one end of the main winding is connected to a DC power source, and one end of the auxiliary winding is the integration circuit A transformer connected to the output of
An FET having a drain connected to the other end of the main winding;
A differentiating circuit for coupling the other end of the auxiliary winding to the gate of the FET;
A rectifier circuit that rectifies the output of the secondary winding of the transformer to generate a high voltage output and supplies the output to the load;
An output voltage converter that steps down the high voltage output of the rectifier circuit and outputs it as a feedback voltage;
A reference voltage generator that outputs a voltage having a value equal to the value of the feedback voltage when a voltage applied to the load is equal to a target voltage, as a reference voltage;
The integration circuit outputs a voltage corresponding to the difference between the reference voltage and the feedback voltage,
The output of the integration circuit is supplied to the gate through the auxiliary winding and the differentiation circuit, so that feedback control is performed so that the voltage applied to the load matches the target voltage,
The differentiation circuit is:
A first capacitor connecting the other end of the auxiliary winding and the gate;
A first resistance circuit connected in parallel to the first capacitor;
A second resistance circuit connected between the gate and a ground node;
When the FET is turned on and a current flows from the DC power source to the main winding, a voltage induced in the auxiliary winding is applied to the gate through the differentiation circuit, thereby Causing self-excited oscillation of the transformer,
A high voltage generator, further comprising: a voltage clamp circuit that limits a voltage between the gate and the ground node to a predetermined upper limit value or less. The voltage clamp circuit is:
A zener diode connecting the other end of the auxiliary winding and the ground node;
2. The high voltage generator according to claim 1, wherein the gate voltage is limited to a value obtained by dividing a Zener voltage of the Zener diode by the first resistor circuit and the second resistor circuit. 3. . The voltage clamp circuit is:
A Zener diode connecting the gate and the ground node;
The high voltage generator according to claim 1, wherein the gate voltage is limited to be equal to or lower than a Zener voltage of the Zener diode. The voltage clamp circuit includes one or more diodes connected in series with each other;
The high-voltage generator according to claim 1, wherein the voltage of the gate is limited to be equal to or less than a total forward voltage drop of the one or more diodes connected in series. The second resistance circuit includes a thermistor and a resistance whose resistance value decreases as the temperature increases,
The voltage dividing ratio between the first resistor circuit and the second resistor circuit changes according to the temperature, and thereby the upper limit value of the voltage applied to the gate changes. The high voltage generator described.   The high voltage generator according to claim 5, wherein the thermistor is arranged so that the temperature of the thermistor increases as the temperature of the FET increases. A second capacitor connected between the drain and source of the FET;
7. The high voltage generator according to claim 1, wherein a frequency of the self-excited oscillation is adjusted by the second capacitor.   An image forming apparatus comprising the high voltage generator according to claim 1. A first high voltage generator that generates a negative high voltage;
A second high voltage generator that generates a positive high voltage,
Each of the first high voltage generator and the second high voltage generator includes the high voltage generator according to any one of claims 1 to 7,
The second high voltage generator further includes a negative voltage output resistor connected between a negative electrode output terminal and a positive electrode output terminal of the rectifier circuit constituting the second high voltage generator;
A high voltage power supply apparatus, wherein a negative high voltage output from the first high voltage generator is supplied to a load via the negative voltage output resistor.   An image forming apparatus comprising the high-voltage power supply device according to claim 9.

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