JP2015001832A - Information processor and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generation technique which is capable of reducing a peak current in initializing operations of a plurality of circuit blocks and of suppressing noise.SOLUTION: An information processor includes: clock generation means which generates a plurality of kinds of clocks having edges trued up, from an input clock; delay value determination means which determines a plurality of kinds of delay values for the plurality of kinds of clocks; delay setting means which subjects the plurality of kinds of clocks to delay processing respectively on the basis of the delay values determined by the delay value determination means; control signal generation means which generates a control signal which controls whether the plurality of kinds of clocks delayed by the delay setting means should be supplied during the initializing operation of a corresponding circuit block; and clock control means which switches a clock to be supplied to the corresponding circuit, on the basis of the control signal.

Description

  The present invention relates to a technique for generating a clock to be supplied to a circuit block, in particular, a clock to be supplied to a plurality of circuit blocks, each of which can control supply and cutoff of a power supply voltage.

  With the miniaturization of elements due to advances in semiconductor manufacturing technology, information processing devices such as LSI (Large Scale Integration) have been scaled up with the evolution of semiconductor processes, and the number of transistors mounted has increased dramatically. . Further, information processing apparatuses such as LSIs are required to improve performance such as high-speed operation and low power consumption. Processing performance can be improved by increasing the number of arithmetic elements such as a CPU (Central Processing Unit), a DSP (Digital Signal Processor), an arithmetic unit or an arithmetic unit that are generally installed in an information processing apparatus. However, increasing the number of computing elements mounted on the information processing apparatus increases power consumption.

  The power consumption in the information processing apparatus includes dynamic power consumed by functional operation and static power consumed only by supplying power to the mounted transistor. Dynamic power is power consumed when a functional operation is performed in synchronization with a system clock, and current is consumed in synchronization with a clock edge. Static power is power consumed for charge and leakage current charged in the parasitic capacitance of the transistor. In order to reduce the leakage current, it is effective to use a circuit structure in which supply and interruption of the power supply voltage can be controlled. Therefore, the power consumption can be reduced by increasing the number of circuit blocks that can be controlled in the power supply mounted on the LSI.

  By the way, when a circuit block capable of controlling the power supply is used for processing, the initialization operation of the target circuit block is executed when the power supply returns from the power-off state. At this time, since the circuit operates at a time in synchronization with the clock, a larger current flows than in the normal operation, and in particular, a large amount of current instantaneously flows at the clock edge used in the initialization operation. Further, in an information processing apparatus in which a large number of arithmetic elements are mounted on an LSI, circuit blocks that can be controlled by power supplies are configured in various other forms, and therefore an initialization operation also occurs at random. For this reason, when a large number of circuit blocks configured in the information processing apparatus start the initialization operation at the same time, a large current instantaneously flows in synchronization with the initialization operation clock, and noise is generated in the signal. .

  Therefore, Patent Document 1 proposes a technique for intentionally shifting the start timing of the initialization operation for each circuit block to suppress the peak current in order to suppress the instantaneous current during the initialization operation in the information processing apparatus. Has been. Patent Document 2 proposes a technique for suppressing peak power by shifting a certain amount of clock timing within a range that does not impede data transfer during operation of an information processing apparatus.

JP 2011-248579 A JP 2011-034470 A

However, in the technique described in Patent Document 1, when an initialization operation clock used for an initialization operation is supplied to each circuit block, it is generated by shifting in units of cycles. For this reason, the time required for the initialization operation in the entire system is increased, and the processing performance is deteriorated. In the technique described in Patent Document 2, the peak power is suppressed by shifting a fixed amount of clock timing within a range that does not hinder data transfer during operation. Therefore, delay adjustment that enables data transfer must be performed everywhere between circuit blocks, which takes time and effort. In addition, since the normal operation clock is restricted, the initialization operation clock cannot be adjusted at any timing.
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a clock generation technique capable of reducing a peak current and suppressing noise in an initialization operation of a plurality of circuit blocks.

  In order to solve the above-described problems, an information processing apparatus according to the present invention has the following configuration. That is, the information processing apparatus includes a clock generation unit that generates a plurality of types of clocks having edges aligned from an input clock, a delay value determination unit that determines a plurality of types of delay values for the plurality of types of clocks, and the delay value determination A delay setting means for performing a delay process on each of the plurality of types of clocks based on the delay value determined by the means, and the plurality of types of clocks delayed by the delay setting means in an initial stage of a corresponding circuit block Control signal generating means for generating a control signal for controlling whether or not to supply during the merging operation, and clock control means for switching the clock supplied to the corresponding circuit block based on the control signal.

  According to the present invention, it is possible to provide a clock generation technique capable of reducing a peak current and suppressing noise in an initialization operation of a plurality of circuit blocks.

It is a figure which shows the structural example of the information processing apparatus which concerns on 1st Embodiment. It is an operation | movement flowchart of the information processing apparatus in 1st Embodiment. It is a figure which shows the structural example of a clock generation part. It is a figure which shows the example of the delay value setting of the clock for initialization operation | movement. It is an operation | movement flowchart of a delay value determination part. It is a figure which shows the structural example of a delay setting part. It is a figure explaining the start timing of each clock in initialization operation | movement. It is a figure which shows the example of the allocation of the clock with respect to each circuit block. It is a figure which shows the example of a timing of the clock before and behind delay addition. It is a block diagram which shows the structure of the whole processing apparatus. It is a figure which shows the structural example of the information processing apparatus which concerns on 2nd Embodiment. It is a figure which shows the structural example of a clock generation part. It is a figure which shows the structural example of a delay setting part. It is a figure which shows the structure of the circuit which can control power supply exemplarily.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the scope of the present invention.

(First embodiment)
An information processing apparatus 100 having a plurality of circuit blocks will be described as an example as a first embodiment of the information processing apparatus according to the present invention.

<Device configuration>
FIG. 1 is a diagram illustrating a configuration example of an information processing apparatus 100 according to the first embodiment. Here, the information processing apparatus 100 includes a clock generation unit 101, a delay value determination unit 102, a delay setting unit 103, a control signal generation unit 104, a clock control unit 105, an OSC 106, and four circuit blocks A107 to D110.

  The oscillator (OSC) 106 is a functional unit that generates a clock that serves as a reference for signal processing. Specifically, a reference clock CLK for initialization operation and a normal operation clock CLK4 are generated.

  The clock generation unit 101 generates a plurality of types of clocks (herein, CLK0, CLK1, CLK2, and CLK3) that have the same edges used during the initialization operation from the reference clock CLK for the initialization operation. The clock generation unit 101 supplies the generated multiple types of clocks with aligned edges to the delay setting unit 103. In addition, the clock generation unit 101 transmits the clock information 111 to the delay value determination unit 102. The clock information 111 includes information on the cycle (including frequency division) generated by the clock generation unit and the number of clocks.

  The control signal generation unit 104 generates a control signal to be transmitted to the clock control unit 105 during the initialization operation. In the initialization operation, in order to initialize a target circuit block, a reset signal is input from the outside (for example, a CPU 1001 described later) and the initialization is executed. For example, reset signals (RESET_A, RESET_B, RESET_C, and RESET_D) corresponding to the circuit blocks A107, circuit block B108, circuit block C109, and circuit block D110 are input. The control signal generation unit 104 generates a control signal for controlling a clock at initialization based on the reset signal input to each circuit block, and transmits the control signal to the clock control unit 105. In addition, the control signal generation unit 104 holds information on a circuit block that is a target of the initialization operation, and transmits information 113 on the target circuit block to the delay value determination unit 102.

  The initialization operation described here is executed not only when the information processing apparatus 100 is switched from the power-off state to the power supply state, such as when the system is started, but also when the processing content of the information processing apparatus 100 is switched. . For example, the case where the power supply to the power controllable circuit block included in the information processing apparatus 100 returns from the power cut-off state to the power supply state is also included.

  FIG. 14 is a diagram exemplarily showing a configuration of a circuit capable of controlling the power supply. For example, the circuit 1401 capable of controlling the supply and cutoff of the power supply voltage is a part of an LSI circuit configured on a silicon substrate. The circuit 1401 is configured to include a circuit block 1402 (details inside the block are omitted) constituted by a logic circuit, and a power supply control unit 1403 that controls the power supply. Based on the value of the input signal 1404, the power control unit 1403 determines whether to supply power to the circuit block 1402 or to turn off the power. The circuit block 1402 operates in the power supply state. Here, it is assumed that the circuit block A 107, the circuit block B 108, the circuit block C 109, and the circuit block D 110 each include the configuration shown in FIG.

  The delay value determination unit 102 is a functional unit that generates delay value information 112 to be set for each clock generated by the clock generation unit 101 and transmits the delay value information 112 to the delay setting unit 103. Although details will be described later, the delay value determination unit 102 sets delay value information to be set for each clock based on the clock information 111 acquired from the clock generation unit 101 and the circuit block information 113 acquired from the control signal generation unit 104. 112 is generated. In addition, the delay value determination unit 102 is configured to determine the number of clocks according to the circuit block information 113 and transmit it to the control signal generation unit 104 as clock allocation information 114.

  The delay setting unit 103 is a functional unit that adds a delay to each clock based on the delay information determined by the delay value determining unit 102. Then, the delay setting unit 103 supplies the clock with the delay added to the control signal generation unit 104 and the clock control unit 105.

  Based on the control signal transmitted from the control signal generation unit 104, the clock control unit 105 switches the initialization operation clock (CLK0_D, CLK1_D, CLK2_D, CLK3_D) and the normal operation clock (CLK4) to each circuit block. Supply. Here, the clock CLK_A supplied to the circuit block A 107 is controlled by the control signal SL_A, and the clock CLK_B supplied to the circuit block B 108 is controlled by the control signal SL_B. Similarly, the clock CLK_C supplied to the circuit block C109 is controlled by the control signal SL_C, and the clock CLK_D supplied to the circuit block D110 is controlled by the control signal SL_D.

  FIG. 10 is a block diagram illustrating a configuration of the entire processing apparatus including the information processing apparatus 100. The CPU 1001 is a functional unit that controls the entire processing apparatus. A ROM (Read Only Memory) 1002 stores a boot program and the like. A RAM (Random Access Memory) 1003 is a functional unit used as a work area of the CPU 1001, for example. A hard disk drive (HDD) 1004 is an OS (Operating System), an application for creating circuit configuration information, and a functional unit for storing various data.

  The keyboard 1005 and the mouse 1006 function as a user interface that receives an instruction from the user. The display control unit 1007 incorporates a video memory and a display controller. The display device 1008 is a functional unit that receives a video signal from the display control unit 1007 and displays various types of information. An interface (I / F) 1009 is a functional unit for connecting to various external devices. For example, the I / F 1009 can write processing information created by the processing device in the external memory 1010 by connecting the external memory 1010 shown in FIG.

  When the processing apparatus shown in FIG. 10 is turned on, the CPU 1001 executes the boot program stored in the ROM 1002 and loads the OS stored in the HDD 1004 into the RAM 1003. After that, by starting an application that creates processing information, it functions as a device that performs predetermined processing. Further, when the system is activated, a reset signal is transmitted to the information processing apparatus 100, and the information processing apparatus 100 is changed from the power-off state to the power supply state, and the initialization operation is executed.

  FIG. 3 is a diagram illustrating a configuration example of the clock generation unit in the first embodiment. FIG. 3A is a diagram showing a configuration in the case where clocks for initialization operation supplied to different circuit blocks (circuit block A107 to circuit block D110) are supplied in the same cycle and in the same phase. In this case, the clock generator 101 outputs four clock signals (CLK0 to CLK3) with the same period and the same phase. On the other hand, FIG. 3B is a diagram illustrating a configuration in which a divided clock is used as an initialization operation clock supplied to different circuit blocks (circuit block A107 to circuit block D110). In this case, the clock generator 101 outputs the original clock CLK0 and three clocks (CLK1, CLK2, CLK3) divided by the frequency divider 302.

  FIG. 4 is a diagram illustrating an example of setting a delay value of the initialization operation clock according to the first embodiment. FIG. 4A shows an example of delay value setting in the case of supplying with the same period and the same phase. On the other hand, FIG. 4B is an example of setting a delay value when a divided clock is used.

The delay value setting 401 indicates that an initialization operation clock is set in which the delay value of CLK1 is 1/4 cycle, the delay value of CLK2 is 1/8 cycle, and the delay value of CLK3 is 1/16 cycle. That is, 1/2 ^N (N is an integer of 2 or more) of the clock period of CLK0 is set as the delay value with respect to CLK0. By setting a different delay value for each clock, the phase of the initialization operation clock can be shifted.

  On the other hand, the delay value setting 402 indicates a case where the phase is shifted every 1/8 period for each clock, and the delay value setting 403 indicates a case where the phase is shifted every 1/16 period for each clock.

  FIG. 9 is a diagram illustrating an example of clock timings before and after adding a delay. FIG. 9A shows four clock signals (CLK 0, CLK 1, CLK 2, CLK 3) that are input to the delay setting unit 103 and have the same period and the same phase. FIG. 9B shows four clock signals (CLK0_D, CLK1_D, CLK2_D, CLK3_D) output from the delay setting unit 103, each having a different delay amount (phase).

  For example, when the input of the delay setting unit 103 is generated at the timing t1 in FIG. 9A, the output signal of the delay setting unit 103 is as shown in FIG. 9B. CLK1_D is a clock in which the phase of CLK0 is shifted by 1/4 period at the timing t1, CLK2_D is a clock in which 1/8 period is shifted, and CLK3_D is a clock in which 1/16 period is shifted. In this case, since the clocks have the same period, the rising edges of the other input clocks (CLK0, CLK2, CLK3) can be shifted by delaying the rising edge of CLK1 to CLK1_D. Since the input clock has the same period, the falling edge can be shifted at the same time. Here, the clock phase is adjusted by 1 / (power of 2), but the phase may be shifted by a value other than the above setting if the rising edge and falling edge do not overlap.

  However, for example, when CLK1_D is generated by shifting CLK1 by 1/4 period and CLK3_D is generated by shifting CLK3 by 3/4 period, the clock of CLK1_D and the clock of CLK3_D are in opposite phases. Therefore, the falling edge of CLK1_D and the rising edge of CLK3_D overlap, and the rising edge of CLK1_D and the falling edge of CLK3_D overlap. For this reason, it is necessary to separately set in consideration of avoiding the occurrence of overlap.

Further, in the delay value setting 404 of FIG. 4B, the delay value of CLK0 is 1/4 period of CLK0, CLK1 is 1/4 period of CLK1, delay value of CLK2 is 1/4 period of CLK2, and delay of CLK3. It shows that the value is set in a quarter cycle of CLK3. Similarly, the delay value setting 405 shows an example in which the phase is shifted in 1/8 period of each clock. That is, 1/2 ^N (N is an integer of 2 or more) of each clock cycle is set as the delay value.

  FIG. 9C illustrates four clock signals (CLK0 and divided CLK1, CLK2, and CLK3) input to the delay setting unit 103. FIG. 9D shows four clock signals (CLK0_D, CLK1_D, CLK2_D, and CLK3_D) output from the delay setting unit 103, each having a different delay amount (phase).

  For example, when the input of the delay setting unit 103 is generated at the timing t1 in FIG. 9C, the clock cycle of each clock signal is different because the divided clock is used. Here, assuming that the period of CLK0 is T, the period of CLK1 is 2T, the period of CLK2 is 4T, and the period of CLK3 is 8T. Here, for example, when CLK1 is shifted by 1/4 period and CLK3 is shifted by 1/16 period as in the delay value setting 401, the rising edges of the clocks overlap each other. Therefore, when a divided clock is used, as shown in FIG. 4B, a fixed delay ratio is set for each clock so that no overlap occurs. That is, CLK0_D is generated by shifting CLK0 by 1/4 cycle, CLK1_D by shifting CLK1 by 1/4 cycle, CLK2_D by shifting CLK2 by 1/4 cycle, and CLK3_D by shifting CLK3 by 1/4 cycle.

  As described above, the clock added with a delay by the delay setting unit 103 is assigned as a clock of each circuit block (here, circuit blocks A to D) via the clock control unit 105.

<Operation of the device>
FIG. 2 is a flowchart illustrating an operation example of the information processing apparatus according to the first embodiment. FIG. 7 is a diagram for explaining the start timing of each clock in the initialization operation in the first embodiment.

  7 shows a normal operation clock (CLK4) and an initialization operation clock (CLK) which are clocks output from the OSC. Here, the initialization operation clock is described as a clock having a frequency ½ that of the normal operation clock (twice the period), but it may be a clock of other frequency or the same. Good. Next, clocks (CLK0, CLK1, CLK2, CLK3) output by the clock generation unit 101 based on CLK are shown. Furthermore, clocks (CLK0_D, CLK1_D, CLK2_D, CLK3_D) output by the delay setting unit 103 are shown.

  In addition, the input timing of the reset signals (RESET_A, RESET_B, RESET_C, RESET_D) corresponding to each circuit block of the circuit blocks A to D is shown. And the timing of the control signals (SL_A, SL_B, SL_C, SL_D) generated by the control signal generation unit 104 based on the reset signal is shown.

  7 shows clocks (CLK_A, CLK_B, CLK_C, CLK_D) output by the clock control unit 105. Note that CLK_A corresponds to a signal obtained by switching the output clock from CLK4 to CLK0_D at the rise timing of SL_A. Similarly, CLK_B corresponds to a signal in which the output clock is switched from CLK4 to CLK1_D at the rise timing of SL_B. CLK_C corresponds to a signal obtained by switching the output clock from CLK4 to CLK2_D at the rise timing of SL_C. CLK_D corresponds to a signal obtained by switching the output clock from CLK4 to CLK3_D at the rise timing of SL_D.

  In step S <b> 201, the information processing apparatus 100 inputs a reference clock (CLK) used for processing from the OSC 106 to the clock generation unit 101.

  In step S202, the clock generation unit 101 generates a plurality of types of clocks with aligned edges from the reference clock input in step S201. That is, as described above, the clock generation unit 101 generates four initialization operation clocks (CLK0, CLK1, CLK2, and CLK3). The following description corresponds to the case where the frequency-divided clock shown in FIG.

  In step S203, the delay value determination unit 102 acquires the clock information 111 at the time of the initialization operation. Then, the delay value determination unit 102 acquires information on a plurality of types of clocks with the aligned edges generated in S202 from the clock generation unit 101. The clock information 111 includes information on the number of clocks that can be used as the initialization operation clock, the clock cycle, and the synchronization relationship. Here, information on the divided clock of CLK with four clocks is acquired.

  In step S204, the delay value determination unit 102 acquires circuit block information 113 at the time of initialization operation. Then, the delay value determination unit 102 acquires information on the number of circuit blocks that are the targets of the initialization operation from the control signal generation unit 104. In particular, when a circuit block that can control the supply and interruption of the power supply voltage is included, the circuit block information is acquired again when the processing content is switched. This is because the target circuit block differs depending on the processing contents when the power supply is resumed from the power-off state.

  In step S205, the delay value determination unit 102 determines a delay value for each initialization operation clock. The determination of the delay value will be described in detail with reference to FIG.

  FIG. 5 is a flowchart illustrating an operation example of the delay value determination unit in the first embodiment.

  In step S501, the delay value determining unit 102 compares the number of clocks for initialization operation and the number of acquired circuit blocks from the clock information acquired in S203 and the circuit block information acquired in S204.

  In step S502, the delay value determination unit 102 determines whether the number of initialization operation clocks is equal to the number of circuit blocks as a result of the comparison in step S501. If the number of clocks for initialization operation is equal to the number of circuit blocks, the process proceeds to S505. On the other hand, if they are not equal, the process proceeds to S503. Here, since the case where the number of clocks for initialization and the number of circuit blocks is equal as shown in FIG. 1 will be described, the process proceeds to S505.

  In step S503, the delay value determination unit 102 determines the magnitude relationship between the number of initialization operation clocks and the number of circuit blocks. If the number of clocks for initialization operation is larger than the number of circuit blocks, the process proceeds to S505. On the other hand, when the number of clocks for initialization operation is smaller than the number of circuit blocks, the process proceeds to S504. Here, the determination result is transmitted to the control signal generation unit 104 as the clock allocation information 114.

  In step S504, the control signal generation unit 104 performs circuit block group setting from circuit block information acquired in advance. That is, since the number of initialization operation clocks that can be set by the clock control unit 105 is smaller than the number of circuit blocks, another initialization operation clock is not assigned to all circuit blocks, and grouping is performed. It is. Here, for example, the priority of the group to which the clock for initialization operation is assigned with the highest priority and the group to be assigned next are determined.

  FIG. 8 is a diagram illustrating an example of clock allocation to each circuit block. For example, when there are five circuit blocks to be initialized and the number of clocks is four, as shown in FIG. 8, the group that performs the initialization operation with the highest priority is the circuit block 1, the circuit block 2, the circuit block 3, The circuit block 4 is assigned, and the circuit block 5 is assigned to the next group.

  In this case, the processing of the group 1 assigned with priority first is performed, and the processing of the group 2 assigned next is performed after the processing of the circuit block of the group 1 is completed. At this time, the end of the process may be detected in the group unit process and the next process may be started, or the end of the process may be detected in the circuit block unit constituting the group and the next process may be started. However, if a sufficient number of initialization operation clocks can be prepared in advance, assignment of circuit blocks to be initialized becomes easy, and group assignment becomes unnecessary.

  The group may be determined based on gate scale information of each circuit block and period information necessary for resetting. For example, a block with a large gate scale can be assigned with the highest priority, or a circuit block with a short reset period can be assigned with the highest priority. However, the circuit block designated by the user may be preferentially assigned, or the assignment may be determined by combining other circuit block operation states and the plurality of information described above.

  In step S505, the control signal generation unit 104 assigns an initialization operation clock to the group set in S504. Here, since four circuit blocks are assigned to group 1, it is determined which of the four initialization operation clocks is assigned to each circuit block.

  Since the number of circuit blocks in the group is four or less, any one of the delay values of the delay value settings 401 to 403 in FIG. 4A and the delay value settings 404 to 405 in FIG. Assigned to. In the case of clocks having the same period and phase, the delay value setting of FIG. 4A is used, and in the case of using the divided clock, the delay value setting of FIG. 4B is used. Become. As in S504, the clocks may be allocated by changing the priority order based on the gate scale information of each circuit block and the period information necessary for resetting.

  In step S506, the delay setting unit 103 selects one of the initialization operation clocks. Here, one of the clocks CLK0, CLK1, CLK2, and CLK3 is selected.

  In step S507, the delay setting unit 103 acquires a delay value for the clock selected in S506. For example, a delay value for CLK0 is acquired.

  In step S508, the delay setting unit 103 determines whether delay values have been acquired for all the clocks supplied to the circuit block that is the target of the initialization operation. If the delay values of all the clocks have not been acquired, the process proceeds to S506, and the delay value of the next target clock is acquired. Then, when the acquisition of delay values for all clocks is completed, the operation process is terminated.

  In step S206, the delay setting unit 103 adds a delay to each clock based on the delay value acquired in S205. For example, when the above-mentioned frequency-divided clock is used, a delay of 1/8 period of each clock is added to CLK0, CLK1, CLK2, and CLK3 as in delay value setting 405 in FIG. To do.

  The delay value determining unit 102 determines the number of clocks for initialization operation from the clock allocation information 114. When the number of circuit blocks to be processed is large, the control signal generating unit 104 determines a group. When the assignment of the initialization operation clock to each circuit block is completed, it is possible to switch to the initialization operation clock.

  Even when a new initialization operation is required, a process for assigning a new initialization operation clock can be bypassed if the number of circuit blocks is the same before and after the initialization operation. In that case, the initialization operation clock of the circuit block for which processing has been completed may be assigned to the initialization operation clock of the new circuit block.

  FIG. 6 is a diagram illustrating a configuration example of the delay setting unit in the first embodiment. The delay value information 112 acquired from the delay value determining unit 102 is supplied to the delay adding unit 601, the delay adding unit 602, the delay adding unit 603, and the delay adding unit 604 for each clock.

  For example, as shown in the enlarged view, the delay adding unit 602 can shift the specific phase by a circuit configuration that monitors the output clock and compensates for the wiring delay, such as a delay lock loop (DLL) 605. Moreover, the structure which arranges one or more delay elements in series, and selects arbitrary delay values with a switch (switching means) may be sufficient. The other delay adding unit 601, delay adding unit 603, and delay adding unit 604 have the same configuration.

  Based on the delay value information 112 acquired from the delay value determining unit 102, the delay adding unit 601 outputs CLK0_D obtained by delaying CLK0 by 1/8 period of CLK0. Similarly, the delay adding unit 602 outputs CLK1_D obtained by delaying CLK1 by 1/8 period of CLK1 based on the delay value information 112 acquired from the delay value determining unit 102. Based on the delay value information 112 acquired from the delay value determining unit 102, the delay adding unit 603 outputs CLK2_D obtained by delaying CLK2 by 1/8 period of CLK2. Based on the delay value information 112 acquired from the delay value determining unit 102, the delay adding unit 604 outputs CLK3_D obtained by delaying CLK3 by 1/8 period of CLK3.

  Here, as shown in FIG. 7, CLK0 is CLK0_D shifted to the timing of T21, and CLK1 is CLK1_D shifted to the timing of T22. CLK2 is CLK2_D shifted to the timing of T23, and CLK3 is CLK3_D shifted to the timing of T24.

  In step S207, the control signal generation unit 104 generates a control signal for initialization based on a reset signal for each circuit block. That is, when receiving the reset signals (RESET_A, RESET_B, RESET_C, and RESET_D), the control signal generation unit 104 generates a control signal from the number of clocks necessary for the initialization operation of the target circuit block.

  A control signal SL_A is generated based on the reset signal RESET_A of the circuit block A107, and a control signal SL_B is generated based on the reset signal RESET_B of the circuit block B108. Similarly, the control signal SL_C is generated based on the reset signal RESET_C of the circuit block C109, and the control signal SL_D is generated based on the reset signal RESET_D of the circuit block D110. The control signal is controlled to become inactive when the number of clocks necessary for the initialization operation of the circuit block is completed.

  When the circuit block E exists in addition to the circuit block, the group processing is performed as described above, and any one of the control signals (SL_A, SL_B, SL_C, SL_D) is output from the circuit block E. It will be assigned to the control signal.

  In step S208, the clock control unit 105 switches between the normal operation clock and the initialization operation clock according to the control signal generated and received in S207. Here, in the circuit block A107, during normal operation, the normal operation clock CLK4 generated by the clock generation unit 101 is selected. On the other hand, during the initialization operation, the original delay operation clock CLK0_D subjected to the delay process is selected.

  Similarly, in the circuit block B108, the normal operation clock CLK4 is selected during the normal operation, and the original initialization operation clock CLK1_D subjected to the delay process is selected during the initialization operation. In the circuit block C109, the normal operation clock CLK4 is selected in the normal operation, and the original initialization operation clock CLK2_D subjected to the delay process is selected in the initialization operation. In the circuit block D110, the normal operation clock CLK4 is selected during the normal operation, and the original initialization operation clock CLK3_D subjected to the delay process is selected during the initialization operation.

  As described above, according to the first embodiment, it is possible to avoid the overlapping of the rising edge and the falling edge of each initialization operation clock during the initialization operation of a plurality of circuit blocks. Therefore, the peak current during the initialization operation in the entire system can be reduced, and noise can be suppressed.

  This configuration can be applied to, for example, the change timing from the power cutoff state to the power supply state in the initialization operation at the time of system startup. Also, the present invention can be applied to an information processing apparatus that includes a plurality of circuit blocks each capable of controlling supply and cutoff of a power supply voltage and that switches circuit blocks to be used depending on data processing contents. In this case, for example, the present invention is applied to the change timing from the power-off state to the power supply state that occurs when the data processing content is changed.

  In the first embodiment, the case of using the divided clock (corresponding to FIG. 3B, FIG. 4B, and FIG. 9D) has been described. However, clocks having the same period and the same phase are used. It can also be realized with the configuration used. In that case, it is preferable to add a delay to each clock as shown in FIGS. 3 (A), 4 (A), and 9 (B). Further, a combination of these two methods may increase the number of initialization operation clocks.

(Second Embodiment)
Another example of the information processing apparatus 100 having a plurality of circuit blocks will be described below as a second embodiment of the information processing apparatus according to the present invention.

<Device configuration>
FIG. 11 is a diagram illustrating a configuration example of the information processing apparatus 100 according to the second embodiment. Here, the configurations of the clock generation unit 1101 and the delay setting unit 1103 are different from those in FIG. Therefore, in the following, description of configurations other than the clock generation unit 1101 and the delay setting unit 1103 is omitted.

  The clock generation unit 1101 receives the input of the reference clock CLK and the normal operation clock CLK4. Based on the reference clock CLK, a plurality of types of clocks (herein, CLK0, CLK1, CLK2, and CLK3) used in the initialization operation are generated.

  The clock generation unit 1101 is configured to receive input of control signals (SL_A, SL_B, SL_C, SL_D) from the control signal generation unit 104. Based on the input of the control signal, the clock generation unit 1101 outputs four clock signals (here, CLK0_S1, CLK1_S1, CLK2_S1, CLK3_S1). For example, CLK0_S1 is a clock generated by selecting either the normal operation clock (CLK4) or CLK0. Similarly, CLK1_S1 is a clock generated by selecting either the normal operation clock (CLK4) or CLK1. CLK2_S1 is a clock generated by selecting either the normal operation clock (CLK4) or CLK2. CLK3_S1 is a clock generated by selecting either the normal operation clock (CLK4) or CLK3.

  The delay setting unit 1103 sets the delay value information 112 determined by the delay value determining unit 102 for each clock (CLK0_S1, CLK1_S1, CLK2_S1, CLK3_S1). Similar to the clock generation unit 1101, the control signal generation unit 104 is configured to receive input of control signals (SL_A, SL_B, SL_C, SL_D) for switching between the initialization operation clock and the normal operation clock. Based on the control signal, a clock obtained by adding a delay to the initialization operation clock is output during the initialization operation, and the normal operation clock is output during the normal operation.

  That is, in the initialization operation, the clocks (CLK0_S2, CLK1_S2, CLK2_S2, CLK3_S2) added with a delay with respect to the clocks (CLK0_S1, CLK1_S1, CLK2_S1, CLK3_S1) are output. On the other hand, during normal operation, the normal operation clock (CLK4) is output as CLK0_S2 to CLK3_S2.

  FIG. 12 is a diagram illustrating a configuration example of the clock generation unit in the second embodiment. Here, a configuration diagram is shown in the case where a divided clock is used as an initialization operation clock supplied to different circuit blocks (circuit block A 107 to circuit block D 110).

  The clock generator 1101 outputs clocks (CLK0_S1, CLK1_S1, CLK2_S1, CLK3_S1) supplied to each circuit block by the four internal selectors 1201 to 1204.

  Specifically, the selectors 1201 to 1204 switch between the initialization operation clock and the normal operation clock based on the control signals (SL_A, SL_B, SL_C, and SL_D), respectively. At initialization operation, an initialization operation clock is selected. That is, the selector 1201 selects the CLK input based on the control signal SL_A, and the selector 1202 selects the divided clock 1205 based on the control signal SL_B. Similarly, the selector 1203 selects the divided clock 1206 based on the control signal SL_C, and the selector 1204 selects the divided clock 1207 based on the control signal SL_D. On the other hand, during normal operation, the selectors 1201 to 1204 select the normal operation clock CLK4.

  Here, for the sake of simplicity of explanation, the case where the number of clocks for normal operation is one (CLK4) is described, but a configuration in which a plurality of clocks for normal operation exist may be used. Further, the frequency-divided clocks 1205 to 1207 generated by the frequency divider 302 may be used as the normal operation clock. Furthermore, the same clock may be assigned to a plurality of clock outputs (for example, CLK1_S1, CLK2_S1).

  FIG. 13 is a configuration example of the delay setting unit in the second embodiment. The delay value information 112 acquired from the delay value determining unit 102 is supplied to the delay adding unit 601, the delay adding unit 602, the delay adding unit 603, and the delay adding unit 604 for each clock. Further, the control signal SL_A is supplied to the selector 1301, and the control signal SL_B is supplied to the selector 1302. Similarly, the control signal SL_C is supplied to the selector 1303, and the control signal SL_D is supplied to the selector 1304.

  Each of the delay adding units 601 to 604 can be configured by a circuit configuration that monitors the output clock and compensates for the wiring delay as described with reference to FIG.

  For example, the delay adding unit 601 outputs a clock 1305 obtained by delaying CLK0_S1 by 1/8 period of CLK0_S1 based on the delay value information 112 acquired from the delay value determining unit 102. Similarly, the delay adding unit 602 outputs a clock 1306 obtained by delaying CLK1_S1 by 1/8 period of CLK1_S1 based on the delay value information 112 acquired from the delay value determining unit 102. Based on the delay value information 112 acquired from the delay value determining unit 102, the delay adding unit 603 outputs a clock 1307 obtained by delaying CLK2_S1 by 1/8 period of CLK2_S1. Based on the delay value information 112 acquired from the delay value determining unit 102, the delay adding unit 604 outputs a clock 1308 obtained by delaying CLK3_S1 by 1/8 period of CLK3_S1.

  Based on the control signal SL_A, the selector 1301 selects the clock 1305 at the time of initialization operation, selects CLK0_S1 at the time of normal operation, and outputs it as CLK0_S2. Similarly, based on the control signal SL_B, the selector 1302 selects the clock 1306 during the initialization operation, selects CLK1_S1 during normal operation, and outputs it as CLK1_S2. Based on the control signal SL_C, the selector 1303 selects the clock 1307 at the time of initialization operation, selects CLK2_S1 at the time of normal operation, and outputs it as CLK2_S2. Based on the control signal SL_D, the selector 1304 selects the clock 1308 during the initialization operation, selects CLK3_S1 during the normal operation, and outputs it as CLK3_S2.

  Therefore, the delay adding unit 604 outputs a clock generated by the clock generating unit 1101 and added with a delay by the delay setting unit 1103 during the initialization operation. On the other hand, the delay adding unit 604 outputs the clock generated by the clock generating unit 1101 as it is (without adding a delay) during normal operation.

  In the second embodiment, the clock generator 1101 inputs a reference clock for initialization operation and a normal operation clock, and controls the clock by switching the control signal from the control signal generator 104. . Further, the delay setting unit 1103 is configured to generate a clock by switching between a path for adding a delay and a path for normal operation during the initialization operation. However, the configuration of the clock generation unit 1101 and the configuration of the delay setting unit 1103 may be configured as one circuit.

  For example, the normal operation clock (CLK4) input to the clock generation unit 1101 having the above configuration may be input to the delay setting unit 1103. In this case, the configuration is such that both the switching of the initialization operation clock and the normal operation clock and the addition of the delay of the initialization operation clock are performed. In this case, the control signal generated by the control signal generation unit 104 need only be supplied to the delay setting unit 1103.

  As described above, according to the second embodiment, it is possible to avoid the overlapping of the rising edge and the falling edge of each initialization operation clock during the initialization operation of a plurality of circuit blocks. Therefore, the peak current during the initialization operation in the entire system can be reduced, and noise can be suppressed.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

Claims (12)

A clock generation means for generating a plurality of types of clocks with edges aligned from an input clock;
Delay value determining means for determining a plurality of types of delay values for the plurality of types of clocks;
Delay setting means for performing delay processing on each of the plurality of types of clocks based on the delay value determined by the delay value determining means;
Control signal generating means for generating a control signal for controlling whether or not to supply the plurality of types of clocks delayed by the delay setting means during the initialization operation of the corresponding circuit block;
Clock control means for switching a clock to be supplied to a corresponding circuit block based on the control signal;
An information processing apparatus comprising:   2. The information according to claim 1, wherein the clock control unit switches to one of the plurality of types of clocks delayed by the delay setting unit in the input clock during the initialization operation of the corresponding circuit block. Processing equipment. The clock generation means generates the plurality of types of clocks as the same clock as the input clock,
The information processing apparatus according to claim 1, wherein the delay value determining unit determines a plurality of different delay values for each of the plurality of clocks. The information processing apparatus according to claim 3, wherein the plurality of types of delay values are determined as 1/2 ^N of a period of the input clock (N is an integer of 2 or more). The clock generation means generates the plurality of types of clocks as frequency-divided clocks of the input clock signal that are different from each other,
The delay value determining means determines 1/2 ^N (N is an integer of 2 or more) of each clock cycle as a delay value for each of the plurality of types of clocks. 2. The information processing apparatus according to 2. The delay setting means includes
A plurality of delay adding means having different delay values;
Switching means for switching to any of the plurality of delay adding means;
The information processing apparatus according to any one of claims 1 to 5, further comprising:   The information processing apparatus according to claim 6, wherein the delay adding unit includes a delay locked loop (DLL).   The information processing apparatus according to claim 6, wherein the delay adding unit includes one or more delay elements connected in series.   The information processing apparatus according to claim 1, wherein the circuit block is a circuit block capable of controlling supply and interruption of a power supply voltage.   The information processing apparatus according to claim 1, further comprising grouping means for grouping a plurality of circuit blocks to be subjected to the initialization operation. A clock generation process for generating multiple types of clocks with aligned edges from the input clock;
A delay value determining step for determining a plurality of types of delay values for the plurality of types of clocks;
A delay setting step for performing a delay process on each of the plurality of types of clocks based on the delay value determined in the delay value determination step;
A control signal generating step for generating a control signal for controlling whether or not to supply the plurality of types of clocks delayed in the delay setting step during the initialization operation of the corresponding circuit block;
A clock control step of switching a clock to be supplied to a corresponding circuit block based on the control signal;
A method for controlling an information processing apparatus, comprising:   The program for functioning a computer as each means of the information processing apparatus as described in any one of Claims 1 thru | or 10.

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