JP2014518462A - Interleaving method and deinterleaving method - Google Patents

Abstract

A reordering of the bits of the codeword is made such that at least one of the spatial multiplex blocks is made up of B / 2 different cyclic block bits, and each of the constellation words of the at least one of the spatial multiplex blocks is associated with the constellation. It made from bits of half a is B _t / 2 pieces of cyclic block word bit number B _t, wherein at least one of the spatial multiplexing block of the constellation word husband each of said pair of bits s are B _t / This is done so that it is made from one common cyclic block of the two cyclic blocks.

Description

  The present invention relates to the field of digital communications, and more particularly, a quasi-cyclic low-density parity-check (QC-LDPC) code, QAM (quadrature amplitude modulation) for a plurality of transmit antennas. , And interleaving method used in a bit-interleaved coding and modulation (BICM) system, interleaver, transmitter including the same, and deinterleaving method corresponding thereto, The present invention relates to an interleaver and a receiver including the interleaver.

In recent years, a communication system including a transmitter including a bit-interleaved coding and modulation (BICM) encoder has been proposed (for example, see Non-Patent Document 1).
For example, the BICM encoder performs the following steps.
(1) The data block is encoded using, for example, a quasi-cyclic low-density parity-check (QC LDPC) code.

(2) Bit interleaving including parity interleaving and column-row interleaving is performed on the bits of the codeword obtained as a result of encoding.
(3) The bit-interleaved codeword is demultiplexed into constellation words. However, demultiplexing includes processing equivalent to permutation of columns of an interleaver matrix in column-row interleaving when the modulation scheme is 16QAM, 64QAM, 256QAM, or the like.

  (4) Map constellation words to constellations.

ETSI EN 302 755 V1.2.1 (DVB-T2 standard)

By the way, if the bits of the code word based on the QC LDPC code can be appropriately mapped to the constellation word, the reception performance of the communication system is improved.
Similarly, even in a communication system including a transmitter including a BICM encoder with spatial multiplexing, if a bit of a code word based on a QC LDPC code can be appropriately mapped to a plurality of constellation words in a spatial multiplexing block, the communication system Lead to improved reception performance.

  The present invention can appropriately improve the reception performance of a communication system by appropriately mapping the bits of a code word based on a pseudo cyclic low density parity check code to a plurality of constellation words of one or more spatial multiplexing blocks. An interleaving method for rearranging the bits of the codeword, an interleaver, and a transmitter including the same, and a deinterleaving method, a deinterleaver corresponding to these, and a receiver including the interleaving method. Objective.

In order to achieve the above object, the interleaving method of the present invention comprises:
1 from the code word of the pseudo cyclic low density parity check code, executed in a transmitter in a communication system using pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmission antennas. An interleaving method for rearranging the bits of the codeword in order to generate a plurality of constellation words of the above spatial multiplexing block,
The codeword is composed of N cyclic blocks each consisting of Q bits,
The spatial multiplexing block is composed of B bits, and the spatial multiplexing block is composed of T constellation words,
Each of the constellation words represents one of a plurality of constellation points of a predetermined constellation used for constellation mapping of the constellation word,
A plurality of bits of each said constellation word are divided into bit pairs of the same robust level;
The interleaving method is:
Reordering the bits of the codeword,
At least one said spatial multiplexing block is made up of bits of B / 2 different cyclic blocks;
Each of the constellation words of the at least one spatial multiplex block is made up of bits of B _t / 2 cyclic blocks that are ½ of the number of bits B _t of the constellation word;
Such that each bit pair of each of the constellation words of the at least one spatial multiplexing block is made up of one common cyclic block of B _t / 2 cyclic blocks,
It is characterized by doing.

  According to the interleaving method, it is possible to appropriately map the bits of the codeword based on the pseudo cyclic low density parity check code to the constellation word, thereby improving the reception performance of the communication system.

1 is a block diagram of a transmitter having multiple antennas and performing bit interleaved code modulation using spatial multiplexing. FIG. FIG. 2 is a block diagram of the spatial multiplexing bit interleave coded modulation encoder of FIG. 1. The figure which shows an example of the parity check matrix of the pseudo cyclic low density parity check code | symbol with the cyclic coefficient Q = 8. FIG. 6 is a schematic diagram illustrating different robust levels in 8-PAM symbols using Gray coding. The block diagram of the QAM mapper for 4-QAM (QPSK). 16 is a block diagram of a QAM mapper for 16-QAM. Block diagram of a QAM mapper for 64-QAM. 1 is a schematic diagram of a spatial multiplexing system in which the number of bits per SM block is equal to 4 with two antennas according to an embodiment of the present invention. 1 is a schematic diagram of a spatial multiplexing system in which the number of bits per SM block is equal to 6 with two antennas according to an embodiment of the present invention. 1 is a schematic diagram of a spatial multiplexing system in which the number of bits per SM block is equal to 8 with two antennas according to an embodiment of the present invention. 1 is a schematic diagram of a spatial multiplexing system in which the number of bits per SM block is equal to 10 with two antennas according to an embodiment of the present invention. The block diagram of the transmitter in the communication system which concerns on embodiment of this invention. FIG. 8 is a block diagram of the BICM encoder of FIG. 7. FIG. 9 is a block diagram showing a configuration example of the bit interleaver in FIG. 8. The block diagram which shows the other structural example of the bit interleaver of FIG. The figure which shows an example of the bit rearrangement function of the section permutation unit of FIG. 9 in the case of B = 4 which concerns on embodiment of this invention. The figure which shows an example of the bit rearrangement function of the section permutation unit of FIG. 9 in the case of B = 6 which concerns on embodiment of this invention. The figure which shows an example of the bit rearrangement function of the section permutation unit of FIG. 9 in the case of B = 8 which concerns on embodiment of this invention. The figure which shows an example of the bit rearrangement function of the section permutation unit of FIG. 9 in the case of B = 10 which concerns on embodiment of this invention. FIG. 11B is a diagram for explaining an operation example of a section permutation unit that performs the rearrangement of bits illustrated in FIG. 11A. The figure for demonstrating one operation example of the section permutation unit which rearranges the bit shown to FIG. 11B. FIG. 11B is a diagram for explaining an operation example of the section permutation unit that performs the rearrangement of bits illustrated in FIG. 11C. FIG. 11D is a diagram for explaining an operation example of a section permutation unit that performs the rearrangement of bits illustrated in FIG. 11D. The figure which shows the example of 1 structure of the bit interleave coding modulation encoder of FIG. 8 in the case of B = 4. The figure which shows the example of 1 structure of the bit interleave coding modulation encoder of FIG. 8 in the case of B = 6. The figure which shows the example of 1 structure of the bit interleave coding modulation encoder of FIG. 8 in the case of B = 8. The figure which shows the example of 1 structure of the bit interleave coding modulation encoder of FIG. 8 in the case of B = 10. The block diagram of the receiver in the communication system which concerns on embodiment of this invention.

<< Background to Invention >>
FIG. 1 is a block diagram illustrating a configuration of the transmitter 1000. The transmitter 1000 includes an input processing unit 1100, a bit-interleaved coding and modulation (BICM) encoder 1200, modulators 1300-1 to 1300-4, and power amplifiers 1400-1 to 1400-4. And transmission antennas 1500-1 to 1500-4.

The input processing unit 1100 converts an input bitstream related to a broadcast service into a block having a predetermined length. This block is called a baseband frame.
The BICM encoder 1200 converts the baseband frame into a plurality of data streams composed of a plurality of complex symbols. The number of data streams is equal to the number of transmit antennas.

  Each data stream is further processed by a modulation chain including at least modulators 1300-1 to 1300-4 and power amplifiers 1400-1 to 1400-4, and is output from transmitting antennas 1500-1 to 1500-4. Each modulator 1300-1 to 1300-4 performs processing such as orthogonal frequency division multiplexing on the input from the BICM encoder 1200. Each power amplifier 1400-1 to 1400-4 performs power amplification on the input from each modulator 1300-1 to 1300-4.

Details of the BICM encoder 1200 of FIG. 1 will be described below with reference to FIG.
FIG. 2 is a block diagram of the spatial multiplexing BICM encoder 1200 of FIG.
The BICM encoder 1200 includes an LDPC encoder 1210, a bit interleaver 1220, a demultiplexer 1230, QAM mappers 1240-1 to 1240-4, and a spatial-multiplexing (SM) encoder 1250.

The LDPC encoder 1210 encodes an input block, that is, a baseband frame into a codeword using an LDPC code, and outputs the codeword to the bit interleaver 1220.
Bit interleaver 1220 performs bit interleaving to rearrange the bits of the LDPC codeword and outputs the result to demultiplexer 1230.
The demultiplexer 1230 demultiplexes the bit interleaved codeword into a plurality of bit streams and outputs the demultiplexed code words to the QAM mappers 1240-1 to 1240-4.

  Each QAM mapper 1240-1 to 1240-4 maps each of a plurality of constellation words constituting each bit stream to a complex symbol and outputs it to a selectable SM encoder 1250. Each of the constellation words indicates one of a plurality of constellation points of a predetermined constellation used for constellation mapping of the constellation word.

The SM encoder 1250 typically multiplies the input signal vector by an orthogonal square matrix.
The LDPC code is a linear error correction code that is completely defined by a parity check matrix (PCM), and the PCM is also called a codeword bit (also called a variable node) and a parity check (also called a check node). It is a binary sparse matrix that represents the connection (connection). The PCM columns and rows correspond to variable nodes and check nodes, respectively. The connection between the variable node and the check node is indicated by an element “1” in the PCM.

  There is a type of LDPC code called a quasi-cyclic low-density parity check (QC LDPC) code. The QC LDPC code has a structure particularly suitable for hardware implementation. In fact, most of today's standards use QC LDPC codes. The PCM of the QC LDPC code has a special structure having a plurality of cyclic matrices. A cyclic matrix is a square matrix in which each row is cyclically shifted by one element from the previous row, with one, two, or more folded diagonal columns. Can exist. The size of each cyclic matrix is Q × Q. Here, Q is referred to as a cyclic factor of the QC LDPC code. With such a quasi-cyclic structure, Q check nodes can be processed in parallel, and the QC LDPC code is clearly advantageous for efficient hardware implementation.

FIG. 3 is a diagram illustrating a PCM of a QC LDPC code having a cyclic coefficient Q = 8 as an example. In FIG. 3, one of the smallest squares represents one element of the PCM, among which the black square element is “1” and the other elements are “0”.
The PCM of FIG. 3 has a cyclic matrix with one or two superimposed diagonal columns, and the QC LDPC code corresponding to the PCM of FIG. 3 is a block of 8 × 12 = 96 bits, 8 × 18 = 144. Encode to a bit codeword. Therefore, the coding rate of this QC LDPC code is 96/144 = 2/3. The codeword bits are divided into a plurality of blocks having Q bits. A Q-bit block is referred to as a cyclic block in this specification and is expressed as QB.

  The QC LDPC code corresponding to the PCM in FIG. 3 belongs to a special type of QC LDPC code called a repeat-accumulate quasi-cyclic low-density parity check (RA QC LDPC) code. RA QC LDPC codes are known for their ease of encoding and have been adopted in many standards (eg, second generation DVB standards such as DVB-S2, DVB-T2, and DVB-C2 standards). Yes. The right side of the PCM corresponds to a parity bit, and the arrangement of “1” elements in that portion has a staircase structure.

DVB stands for Digital Video Broadcasting, DVB-S2 stands for Digital Video Broadcasting-Second Generation Satellite, DVB-T2 stands for Digital Video Broadcasting-Second Generation Terrestrial, and DVB-C2 stands for Digital Video Broadcasting. Broadcasting-Abbreviation for Second Generation Cable.
Usually, the bits of the LDPC codeword have different importance levels, and the constellation bits have different robust levels. Mapping the LDPC codeword bits directly, ie, without interleaving, to the constellation bits does not lead to optimal performance. For this reason, the bits of the codeword need to be interleaved before being mapped to the constellation.

  In order to interleave the bits of the codeword, as shown in FIG. 2, a bit interleaver 1220 and a demultiplexer 1230 are provided between the LDPC encoder 1210 and the QAM mappers 1240-1 to 1240-4. By carefully designing the bit interleaver 1220 and the demultiplexer 1230, the relationship between the bits of the LDPC codeword and the bits encoded by the constellation is optimized, leading to improved reception performance. The performance is usually measured using a bit error rate (BER) as a function of signal-to-noise ratio (SNR).

  The main reason for the different importance of LDPC codeword bits is that the number of parity checks associated with all bits is not necessarily the same. The greater the number of parity checks (check nodes) associated with codeword bits (variable nodes), the higher the importance of codeword bits in the iterative LDPC decoding process. A further reason is that the connectivity for cycling in the Tanner graph representation of the LDPC code varies from variable node to variable node. For this reason, even if the number of parity checks related to the codeword bits is the same, the importance of the codeword bits may be different. These views are well known in the art. In principle, as the number of check nodes connected to a variable node increases, the importance of the variable node increases.

In particular, in the case of a QC LDPC code, all the bits included in the Q-bit cyclic block have the same number of related parity checks, and the connectivity to the cyclic in the Tanner graph is the same. The degree will be the same.
Similarly, it is a well-known fact that the bits encoded in the constellation have different robust levels. For example, a complex quadrature amplitude modulation (QAM) constellation consists of two independent pulse amplitude modulation (PAM) symbols, one of which corresponds to the real part and the other to the imaginary part. Correspond. In a square constellation, two PAM symbols encode the same number of bits. The robust levels of a plurality of bits encoded in the PAM symbol are different from each other. As an example, FIG. 4 illustrates an 8-PAM symbol using Gray coding. The reason why the robust levels of the plurality of bits encoded in the PAM symbol are different from each other is that the distance between the two subsets defined by the bit (0 or 1) is different for each bit. The greater this distance, the higher the robust level or reliability of that bit. In FIG. 4, the robust level of bit b3 is the highest, and the robust level of bit b1 is the lowest.

Block diagrams of the most commonly used QAM mapper for the QAM constellation are shown in FIGS. 5A-5C.
FIG. 5A is a block diagram of a QAM mapper for a 4-QAM constellation. The QAM mapper 1240A includes PAM mappers 1241A and 1245A for 2-PAM constellations for the real part and the imaginary part. The QAM mapper 1240A encodes 2 bits in total by the PAM mappers 1241A and 1245A. The 4-QAM constellation has one robust level.

  FIG. 5B is a block diagram of a QAM mapper for a 16-QAM constellation. The QAM mapper 1240B includes PAM mappers 1241B and 1245B for 4-PAM constellations for the real part and the imaginary part. The QAM mapper 1240B encodes a total of 4 bits by 2 bits by the PAM mappers 1241B and 1245B. There are two robust levels in the 16-QAM constellation.

  FIG. 5C is a block diagram of a QAM mapper for a 64-QAM constellation. The QAM mapper 1240C includes PAM mappers 1241C and 1245C for 8-PAM constellation for the real part and the imaginary part. The QAM mapper 1240C encodes 6 bits in total by 3 bits by the PAM mappers 1241C and 1245C. There are three robust levels in the 64-QAM constellation.

However, in each square QAM constellation, the robust levels of bi _{, Re} and bi _{, Im} are equal to each other (i = 1,...).
In a spatial multiplexing system using T transmission antennas, T complex QAM symbols are transmitted in the same channel slot. In OFDM modulation, a channel slot is described as an OFDM cell, which is a subcarrier in the OFDM symbol. The T complex QAM symbols do not necessarily have to be the same size, and form a spatial multiplexing (SM) block.

The T complex QAM symbols in one SM block are either not encoded or jointly encoded by applying an additional encoding step by the SM encoder 1250 shown in FIG. ), Transmitted from the antenna.
Joint encoding is usually performed by multiplying a vector of 2T real components by an orthogonal square matrix. In the most general case, joint coding is applied to multiple K channel slots, ie, K × T complex QAM symbols. Joint coding effectively uses the additional time and / or frequency diversity available in the K channel slots.

Throughout this specification, the number of bits transmitted in one channel slot is denoted by B, and the number of bits in each complex QAM symbol is denoted by B _t . Where t is an antenna index from 1 to T.
<< Embodiment >>
The special technique of the present invention provides an interleaving method for rearranging the bits of a codeword (QC LDPC codeword) based on a QC LDPC code that guarantees the following contents.

(I) The B _t bits of each QAM symbol are exactly B _t / 2 cyclic blocks of the QC LDPC codeword so that each of the B _t / 2 cyclic blocks is associated with the same robust level bit. Mapped to
(Ii) The T QAM symbols of the spatial multiplexing block (SM block) are mapped to different cyclic blocks of the QC LDPC codeword.

In other words,
(I) Each constellation word (number of bits B _t ) is made up of B _t / 2 cyclic block bits of different QC LDPC codewords,
(II) Bit pairs with the same donkey stress level in the constellation word are made from the same cyclic block,
(III) Constellation words for different antennas are made from bits of different cyclic blocks.

However, the SM block is made up of bits of B / 2 cyclic blocks.
The SM block consists of B bits, and the SM block consists of T constellation words.
In a preferred embodiment of the present invention, the communication system uses a square QAM constellation. Therefore, the number of bits B _t for each constellation word for the antenna t is always an even number, and two QAM components (real part and imaginary part) are modulated by the same number of bits B _t / 2, respectively.

Preferably, Q × B / 2 bits of B / 2 cyclic blocks are mapped to Q / 2 spatial multiplexing blocks. In this case, B / 2 cyclic blocks are described as a section.
The structure for the spatial multiplexing system in the case where the number of bits per spatial multiplexing block is equal to 4, 6, 8, 10 with two transmit antennas is shown in FIGS. 6A to 6D. Bits of groups belonging to the same SM block are surrounded by thick lines. In this example, the LDPC parameter has a cyclic coefficient Q = 8 and a cyclic block number N for each codeword = 15.

  The mapping of bits to constellation words in one section is performed independently of other sections. This enables particularly efficient mounting. A plurality of section permutation units are provided for each section, and parallel operation is adopted. This implementation can be described as a parallel interleaver. Instead of providing one section permutation unit for each section, section permutation units smaller than the number of sections may be used in a time division manner.

  If N is not a multiple of B / 2, in the case of B = 4, 8 in the above example, the codeword cannot be divided into sections each consisting of B / 2 cyclic blocks. Therefore, the code word is a group of a number X of cyclic blocks (hereinafter referred to as “remainder group”), which is a remainder value obtained by dividing N by B / 2, and a B / 2 cyclic block. Divide into two or more sections. However, the mapping in the remaining groups is not the subject of the present invention, and one option is to perform the mapping continuously.

When N is a multiple of B / 2, if B = 6 and 10 in the above example, the codeword can be divided into one or more sections each consisting of B / 2 cyclic blocks.
Further, the order of the N cyclic blocks is usually different from the order in the definition of the LDPC code, and is defined by the permutation of N elements.
<Transmitter>
Hereinafter, a transmitter in a communication system according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 7 is a block diagram showing a configuration of transmitter 100 according to the embodiment of the present invention. The transmitter 100 includes an input processing unit 110, a bit-interleaved coding and modulation (BICM) encoder 120, modulators 130-1 to 130-4, and power amplifiers 140-1 to 140-4. And transmission antennas 150-1 to 150-4. However, each constituent unit excluding the BICM encoder 120 performs substantially the same processing as each corresponding constituent unit of the transmitter 1000 of FIG. 1, and detailed description thereof is omitted.

The details of the BICM encoder 120 of FIG. 7 will be described below with reference to FIG.
FIG. 8 is a block diagram of the spatial multiplexing BICM encoder 120 of FIG.
The BICM encoder 120 includes an LDPC encoder 121, a bit interleaver 122, a demultiplexer 123, QAM mappers 124-1 to 124-4, and a spatial-multiplexing (SM) encoder 125. However, each constituent unit except the bit interleaver 122 and the demultiplexer 123 performs substantially the same processing as each corresponding constituent unit of the BICM encoder 1200 of FIG.

The LDPC encoder 121 generates a code word by encoding using the QC LDPC code and outputs the code word to the bit interleaver 122. However, the codeword generated by the LDPC encoder 121 is composed of N cyclic blocks, and each cyclic block is composed of Q bits.
The bit interleaver 122 receives the code word from the LDPC encoder 121 and rearranges the bits of the received code word. The demultiplexer 123 demultiplexes the bits of the reordered code word (separates into a plurality of bit strings and rearranges the plurality of bit strings), and maps the constellation words. The bit interleaver 122 and the demultiplexer 123 perform processing so as to satisfy the above (i) to (ii), in other words, (I) to (III).

The QAM mappers 124-1 to 124-4 map the constellation words supplied from the demultiplexer 123 to complex QAM symbols, and the SM encoder 125 converts the complex QAM symbols supplied from the QAM mappers 124-1 to 124-4. Encoding for spatial multiplexing is performed.
Hereinafter, an example of the bit interleaver 122 of FIG. 8 will be described with reference to FIG.

FIG. 9 is a block diagram showing a configuration example of the bit interleaver 122 of FIG.
In the bit interleaver 122 shown in FIG. 9 as an example of configuration, N cyclic blocks are one or a plurality of sections made up of B / 2 cyclic blocks and the number of remainders obtained by dividing N by B / 2. Divided into groups of X cyclic blocks (remaining groups). If N is a multiple of B / 2, there are no remaining groups.

For example, when N = 15, Q = 8, and B = 4 corresponding to FIG. 6A, the number of cyclic blocks associated with one section is B / 2 = 2, and the number of spatial multiplexing blocks (SM blocks) is Q / 2. = 4, the number of sections is 7, and the number of remaining cyclic blocks is 1.
When N = 15, Q = 8, and B = 6 corresponding to FIG. 6B, the number of cyclic blocks associated with one section is B / 2 = 3, the number of SM blocks is Q / 2 = 4, and the number of sections is 5.

When N = 15, Q = 8, and B = 8 corresponding to FIG. 6C, the number of cyclic blocks associated with one section is B / 2 = 4, the number of SM blocks is Q / 2 = 4, and the number of sections is 3. The number of remaining cyclic blocks is 3.
When N = 15, Q = 8, and B = 10 corresponding to FIG. 6D, the number of cyclic blocks associated with one section is B / 2 = 5, the number of SM blocks is Q / 2 = 4, and the number of sections is 3.

  9 includes section permutation units 122-1, 122-2, 122-3,... For each section. If N is not a multiple of B / 2, there are cyclic blocks that do not belong to any section. However, bit reordering is not performed for cyclic blocks that do not belong to any section. Alternatively, the bits may be rearranged according to an arbitrary permutation rule.

  The section permutation units 122-1, 122-2, 122-3,..., Q × (B / 2) bits of B / 2 cyclic blocks, and Q bits of cyclic block QB Are rearranged so as to be mapped to two bits in each Q / 2 SM block. Then, the demultiplexer 123 rearranges and outputs each SM block so that two bits of the same cyclic block in the SM block are mapped to two bits of the same robust level of the same constellation. Each section permutation unit 122-1, 122-2, 122-3, ... may operate independently of other section permutation units. Note that it is not necessary to provide one section permutation unit for each section, and a smaller number of section permutation units than the number of sections may be used in a time division manner.

However, as shown in FIG. 10, the bit interleaver 122 in FIG. 8 has a configuration in which an inter-cyclic block permutation unit 310, a permutation unit in cyclic block 320 ₁ ,... Are added to the configuration in FIG. It is good.
The inter-cyclic block permutation unit 310 rearranges the cyclic blocks, and the intra-cyclic block permutation units 320 ₁ ,... Rearrange the bits of the cyclic blocks.

  Note that the reordering of cyclic blocks by the inter-cyclic block permutation unit 310 is not particularly limited, but for example, the permutation unit between cyclic blocks 310 has a bit reordering and deserialization by the section permutation unit. Considering the rearrangement of bits by the multiplexer, the cyclic blocks may be rearranged so that the bits of the cyclic block made up of bits with higher importance are mapped to the bits with the higher robust level of the constellation word. .

The bit interleaver may have a configuration in which one of the inter-cyclic block permutation unit 310, the intra-cyclic block permutation unit 320 ₁ ,... Is removed from the configuration of FIG. In this configuration, the arrangement of permutation unit between cyclic blocks 310 and permutation unit 320 ₁ within cyclic block may be replaced. Each in-cyclic block permutation unit 320 ₁ ,... May operate independently of other in-cyclic block permutation units. Note that it is not necessary to provide one in-cyclic block permutation unit for each cyclic block, and a smaller number of in-cyclic block permutation units than the number of cyclic blocks may be used in a time division manner.

Hereinafter, with respect to the operation example of the section permutation unit in FIG. 9, Q = 8 and B = 4, 6, 8, and 10 are used with reference to FIGS. 11A to 11D and FIGS. 12A to 12D. I will explain.
FIG. 11A is a diagram illustrating an example of a section permutation unit rearrangement function when Q = 8 and B = 4, and FIG. 12A is a section permutation unit that performs the rearrangement of bits illustrated in FIG. 11A. It is a figure for demonstrating one operation example.

As shown in FIG. 11A, the section permutation unit 122-1A converts the bits of B / 2 = 2 cyclic blocks QB ₁ and QB ₂ into Q / 2 = 4 SM blocks SMB _{1 to} SMB ₄ . The input bits are rearranged so that they are mapped to bits.
For rearranging the input bits in FIG. 11A, the section permutation unit 122-1A, for example, in the row direction of the interleaver matrix of Q columns B / 2 rows = 8 columns 2 rows as shown in FIG. 12A. Processing equivalent to column-row interleaving is performed in which bits are written and bits are read in the column direction. In FIG. 12A and FIGS. 12B to 12D described later, the bit writing order is indicated by a dotted arrow, and the bit reading order is indicated by a solid arrow.

FIG. 11B is a diagram showing an example of a section permutation unit rearrangement function when Q = 8 and B = 6, and FIG. 12B is a section permutation unit for rearranging bits shown in FIG. 11B. It is a figure for demonstrating one operation example.
As shown in FIG. 11B, the section permutation unit 122-1B converts the bits of B / 2 = 3 cyclic blocks QB _{1 to} QB ₃ into Q / 2 = 4 SM blocks SMB _{1 to} SMB ₄ . The input bits are rearranged so that they are mapped to bits.

For rearranging the input bits in FIG. 11B, the section permutation unit 122-1B, for example, in the row direction of the interleaver matrix of Q columns B / 2 rows = 8 columns 3 rows as shown in FIG. 12B. Processing equivalent to column-row interleaving is performed in which bits are written and bits are read in the column direction.
FIG. 11C is a diagram illustrating an example of a section permutation unit rearrangement function when Q = 8 and B = 8, and FIG. 12C is a section permutation unit that performs the rearrangement of bits illustrated in FIG. 11C. It is a figure for demonstrating one operation example.

As shown in FIG. 11C, the section permutation unit 122-1C converts the bits of B / 2 = 4 cyclic blocks QB _{1 to} QB ₄ into Q / 2 = 4 SM blocks SMB _{1 to} SMB ₄ . The input bits are rearranged so that they are mapped to bits.
For rearranging the input bits in FIG. 11C, the section permutation unit 122-1C, for example, in the row direction of the interleaver matrix of Q columns B / 2 rows = 8 columns 4 rows as shown in FIG. 12C. Processing equivalent to column-row interleaving is performed in which bits are written and bits are read in the column direction.

FIG. 11D is a diagram illustrating an example of a section permutation unit rearrangement function when Q = 8 and B = 10, and FIG. 12D is a section permutation unit that performs the rearrangement of bits illustrated in FIG. 11D. It is a figure for demonstrating one operation example.
As shown in FIG. 11D, the section permutation unit 122-1D uses B / 2 = 5 cyclic blocks QB _{1 to} QB ₅ as bits and Q / 2 = 4 SM blocks SMB _{1 to} SMB ₄ bits. The input bits are rearranged so as to be mapped to.

For rearranging the input bits in FIG. 11D, the section permutation unit 122-1D, for example, in the row direction of the interleaver matrix of Q columns B / 2 rows = 8 columns 5 rows as shown in FIG. 12D. Processing equivalent to column-row interleaving is performed in which bits are written and bits are read in the column direction.
The section permutation unit described with reference to FIGS. 11A to 11D and FIGS. 12A to 12D is generalized as follows.

The section permutation unit receives the bits of the cyclic blocks QB _{B / 2} × _{i + 1 to} QB _{B / 2} × _{i + B / 2} and inputs SM blocks SMB _{Q / 2} × _{i + 1 to} SMB _{Q / 2} × Output _{i + Q / 2} bit. The section permutation unit performs processing equivalent to column-row interleaving in which bits are written in the row direction of the Q-column B / 2-row interleaver matrix and bits are read in the column direction.

Hereinafter, an operation example of the BICM encoder 120 of FIG. 8 in the path of the bit interleaver, demultiplexer, and QAM mapper will be described with reference to FIGS. 13A to 13D. However, the number of transmission antennas (the number of constellation words for each SM block) is 2.
FIG. 13A is a block diagram illustrating a configuration example of the path of the bit interleaver, demultiplexer, and QAM mapper of the BICM encoder when B = 4.

  The LDPC codeword generated by the LDPC encoder (not shown) (see FIG. 8) in the BICM encoder 120A is supplied to the bit interleaver 122A including the section permutation unit described with reference to FIGS. 11A and 12A. The bits of the LDPC codeword are rearranged by the bit interleaver 122A, and the codeword whose bits are rearranged is supplied to the demultiplexer 123A.

The demultiplexer 123A in the example of FIG. 13A, and outputs the rearranged bit y ₁ ~y ₄ bits _{y 1, y 3, y 2} , y 4. As a result, the bits (y ₁ , y ₃ ) are mapped to the constellation word C _A (b _{1, Re} , b _{1, Im} ), and the bits (y ₂ , y ₄ ) are mapped to the constellation word C _B (b _{1, Re} , b1 _{, Im} ).
The 4-QAM mappers 124A-1 and 124A-2 respectively convert the constellation words C _A and C _B (b _{1, Re} , b _{1, Im} ) into complex symbols (Re, Im) by two 2-PAM mappers. Map.

The SM encoder 125A performs encoding to spatially multiplex complex symbols in order to generate transmission signals Tx1 and Tx2.
FIG. 13B is a block diagram illustrating a configuration example of the path of the bit interleaver, demultiplexer, and QAM mapper of the BICM encoder when B = 6.
The LDPC codeword generated by the LDPC encoder (not shown) (see FIG. 8) in the BICM encoder 120B is supplied to the bit interleaver 122B including the section permutation unit described with reference to FIGS. 11B and 12B. The bits of the LDPC codeword are rearranged by the bit interleaver 122B, and the codeword whose bits are rearranged is supplied to the demultiplexer 123B.

The demultiplexer 123B in the example of FIG. 13B, and outputs the rearranged bit y ₁ ~y ₆ bits _{y 1, y 2, y 4} , y 5, y 3, y 6. As a result, the bits (y ₁ , y ₂ , y ₄ , y ₅ ) are mapped to the constellation word C _A (b _{1, Re} , b _{2, Re} , b _{1, Im} , b _{2, Im} ), and the bit ( y ₃ , y ₆ ) are mapped to the constellation word C _B (b _{1, Re} , b _{1, Im} ).
16-QAM mapper 124B-1 is constellation word C _A by two 4-PAM mapper _{(b 1, Re, b 2} , Re, b 1, Im, b 2, Im) complex symbols (Re, Im) To map. On the other hand, the 4-QAM mapper 124B-2 maps the constellation word C _B (b _{1, Re} , b _{1, Im} ) to the complex symbol (Re, Im) using two 2-PAM mappers.

The SM encoder 125B performs encoding for spatially multiplexing complex symbols in order to generate transmission signals Tx1 and Tx2.
FIG. 13C is a block diagram illustrating a configuration example of the path of the bit interleaver, demultiplexer, and QAM mapper of the BICM encoder when B = 8.
The LDPC codeword generated by the LDPC encoder (not shown) (see FIG. 8) in the BICM encoder 120C is supplied to the bit interleaver 122C including the section permutation unit described with reference to FIGS. 11C and 12C. The bits of the LDPC codeword are rearranged by the bit interleaver 122C, and the codeword whose bits are rearranged is supplied to the demultiplexer 123C.

Demultiplexer 123C in the example of FIG. 13C, and outputs the rearranged bit y ₁ ~y ₈ bit _{y 1, y 2, y 5} , y 6, y 3, y 4, y 7, y 8. As a result, the bits (y ₁ , y ₂ , y ₅ , y ₆ ) are mapped to the constellation word C _A (b _{1, Re} , b _{2, Re} , b _{1, Im} , b _{2, Im} ), and the bit ( y ₃ , y ₄ , y ₇ , y ₈ ) are mapped to the constellation word C _B (b _{1, Re} , b _{2, Re} , b _{1, Im} , b _{2, Im} ).

16-QAM mapper 124C-1,124C-2, respectively, constellation word by two 4-PAM mapper _{C A, C B (b 1} , Re, b 2, Re, b 1, Im, b 2, Im ) To a complex symbol (Re, Im).
The SM encoder 125C performs encoding for spatially multiplexing complex symbols in order to generate transmission signals Tx1 and Tx2.

FIG. 13D is a block diagram illustrating a configuration example of the path of the bit interleaver, demultiplexer, and QAM mapper of the BICM encoder when B = 10.
The LDPC codeword generated by the LDPC encoder (not shown) (see FIG. 8) in the BICM encoder 120D is supplied to the bit interleaver 122D including the section permutator described with reference to FIGS. 11D and 12D. The bits of the LDPC codeword are rearranged by the bit interleaver 122D, and the codeword whose bits are rearranged is supplied to the demultiplexer 123D.

Demultiplexer 123D in the example of FIG. 13D, arranges the bit y ₁ ~y ₁₀ bit _{y 1, y 2, y 3} , y 6, y 7, y 8, y 4, y 5, y 9, y 10 Change to output. As a result, the bits (y ₁ , y ₂ , y ₃ , y ₆ , y ₇ , y ₈ ) are converted into constellation words C _A (b _{1, Re} , b _{2, Re} , b _{3, Re} , b _{1, Im} , b _{2, Im} , b _{3, Im} ) and the bits (y ₄ , y ₅ , y ₉ , y ₁₀ ) are converted to the constellation word C _B (b _{1, Re} , b _{2, Re} , b _{1, Im} , b2 _{, Im} ).

The 64-QAM mapper 124D-1 is converted by the two 8-PAM mappers into the constellation word C _A (b _{1, Re} , b _{2, Re} , b _{3, Re} , b _{1, Im} , b _{2, Im} , b _{3, Im} ) is mapped to complex symbols (Re, Im). On the other hand, the 16-QAM mapper 124D-2 converts the constellation word C _B (b _{1, Re} , b _{2, Re} , b _{1, Im} , b _{2, Im} ) into a complex symbol (Re, Im).

The SM encoder 125D performs encoding for spatially multiplexing complex symbols in order to generate transmission signals Tx1 and Tx2.
The generalization of the demultiplexer described with reference to FIGS. 13A to 13D is as follows. However, the number of bits of the SM block is B, the number of antennas (constellation words) is T, and the number of bits of the constellation word C _i is B _i = 2 × Mi. Note that i is an index of an antenna (constellation word) and is an integer of 1 or more and T or less.

The demultiplexer converts the bits (y ₁ , y ₂ ,..., Y _M1 , y _{B / 2 + 1} , y _{B / 2 + 2} ,..., Y _{B / 2 + M1} ) to the constellation word C _1. the bit _{(y M1 + 1, y M1} + 2, ···, y M1 + M2, y B / 2 + M1 + 1, y B / 2 + M1 + 2, ···, y B / 2 + _{M1 + M2)} to constellation word C _2, bits _{(y M1 + M2 + 1,} y M1 + M2 + 2, ···, y M1 + M2 + M3, y B / 2 + M1 + M2 + 1, _{y B / 2 + M1 + M2} + 2, ···, in _{y B / 2 + M1 + M2} + M3) the constellation word C _3, as mapped ..., in, rearranges the input bit Output. _{That, L i = L i-1} + M i-1 ( provided that, L ₁ = 0) when to, demultiplexer, the i th constellation word C _i, bit _{(y Li + 1, y Li} + 2, ..., y _{Li + Mi} , y _{B / 2 + Li + 1} , y _{B / 2 + Li + 2} , ..., y _{B / 2 + Li + Mi} ) Sort and output.

<Receiver>
Hereinafter, a receiver in a communication system according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 14 is a block diagram showing a configuration of receiver 200 in the embodiment of the present invention. The receiver reflects the function of the transmitter. A typical receiver has R receiving antennas, and receives signals transmitted from T transmitting antennas of the transmitter. R and T are not necessarily the same.

  14 includes reception antennas 210-1 to 210-4, RF (radio frequency) front end units 220-1 to 220-4, demodulators 230-1 to 230-4, and a MIMO decoder 240. A multiplexer 250, a bit deinterleaver 260, and an LDPC decoder 270. The MIMO decoder 240 includes a spatial-multiplexing (SM) decoder 241 and QAM demappers 245-1 to 245-4.

  Signals received by the receiving antennas 210-1 to 210-4 are processed by the RF front end units 220-1 to 220-4 and the demodulators 230-1 to 230-4. The RF front end units 220-1 to 220-4 generally include a tuner and a downconverter, select a desired frequency channel by the tuner, and downconvert to a desired frequency band by the downconverter. Demodulators 230-1 to 230-4 obtain one received symbol and T channel fading coefficients for each channel slot. Received symbols and channel fading coefficients are complex values. For each channel slot, R received symbols and T × R channel fading coefficients are supplied as inputs to the SM decoder 241. The SM decoder 241 performs SM decoding using R received symbols and T × R fading coefficients, and outputs T complex QAM symbols. Complex symbols are subjected to QAM constellation demapping, multiplexing, deinterleaving, and LDPC decoding. That is, the exact reverse processing steps in the transmitter of FIGS. 8 and 9 are performed.

The QAM demappers 245-1 to 245-4 respectively perform QAM constellation demapping corresponding to the QAM constellation mapping by the QAM mappers 124-1 to 124-4 included in the transmitter, for the input complex QAM symbols. Do.
The multiplexer 250 performs, on the inputs from the QAM demappers 245-1 to 245-4, processing reverse to that of the demultiplexer 123 included in the transmitter (rearrangement before being rearranged by the demultiplexer 123, processing for multiplexing). .

The bit deinterleaver 260 performs processing reverse to the bit interleaver 122 included in the transmitter with respect to the input from the multiplexer 250 (processing to return the data before being rearranged by the bit interleaver 122), that is, bit deinterleaving. I do.
The LDPC decoder 270 performs LDPC decoding on the input from the bit deinterleaver 260 based on the same QC-LCPC code as the LDPC encoder 121 of the transmitter.

  SM decoding and QAM constellation demapping are sometimes referred to in the art as multiple-input multiple output (MIMO) decoding. In high performance implementations, so-called maximum-likelihood decoding is performed, and SM decoding and QAM constellation demapping are performed jointly in one MIMO decoder 240. These findings are well known in the art.

≪Supplement (Part 1) ≫
The present invention is not limited to the contents described in the above embodiment, and can be implemented in any form for achieving the object of the present invention and the object related thereto or incidental thereto. .
(1) The present invention can be applied to any value (for example, 2, 4, 8, etc.) other than 1 for the number of antennas.

The present invention is applicable to any QAM constellation in which the constellation includes a square QAM constellation (4-QAM, 16-QAM, 64-QAM, 256-QAM, etc.). Note that the value of B is the sum of the number of bits of the constellation to be used.
In the present invention, a pseudo-cyclic parity check code (for example, ETSI EN 302 755 of the DVB-T2 standard) used in second-generation digital video broadcasting standards such as DVB-S2, DVB-T2, and DVB-C2 is used. Any pseudo cyclic parity check code such as the pseudo cyclic parity check code defined in Table A1 to Table 6 is applicable. Note that the values of N and Q vary depending on the pseudo cyclic parity check code used.

  (2) The present invention is not limited to a special form for implementation of a method or device using software or hardware described in the embodiments. The present invention can be executed by a computer, a microprocessor, a microcontroller, etc., in the form of a computer-readable recording medium embodied by computer-executable instructions for executing all the steps according to the above-described embodiments. It may be realized. The present invention may be realized in the form of an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

≪Supplement (Part 2) ≫
The interleaving method, the interleaver, and the transmitter including the interleaving method according to the embodiment, the deinterleaving method, the deinterleaver, the receiver including the interleaving method, and the effect thereof will be summarized.
(1) The first interleaving method is
1 from the code word of the pseudo cyclic low density parity check code, executed in a transmitter in a communication system using pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmission antennas. An interleaving method for rearranging the bits of the codeword in order to generate a plurality of constellation words of the above spatial multiplexing block,
The codeword is composed of N cyclic blocks each consisting of Q bits,
The spatial multiplexing block is composed of B bits, and the spatial multiplexing block is composed of T constellation words,
Each of the constellation words represents one of a plurality of constellation points of a predetermined constellation used for constellation mapping of the constellation word,
A plurality of bits of each said constellation word are divided into bit pairs of the same robust level;
The interleaving method is:
Reordering the bits of the codeword,
At least one said spatial multiplexing block is made up of bits of B / 2 different cyclic blocks;
Each of the constellation words of the at least one spatial multiplex block is made up of bits of B _t / 2 cyclic blocks that are ½ of the number of bits B _t of the constellation word;
Such that each bit pair of each of the constellation words of the at least one spatial multiplexing block is made up of one common cyclic block of B _t / 2 cyclic blocks,
It is characterized by doing.

The first deinterleaving method is
A deinterleaving method performed in a receiver in a communication system using pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas, comprising:
The deinterleaving method is:
A process reverse to the bit rearrangement performed by the first interleaving method is performed on one or more spatial multiplexing blocks composed of a plurality of constellation words.

The first interleaver is
A pseudo cyclic low density parity check code, spatial multiplexing, and a transmitter in a communication system using T (T is an integer greater than 1) transmission antennas include one or more codewords of the pseudo cyclic low density parity check code An interleaver that rearranges the bits of the codeword to generate a plurality of constellation words of a spatial multiplexing block,
The codeword is composed of N cyclic blocks each consisting of Q bits,
The spatial multiplexing block is composed of B bits, and the spatial multiplexing block is composed of T constellation words,
Each of the constellation words represents one of a plurality of constellation points of a predetermined constellation used for constellation mapping of the constellation word,
A plurality of bits of each said constellation word are divided into bit pairs of the same robust level;
The interleaver is
Reordering the bits of the codeword,
At least one said spatial multiplexing block is made up of bits of B / 2 different cyclic blocks;
Each of the constellation words of the at least one spatial multiplex block is made up of bits of B _t / 2 cyclic blocks that are ½ of the number of bits B _t of the constellation word;
Such that each bit pair of each of the constellation words of the at least one spatial multiplexing block is made up of one common cyclic block of B _t / 2 cyclic blocks,
It is characterized by doing.

The first deinterleaver is
A deinterleaver provided in a receiver in a communication system using a pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmission antennas,
The deinterleaver is
Performing reverse processing to the bit rearrangement performed by the first interleaver on T complex symbols corresponding to each of one or more spatial multiplexing blocks composed of a plurality of T constellation words. It is characterized by.

The first transmitter is
A transmitter in a communication system using pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas,
A pseudo cyclic low density parity check encoder that generates a codeword using a pseudo cyclic low density parity check code;
A first interleaver that rearranges the bits of the codeword to output one or more spatial multiplexing blocks;
A constellation mapper that maps each of a plurality of constellation words constituting each of the spatial multiplexing blocks to a complex symbol;
It is characterized by providing.

The first receiver
A receiver in a communication system using a pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas,
A MIMO decoder for converting signals received by a plurality of receiving antennas into T complex symbols corresponding to each of one or more spatial multiplexing blocks including T constellation words;
A first deinterleaver that performs a deinterleaving process on the T complex symbols;
A pseudo cyclic low density parity check decoder that decodes a deinterleaving processing result by the deinterleaver using the pseudo cyclic low density parity check code;
It is characterized by providing.

According to these, the reception performance of the communication system can be improved.
(2) The second interleaving method is the first interleaving method,
When the N is a multiple of B / 2, the N cyclic blocks are divided into a plurality of sections including B / 2 cyclic blocks,
If N is not a multiple of B / 2, NX cyclic blocks excluding the remaining X cyclic blocks divided by B / 2 are divided into a plurality of sections consisting of B / 2 cyclic blocks. ,
The interleaving method is:
Reordering the bits of the codeword,
Furthermore, for the at least one spatial multiplexing block, the spatial multiplexing block is made only from the bits of the B / 2 cyclic blocks divided into one section,
It is characterized by doing.

The second interleaver is the first interleaver,
When the N is a multiple of B / 2, the N cyclic blocks are divided into a plurality of sections including B / 2 cyclic blocks,
If N is not a multiple of B / 2, NX cyclic blocks excluding the remaining X cyclic blocks divided by B / 2 are divided into a plurality of sections consisting of B / 2 cyclic blocks. ,
The interleaver is
Reordering the bits of the codeword,
Furthermore, for the at least one spatial multiplexing block, the spatial multiplexing block is made only from the bits of the B / 2 cyclic blocks divided into one section,
It is characterized by doing.

These enable hardware or software implementation with a high degree of parallelism.
(3) The third interleaving method is the second interleaving method,
The codeword bit rearrangement is performed independently for each of the sections.

The third interleaver is the second interleaver,
The codeword bit rearrangement is performed independently for each of the sections.
According to these, since each section performs bit rearrangement independently of other sections, hardware or software implementation with a high degree of parallelism becomes possible.

(4) The fourth interleaving method is the first interleaving method,
Reordering the bits of the codeword,
further,
In each of the cyclic blocks of at least some of the N cyclic blocks, such that all Q bits of the cyclic block are mapped to the same robust level bits,
It is characterized by doing.

The fourth interleaver is the first interleaver,
Reordering the bits of the codeword,
further,
In each of the cyclic blocks of at least some of the N cyclic blocks, such that all Q bits of the cyclic block are mapped to the same robust level bits,
It is characterized by doing.

  According to these, the bits having the same importance of the code word are mapped to the bits having the same robust level of the constellation word, and matching between the importance and the robust level is obtained. For example, the most significant bit of a codeword is mapped to the bit with the most robust level of the constellation word, and the least significant bit of the codeword is mapped to the bit with the least robust level of the constellation word. You may make it map. In this case, high reliability is obtained for the bits having high importance of the code word at the time of reception, and high reception performance is obtained.

(5) The fifth interleaving method is the first interleaving method,
The predetermined constellation is a square QAM constellation.
The fifth interleaver is the first interleaver,
The predetermined constellation is a square QAM constellation.

  According to these, since the square QAM constellation can be divided into two PAM symbols of the same type that encode the same number of bits, the bit pairs can be easily mapped to bits of the same robust level.

  INDUSTRIAL APPLICABILITY The present invention can be used for bit interleave coding modulation that performs spatial multiplexing using a pseudo cyclic low density parity check code.

DESCRIPTION OF SYMBOLS 100 Transmitter 110 Input processing part 120 BICM encoder 121 LDPC encoder 122 Bit interleaver 123 Demultiplexer 124-1 to 124-4 QAM mapper 125 SM encoder 130-1 to 130-4 Modulator 140-1 to 140-4 Amplifier 150 -1 to 150-4 transmitting antenna 200 receiver 210-1 to 210-4 receiving antenna 220-1 to 220-4 RF front end unit 230-1 to 230-4 demodulator 240 MIMO decoder 241 SM decoder 245-1 245-4 QAM Demapper 250 Multiplexer 260 Bit Deinterleaver 270 LDPC Decoder

Claims (14)

1 from the code word of the pseudo cyclic low density parity check code, executed in a transmitter in a communication system using pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmission antennas. An interleaving method for rearranging the bits of the codeword in order to generate a plurality of constellation words of the above spatial multiplexing block,
The codeword is composed of N cyclic blocks each consisting of Q bits,
The spatial multiplexing block is composed of B bits, and the spatial multiplexing block is composed of T constellation words,
Each of the constellation words represents one of a plurality of constellation points of a predetermined constellation used for constellation mapping of the constellation word,
A plurality of bits of each said constellation word are divided into bit pairs of the same robust level;
The interleaving method is:
Reordering the bits of the codeword,
At least one said spatial multiplexing block is made up of bits of B / 2 different cyclic blocks;
Each of the constellation words of the at least one spatial multiplex block is made up of bits of B _t / 2 cyclic blocks that are ½ of the number of bits B _t of the constellation word;
Such that each bit pair of each of the constellation words of the at least one spatial multiplexing block is made up of one common cyclic block of B _t / 2 cyclic blocks,
Performing an interleaving method. When the N is a multiple of B / 2, the N cyclic blocks are divided into a plurality of sections including B / 2 cyclic blocks,
If N is not a multiple of B / 2, NX cyclic blocks excluding the remaining X cyclic blocks divided by B / 2 are divided into a plurality of sections consisting of B / 2 cyclic blocks. ,
The interleaving method is:
Reordering the bits of the codeword,
Furthermore, for the at least one spatial multiplexing block, the spatial multiplexing block is made only from the bits of the B / 2 cyclic blocks divided into one section,
The interleaving method according to claim 1, wherein the interleaving method is performed. The interleaving method according to claim 2, wherein the rearrangement of the bits of the codeword is performed independently for each of the sections. Reordering the bits of the codeword,
further,
In each of the cyclic blocks of at least some of the N cyclic blocks, such that all Q bits of the cyclic block are mapped to the same robust level bits,
The interleaving method according to claim 1, wherein the interleaving method is performed. The interleaving method according to claim 1, wherein the predetermined constellation is a square QAM constellation. A deinterleaving method performed in a receiver in a communication system using pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas, comprising:
The deinterleaving method is:
The deinterleaving method characterized by performing reverse processing to the bit rearrangement performed by the interleaving method according to claim 1 for one or more spatial multiplexing blocks composed of a plurality of constellation words. A pseudo cyclic low density parity check code, spatial multiplexing, and a transmitter in a communication system using T (T is an integer greater than 1) transmission antennas include one or more codewords of the pseudo cyclic low density parity check code An interleaver that rearranges the bits of the codeword to generate a plurality of constellation words of a spatial multiplexing block,
The codeword is composed of N cyclic blocks each consisting of Q bits,
The spatial multiplexing block is composed of B bits, and the spatial multiplexing block is composed of T constellation words,
Each of the constellation words represents one of a plurality of constellation points of a predetermined constellation used for constellation mapping of the constellation word,
A plurality of bits of each said constellation word are divided into bit pairs of the same robust level;
The interleaver is
Reordering the bits of the codeword,
At least one said spatial multiplexing block is made up of bits of B / 2 different cyclic blocks;
Each of the constellation words of the at least one spatial multiplex block is made up of bits of B _t / 2 cyclic blocks that are ½ of the number of bits B _t of the constellation word;
Such that each bit pair of each of the constellation words of the at least one spatial multiplexing block is made up of one common cyclic block of B _t / 2 cyclic blocks,
An interleaver characterized by performing. When the N is a multiple of B / 2, the N cyclic blocks are divided into a plurality of sections including B / 2 cyclic blocks,
If N is not a multiple of B / 2, NX cyclic blocks excluding the remaining X cyclic blocks divided by B / 2 are divided into a plurality of sections consisting of B / 2 cyclic blocks. ,
The interleaver is
Reordering the bits of the codeword,
Furthermore, for the at least one spatial multiplexing block, the spatial multiplexing block is made only from the bits of the B / 2 cyclic blocks divided into one section,
The interleaver according to claim 7, wherein the interleaver is performed. The interleaver according to claim 8, wherein the rearrangement of the bits of the codeword is performed independently for each of the sections. Reordering the bits of the codeword,
further,
In each of the cyclic blocks of at least some of the N cyclic blocks, such that all Q bits of the cyclic block are mapped to the same robust level bits,
The interleaver according to claim 7, wherein the interleaver is performed. The interleaver according to claim 7, wherein the predetermined constellation is a square QAM constellation. A deinterleaver provided in a receiver in a communication system using a pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmission antennas,
The deinterleaver is
8. The reverse processing to the bit rearrangement performed by the interleaver according to claim 7, for T complex symbols corresponding to each of one or more spatial multiplexing blocks composed of a plurality of T constellation words. A deinterleaver characterized in that it performs. A transmitter in a communication system using pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas,
A pseudo cyclic low density parity check encoder that generates a codeword using a pseudo cyclic low density parity check code;
The interleaver according to claim 7, wherein the interleaver outputs one or more spatial multiplexing blocks by rearranging the bits of the codeword.
A constellation mapper that maps each of a plurality of constellation words constituting each of the spatial multiplexing blocks to a complex symbol;
A transmitter comprising: A receiver in a communication system using a pseudo cyclic low density parity check code, spatial multiplexing, and T (T is an integer greater than 1) transmit antennas,
A MIMO decoder for converting signals received by a plurality of receiving antennas into T complex symbols corresponding to each of one or more spatial multiplexing blocks including T constellation words;
The deinterleaver according to claim 12, wherein a deinterleaving process is performed on the T complex symbols.
A pseudo cyclic low density parity check decoder that decodes a deinterleaving processing result by the deinterleaver using the pseudo cyclic low density parity check code;
A receiver comprising:

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