JP2014232956A - Imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging device capable of rapidly displaying an index screen while suppressing circuit scale and power consumption.SOLUTION: An imaging device comprises: imaging means; and first and second processing circuits. The first processing circuit including a first CPU and first communication means records image data acquired from the imaging means, in a recording medium; and stores the acquired image data in a first memory. The second processing circuit including a second CPU and second communication means records image data acquired from the imaging means, in the recording medium; stores the acquired image data in a second memory; and displays an index screen of the image data recorded in the recording medium by using the image data stored in the second memory according to an instruction to display the index screen. The second CPU issues an instruction to transfer image data to the first processing circuit according to completion of recording the image data in the recording medium according to the imaging instruction.

Description

  The present invention relates to an imaging apparatus, and more particularly to an imaging apparatus that records a moving image.

  2. Description of the Related Art Conventionally, an imaging device such as a digital camera that captures a moving image and records it on a recording medium such as a memory card is known (for example, Patent Document 1). In recent years, consumer digital cameras that can take images with a large number of pixels have also appeared.

  When the number of pixels of an image to be captured increases, the amount of data to be processed increases. In particular, during continuous shooting of still images, it is necessary to process image data faster than before. In order to increase the processing capacity of the image data, a processing circuit such as a memory having a large storage capacity and a high-speed access and a microcomputer capable of processing the image data at a higher speed is required.

  However, using such a high-performance memory or microcomputer leads to an increase in circuit scale and an increase in power consumption. A consumer digital camera may not be able to use a high-performance memory or microcomputer because of restrictions on size and cost, or due to a demand for minimizing power consumption.

  Therefore, it is conceivable to provide a plurality of processing circuits and process and record the captured images in parallel by the plurality of processing circuits. Also, when playing back recorded images, an index screen including a list of reduced images (thumbnail) images of the recorded images is displayed, and an image selected by the user from the thumbnail images displayed on the index screen is played back Is common.

JP 2005-101835 A

  When the index screen is displayed, it is necessary to reduce the screen size after reproducing and decoding the image data from the recording medium. Therefore, there is a problem that it takes time to display the index screen. Therefore, when the captured image is stored in the memory and the index screen is displayed, the image data stored in the memory is reduced and displayed, so that the index screen can be displayed quickly after shooting. Conceivable.

  However, as described above, when images recorded by a plurality of processing circuits are stored in a memory, each processing circuit needs to read image data from the memory and generate an index screen. For this reason, it may be time-consuming to display.

  An object of the present invention is to solve such problems and to provide an imaging apparatus capable of quickly displaying an index screen while suppressing the circuit scale and power consumption.

  According to an aspect of the present invention, a first processing circuit having an imaging unit, a first CPU, and a first communication unit records image data acquired from the imaging unit in response to a shooting instruction. A second processing circuit that has a first processing circuit that records the acquired image data in a first memory and stores the acquired image data in a first memory, a second CPU, and a second communication means, In response, the image data acquired from the imaging means is recorded on the recording medium, the acquired image data is stored in the second memory, and the image stored in the second memory in response to an index screen display instruction is stored. A second processing circuit for displaying an index screen of the image data recorded on the recording medium using the data, and the second CPU finishes recording of the image data on the recording medium in response to a shooting instruction According to before An image data transfer instruction is issued to the first processing circuit, and image data transmitted from the first processing circuit in response to the transfer instruction is stored in the second memory. An apparatus is provided.

  According to the present invention, it is possible to quickly display an index screen while suppressing the circuit scale and power consumption.

1 is a block diagram illustrating a configuration of an imaging device according to an embodiment. 7 is a flowchart showing processing at the time of recording by the processing circuit 200. 5 is a flowchart showing processing at the time of recording by the processing circuit 100. 5 is a flowchart showing index image reception processing by the processing circuit 200; 5 is a flowchart showing index image transmission processing by the processing circuit 100; The flowchart which shows the display process of an index screen.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the following embodiment, It shows only the specific example advantageous for implementation of this invention. Moreover, not all combinations of features described in the following embodiments are indispensable for solving the problems of the present invention.

  FIG. 1 is a block diagram illustrating an exemplary configuration of an imaging apparatus 500 according to an embodiment of the present invention. The imaging apparatus 500 includes two processing circuits 100 (first processing circuit) and a processing circuit 200 (second processing circuit). In the present embodiment, each of these two processing circuits 100 and 200 is configured as one integrated circuit (IC).

  In addition, a data bus 300 for performing communication between the two processing circuits 100 and 200 is provided. The processing circuits 100 and 200 can acquire moving image data from the imaging unit 400 independently of each other. Each of the processing circuits 100 and 200 can process moving image data acquired from the imaging unit 400.

  Next, the configuration of the processing circuit 100 and the processing circuit 200 will be described. The processing circuit 100 includes an image processing unit 101, a CPU 102 (Central Processing Unit) (first CPU), a memory 103, a recording / reproducing unit 104, a codec unit 105, a communication unit 106, and a bus 107. In this embodiment, an SDRAM is used as the memory 103. Further, the memory 103 is built in the processing circuit 100, but may be provided outside the processing circuit 100.

  The CPU 102 controls the operation of the entire imaging apparatus 500 according to a computer program (software) stored in the memory 103. The memory 103 functions as a work area for the CPU 102. The work area of the CPU 102 is not limited to the memory 103, and may be an external recording device such as a hard disk drive. The image processing unit 101 performs image processing such as pixel interpolation processing and color conversion processing on still image data acquired from the imaging unit 400. The image processing unit 101 converts moving image data in the RGB color space acquired from the imaging unit 400 into a data format in the YUV color space. Further, the image processing unit 101 reduces or enlarges (resizes) the number of pixels (screen size) of the image acquired by the imaging unit 400.

  The imaging unit 400 and the image processing unit 101 are controlled by the CPU 102 to perform autofocus (AF) processing and automatic exposure control (AE) processing. When the CPU 102 instructs to perform shooting, the imaging unit 400 and the image processing unit 101 execute shooting processing including processing such as exposure processing and development processing. The imaging unit 400 includes an imaging element such as a CCD or CMOS, an AD converter, and the like. The imaging unit 400 converts an analog signal obtained by the imaging element into digital data and outputs the digital data. The still image data acquired from the imaging unit 400 is stored in the memory 103 as YUV format still image data. The still image data stored in the memory 103 is encoded by the codec unit 105 (first encoding unit, first decoding unit), and the data amount of the still image data is compressed.

  The recording / playback unit 104 writes the encoded still image data in the recording medium 211 during recording. The codec unit 105 encodes still image data acquired from the imaging unit 400 by a known encoding method such as JPEG at the time of shooting.

  The communication unit 106 (first communication unit) transmits and receives moving image data and other necessary commands to and from the processing circuit 200. The communication unit 106 includes a data reception unit 106a for receiving moving image data, a data transmission unit 106b for transmitting image data, and a message communication unit 106c for sending messages such as control commands. Communication in the communication unit 106 is performed via a dedicated data bus 300. Each communication can be performed independently.

  In the present embodiment, as will be described later, after continuous shooting, the index image data processed by the processing circuit 100 is transmitted to the processing circuit 200 by the communication unit 106.

  The processing circuit 200 includes an image processing unit 201, a CPU 202 (second CPU), a memory 203, a recording / playback unit 204, a codec unit 205, a communication unit 206, a file control unit 207, a display unit 208, an operation unit 209, and a bus 210. Have. In the present embodiment, an SDRAM is used as the memory 203. Further, although the memory 203 is built in the processing circuit 100, the memory 203 can be provided outside the processing circuit 200. Each block of the image processing unit 201, CPU 202, memory 203, codec unit 205, and communication unit 206 (second communication unit) has the same function as each block in the processing circuit 100.

  At the time of shooting, the processing circuit 200 acquires moving image data from the imaging unit 400 and performs encoding processing by the codec unit 205 (second encoding unit, second decoding unit). The recording / playback unit 204 records still image data encoded by the codec unit 205 on the recording medium 212 during recording. The recording medium 211 is a random access medium such as a memory card. Further, in the present embodiment, mounting and discharging can be easily performed by a mounting and discharging mechanism (not shown). Further, the recording medium 211 may be built in the imaging apparatus 500. The CPU 202 controls recording of still image data in accordance with the number of pixels specified by the operation unit 209 and the image quality setting. The recording / playback unit 204 reads still image data selected by the user from the recording medium 211 during playback, as will be described later. The codec unit 205 decodes still image data read from the recording medium 211 during reproduction.

  The image processing unit 201 (second resizing unit) changes the image size of the moving image data acquired from the imaging unit 400 according to the size of the display unit 208 and stores it in the memory 203 at the time of shooting. Then, the resized data is supplied to the display unit 208 and displayed. At the time of reproduction, the image processing unit 201 changes the size of the reproduced still image data in accordance with the size of the display unit 208 and stores it in the memory 203. Then, the resized data is supplied to the display unit 208 and displayed. The display unit 208 displays various necessary information in addition to the captured image and the reproduced image. The CPU 202 generates information to be displayed on the display unit 208 and sends it to the display unit 208.

  The file control unit 207 manages still images recorded on the recording medium 211 as files according to a predetermined file system. In the present embodiment, image files recorded on the recording medium 211 are managed according to the FAT file system. In the present embodiment, the file control unit 207 is provided in the processing circuit 200. The file control unit 207 reads management information (such as FAT and directory entry) related to the file system from the recording medium 211 when the power is turned on or when a recording medium is loaded, and stores the management information in the memory 203. Then, the management information stored in the memory 203 is changed (updated) with the recording process on the recording medium 211. Then, management information is read from the memory 203 at a predetermined timing such as when a still image is recorded, and is recorded on the recording medium 211 by the recording / playback unit 204, thereby updating the management information on the recording medium 212.

  The operation unit 209 functions as a user interface for operating the imaging apparatus 500. The operation unit 209 includes a power button for operating the imaging apparatus 500, a mode change button, a shutter button, a cross button, a menu button, and the like, and each button includes a switch, a touch panel, and the like. The CPU 202 controls the imaging device 500 in accordance with a user instruction input via the operation unit 209. When a button on the operation unit 209 is operated by the user, an operation signal corresponding to each button is input from the operation unit 209 to the CPU 202. The CPU 202 analyzes the operation signal input from the operation unit 209 and determines processing corresponding to the operation signal according to the analysis result. The CPU 202 controls each unit of the imaging device 500 so as to execute processing corresponding to the operation signal input from the operation unit 209. In addition, when the shutter button of the operation unit 209 is continuously operated by the user, the CPU 202 performs continuous shooting of still images by issuing shooting instructions continuously at a predetermined timing.

  Next, processing at the time of recording in the imaging apparatus 500 will be described. FIG. 2 is a flowchart showing processing at the time of recording in the processing circuit 200. The processing in FIG. 2 is executed by the CPU 202 controlling each unit. First, prior to recording, the file control unit 207 determines a free area in the recording medium 211 based on management information (FAT) read from the recording medium 211. The file control unit 207 determines a write address for writing data to the recording medium 211 based on the free space.

  When there is an instruction to shoot a still image from the operation unit 209, the CPU 202 communicates through the communication unit 206 so that the processing circuit 100 processes a still image captured by the imaging unit 400 in a shooting standby state. It is determined whether or not there is (S201). When the processing circuit 100 is in a standby state, the CPU 202 outputs a photographing instruction to the processing circuit 100 through the communication unit 206 (S213). When the processing circuit 100 is not in the standby state, the CPU 202 acquires one frame of still image data from the imaging unit 400, converts it into YUV color space data in the image processing unit 201, and stores it in the memory 203 (S202). . Next, the CPU 202 encodes the still image data stored in the memory 203 by the codec unit 205 and stores it in the memory 203 (S203). Here, since the still image data stored in the memory 203 is used as an index image, the still image data is held in the memory 203 until the power is turned off or the empty area of the memory 203 is deleted and deleted.

  When the processing of still image data for one screen is completed, the CPU 202 instructs the file control unit 207 to write the encoded data. The file control unit 207 determines a write address from the free area of the recording medium 212 and instructs the recording / playback unit 204 to write data. The recording / playback unit 204 reads the encoded data from the memory 203 and writes it to the designated address of the recording medium 211 (S204). When the data writing is completed, the file control unit 207 updates the contents of the management information stored in the memory 203 and also updates the free area (S205).

  Next, the CPU 202 determines whether or not information on the amount of encoded still image data has been notified from the processing circuit 100 (S206). When the data amount information is notified, the CPU 202 encodes the code by the processing circuit 100 based on the write address of the still image data written immediately before to the recording medium 211 by the recording / playback unit 204 and the notified data amount. Determine the write address of the data. Then, the determined write address is transmitted from the data transmission unit 206a to the processing circuit 100 (S207). In other words, the CPU 202 determines the write address so that the processing circuit 100 writes the encoded data from the beginning of the next cluster after the cluster including the last write address of the still image data written immediately before the continuous shooting.

  After transmitting the write address information in this manner, the CPU 202 determines whether or not a notification of completion of writing of encoded data has been transmitted from the processing circuit 100 (S208). When the writing completion notification is received by the data receiving unit 206b, the CPU 202 instructs the file control unit 207 to update the FAT. The file control unit 207 updates the contents of the FAT stored in the memory 203 in accordance with the writing by the processing circuit 100 (S209).

  Next, the CPU 202 determines whether or not a shooting instruction is operated by the operation unit 209 (S210). If a shooting instruction operation has been performed, the CPU 202 returns to S201 and continues processing. When the shooting instruction operation is not performed, the CPU 202 instructs the recording / playback unit 204 to write the management information stored in the memory 203 to the recording medium 211. The recording / playback unit 204 reads the management information from the memory 203 and records it in the recording medium 211 (S211). Next, the CPU 202 performs a transfer process for transferring the index image from the processing circuit 100 (S212).

  FIG. 3 is a flowchart showing processing at the time of recording in the processing circuit 100. The processing in FIG. 3 is executed by the CPU 102 controlling each unit. The CPU 102 determines whether or not a photographing instruction (see S213 in FIG. 2) is received from the processing circuit 200 through the communication unit 106 (S301). If a shooting instruction has not been received, the process proceeds to S307. When receiving a shooting instruction, the CPU 102 acquires one frame of image data from the imaging unit 400, converts the image data into YUV color space data in the image processing unit 101, and stores the YUV color space data in the memory 103 (S302). Here, the still image data stored in the memory 103 is transferred to the processing circuit 200 as an index image after the recording of the still image is completed. For this reason, the data is retained in the memory 103 until the power is turned off, the empty area of the memory 103 is deleted and deleted, or the transfer to the processing circuit 200 is completed. Next, the CPU 102 transmits the size information of the encoded still image data to the processing circuit 200 by the message communication unit 106c (S304).

  Next, the CPU 102 determines whether or not the write address information (see S207 in FIG. 2) transmitted from the processing circuit 200 in the recording medium 211 has been received (S305). If the write address information has been received, the CPU 102 instructs the recording / playback unit 104 to write the still image data stored in the memory 103 to the designated write address in the recording medium 211. The recording / playback unit 104 reads the encoded still image data from the memory 103 and writes it to the specified write address of the recording medium 211 (S306). When writing of the encoded data is completed, the CPU 102 transmits a writing completion notification to the processing circuit 200 by the message communication unit 106c (S307). (See S208 in FIG. 2.)

  Next, the transfer process will be described. FIG. 4 is a flowchart showing the index image transfer process (S212) in the processing circuit 200. The processing in FIG. 4 is realized by the CPU 202 controlling each unit. First, the CPU 202 issues an index image transfer instruction to the processing circuit 100 through the message communication unit 206c (S401). Next, the CPU 202 determines whether or not the message communication unit 206c has received from the processing circuit 100 a response indicating that all have been transferred (S402). If all the transferred responses are received, the process is terminated. If there is untransferred image data, the data receiving unit 206b receives image data for one-screen index from the processing circuit 100 (S403). When receiving image data, the CPU 202 determines whether or not there is a free area in the memory 203 for storing the image data (S404). If there is a free area, the CPU 202 stores the received image data in the memory 203 (S405). If there is no free space in the memory 203, the CPU 202 secures a free space by deleting the oldest image data from the image data stored in the memory 203 (S406), and stores the received image data.

  FIG. 5 is a flowchart showing the index image transfer process in the processing circuit 100. The processing in FIG. 5 is realized by the CPU 102 controlling each unit. This process is started in response to receiving an index image transfer instruction (see S401 in FIG. 4) from the processing circuit 200 by the message communication unit 106c. First, the CPU 102 determines whether there is untransferred image data among index screen image data stored in the memory 103 (S501). In this embodiment, the CPU 102 stores the transferred information in the memory 103 when the image data stored in the memory 103 is transferred to the processing circuit 200. In this embodiment, the CPU 102 deletes the oldest image data from the image data stored in the memory 103 when there is no free space for storing the image data as the index image in the memory 103. Create free space. Then, the image data of the newly photographed still image is held as image data for the index image. If all the data has been transferred, the CPU 102 transmits a response indicating that all the image data has been transferred to the processing circuit 200 by the message communication unit 106c (see S402 in FIG. 4), and ends the processing (S502). ). On the other hand, when there is untransferred image data, the CPU 102 selects the latest image data from the untransferred image data stored in the memory 103 (S503). Then, the CPU 102 reads the selected image data from the memory 103, and transmits it to the processing circuit 200 by the data transmission unit 106b (S504).

  As described above, after the photographing is completed, the image data for the index image is transmitted from the processing circuit 100 to the processing circuit 200 and stored in the memory 203.

  Next, index screen generation processing during playback will be described. When there is an instruction to display an index screen from the operation unit 209, the CPU 202 generates an index screen. In this embodiment, when there is an instruction to display an index screen, thumbnail images for n screens are generated from the latest images in the order of shooting, and an index screen including these n screen thumbnail images is displayed. Note that the number n of thumbnail images to be displayed on one screen may be determined by the user operating the operation unit 209. In this case, the CPU 102 determines a thumbnail image to be displayed based on the set number of screens n.

  FIG. 6 is a flowchart showing index screen display processing by the processing circuit 200. The processing in FIG. 6 is executed by the CPU 202 controlling each unit. First, the CPU 202 designates one of the thumbnail images determined as described above (S601). Then, the CPU 202 determines whether or not the designated image data is stored in the memory 203 (S602). If the designated image data is stored in the memory 203, the CPU 202 decodes the designated image data by the codec unit 205 (S603). The CPU 202 reduces the size of the image data decoded by the image processing unit 201 and stores it in the storage area for the index screen in the memory 203 (S604). Next, the CPU 202 determines whether or not all thumbnail images to be displayed are stored in the memory 203 and the display preparation is completed (S605). When all thumbnail images are stored in the memory 203 and display preparation is completed, the CPU 202 reads each thumbnail image data from the memory 203, generates an index screen, and displays it on the display unit 208 (S606).

  If the designated image data is not stored in the memory 203 in S602, the CPU 202 inquires of the processing circuit 100 whether or not the designated image data is stored in the memory 103 of the processing circuit 100 by the message communication unit 206c. (S607). As a result, when the message communication unit 206c receives a response from the processing circuit 100 that the designated image data is stored in the memory 103, the CPU 202 instructs the processing circuit 100 to transfer the designated image data. (S608). The CPU 202 receives image data by the data receiving unit 206b (S609), and decodes the designated image data by the codec unit 205. As described above, when the image data related to the display instruction is not stored in the memory 203, the CPU 202 tries to acquire the image data related to the display instruction to the memory 103 of the processing circuit 100.

  If the CPU 202 receives a response indicating that the designated image data is not stored in the memory 103 in S607, the CPU 202 reads the designated image data from the recording medium 211 using the recording / playback unit 204 (S610). In this way, when the CPU 202 fails to acquire the image data related to the display instruction as a result of the trials in S607 to S609, the CPU 202 can acquire the image data related to the display instruction from the recording medium 211. Then, the read image data is decoded by the codec unit 205.

  After the index screen is displayed on the display unit 208 in this way, the user can specify an image to be played by operating the operation unit 209 and can instruct playback. When reproduction is instructed, the CPU 202 reads the designated image data from the recording medium 211 by the recording / reproducing unit 204 and decodes it by the codec unit 205. Then, the decoded still image data is reduced by the image processing unit 201 and displayed by the display unit 208.

  As described above, in the present embodiment, in the configuration in which still images are captured and recorded by the two processing circuits 100 and 200, the image data is transferred from the processing circuit 100 to the processing circuit 200 after the capturing is completed. The transferred image data is stored in the memory 203 in the processing circuit 200. For this reason, when there is an instruction to display an index screen, a thumbnail image is generated from the image data stored in the memory 203 and the index screen can be displayed to quickly display the index screen. Further, during continuous shooting, since image data is not transferred from the processing circuit 100 during continuous shooting, the processing load on the CPUs 102 and 202 can be reduced.

(Other embodiments)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed. In this case, the program and the storage medium storing the program constitute the present invention.

Claims (4)

Imaging means;
A first processing circuit having a first CPU and a first communication unit, which records image data acquired from the imaging unit in response to a shooting instruction on a recording medium and stores the acquired image data in a first A first processing circuit stored in the memory of
A second processing circuit having a second CPU and a second communication unit, which records image data acquired from the imaging unit in response to a shooting instruction on the recording medium and stores the acquired image data in the second processing circuit. A second processing circuit for displaying an index screen of image data recorded on the recording medium using image data stored in the second memory in response to an instruction to display the index screen; With
The second CPU issues an image data transfer instruction to the first processing circuit in response to the end of recording of the image data on the recording medium in response to the photographing instruction, and the second CPU in response to the transfer instruction. An image pickup apparatus, wherein the image data transmitted from the first processing circuit is stored in the second memory.   When the second CPU receives the image data transmitted from the first processing circuit in response to the transfer instruction, the second CPU has a free area for storing the received image data in the second memory. If there is no free space, the free space is secured by deleting the oldest image data from the image data stored in the second memory, and the received image data The imaging apparatus according to claim 1, wherein the imaging apparatus is stored in the second memory.   The second CPU instructs the first processing circuit to transmit the image data according to the display instruction when the image data according to the display instruction is not stored in the second memory. The imaging apparatus according to claim 1, wherein the imaging apparatus is characterized.   The said 2nd CPU acquires the image data which concerns on the said display instruction from the said recording medium, when the image data which concerns on the said display instruction cannot be acquired from the said 1st processing circuit. Imaging device.

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