JP2014230202A - Optical receiver and optical reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hinder degradation of characteristics by improving a sub-carrier that cannot be demodulated, without increasing a sampling rate(=baud rate) in an OFDMA-PON system.SOLUTION: An optical receiver comprises: a photoelectric conversion circuit 1 having a light receiving element 11 that converts a received light signal into an analog electric signal, and TIA 12 that amplifies an analog electric signal; a delay circuit 21 that separates an analog electric signal from the photoelectric conversion circuit 1 into a plurality of analog electric signals; a delay generating circuit 2 having a multiplexing circuit 22 that multiplexes delayed signals again, thereby generating a single analog electric signal; analog digital converter 3 that converts an analog electric signal, output from the delay generating circuit 2, into a digital signal; and a digital signal processing circuit 4 that processes a digital signal output from the analog digital converter 3.

Description

  The present invention relates to an optical receiver and an optical receiving method, and more particularly to an optical receiver and an optical receiving method used in an OFDMA-PON system.

  Research on next-generation optical access systems is underway. As one method for realizing an access system, orthogonal frequency division multiple access (OFDMA), in which a plurality of ONUs (Optical Network Units) connected to a line network perform communication using different orthogonal frequency subcarriers, is provided. Application of the Multiple Access) method is being studied. The ONU generally means a subscriber terminal device used by each user.

  Also, a PON (Passive Optical Network) system is widely used as a method for realizing a public line network using optical fibers. The PON system includes one OLT (Optical Line Terminal) and a plurality of ONUs. The OLT generally means a station side device. The OLT and each ONU are connected via an optical coupler. Therefore, in the PON system, a large number of ONUs can share one OLT and most of the transmission path (optical fiber).

  In the conventional PON system, the time division multiple access (TDMA) method was applied. However, by applying the OFDMA technology, communication that is not interrupted in the time direction and flexible and elastic bandwidth allocation. Is possible. For example, Non-Patent Document 1 discloses a result of an examination of subcarrier multiple access of two ONUs having a transmission capacity of 30 Gbps by applying an IFDMA (Interleaved FDMA) method, which is one of OFDMA methods, to an access system. ing.

  In general, in the OFDMA system, (1) an OFDMA modulation signal in which data is superimposed on each subcarrier using Fast Fourier Transform (FFT), and (2) a guard interval is added to the head of the OFDMA modulation signal. This is a block transmission in which one OFDMA symbol is constituted by a copy of the latter half samples of the OFDM modulated signal called cyclic prefix (CP), and modulation / demodulation processing is performed for each symbol. The cyclic prefix includes the delay time of an incoming wave caused by multipath (in the case of wireless), the waveform spread due to the effect of the transmission path (wireless and optical common), and the arrival timing delay of the accommodated multiple users (ONU) (wireless, Designed to be long enough to absorb light). In other words, the arrival timings of a plurality of ONUs need only be synchronized with accuracy within a cyclic prefix.

  However, on the other hand, if a timing offset equal to or less than the baud rate occurs in the arrival timing of the accommodated ONUs, demodulation is not possible in a system where the sampling rate and the baud rate are equal, that is, the sampling rate = baud rate (single sampling). It is known that possible subcarriers may be generated, and in such a case, a significant deterioration in characteristics is caused.

  In Non-Patent Document 2, when the ideal roll-off filter is assumed to be applied when the sampling rate is equal to the baud rate, the spectrum intensity is 0 in the frequency subcarrier of (sampling rate / 2), and demodulation is impossible. As a solution to that problem, the application of oversampling where sampling rate> baud rate is disclosed. As shown in Non-Patent Document 2, in the field of conventional wireless communication, a signal sampling rate of 2 times or more of the baud rate is generally used. The rate is realized using oversampling higher than the baud rate.

Yuki Yoshida, et al., “Experimental Demonstration of 2xONU 30Gbps Digitally-Supported-Coherent IFDMA-PON Uplink,” OFC / NFOEC 2012, OW3B.5. T. Obara, Kazuki Takeda, and F. Adachi, “Oversampling frequency-domain equalization for single-carrier transmission in the presence of timing offset,” The 6th IEEE VTS Asia Pacific Wireless Communications Symposium (APWCS2009), Ewha Womans University, Seoul, Korea, 20-21 Aug. 2009.

  However, in the field of optical communication, the baud rate for radio signals is very high (for example, the baud rate of 10G-EPON for light is 10 GHz and 32 GHz for a 100 Gbps transponder, whereas the baud rate of LTE (Long Term Evolution) is used. ADC (Analog Digital Converter) circuit and signal processing (DSP: Digital Signal Processing) circuit with a sampling rate that realizes over-sampling twice or more are difficult and very expensive. It becomes. Furthermore, an increase in sampling rate is equivalent to an increase in the number of parallel developments of digital signals, causing an increase in interface circuit and signal processing circuit scale and a significant increase in power consumption.

  In PON systems where low power consumption and low cost are permanent issues, it is required to realize OFDMA-PON at a low sampling rate, but the transmission timing of multiple ONUs can be controlled with an accuracy higher than the baud rate. In order to solve the above problems, it is necessary to increase the sampling rate at the expense of power consumption and cost.

  The present invention has been made to solve such a problem. In the OFDMA-PON system, characteristics are improved by improving subcarriers that cannot be demodulated without increasing the sampling rate (sampling rate = baud rate). An object of the present invention is to obtain an optical receiver and an optical receiving method capable of suppressing deterioration of the optical signal.

  The present invention provides a photoelectric conversion circuit having a light receiving element that converts a received optical signal into an analog electric signal and an amplification circuit that amplifies the analog electric signal, and the analog electric signal from the amplification circuit of the photoelectric conversion circuit. A delay generation circuit having a delay circuit that branches into a plurality of signals and delays each branched signal; and a multiplexing circuit that combines the delayed signals again to generate a single analog electric signal; An analog-digital conversion circuit that converts the analog electrical signal output from the multiplexing circuit of the delay generation circuit into a digital signal; and a digital signal processing circuit that processes the digital signal output from the analog-digital conversion circuit. An optical receiver provided.

  The present invention provides a photoelectric conversion circuit having a light receiving element that converts a received optical signal into an analog electric signal and an amplification circuit that amplifies the analog electric signal, and the analog electric signal from the amplification circuit of the photoelectric conversion circuit. A delay generation circuit having a delay circuit that branches into a plurality of signals and delays each branched signal; and a multiplexing circuit that combines the delayed signals again to generate a single analog electric signal; An analog-digital conversion circuit that converts the analog electrical signal output from the multiplexing circuit of the delay generation circuit into a digital signal; and a digital signal processing circuit that processes the digital signal output from the analog-digital conversion circuit. In the OFDMA-PON system, the sampling rate is not increased (sampling rate). Preparative = baud rate), to improve the subcarriers become impossible demodulation, it is possible to suppress degradation of the characteristics.

It is a block diagram which shows the structure of the optical receiver of the IM-DD system which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the optical receiver of the coherent system which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the OFDMA-POM system which concerns on Embodiment 1-3 of this invention. It is the figure which simulated (1) ONU output and (2) OLT input signal in the OFDMA-POM system which concerns on Embodiment 1-3 of this invention. It is a figure explaining the process of a branch and delay in the delay generation circuit of the optical receiver which concerns on Embodiment 1 of this invention. It is a figure explaining the effect of the optical receiver which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the optical receiver of the IM-DD system which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the optical receiver of the coherent system which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the optical receiver of the IM-DD system which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the optical receiver of the coherent system which concerns on Embodiment 3 of this invention. It is a figure explaining the effect of the optical receiver which concerns on Embodiment 3 of this invention.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing a configuration of an optical receiver according to Embodiment 1 of the present invention. In FIG. 1, an OFDMA-PON OLT optical receiver is taken as an example of the optical receiver according to the first embodiment, and an IM-DD (Intensity Modulation-Direct Detection) system is applied to the OLT optical receiver. The structure when it is made to show is shown.

  In the IM-DD system, an optical signal whose intensity is modulated with a baseband signal is transmitted, and the baseband signal is reproduced and demodulated again by direct detection (intensity detection). In this method, information is put on a change in light intensity.

  The optical receiver shown in FIG. 1 converts an input optical signal into an analog electrical signal, amplifies and outputs the signal, and branches the amplified analog electrical signal into a plurality of branches, and delays each branched signal. A delay generation circuit 2 that re-combines and outputs the delayed signals, an analog-digital converter 3 (ADC circuit) that converts an analog electrical signal output from the delay generation circuit 2 into a digital signal, and the digital It comprises a digital signal processing circuit 4 that processes signals and demodulates them.

  The photoelectric conversion circuit 1 receives a received OFDMA optical signal and converts it into a current (analog electric signal), and a transimpedance as an amplifier circuit that amplifies a weak current signal and converts it into a voltage signal. It comprises an amplifier (TIA: Transimpedance Amplifier) 12. The light receiving element 11 may be configured by a photodiode (PD: Photodiode) or may be configured by an APD (Avalanche Photodiode).

  The delay generation circuit 2 includes n delay circuits 21 to which analog electrical signals branched into n are respectively input, and a multiplexing circuit 22 that re-combines the analog electrical signals to which delays are respectively added by the delay circuit 21. It consists of and. Each delay circuit 21 is a variable delay circuit capable of making the delay amount variable with the sampling period Ts width. Each delay circuit 21 receives one analog electric signal branched into n pieces, and receives a delay amount control signal from the digital signal processing circuit 4. Based on the delay amount control signal, Thus, the delay adjustment up to the sampling period Ts can be performed. Therefore, the delay circuit 21 gives a delay of the sampling period Ts or less to each of the n analog electric signals branched based on the delay amount control signal. Further, the multiplexing circuit 22 receives analog electric signals to which the respective delays are added from the delay circuit 21, and receives the gain control signal from the digital signal processing circuit 4 to input those analog signals to which the delay has been added. For each electrical signal, the gain is adjusted by the gain control signal and then combined. Note that the number n of analog electrical signals in the delay generation circuit 2 is equal to the number of ONUs accommodated by the OFDMA-PON system (n = ONU number).

  The analog-digital converter 3 samples a continuous analog electric signal output from the delay generation circuit 2 at the same sampling frequency (sampling period Ts) as the baud rate of the signal band, and converts it into a digital signal.

  In addition to the demodulation processing circuit 43 that processes and demodulates the OFDMA signal, the digital signal processing circuit 4 evaluates the reception characteristics of each ONU, and the delay of the delay circuit 21 from the reception characteristics of each ONU. And a control circuit 42 that calculates and outputs a delay amount control signal for controlling the amount and a gain control signal for controlling the gain of the multiplexing circuit 22. The evaluation circuit 41 evaluates reception characteristics for each ONU using, for example, an error rate calculation circuit using statistical data of the primary modulation signal, or an error correction code (FEC: Forward Error Correction). Further, the control circuit 42 searches for the delay amount with the best reception characteristics for each of the n ONUs based on the evaluation result, determines the delay amount, and based on the evaluation result, The gain is controlled for each of the n ONUs so that the waved signal follows the input width of the analog-digital converter 3.

  FIG. 1 shows the configuration when the IM-DD scheme is applied. However, the present invention is not limited to this configuration, and a coherent scheme that can improve the optical reception sensitivity by 10 to 25 dB as compared with the IM-DD scheme. It is also possible to apply to the first mode. The coherent method is an important technology when constructing an optical network using a wide frequency band of light.

  FIG. 2 is a configuration diagram showing the configuration of the OFDMA-PON OLT optical receiver according to the first embodiment when the coherent scheme is applied. In FIG. 2, as an optical receiver according to the first embodiment, an OFDMA-PON OLT optical receiver is taken as an example, as in FIG. However, FIG. 2 is different from FIG. 1 in that a coherent scheme is applied to the OLT optical receiver. In FIG. 2, the same reference numerals as those in FIG. 1 are given to the components corresponding to the respective components in FIG. 1, and “b” is added after the reference symbols.

  The optical receiver shown in FIG. 2 has a coherent photoelectric conversion circuit 1b that receives an OFDMA optical signal, converts it into an analog electric signal, amplifies it, and outputs it, branches the analog electric signal, and outputs an arbitrary signal to each of the branched signals. A delay generation circuit 2b that applies a delay and combines the delayed signals again, and a continuous analog signal output from the delay generation circuit 2b is sampled at the same sampling frequency (sampling period Ts) as the baud rate of the signal band. An analog-digital converter 3b for converting into a digital signal and a digital signal processing circuit 4b for processing and demodulating the digital signal from the analog-digital converter 3b.

  The photoelectric conversion circuit 1b is a laser 11b that oscillates local oscillation light (LO light), and an optical signal that is split into two signals for Ich and Qch, and is output by mixing each with LO light. A 90-degree hybrid 12b and a balanced receiver 13b that converts an optical signal output from the optical 90-degree hybrid 12b into an analog electric signal, amplifies it, and outputs it. The balanced receiver 13b is a balanced PD as a light receiving element that converts an optical signal interfered by the optical 90-degree hybrid 12b into an analog electrical signal (current), and an amplification circuit that amplifies and outputs the analog electrical signal. It consists of TIA.

  The delay generation circuit 2b receives n Ich delay circuits 21b to which n analog electrical signals branched for Ich are input and n analog electrical signals branched to Qch respectively. N Qch delay circuits 21b, an Ich multiplexing circuit 22b that multiplexes the analog electrical signals to which the respective delays are added by the Ich delay circuit 21b, and a Qch delay circuit 21b. It comprises a Qch multiplexing circuit 22b for again multiplexing the analog electrical signals to which the respective delays have been added.

  Each of the Ich and Qch delay circuits 21b is supplied with one analog electrical signal branched into 1 each for Ich and Qch, and for each analog electrical signal from the digital signal processing circuit 4b. N delay amount control signals are input, and based on the delay amount control signal, the delay adjustment can be performed up to the sampling period Ts at the maximum. Also, the Ich and Qch multiplexing circuit 22b receives analog electrical signals to which the respective delays are added from the Ich and Qch delay circuits 21b, and each analog electrical signal from the digital signal processing circuit 4b. Each of the n gain control signals is input, and the analog electric signals to which the delay is added are combined by adjusting the gain by the gain control signal. Further, the number n of branches of the analog electric signal is equal to the number of ONUs accommodated (n = number of ONUs).

  The analog-digital converter 3b samples the continuous analog electric signal output from the delay generation circuit 2b at the same sampling frequency (sampling period Ts) as the baud rate of the signal band, and converts it into a digital signal.

  In addition to the demodulation processing circuit 43b that processes and demodulates the OFDMA signal, the digital signal processing circuit 4b evaluates the reception characteristics of each ONU, and the delay of the delay circuit 21b from the reception characteristics of each ONU. A control circuit 42b for calculating and outputting a delay amount control signal for controlling the amount and a gain control signal for controlling the gain of the multiplexing circuit 22b.

  As described above, in the case of the coherent OFDMA-PON OLT optical receiver configuration shown in FIG. 2, since two types of signals for Ich and Qch are formed in the analog front end, the circuit is doubled. However, the functions and operations of the delay circuit 21b, the multiplexing circuit 22b, the demodulation processing circuit 43b, the evaluation circuit 41b, and the control circuit 42b are the same as those of the IM-DD type OFDMA-PON OLT optical reception shown in FIG. It is the same as the vessel.

  Next, the operation of the optical receiver according to the first embodiment shown in FIGS. 1 and 2 will be described. The operation of the optical receiver according to the first embodiment shown in FIGS. 1 and 2 is basically the same. Therefore, in the following description, in order to simplify the description, the operation will be described using the configuration of FIG. 1 as an example, and FIG. 2 will be omitted. FIG. 3 is a diagram illustrating a configuration of the OFDMA-PON system. As shown in FIG. 3, the OFDMA-PON system has a configuration in which a plurality of ONUs 100 (n in this case) are accommodated in one OLT 103 through an optical fiber 101 and an optical coupler 102. The OLT 103 uses the optical receiver of the first embodiment. The ONU 100 accommodated in the OLT 103 transmits a signal using subcarriers not used by other ONUs 100 in synchronization with accuracy within the cyclic prefix length by the subcarrier allocation control signal and the transmission timing control signal from the OLT 103. . A diagram simulating the optical signal output from each ONU 100 before being multiplexed by the optical coupler 102 (FIG. 3 (1)) is shown in the left side of FIG. 4 ((1) ONU output signal). Further, a diagram simulating an optical signal input to the OLT 103 after being multiplexed by the optical coupler 102 (FIG. 3 (2)) is shown on the right side of FIG. 4 ((2) OLT input signal).

  A normal OFDMA signal is created as a discrete signal by a digital signal processing circuit on the transmission side, and is converted from a digital discrete signal to an analog continuous signal by a DAC (Digital Analog Converter) circuit and transmitted. The ideal sampling point is different. Therefore, the combined OLT input signal (the diagram on the right side of FIG. 4) becomes a single analog signal having an ideal sampling point that differs for each ONU 100.

  The OFDMA optical signal input to the OLT 103 is first converted into an electrical analog signal by the photoelectric conversion circuit 1 as shown in FIG. The converted electrical signal is input to the delay generation circuit 2 and branched into n paths. Different amounts of delay are given to the branched signals by the delay circuit 21. The delayed signal is amplified with an arbitrary gain by the multiplexing circuit 22 and combined to regenerate a single analog signal. The analog signal generated again is converted from an analog signal into a digital signal having a sampling rate of 1 times by the analog-digital converter 3 and is passed to the digital signal processing circuit 4. The digital signal processing circuit 4 performs timing and frequency synchronization on the input digital signal as necessary, performs channel estimation and equalization processing, performs demodulation processing on the primary modulation signal, and finally , Converted into bits by demapping processing. In the first embodiment, the digital signal processing circuit 4 uses an error rate calculation circuit using statistical data of the primary modulation signal or an evaluation circuit 41 using an error correction code (FEC) or the like for each ONU. The control circuit 42 controls the delay amount and gain used in the delay generation circuit 2 according to the evaluation result.

  The delay circuit 21 is a delay circuit that can adjust the delay of the sampling period Ts at the maximum, and is set to Ts / 2 as the initial delay amount. The n delay circuits 21 correspond to n ONUs # 1 to #n (reference numeral 100), respectively, and the delay circuit # 1 (reference numeral 21) is used to optimize the timing of the ONU # 1 (reference numeral 100). Delay circuit # 2 (symbol 21) for optimizing the timing of ONU # 2 (symbol 100), and delay circuit #n (symbol 21) for optimizing the timing of ONU #n (symbol 100), respectively. Use. Since the sampling timing offset causes characteristic deterioration as it moves away from the ideal sample point, the reception characteristics BER # 1 of ONUs # 1 to #n (reference numeral 100), which are evaluation results in the evaluation circuit 41 of the digital signal processing circuit 4, are obtained. The control circuit 42 assigns a delay amount (delay value) to each of the ONUs 100 in a time-sharing manner at the beginning of communication so that .about. # N is the best. Search control is performed. When the delay amount for all ONUs 100 is determined by the search, the control circuit 42 outputs a delay amount control signal indicating the delay amount to each delay circuit 21, and the delay circuit 21 receives the delay amount control signal. 5, an optimum delay is given to each ONU 100 and output to the multiplexing circuit 22 as shown in FIG. In the multiplexing circuit 22, the signals from the delay circuit 21 are received and combined. However, since the combined signal has an excessive amplitude, the signals are multiplexed so as to follow the input width of the analog-digital converter 3. It is necessary to control the gain. Therefore, the control circuit 42 adjusts the gain for each of the n ONUs 100 based on the reception characteristics BER # 1 to #n of the ONUs # 1 to #n (reference numeral 100) that are the evaluation results of the evaluation circuit 41, The n gain control signals for each signal are output to the multiplexing circuit 22. As described above, the control circuit 42 controls the delay amount and the gain by the feedback control using the evaluation result of the reception characteristic for each ONU by the evaluation circuit 41. Further, at the time of this multiplexing, weighting may be performed by changing the gain of the output of each delay circuit 21.

  In the above description, the configuration of the IM-DD optical receiver in FIG. 1 has been described as an example, but the operation is the same in the configuration of the coherent optical receiver illustrated in FIG. The description is omitted here. In the configuration of FIG. 2, the delay amount of delay circuits # 1 to #n (reference numeral 21b) prepared in each ONU 100 and the gain of the multiplexing circuit 22 are controlled to the same value on the Ich side and the Qch side.

Next, effects of the optical receiver according to Embodiment 1 will be described.
For example, under the conditions of the number of accommodated users n = 8, the number of frequency subcarriers 128, the cyclic prefix 8, the primary modulation scheme QPSK, and the reception SNR = 30 dB, the case of applying the first embodiment and the reception by 1 time sampling The received Q value characteristics of any 1 ONU were compared in the case of the case and when the oversampling of 2 times was applied. The results are shown in FIG. In FIG. 6, Δ is a graph of the first embodiment, ○ is a one-time sampling, and □ is an oversampling graph. Referring to FIG. 6, in the 1 × sampling and the first embodiment, the highest Q value characteristic can be obtained when there is no deviation from the ideal sample point. As the deviation from the point increases, the characteristic (Q value) deteriorates. As described in Non-Patent Document 2, this is due to the influence of aliasing noise from outside the band when the signal is converted into a discrete signal, and in particular, a point that cannot be demodulated by 1 × sampling occurs. In this condition, compared with the case where oversampling is applied, characteristic deterioration of about 14 dB is caused. On the other hand, when the first embodiment is applied, even if a reception timing offset occurs, the characteristic deterioration can be prevented, and the characteristic deterioration is improved to about 2 dB. In the first embodiment, since the reception timing is adjusted for each ONU 100 to be accommodated, it is possible to avoid the condition that all the ONUs 100 cannot demodulate. It is possible to prevent deterioration of characteristics. Furthermore, since oversampling is not applied, an inexpensive analog-digital converter can be used, an inexpensive digital signal processing circuit can be applied, and the power consumption of a signal processing circuit with high power consumption can be reduced.

  As described above, the optical receiver according to the first embodiment includes a photoelectric conversion circuit 1 including a light receiving element that converts a received optical signal into an analog electric signal and a TIA as an amplifier circuit that amplifies the analog electric signal. 1b and the analog electric signals from the amplifier circuits of the photoelectric conversion circuits 1 and 1b are branched into a plurality of signals, and the delay circuits 21 and 21b that give a delay to each of the branched signals and the signals that give the delay are combined again. The delay generation circuits 2 and 2b having the multiplexing circuits 22 and 22b that regenerate a single analog electric signal, and the analog electric signals output from the multiplexing circuits 22 and 22b of the delay generation circuits 2 and 2b are converted into digital signals. Analog-digital converters 3 and 3b for converting to digital signals, and digital signal processing circuits 4 and 4b for processing digital signals output from the analog-digital converters 3 and 3b To have. With this configuration, the received signal is branched, and a delay equal to or shorter than the sampling period Ts is given to each branched signal, and the reception timing is adjusted for each ONU. Therefore, a condition that cannot be demodulated in all ONUs is avoided. It becomes possible to do. In conventional 1 × sampling rate optical receivers, there were subcarriers that could not be demodulated due to folding from outside the signal band, so there was no solution other than applying oversampling that would cause excessive power consumption. By applying the configuration of the first embodiment, the analog-to-digital converters 3 and 3b convert the analog signal to a digital signal having a 1-times sampling rate without increasing the sampling rate (sampling rate = boat rate). By improving subcarriers that cannot be demodulated, characteristics can be improved without applying oversampling. Note that the delay amount is controlled by feedback control using the evaluation results so that the evaluation circuits 41 and 41b evaluate the reception characteristics of the OFDMA optical signal for each ONU, and the delay amount provides the best reception characteristics. As a result, the reception characteristics can be greatly improved. Also, the gain is controlled by feedback control using the evaluation results of the evaluation circuits 41 and 41b so as to follow the input width of the analog-digital converter 3 so that the amplitude does not become excessive due to multiplexing. Since it did in this way, the expansion of the amplitude by multiplexing is suppressed and appropriate gain control can be performed. In the first embodiment, since oversampling is not applied, an inexpensive analog-digital converter can be used, an inexpensive digital signal processing circuit can be applied, and a low power consumption of a signal processing circuit with high power consumption is achieved. It leads to electric power. Further, in the first embodiment, after branching, the analog signal is recombined at the stage of analog signals. Therefore, only one demodulation processing circuit for performing demodulation is provided, so the configuration of the digital signal processing circuit is The effect that it can be simplified is obtained.

Embodiment 2. FIG.
FIG. 7 is a configuration diagram showing the configuration of the optical receiver according to Embodiment 2 of the present invention. In FIG. 7, as an optical receiver according to the second embodiment, an OFDM-PON OLT optical receiver of the IM-DD scheme will be described as an example.

  The optical receiver shown in FIG. 7 converts an input optical signal into an analog electric signal (current), amplifies and outputs the signal, and branches the amplified analog electric signal into a plurality of branched signals. A delay generation circuit 2c that delays the signal, and combines and outputs the delayed signals, and an analog-digital converter 3 (ADC circuit) that converts the analog electric signal output from the delay generation circuit 2c into a digital signal; , And a digital signal processing circuit 4c that processes and demodulates the digital signal.

  The photoelectric conversion circuit 1 has the same configuration as the photoelectric conversion circuit 1 in FIG. 1 and performs the same operation. That is, the photoelectric conversion circuit 1 receives a received OFDMA optical signal and converts it into a current (analog electrical signal), and an amplification circuit that amplifies a weak current signal and converts it into a voltage signal. It comprises a transimpedance amplifier (TIA) 12. The light receiving element 11 may be composed of PD or APD.

  The delay adjustment circuit 2c again combines the n delay circuits 21c (delay circuits # 1 to #n) to which the n analog electrical signals are respectively input and the analog electrical signals to which the respective delays are added. And a wave multiplexing circuit 22c. The delay circuit 21c (delay circuits # 1 to #n) is a fixed delay circuit in which a fixed delay amount is set in advance. Each of the analog electric signals branched into n pieces is inputted and individually inputted. Based on the set delay amount, the delay adjustment up to the sampling period Ts is performed at the maximum. Further, the multiplexing circuit 22c receives the analog electric signals to which the respective delays are added from the delay circuit 21c, and receives the gain control signal from the digital signal processing circuit 4c, and those analog signals to which the delay is added. The gain is adjusted by adjusting the gain of the electric signal by the gain control signal. Further, the number n of branches of the analog electric signal is equal to the number of ONUs accommodated (n = number of ONUs).

  The analog-digital converter 3 has the same configuration as the analog-digital converter 3 in FIG. 1 and performs the same operation. That is, the analog-digital converter 3 samples a continuous analog electric signal output from the delay generation circuit 2c at the same sampling frequency (sampling period Ts) as the baud rate of the signal band, and converts it into a digital signal.

  In addition to the demodulation processing circuit 43c that processes and demodulates the OFDMA signal, the digital signal processing circuit 4c includes an evaluation circuit 41c that evaluates the reception characteristics of each ONU, and the reception characteristics of each ONU. A control circuit 42c that calculates and outputs a gain control signal for controlling the gain. The difference from the digital signal processing circuit 4 in FIG. 1 is that the control circuit 42 c does not control the delay amount of the delay circuit 21 in the digital signal processing circuit 4 c in FIG. 7. The configuration and operation of the demodulation processing circuit 43c and the evaluation circuit 41c are the same as the configuration and operation of the demodulation processing circuit 43 and the evaluation circuit 41 of FIG.

  The difference between the configuration of the optical receiver of FIG. 1 and the configuration of the optical receiver of FIG. 7 is that the delay amount of the delay circuit 21 of the delay generation circuit 2 is variable in FIG. Although the delay amount is controlled by the circuit 42, in FIG. 7, the delay amount of the delay circuit 21c of the delay generation circuit 2c is fixed, and the control circuit 42c of the digital signal processing circuit 4c controls the delay amount. The difference is that the control circuit 42c determines a path that gives a delay in which the characteristic is improved most in each ONU, using the evaluation result of the characteristic by the evaluation circuit 41c. Other configurations and operations are the same as those in FIG.

  FIG. 8 is a configuration diagram showing a configuration of a coherent optical receiver according to Embodiment 2 of the present invention. The optical receiver shown in FIG. 8 has a coherent photoelectric conversion circuit 1b that receives an OFDMA optical signal, converts it to an analog electric signal, amplifies it, and outputs it, and branches the analog electric signal, and fixes the signal to each of the branched signals. A delay generation circuit 2d that gives a delay amount and combines the delayed signals again, and a continuous analog signal output from the delay generation circuit 2d is sampled at the same sampling frequency (sampling period Ts) as the baud rate of the signal band. And a digital signal processing circuit 4d for processing and demodulating the digital signal from the analog-digital converter 3b.

  The difference between the configuration of the optical receiver in FIG. 2 and the configuration of the optical receiver in FIG. 8 is that in FIG. 2, the delay amount of the delay circuit 21b of the delay generation circuit 2b is variable, and the control of the digital signal processing circuit 4b. Although the delay amount is controlled by the circuit 42b, in FIG. 8, the delay amount of the delay circuit 21d of the delay generation circuit 2d is fixed, and the control circuit 42d of the digital signal processing circuit 4d controls the delay amount. The difference is that the control circuit 42c determines a path that gives a delay in which the characteristic is improved most in each ONU, using the evaluation result of the characteristic by the evaluation circuit 41c. Since other configurations and operations are the same as those in FIG. 2, the same reference numerals or the same reference numerals are denoted by “d”, and description thereof is omitted here.

  In the coherent optical receiver of FIG. 8, since two types of signals for Ich and Qch are formed in the analog front end, the circuit is doubled, and the delay circuit 21d and the multiplexing circuit Although 22d is required twice, the configuration and operation are basically the same as those of the IM-DD optical receiver shown in FIG. In the configuration of FIG. 8, the fixed delay amount of the delay circuit 21d (# 1 to #n) prepared in each ONU 100 is set to the same value on the Ich side and the Qch side, and the respective delays are set. The amount is the same value as that of the delay circuit 21c (# 1 to #n) shown in FIG.

  Next, the operation will be described. The operation of the optical receiver according to the second embodiment shown in FIGS. 7 and 8 will be described. The operation of the optical receiver according to the second embodiment shown in FIGS. 7 and 8 is basically the same. Therefore, in order to simplify the description, in the following description, the operation will be described using the configuration of FIG. 7 as an example. The optical receiver shown in the second embodiment is also applied to the OFDMA-PON system shown in FIG. 3 in which a plurality of ONUs 100 are accommodated in one OLT via the optical fiber 101 and the optical coupler 102. Since the OFDMA-PON system configuration and ONU operation are the same as those in the first embodiment, description thereof will not be given here.

  As shown in FIG. 7, the OFDMA optical signal input to the optical receiver according to the second embodiment is first converted into an electrical analog signal by the photoelectric conversion circuit 1. The converted electrical signal is input to the delay generation circuit 2c and branched into N (N ≧ 2) paths. The branched signals are given different delay amounts such as wiring lengths by the fixed delay circuit 21c. The delayed signal is amplified by the multiplexing circuit 22c with a gain based on the gain control signal from the control circuit 42c, and is combined to regenerate a single analog signal. The regenerated analog signal is converted from an analog signal to a digital signal having a 1 × sampling rate by the analog / digital converter 3 and passed to the digital signal processing circuit 4c. In the digital signal processing circuit 4c, timing / frequency synchronization is performed on the digital signal as necessary, channel estimation and equalization processing are performed, demodulation to a primary modulation signal is performed, and finally, bit mapping is performed by demapping processing. Is converted to In the second embodiment, in the digital signal processing circuit 4c, characteristics are evaluated for each ONU using an error rate calculation circuit using statistical data of the primary modulation signal or an evaluation circuit 41c using an error correction code (FEC) or the like. The control circuit 42c controls the gain of each delay path according to the evaluation result.

  As described above, the delay circuits 21c and 21d according to the second embodiment give a delay by a fixed delay amount to each branched path, and can be easily realized by controlling the wiring length. Each delay amount is adjusted such that when the number of branches is N (N ≧ 2) and the sampling period is Ts, each branch path is adjusted to have a different delay time of Ts / N. Compared to the above, the path having the longest delay time is given a delay amount of Ts * (N−1) / N. In the example of FIGS. 7 and 8, delay amount = 0 is given by delay circuit # 1, delay amount = Ts * 1 / N is given by delay circuit # 2, and delay amount = Ts * 2 / N is given by delay circuit # 3. The delay amount = Ts * (N−1) / N is given by the delay circuit #n. The sampling timing offset causes characteristic deterioration as the distance from the ideal sample point increases. Therefore, the multiplexing circuit 22c is controlled so as to select and multiplex a signal passing through the delay path closest to the ideal sample point of each ONU. Specifically, the control circuit 42c has a training period for each ONU at the beginning of communication. In the training period, the control circuit 42c selects one signal in order from N branch paths, and a signal input from the selected path. The gain is controlled so as to pass only through, and the evaluation result obtained by evaluating the characteristics by the evaluation circuit 41c is used to determine the path (that is, the delay circuit 21) that gives the delay with the most improved characteristics in each ONU. When a route through which all ONUs are routed is determined, gain control is performed so that signals input from other than the route used in the multiplexing circuit 22c are not output. The multiplexing circuit 22 c also has a function of controlling the gain so as to follow the input width of the analog-digital converter 3 and multiplexing.

  In the above description, the configuration of the IM-DD optical receiver in FIG. 7 is described as an example, but the operation is the same in the configuration of the coherent optical receiver illustrated in FIG. The description is omitted here. In the configuration of FIG. 8, control is performed so that the route to be selected is the same on the Ich side and the Qch side.

Next, the effect in Embodiment 2 is shown.
In the second embodiment, the granularity of the delay amount that can be given is improved according to the number of branches n. However, unlike the first embodiment, an optimum delay cannot be given to each ONU. Therefore, the improvement in characteristics is inferior. However, since the delay amount after branching is fixed, it is highly feasible to adjust by the wiring length as described above. Further, unlike the first embodiment, since the delay amount is not adjusted, the configuration of the control circuits 42c and 42d can be simplified.

  As described above, in the second embodiment, the same effect as in the first embodiment can be obtained, and in the second embodiment, the delays of the delay circuits 21c and 21d of the delay generation circuits 2c and 2d can be obtained. Since the amount is fixed, the ease of realization such as adjustment by the wiring length is high. In addition, since the control circuits 42c and 42d of the digital signal processing circuits 4c and 4d do not control the delay amount, the configuration of the control circuits 42c and 42d can be simplified.

Embodiment 3 FIG.
FIG. 9 is a configuration diagram showing a configuration of an optical receiver according to Embodiment 3 of the present invention. In FIG. 9, an IM-DD OLT optical receiver for OFDMA-PON will be described as an example of the optical receiver according to the third embodiment.

  The optical transmitter / receiver shown in FIG. 9 converts an input optical signal into an analog electrical signal (current), amplifies it, and outputs it, and branches the amplified analog electrical signal into a plurality of branches, A delay generation circuit 2e for combining the delay-added signal and outputting the delayed signal, and an analog-digital converter 3 (ADC circuit) for converting the analog electric signal output from the delay generation circuit 2e into a digital signal. And a digital signal processing circuit 4e for processing and demodulating the digital signal.

  The photoelectric conversion circuit 1 has the same configuration as the photoelectric conversion circuit 1 in FIG. 1 and performs the same operation. That is, the photoelectric conversion circuit 1 receives a received OFDMA optical signal and converts it into a current (analog electrical signal), and an amplification circuit that amplifies a weak current signal and converts it into a voltage signal. It comprises a transimpedance amplifier (TIA) 12. The light receiving element 11 may be composed of PD or APD.

  The delay adjustment circuit 2e is composed of a fixed delay circuit 21e and a fixed delay circuit 21f that branch the input electric analog signal into two branches and give different delays to each other, and a multiplexing circuit 22e that combines the two analog signals. .

  The analog-digital converter 3 has the same configuration as the analog-digital converter 3 in FIG. 1 and performs the same operation. That is, the analog-digital converter 3 samples the continuous analog electric signal output from the delay generation circuit 2e at the same sampling frequency (sampling period Ts) as the baud rate of the signal band, and converts it into a digital signal.

  The digital signal processing circuit 4e includes a demodulation processing circuit 43e that performs demodulation processing of the OFDMA signal, and does not include the evaluation circuit and the control circuit described in the first and second embodiments.

  The difference between the configuration of the optical receiver in FIG. 1 and the configuration of the optical receiver in FIG. 9 is branched into n in FIG. 1, but is divided into two in FIG. The delay amount of the delay circuit 21 of the delay generation circuit 2 is variable and the delay amount is controlled by the control circuit 42 of the digital signal processing circuit 4, but in FIG. 9, the delay of the delay generation circuit 2e is controlled. The delay amounts of the circuits 21e and 21f are fixed, the digital signal processing circuit 4e does not control the delay amount, the digital signal processing circuit 4e in FIG. 9 does not control the gain of the multiplexing circuit 22e, 9 is different in that the digital signal processing circuit 4e does not have a configuration corresponding to the evaluation circuit 41 and the control circuit 42 shown in FIG. Other configurations and operations are the same as those in FIG.

  FIG. 10 is a configuration diagram showing a configuration of a coherent optical receiver according to Embodiment 3 of the present invention. The optical receiver shown in FIG. 10 has a coherent photoelectric conversion circuit 1b that receives an OFDMA optical signal, converts it into an analog electrical signal, amplifies it, and outputs it, and branches the analog electrical signal into two signals. A delay generation circuit 2g that gives a fixed delay amount to the signal, and combines the delayed signals again, and a continuous analog signal output from the delay generation circuit 2g is sampled at the same sampling frequency as the baud rate of the signal band (sampling An analog-digital converter 3b that samples at a cycle Ts) and converts it into a digital signal, and a digital signal processing circuit 4g that processes and demodulates the digital signal from the analog-digital converter 3b.

  The difference between the configuration of the optical receiver in FIG. 2 and the configuration of the optical receiver in FIG. 10 is branched into n in FIG. 2, but is divided into two in FIG. The delay amount of the delay circuit 21b of the delay generation circuit 2b is variable, and the delay amount is controlled by the control circuit 42b of the digital signal processing circuit 4b. In FIG. The delay amounts of the circuits 21g and 21h are fixed, the digital signal processing circuit 4g does not control the delay amount, the digital signal processing circuit 4g in FIG. 10 does not control the gain of the multiplexing circuit 22g, The difference is that the ten digital signal processing circuits 4g do not have configurations corresponding to the evaluation circuit 41b and the control circuit 42b shown in FIG. Other configurations and operations are the same as those in FIG.

  In the coherent receiver configuration shown in FIG. 10, since two types of signals for Ich and Qch are formed in the analog front end, the circuit is doubled, but the delay circuits 21g, 21h, Although two multiplexing circuits 22g are required, the configuration and operation are the same as those of the IM-DD circuit (FIG. 9).

  Next, the operation will be described. The operation of the optical receiver according to the third embodiment shown in FIGS. 9 and 10 will be described. The operation of the optical receiver according to the third embodiment shown in FIGS. 9 and 10 is basically the same. Therefore, in order to simplify the description, in the following description, the operation will be described using the configuration of FIG. 9 as an example. The optical receiver shown in the third embodiment is also applied to an OFDMA-PON system in which a plurality of ONUs shown in FIG. 3 are accommodated in one OLT via an optical fiber and an optical coupler. Since the OFDMA-PON system configuration and the ONU operation are the same as those in the first embodiment, description thereof will not be given here.

  As shown in FIG. 9, in the third embodiment, first, the input OFDMA optical signal is converted into an electrical analog signal by the photoelectric conversion circuit 1. The converted electrical signal is input to the delay generation circuit 2e and branched into two paths. The branched signals are given different preset fixed delay amounts configured by, for example, the electrical wiring length by the delay circuit 21e and the delay circuit 21f. The signal given the delay is amplified with an arbitrary gain by the multiplexing circuit 22e and combined to regenerate a single analog signal. The regenerated analog signal is converted from an analog signal to a digital signal with a sampling rate of 1 by the analog-digital converter 3 and delivered to the digital signal processing circuit 4e. The digital signal processing circuit 4e performs timing and frequency synchronization on the digital signal as necessary, performs channel estimation and equalization processing, performs demodulation processing to a primary modulation signal, and finally demapping processing. Converted to bit string.

  As described above, the delay circuit 21e and the delay circuit 21f give a fixed delay to the branched path, and can be easily realized by controlling the wiring length. As for each delay amount, for example, when one delay amount of the branch is set to delay # 1, a delay amount further delayed by Ts / 2 is added to the other delay amount. That is, when one delay amount is delay # 1 and the other delay amount is delay # 2, delay # 2 = delay # 1 + Ts / 2. The multiplexing circuit 22 e has a function of combining the combined analog signals by controlling the gain so as to follow the input width of the analog-digital converter 3.

  In the above description, the configuration of the IM-DD optical receiver in FIG. 9 has been described as an example, but the operation is the same in the configuration of the coherent optical receiver illustrated in FIG. The description is omitted here. In the configuration of FIG. 10, the delay amounts of delay circuits # 1 to # 2 (reference numerals 21g and 21h) prepared for each of the two branch paths on the Ich side and the Qch side are the Ich side and the Qch side. Set to the same value.

Next, the effect in Embodiment 3 is shown.
When the third embodiment is applied under the conditions of the number of accommodated users n = 1, the number of frequency subcarriers 128, the cyclic prefix 8, the primary modulation scheme QPSK, and the reception SNR = 30 dB, The received Q-value characteristics of an arbitrary 1 ONU when 2 times oversampling was applied were compared. The results are shown in FIG. In FIG. 11, Δ is a graph of the third embodiment, ○ is a 1-time sampling, and □ is a graph of oversampling. In the case of 1-times sampling and the third embodiment, the highest Q value characteristic can be obtained when there is no deviation from the ideal sample point, but the characteristic deteriorates as the sample point is offset. As described in Non-Patent Document 2, this is due to the influence of aliasing noise from outside the band when the signal is converted into a discrete signal. In particular, a point that cannot be demodulated occurs under the condition that a Ts / 2 offset occurs. Compared with the case where oversampling is applied, characteristic deterioration of about 14 dB is caused. On the other hand, when the third embodiment is applied, signals that are shifted by Ts / 2 are received at the same time, so that there is tolerance against timing offset, and the characteristic deterioration is improved to about 3 dB. The third embodiment is easier to design the delay circuit and the multiplexing circuit than the first and second embodiments, and does not require a circuit for controlling the delay and gain adjustment amount. Therefore, it can be realized with the simplest configuration.

  As described above, in the third embodiment, the same effect as in the first and second embodiments can be obtained. Further, in the third embodiment, the analog signal is divided into two in the delay generation circuit. When branching and delaying each by the delay circuit, the other delay amount is set to delay # 2 = delay # 1 + Ts / 2 with respect to one delay amount delay # 1, and signals shifted by Ts / 2 are simultaneously transmitted. Since it is received, it is resistant to timing offset and can be improved to a characteristic deterioration of about 3 dB. In the third embodiment, the delay amounts of the two delay circuits of the delay generation circuits 2e and 2g are fixed, and the digital signal processing circuits 4e and 4g are the evaluation circuits and control circuits shown in FIGS. And the digital signal processing circuits 4e and 4g do not control the delay amount and the gain of the multiplexing circuit, so that the digital signal processing circuits 4e and 4g do not control the delay amount and the gain of the multiplexing circuit. In addition, the delay circuit and the multiplexing circuit can be easily designed, and a circuit for controlling the amount of delay and gain adjustment is not required, so that the circuit can be realized with the simplest configuration.

  1, 1b photoelectric conversion circuit, 2, 2b, 2c, 2d, 2e, 2g delay generation circuit, 3, 3b analog-digital converter, 4, 4b, 4c, 4d, 4e, 4g digital signal processing circuit, 11 light receiving element, 11b Radar, 12 TIA (transimpedance amplifier), 12b 90-degree optical hybrid, 13b balanced transceiver, 21, 21b, 21c, 21d, 21e, 21f, 21g, 21h delay circuit, 22, 22b, 22c, 22d, 22e, 22g Multiplexing circuit, 41, 41b, 41c, 41d evaluation circuit, 42, 42b, 42c, 42d control circuit, 43, 43b, 43c, 43d, 43e demodulation processing circuit, 100 ONU, 101 optical fiber, 102 optical coupler, 103 OLT .

Claims (7)

A photoelectric conversion circuit having a light receiving element that converts a received optical signal into an analog electrical signal and an amplifier circuit that amplifies the analog electrical signal;
The analog electrical signal from the amplifier circuit of the photoelectric conversion circuit is branched into a plurality of signals, a delay circuit that gives a delay for each branched signal, and the delayed signal is combined again to produce a single analog electrical signal. A delay generation circuit having a multiplexing circuit for generating a signal;
An analog-to-digital conversion circuit that converts the analog electrical signal output from the multiplexing circuit of the delay generation circuit into a digital signal;
An optical receiver comprising: a digital signal processing circuit that processes the digital signal output from the analog-digital conversion circuit. The optical receiver according to claim 1, wherein the delay circuit includes a variable delay circuit that varies a delay amount given to each signal by a sampling period width. The digital signal processing circuit includes:
The optical receiver according to claim 2, further comprising: a circuit that evaluates reception characteristics of the received optical signal and controls the delay amount of the delay circuit by feedback control using the evaluation result. The optical receiver according to claim 1, wherein the delay circuit includes a fixed delay circuit in which a delay amount given for each signal is set in advance. The optical receiver according to any one of claims 1 to 4, wherein the multiplexing circuit makes a gain to be provided for each signal at the time of multiplexing variable. The digital signal processing circuit includes:
The optical receiver according to claim 5, further comprising: a circuit that evaluates reception characteristics of the received optical signal and controls the gain of the multiplexing circuit by feedback control using the evaluation result. A photoelectric conversion step of converting the received optical signal into an analog electrical signal and amplifying the analog electrical signal;
A delay in which the analog electrical signal obtained in the photoelectric conversion step is branched into a plurality of signals, a delay is given to each branched signal, and the delayed signals are combined again to generate a single analog electrical signal Generation step;
An analog-digital conversion step for converting the analog electrical signal obtained in the delay generation step into a digital signal;
An optical receiving method comprising: a digital signal processing step for processing the digital signal obtained in the analog-digital conversion step.

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