JP2014229776A - Electrode, electronic component, electronic device and bonding method of electrode - Google Patents

Electrode, electronic component, electronic device and bonding method of electrode Download PDF

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JP2014229776A
JP2014229776A JP2013108910A JP2013108910A JP2014229776A JP 2014229776 A JP2014229776 A JP 2014229776A JP 2013108910 A JP2013108910 A JP 2013108910A JP 2013108910 A JP2013108910 A JP 2013108910A JP 2014229776 A JP2014229776 A JP 2014229776A
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electrode
condition
solder
counterpart
tip
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JP6186884B2 (en
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泰治 酒井
Taiji Sakai
泰治 酒井
今泉　延弘
Nobuhiro Imaizumi
延弘 今泉
将 森田
Masashi Morita
将 森田
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PROBLEM TO BE SOLVED: To provide an electrode having a resistance to a current flowing through a joint, even if miniaturizing the electrode, and less likely to cause defective bonding due to variation in the height of the electrode, and to provide an electronic component, an electronic device and a bonding method of an electrode.SOLUTION: An electrode includes a bonding surface to which the tip of an opponent electrode is welded via a solder when being heat treated under first conditions, and a bank arranged in a region surrounding at least a portion, where the tip of the opponent electrode is bonded, out of the bonding surface, and where the solder spreads when being heat treated under second conditions different from the first conditions.

Description

本願は、電極、電子部品、電子装置および電極の接合方法に関する。   The present application relates to an electrode, an electronic component, an electronic device, and an electrode joining method.

近年、各種の電子部品は、処理能力の増大および小型化の一途を辿っている。このため、例えば、半導体装置等の電子部品は、他の電子部品と電気接続するための電極も微細化している。電子部品の電気接続に関する技術としては、例えば、回路面上に電極を配列した半導体チップを、回路面を基板側へ向けて基板に実装するフリップチップ接続がある（例えば、特許文献１を参照）。   In recent years, various electronic components have been steadily increasing in processing capacity and miniaturized. For this reason, for example, in electronic parts such as semiconductor devices, electrodes for electrical connection with other electronic parts are also miniaturized. As a technique related to electrical connection of electronic components, for example, there is a flip chip connection in which a semiconductor chip in which electrodes are arranged on a circuit surface is mounted on a substrate with the circuit surface facing the substrate side (see, for example, Patent Document 1). .

特開２００７−１９３６０号公報JP 2007-19360 A

電極の微細化は、電極の電流密度の増加を引き起こす。電極の電流密度の増加は、例えば、接合部分を形成する金属を劣化させる。このため、微細な電極同士の接合部分を形成する金属は、接合部分を流れる電流に対して耐性のある安定的な構造を呈する状態にすることが望まれる。例えば、半田の熱処理によって形成される金属間化合物（ＩＭＣ：intermetallic compound）は、接合部分を流れる電流に対して耐性のある安定的な構造を呈する。   The miniaturization of the electrode causes an increase in the current density of the electrode. An increase in the current density of the electrode deteriorates, for example, the metal forming the joint portion. For this reason, it is desired that the metal forming the bonding portion between the fine electrodes be in a state of exhibiting a stable structure resistant to the current flowing through the bonding portion. For example, an intermetallic compound (IMC) formed by heat treatment of solder exhibits a stable structure that is resistant to the current flowing through the joint.

ところで、半田の熱処理によるＩＭＣの生成速度は、半田の量に応じて増減する。よって、微細な電極同士の接合部分を電流に対して耐性のある安定的な構造にしたい場合、接合部分の半田の量を削減することが望まれる。しかし、電子部品の表面に配列される電極には高さにばらつきがあるため、単なる半田量の削減は電極同士の接合不良を招く恐れがある。   By the way, the rate of IMC generation by heat treatment of solder increases or decreases according to the amount of solder. Therefore, when it is desired to form a stable structure that is resistant to current at the junction between fine electrodes, it is desired to reduce the amount of solder at the junction. However, since the electrodes arranged on the surface of the electronic component have variations in height, a mere reduction in the amount of solder may cause a bonding failure between the electrodes.

そこで、本願は、電極を微細化しても、接合部分を流れる電流に対して耐性があり且つ電極の高さのばらつきによる接合不良を生じにくい電極、電子部品、電子装置および電極の接合方法を提供することを課題とする。   Therefore, the present application provides an electrode, an electronic component, an electronic device, and an electrode bonding method that are resistant to a current flowing through a bonding portion even when the electrode is miniaturized, and that hardly cause a bonding failure due to variations in electrode height. The task is to do.

本願は、次のような電極を開示する。
第１の条件で熱処理されると相手電極の先端が半田を介して溶着する接合面と、
前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件で熱処理されると前記半田が濡れ広がる堤部と、を備える、
電極。 The present application discloses the following electrodes.
A joint surface on which the tip of the counterpart electrode is welded via solder when heat-treated under the first condition;
A portion of the joining surface that is disposed in a region surrounding at least a portion to which the tip of the counterpart electrode is joined, and when the heat treatment is performed under a second condition different from the first condition, Comprising
electrode.

また、本願は、次のような電子部品を開示する。
第１の条件で熱処理されると相手電極の先端が半田を介して溶着する接合面と、前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件で熱処理されると前記半田が濡れ広がる堤部と、を備える電極と、
前記電極を、他の電子部品に配列されている前記相手電極に各々対応する位置に複数配
列した部材と、を備える、
電子部品。 Moreover, this application discloses the following electronic components.
When the heat treatment is performed under the first condition, the bonding surface where the tip of the mating electrode is welded via solder, and at least a portion of the bonding surface surrounding the portion where the tip of the mating electrode is bonded, An embankment comprising a bank portion where the solder spreads when heat-treated under a second condition different from the first condition;
A plurality of the electrodes arranged at positions corresponding to the counterpart electrodes arranged in other electronic components, and
Electronic components.

また、本願は、次のような電子装置を開示する。
少なくとも２つの電子部品と、
前記２つの電子部品のうち何れか一方の電子部品に配列される電極、及び、何れか他方の電子部品に配列される相手電極と、を備え、
前記何れか一方の電子部品に配列される各電極は、
第１の条件による熱処理によって前記相手電極の先端が半田を介して溶着している接合面と、
前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件による熱処理によって前記半田が濡れ広がっている堤部と、を各々有している、
電子装置。 The present application also discloses the following electronic device.
At least two electronic components;
An electrode arranged on any one of the two electronic components, and a counter electrode arranged on any other electronic component,
Each electrode arranged in one of the electronic components is
A bonding surface in which the tip of the counterpart electrode is welded via solder by heat treatment according to a first condition;
A bank portion that is disposed in a region surrounding at least a portion of the bonding surface to which the tip of the counterpart electrode is bonded, and in which the solder is spread and spread by heat treatment under a second condition different from the first condition; , Each having
Electronic equipment.

また、本願は、次のような電極の接合方法を開示する。
電極の接合面のうち少なくとも相手電極の先端が接合される部分を取り囲む領域に、前記相手電極の先端が半田を介して前記接合面に溶着する第１の条件とは異なる第２の条件で熱処理されると、前記半田が濡れ広がる堤部を配置した前記電極に対して、前記相手電極の位置合わせを行い、
前記相手電極の位置合わせを行った前記電極に対して、前記第１の条件で熱処理を行い、
前記第１の条件で熱処理を行った前記電極に対して、前記第２の条件で熱処理を行う、
電極の接合方法。 Moreover, this application discloses the following electrode joining methods.
Heat treatment under a second condition different from the first condition in which the tip of the counterpart electrode is welded to the joint surface via solder in a region surrounding at least a portion of the joint surface of the electrode where the tip of the counterpart electrode is joined Then, with respect to the electrode where the bank part where the solder spreads wet is arranged, the position of the counterpart electrode is adjusted,
The electrode subjected to the alignment of the counterpart electrode is heat-treated under the first condition,
The electrode that has been heat-treated under the first condition is heat-treated under the second condition.
Electrode bonding method.

上記端子、電極、電子部品、電子装置および電極の接合方法であれば、電極を微細化しても、接合部分を流れる電流に対して耐性があり且つ電極の高さのばらつきによる接合不良を生じにくくすることができる。   With the terminal, electrode, electronic component, electronic device, and electrode joining method, even if the electrode is miniaturized, it is resistant to the current flowing through the joining portion and hardly causes poor bonding due to variations in the height of the electrode. can do.

図１は、実施形態に係る電極を示した図の一例である。FIG. 1 is an example of a diagram illustrating an electrode according to an embodiment. 図２は、堤部を形成する微粒子の内部構造を示した図の一例である。FIG. 2 is an example of a diagram illustrating the internal structure of the fine particles forming the bank portion. 図３は、電極を相手電極と接合する様子を示した図の一例である。FIG. 3 is an example of a diagram illustrating a state in which an electrode is joined to a counter electrode. 図４は、半導体装置の構成図の一例である。FIG. 4 is an example of a configuration diagram of a semiconductor device. 図５は、半導体装置の電極部を接合する過程を示した図の一例である。FIG. 5 is an example of a diagram illustrating a process of joining the electrode portions of the semiconductor device. 図６は、第２の条件による熱処理時の微粒子の状態を示した図の一例である。FIG. 6 is an example of a diagram showing the state of fine particles during the heat treatment under the second condition. 図７は、変形例に係る電極を示した図の一例である。FIG. 7 is an example of a diagram illustrating an electrode according to a modification. 図８は、変形例に係る電極を相手電極と接合する様子を示した図の一例である。FIG. 8 is an example of a diagram illustrating a state in which the electrode according to the modification is joined to the counterpart electrode. 図９は、電極を形成する基板を示した図の一例である。FIG. 9 is an example of a diagram illustrating a substrate on which an electrode is formed. 図１０は、パターニングされたレジストを形成した基板を示した図の一例である。FIG. 10 is an example of a diagram illustrating a substrate on which a patterned resist is formed. 図１１は、堤部を形成した基板を示した図の一例である。FIG. 11 is an example of a diagram illustrating a substrate on which a bank portion is formed. 図１２は、レジストが除去された基板を示した図の一例である。FIG. 12 is an example of a diagram showing the substrate from which the resist has been removed.

以下、実施形態について説明する。以下に示す実施形態は、単なる例示であり、本願で開示するものの技術的範囲を以下の態様に限定するものではない。   Hereinafter, embodiments will be described. The embodiments described below are merely examples, and the technical scope of what is disclosed in the present application is not limited to the following modes.

図１は、実施形態に係る電極を示した図の一例である。電極１は、例えば、図１に示すように、接合面２と堤部３とを備えている。   FIG. 1 is an example of a diagram illustrating an electrode according to an embodiment. The electrode 1 includes, for example, a joining surface 2 and a bank portion 3 as shown in FIG.

接合面２は、相手電極に対向する面であり、相手電極の先端が半田を介して溶着される面である。溶着に適用可能な半田としては、融点の低い金属であればよく、例えば、錫（Ｓｎ）を主成分とする半田等を適用可能である。接合面２は、例えば、図１に示すように、円柱状の基部４が形成する面であり、基部４の表面のうち相手電極に対向する面である。しかし、接合面２は、図１に示すような円柱状の基部４が形成するものに限定されるものではない。接合面２は、例えば、角柱状の基部が形成するものであってもよいし、或いは、電極１が形成される電子部品の表面の一領域を画定しただけのものであってもよい。   The joint surface 2 is a surface facing the counterpart electrode, and is a surface where the tip of the counterpart electrode is welded via solder. As a solder applicable to welding, any metal having a low melting point may be used. For example, a solder mainly composed of tin (Sn) can be applied. For example, as shown in FIG. 1, the bonding surface 2 is a surface formed by a cylindrical base portion 4, and is a surface facing the counterpart electrode on the surface of the base portion 4. However, the joint surface 2 is not limited to that formed by the columnar base 4 as shown in FIG. For example, the bonding surface 2 may be formed by a prismatic base, or may be one that defines only a region of the surface of the electronic component on which the electrode 1 is formed.

堤部３は、接合面２のうち相手電極の先端が接合される部分を取り囲む領域に配置されている。堤部３は、例えば、図１に示すように、微粒子５によって形成されている。しかし、堤部３は、図１に示すような微粒子５によって形成されるものに限定されるものではない。堤部３は、例えば、粒子ではない個片等によって形成されるものであってもよいし、基部４を盛り上げることによって形成してもよい。   The bank portion 3 is disposed in a region surrounding a portion of the bonding surface 2 where the tip of the counterpart electrode is bonded. The bank portion 3 is formed of, for example, fine particles 5 as shown in FIG. However, the bank portion 3 is not limited to the one formed by the fine particles 5 as shown in FIG. The bank 3 may be formed by, for example, a piece that is not a particle, or may be formed by raising the base 4.

図２は、堤部３を形成する微粒子５の内部構造を示した図の一例である。堤部３を形成する微粒子５は、例えば、図２に示すように、微粒子５の中心部分を形成する核６と、核６の表面を覆う被膜７とを備える。堤部３は、このように、核６の表面を被膜７で覆った微粒子５で形成される。よって、堤部３は、実質的に表面が被膜７で覆われていることになる。なお、堤部３を、基部４を盛り上げて形成する場合、盛り上がっている部分を被膜で覆うことになる。   FIG. 2 is an example of a diagram showing the internal structure of the fine particles 5 forming the bank portion 3. The fine particles 5 forming the bank portion 3 include, for example, a nucleus 6 that forms the central portion of the fine particle 5 and a coating 7 that covers the surface of the nucleus 6 as shown in FIG. The bank portion 3 is thus formed by the fine particles 5 in which the surface of the nucleus 6 is covered with the coating 7. Therefore, the surface of the bank portion 3 is substantially covered with the coating 7. In addition, when forming the bank part 3 by raising the base 4, the part which has risen is covered with a film.

被膜７は、第１の条件による熱処理において半田が堤部３に濡れ広がるのを抑制し、第２の条件による熱処理において半田が堤部３に濡れ広がるのを許容する被膜である。ここで、第１の条件とは、電極１に接合する相手電極の先端を、半田を介して接合面２に接合する際の熱処理に関わる諸条件であり、例えば、電極１が置かれる雰囲気を構成するガスの組成を挙げることができる。また、第２の条件とは、接合面２と相手電極とを接合している半田を堤部３へ濡れ広げる際の熱処理に関わる諸条件であり、例えば、電極１が置かれる雰囲気を構成するガスの組成を挙げることができる。   The coating 7 is a coating that suppresses the solder from spreading to the bank 3 in the heat treatment under the first condition, and allows the solder to spread into the bank 3 in the heat treatment according to the second condition. Here, the first condition is various conditions related to heat treatment when the tip of the mating electrode to be bonded to the electrode 1 is bonded to the bonding surface 2 via solder. For example, the atmosphere in which the electrode 1 is placed is The composition of the gas that constitutes it can be mentioned. The second condition is various conditions related to heat treatment when wetting and spreading the solder that joins the joining surface 2 and the counterpart electrode to the bank 3, and constitutes an atmosphere in which the electrode 1 is placed, for example. Mention may be made of the gas composition.

例えば、酸化膜は半田の濡れ性を阻害する要因の一つとなる。そこで、微粒子５の表面を形成する被膜７を酸化被膜とした場合、酸化被膜を還元しないガス雰囲気で熱処理を行っても、半田が堤部３に濡れ広がりにくい。例えば、被膜７を酸化被膜とし、酸化被膜を還元しないガス雰囲気を第１の条件とした場合、被膜７は、第１の条件による熱処理において半田が堤部３に濡れ広がるのを抑制することができる。また、例えば、被膜７を酸化被膜とし、酸化被膜を還元するガス雰囲気を第２の条件とした場合、被膜７は、第２の条件による熱処理において還元除去され、半田が堤部３に濡れ広がるのを許容することができる。   For example, the oxide film is one of the factors that hinder the wettability of solder. Therefore, when the coating film 7 that forms the surface of the fine particles 5 is an oxide film, the solder hardly spreads to the bank 3 even if heat treatment is performed in a gas atmosphere that does not reduce the oxide film. For example, when the film 7 is an oxide film and the gas atmosphere that does not reduce the oxide film is the first condition, the film 7 can suppress the solder from spreading to the bank 3 in the heat treatment under the first condition. it can. For example, when the film 7 is an oxide film and the gas atmosphere for reducing the oxide film is the second condition, the film 7 is reduced and removed by the heat treatment according to the second condition, and the solder spreads wet on the bank 3. Can be tolerated.

上記電極１は、例えば、次のようにして相手電極と接合可能である。図３は、電極１を相手電極と接合する様子を示した図の一例である。電極１を相手電極９と接合する際は、例えば、先端に半田Ｓを付けた相手電極９の位置合わせを行う（図３（Ａ）を参照）。位置合わせは、例えば、フリップチップボンダー等によって行うことが可能である。なお、半田Ｓは、図３に示したように、相手電極９の先端に予め付けてもよいが、電極１の接合面２に付けてもよいし、相手電極９の先端と電極１の接合面２の両方に付けてもよい。相手電極９の位置合わせが行われることにより、相手電極９の先端に付けられている半田Ｓは、堤部３に包囲された状態となる。   For example, the electrode 1 can be joined to the counterpart electrode as follows. FIG. 3 is an example of a diagram illustrating a state in which the electrode 1 is joined to the counterpart electrode. When the electrode 1 is joined to the counterpart electrode 9, for example, the counterpart electrode 9 with the solder S attached to the tip is aligned (see FIG. 3A). The alignment can be performed by, for example, a flip chip bonder. As shown in FIG. 3, the solder S may be attached to the tip of the counterpart electrode 9 in advance, or may be attached to the joint surface 2 of the electrode 1, or the tip of the counterpart electrode 9 and the electrode 1 may be joined. You may attach to both of the surfaces 2. By aligning the mating electrode 9, the solder S attached to the tip of the mating electrode 9 is surrounded by the bank 3.

相手電極９の位置合わせを行った後は、第１の条件の下で電極１や相手電極９に対して熱処理を行い、相手電極９の先端を、半田Ｓを介して接合面２に溶着する（図３（Ｂ）を参照）。第１の条件による熱処理では半田Ｓが堤部３に濡れ広がらず、堤部３が半田Ｓを取り囲んだ状態を維持するため、例えば、半田Ｓが接合面２全体に濡れ広がる場合に比べると、接合部分である電極１と相手電極９との間のギャップを大きい状態で維持できる。よって、例えば、電子部品に多数配列されており、各電極１や各相手電極９の高さにばらつきがある場合であっても、高さのばらつきによる接合不良を抑制することができる。   After aligning the counterpart electrode 9, heat treatment is performed on the electrode 1 and the counterpart electrode 9 under the first condition, and the tip of the counterpart electrode 9 is welded to the joint surface 2 via the solder S. (See FIG. 3B). In the heat treatment according to the first condition, the solder S does not wet and spread to the bank portion 3 and the bank 3 surrounds the solder S. For example, compared with a case where the solder S wets and spreads over the entire joining surface 2, It is possible to maintain a large gap between the electrode 1 that is the joint portion and the counterpart electrode 9. Therefore, for example, even when a large number of electronic components are arranged and the heights of the electrodes 1 and the counterpart electrodes 9 vary, it is possible to suppress bonding defects due to variations in height.

相手電極９の先端を接合面２に溶着した後は、第２の条件の下で電極１や相手電極９に対して熱処理を行い、半田Ｓを堤部３に濡れ広げる（図３（Ｃ）を参照）。半田Ｓが堤部３に濡れ広がると、相手電極９が電極１の方へ引き寄せられて、接合部分である電極１と相手電極９との間のギャップが小さくなる。   After the tip of the mating electrode 9 is welded to the joint surface 2, heat treatment is performed on the electrode 1 and the mating electrode 9 under the second condition to spread the solder S onto the bank 3 (FIG. 3C). See). When the solder S wets and spreads on the bank 3, the counterpart electrode 9 is drawn toward the electrode 1, and the gap between the junction electrode 1 and the counterpart electrode 9 becomes small.

なお、第１の条件の下で半田Ｓの濡れ広がりを堤部３で防止しつつ、半田Ｓを接合面２に溶着させるには、接合面２を形成する基部４が、第１の条件の下で電極１の中心部が半田と反応しやすい材質で形成されていることが好ましい。例えば、第１の条件を大気雰囲気とする場合、電極１の中心部が大気中で半田と反応しやすい基部４に好適な材質としては、例えば、銅（Ｃｕ）や金（Ａｕ）を挙げることができる。   In order to weld the solder S to the joint surface 2 while preventing the solder S from spreading on the bank 3 under the first condition, the base 4 forming the joint surface 2 must satisfy the first condition. It is preferable that the center part of the electrode 1 is formed of a material that easily reacts with solder. For example, when the first condition is an air atmosphere, examples of a material suitable for the base 4 in which the central portion of the electrode 1 easily reacts with solder in the air include copper (Cu) and gold (Au). Can do.

また、第１の条件の下で半田Ｓの濡れ広がりを防止しつつ、第２の条件の下で半田Ｓの濡れ広がりを許容する堤部３は、例えば、銅（Ｃｕ）を核６とし、ニッケル（Ｎｉ）を被膜７とする微粒子５によって形成したものを挙げることができる。ニッケルは、大気との接触によって表面に酸化膜を形成する。酸化膜は、一般に、半田の濡れ性を低下させる。よって、被膜７をニッケルで形成すれば、被膜７は、半田Ｓの濡れ広がりを阻害する被膜として機能することになる。あるいは、銅からなる微粒子で、その表面に数ｎｍから数十ｎｍの厚さで強制的に酸化膜が形成されたものでも同様の機能を有する。   In addition, the bank 3 that prevents the solder S from spreading under the first condition and allows the solder S to spread under the second condition has, for example, copper (Cu) as the core 6, Examples thereof include those formed by fine particles 5 having nickel (Ni) as a coating 7. Nickel forms an oxide film on the surface by contact with the atmosphere. The oxide film generally reduces solder wettability. Therefore, if the coating 7 is formed of nickel, the coating 7 functions as a coating that inhibits the wetting and spreading of the solder S. Alternatively, fine particles made of copper and having an oxide film forcibly formed on the surface with a thickness of several nanometers to several tens of nanometers have the same function.

また、微粒子５の粒径は、特に限定されないが、接合面２や相手電極９の大きさを勘案して決定されることが望ましい。接合面２の径を数十μｍ程度とするならば、微粒子５の粒径は、例えば、０．０５〜５μｍの範囲で任意の粒径を選択することが好ましい。   The particle diameter of the fine particles 5 is not particularly limited, but is preferably determined in consideration of the size of the bonding surface 2 and the counterpart electrode 9. If the diameter of the bonding surface 2 is about several tens of μm, it is preferable to select an arbitrary particle size of the fine particles 5 within a range of 0.05 to 5 μm, for example.

また、相手電極９の先端を、半田Ｓを介して接合面２に溶着する際は、例えば、電極１と相手電極９とを相対的に横方向へ振幅させる動作（スクラブ動作と呼ばれる場合もある）を行えば、半田Ｓの表面の酸化膜を除去し、接合面２に対する濡れ性を向上させることができる。電極１と相手電極９とを相対的に横方向へ振幅させる際の動作量は、電極１或いは相手電極９の寸法等に応じて適宜決定される。半田Ｓの表面の酸化膜を除去する目的で行うスクラブ動作であれば、例えば、１乃至３μｍ程度の振幅で酸化膜を十分に除去できると見込まれる。また、電極１と相手電極９とを相対的に横方向へ振幅させる動作を行わなくとも、水溶性または無洗浄フラックスを用いて半田Ｓの表面の酸化膜を除去し、接合面２に対する濡れ性を向上させることもできる。なお、ニッケル（Ｎｉ）を被膜７とし、第１の条件を大気雰囲気とする場合であれば、フラックスを用いた場合であっても、大気中では堤部３を形成する微粒子５が半田Ｓで濡れることは無い。   In addition, when the tip of the counterpart electrode 9 is welded to the joint surface 2 via the solder S, for example, an operation of causing the electrode 1 and the counterpart electrode 9 to relatively swing in the lateral direction (sometimes called a scrub operation). ), The oxide film on the surface of the solder S can be removed, and the wettability with respect to the bonding surface 2 can be improved. The amount of movement when the electrode 1 and the counterpart electrode 9 are caused to relatively swing in the lateral direction is appropriately determined according to the dimensions of the electrode 1 or the counterpart electrode 9 and the like. If the scrub operation is performed for the purpose of removing the oxide film on the surface of the solder S, it is expected that the oxide film can be sufficiently removed with an amplitude of about 1 to 3 μm, for example. In addition, the oxide film on the surface of the solder S is removed using a water-soluble or no-clean flux without performing the operation of causing the electrode 1 and the counterpart electrode 9 to swing relative to each other in the lateral direction, and the wettability with respect to the joint surface 2 Can also be improved. In addition, if nickel (Ni) is used as the coating 7 and the first condition is an air atmosphere, the fine particles 5 forming the bank portion 3 are formed by the solder S in the air even when a flux is used. Never get wet.

また、ニッケル（Ｎｉ）を被膜７とし、ニッケルの表面が大気と触れることによって形成される酸化膜で半田Ｓの濡れを防ぐ場合、第２の条件としては、還元雰囲気を挙げることができる。還元雰囲気は、例えば、電極１を設けた電子部品を収容したチャンバーを真空引きした後、真空引きしたチャンバー内に、蟻酸溶液に窒素ガスをバブリングさせて生成した蟻酸ガスを導入することによって実現できる。堤部３を形成する多数の微粒子５を蟻酸に晒すには、例えば、チャンバー内を２００乃至６００Ｔｏｒｒ程度の減圧雰囲気に
することが好ましい。蟻酸の体積濃度は、酸化膜の性状にもよるが、例えば、ニッケル（Ｎｉ）を被膜７とする場合であれば３乃至１０％程度の体積濃度で十分な還元作用が得られる。このような雰囲気を第２の条件とした状態でチャンバー内の温度を半田Ｓの融点以上に昇温して熱処理を行えば、半田Ｓが堤部３の微粒子５に濡れ広がり、相手電極９が電極１へ引き寄せられることになる。なお、還元雰囲気は、蟻酸のみならず、例えば、酢酸等のその他各種の有機酸を用いたり、或いは、水素（Ｈ2）と窒素（Ｎ2）との混合ガスを用いたりすることによって実現可能である。 When nickel (Ni) is used as the coating 7 and the solder surface is prevented from being wetted by an oxide film formed by contacting the nickel surface with the air, the second condition may be a reducing atmosphere. The reducing atmosphere can be realized by, for example, introducing a formic acid gas generated by bubbling nitrogen gas into a formic acid solution into the evacuated chamber after evacuating the chamber containing the electronic component provided with the electrode 1. . In order to expose a large number of fine particles 5 forming the bank portion 3 to formic acid, for example, the inside of the chamber is preferably set to a reduced pressure atmosphere of about 200 to 600 Torr. Although the volume concentration of formic acid depends on the properties of the oxide film, for example, when nickel (Ni) is used as the coating 7, a sufficient reducing action is obtained at a volume concentration of about 3 to 10%. When heat treatment is performed by raising the temperature in the chamber to the melting point of the solder S or higher under such an atmosphere as the second condition, the solder S wets and spreads on the fine particles 5 on the bank 3 and the counterpart electrode 9 It will be drawn to the electrode 1. The reducing atmosphere can be realized by using not only formic acid but also various other organic acids such as acetic acid or a mixed gas of hydrogen (H 2 ) and nitrogen (N 2 ). It is.

上記電極１は、各種の電子部品同士の電気接続に適用可能である。すなわち、電極１は、例えば、半導体素子同士の接合部分や半導体素子と基板との接合部分等に適用可能である。   The electrode 1 can be applied to electrical connection between various electronic components. That is, the electrode 1 can be applied to, for example, a bonding portion between semiconductor elements, a bonding portion between a semiconductor element and a substrate, or the like.

図４は、半導体装置の構成図の一例である。近年、電子機器の高速化や高機能化に伴い、半導体デバイス等の電子部品の更なる高集積化が求められている。高集積化の実現のため、電極の更なる微細化に対応するべく、例えば図４に示す半導体装置２０の電極部２１のように、電気特性が良好な銅（Ｃｕ）等でポスト（ピラーと呼ばれることもある）を形成し、ポストに付けた半田でボンディングすることが行われる。ポストを使ったボンディングであれば、半田バンプを用いる場合に比べて電極の更なる微細化を図ることができるため、例えば、ＬＳＩ（Large Scale Integration）同士を３次元に積層した構造体も実
現し得る。ところが、電極の微細化は、電極の電流密度の増加を引き起こすため、接合部分を形成する半田等の低融点の金属が電流によって移動する現象（エレクトロマイグレーション）等の発生を招き、接合部分を破断に至らしめる可能性がある。このため、微細な電極同士を半田で接合する場合は、熱処理によって溶融金属をＩＭＣへ変化させ、接合部分を電流に対して安定な構造にするＩＭＣボンディングの採用が考えられる。 FIG. 4 is an example of a configuration diagram of a semiconductor device. In recent years, with the increase in speed and functionality of electronic equipment, further integration of electronic components such as semiconductor devices has been demanded. In order to realize higher integration, in order to cope with further miniaturization of electrodes, for example, an electrode portion 21 of the semiconductor device 20 shown in FIG. Are sometimes called) and bonded with solder attached to the post. With bonding using posts, the electrodes can be made even finer than when solder bumps are used. For example, a structure in which LSIs (Large Scale Integration) are three-dimensionally stacked is also realized. obtain. However, miniaturization of the electrode causes an increase in the current density of the electrode, which causes a phenomenon in which a low melting point metal such as solder forming the joint moves due to current (electromigration), etc., and breaks the joint. There is a possibility of reaching. For this reason, when joining fine electrodes with solder, it is possible to adopt IMC bonding in which the molten metal is changed to IMC by heat treatment, and the joining portion has a structure stable against current.

しかしながら、ＩＭＣボンディングの実現にはいくつかの問題がある。図５は、半導体装置２０の電極部２１を接合する過程を示した図の一例である。例えば、半導体素子と基板とをフリップチップ接合する場合、電極同士の高さのばらつきなどを緩衝させるために半田を厚くする。しかし、半田を厚くすると、半田と電極との界面の面積が半田の量に比較して小さくなるため、接合部分を十分にＩＭＣ化させるための熱処理が長時間化する。また、熱処理によるＩＭＣ化の過程で、拡散速度が速く半田がより多く消費される箇所にはボイドが発生し、逆に、拡散がほとんど進行しない箇所については未反応の錫（Ｓｎ）が残存する。ボイドや未反応の錫の存在は、接合強度の低下やエレクトロマイグレーションに対する寿命の低下を引き起こし、接続部分の信頼性を低下させることになる。   However, there are several problems in realizing IMC bonding. FIG. 5 is an example of a diagram illustrating a process of bonding the electrode portion 21 of the semiconductor device 20. For example, when the semiconductor element and the substrate are flip-chip bonded, the solder is thickened to buffer the variation in height between the electrodes. However, when the thickness of the solder is increased, the area of the interface between the solder and the electrode becomes smaller than the amount of the solder, so that the heat treatment for making the joint portion sufficiently IMC takes a long time. Further, in the process of IMC conversion by heat treatment, voids are generated at locations where the diffusion rate is high and more solder is consumed, whereas unreacted tin (Sn) remains at locations where diffusion hardly progresses. . The presence of voids and unreacted tin causes a decrease in bonding strength and a decrease in life against electromigration, thereby reducing the reliability of the connection portion.

この点につき、上記実施形態に係る電極１であれば半田Ｓが堤部３に包囲されており、第１の条件による熱処理では半田Ｓが堤部３に濡れ広がらないため、電極１と相手電極９との接合に用いる半田Ｓの量そのものを少なくすることができる。よって、例えば、第１の条件による熱処理後に第２の条件による熱処理を更に行い、電極１と相手電極９との間のギャップを小さくすれば、半田Ｓの量に比較して、半田Ｓと電極１との界面の面積や半田Ｓと相手電極９との界面の面積を十分な大きさにすることができる。半田Ｓの量に比較して、半田Ｓと電極１との界面の面積や半田Ｓと相手電極９との界面の面積を十分に大きくすれば、接合部分のＩＭＣ化を短時間で実現できる。   In this regard, in the case of the electrode 1 according to the above-described embodiment, the solder S is surrounded by the bank 3 and the solder S does not wet and spread to the bank 3 in the heat treatment under the first condition. The amount of the solder S used for joining with the solder 9 can be reduced. Therefore, for example, if the heat treatment under the second condition is further performed after the heat treatment under the first condition and the gap between the electrode 1 and the counterpart electrode 9 is reduced, the solder S and the electrode are compared with the amount of the solder S. 1 and the area of the interface between the solder S and the counterpart electrode 9 can be made sufficiently large. If the area of the interface between the solder S and the electrode 1 and the area of the interface between the solder S and the counterpart electrode 9 are made sufficiently larger than the amount of the solder S, the IMC can be realized in a short time.

図６は、第２の条件による熱処理時の微粒子５の状態を示した図の一例である。堤部３を形成する各微粒子５の核６の表面は、第２の条件による熱処理によって半田Ｓに直接晒される。また、各微粒子５は、第２の条件による熱処理によって半田Ｓ内に多数点在する状態となる。よって、堤部３を形成する微粒子５の核６を、例えば、電極１を形成する銅（Ｃｕ）等の材料と同じ材料にした場合、核６が半田Ｓ中に点在しない場合に比べて、接合部分のＩＭＣ化を更に短時間で実現できる。また、核６が半田Ｓ中に点在することによ
り、接合部分全体の強度の向上が図られ、クラック等の接合不良の低減が実現できる。 FIG. 6 is an example of a diagram showing the state of the fine particles 5 during the heat treatment under the second condition. The surface of the core 6 of each fine particle 5 forming the bank portion 3 is directly exposed to the solder S by heat treatment according to the second condition. Further, the fine particles 5 are scattered in the solder S by a heat treatment under the second condition. Therefore, when the nuclei 6 of the fine particles 5 forming the bank portion 3 are made of the same material as, for example, copper (Cu) forming the electrode 1, compared with the case where the nuclei 6 are not scattered in the solder S. In addition, it is possible to realize the IMC at the joint portion in a shorter time. Further, since the nuclei 6 are scattered in the solder S, the strength of the entire bonded portion can be improved, and a reduction in bonding defects such as cracks can be realized.

また、上記電極１であれば、半田Ｓの厚みを十分に確保しても、第２の条件による熱処理後には電極１と相手電極９との間のギャップが小さくなるため、半田Ｓを薄く均一にＩＭＣ化でき、接合部分の信頼性（耐マイグレーション性）を高めることができる。また、第１の条件による熱処理において、半田Ｓの厚みが厚ければ、フリップチップ接合時の緩衝効果が高く、歩留まりの向上が図れる。すなわち、上記電極１であれば、第１の条件による熱処理と第２の条件による熱処理の２段階で半田Ｓを溶融させることができる。よって、上記電極１であれば、最初の熱処理の際（組み立て時）には応力が緩和されるように電極間のギャップを確保し、その後の熱処理の際には電極間のギャップを狭くし、ＩＭＣ化を短時間で処理できる。   In the case of the electrode 1, even if the thickness of the solder S is sufficiently secured, the gap between the electrode 1 and the counterpart electrode 9 becomes small after the heat treatment under the second condition, so that the solder S is thin and uniform. IMC can be achieved, and the reliability (migration resistance) of the joint portion can be improved. Further, in the heat treatment under the first condition, if the thickness of the solder S is large, the buffering effect at the time of flip chip bonding is high, and the yield can be improved. That is, in the case of the electrode 1, the solder S can be melted in two stages, ie, heat treatment under the first condition and heat treatment under the second condition. Therefore, if it is the said electrode 1, the gap between electrodes is ensured so that stress may be relieved at the time of the first heat treatment (during assembly), and the gap between the electrodes is narrowed at the time of subsequent heat treatment, IMC can be processed in a short time.

＜変形例＞
なお、上記電極１は、次のように変形することも可能である。図７は、変形例に係る電極を示した図の一例である。電極１は、例えば、図７に示すように、堤部３が接合面２全体を覆う形態を呈するものであってもよい。すなわち、堤部３は、接合面２のうち相手電極９の先端が接合される部分を取り囲む領域のみならず、接合面２のうち相手電極９の先端が接合される部分の領域に形成されていてもよい。 <Modification>
The electrode 1 can be modified as follows. FIG. 7 is an example of a diagram illustrating an electrode according to a modification. For example, as shown in FIG. 7, the electrode 1 may have a form in which the bank portion 3 covers the entire bonding surface 2. That is, the bank portion 3 is formed not only in the region surrounding the portion where the tip of the counterpart electrode 9 is joined in the joint surface 2 but also in the region of the portion where the tip of the counterpart electrode 9 is joined in the joint surface 2. May be.

本変形例に係る電極１は、例えば、次のようにして相手電極９と接合することが可能である。図８は、本変形例に係る電極１を相手電極９と接合する様子を示した図の一例である。本変形例に係る電極１を相手電極９と接合する際は、例えば、先端に半田Ｓを付けた相手電極９の位置合わせを行う（図８（Ａ）を参照）。   The electrode 1 according to this modification can be joined to the counterpart electrode 9 as follows, for example. FIG. 8 is an example of a diagram illustrating a state in which the electrode 1 according to this modification is joined to the counterpart electrode 9. When the electrode 1 according to this modification is joined to the counterpart electrode 9, for example, the counterpart electrode 9 with the solder S attached to the tip is aligned (see FIG. 8A).

相手電極９の位置合わせを行った後は、半田Ｓを溶かさない状態で相手電極９を電極１側へ加圧する。相手電極９を電極１側へ加圧すると、半田Ｓによって先端が丸く形成されている相手電極９が、堤部３を形成している微粒子５が接合面２の縁へ押し退けられる（図８（Ｂ）を参照）。堤部３を形成している微粒子５が接合面２の縁へ押し退けられることにより、相手電極９の先端に付けられている半田Ｓが堤部３に包囲された状態となる。   After aligning the counterpart electrode 9, the counterpart electrode 9 is pressed toward the electrode 1 in a state where the solder S is not melted. When the counterpart electrode 9 is pressed toward the electrode 1 side, the counterpart electrode 9 whose tip is formed round by the solder S is pushed away by the fine particles 5 forming the bank portion 3 toward the edge of the joint surface 2 (FIG. 8 ( See B)). When the fine particles 5 forming the bank portion 3 are pushed away to the edge of the bonding surface 2, the solder S attached to the tip of the counterpart electrode 9 is surrounded by the bank portion 3.

相手電極９を電極１側へ加圧した後は、第１の条件の下で電極１や相手電極９に対して熱処理を行い、相手電極９の先端を、半田Ｓを介して接合面２に溶着する（図８（Ｃ）を参照）。第１の条件による熱処理では半田Ｓが堤部３に濡れ広がらず、堤部３が半田Ｓを取り囲んだ状態を維持するため、上記実施形態の場合と同様、例えば、半田Ｓが接合面２全体に濡れ広がる場合に比べると、接合部分である電極１と相手電極９との間のギャップを大きい状態で維持できる。   After pressurizing the mating electrode 9 toward the electrode 1, heat treatment is performed on the electrode 1 and the mating electrode 9 under the first condition, and the tip of the mating electrode 9 is attached to the bonding surface 2 via the solder S. Welding is performed (see FIG. 8C). In the heat treatment under the first condition, the solder S does not wet and spread on the bank portion 3 and maintains the state in which the bank portion 3 surrounds the solder S. The gap between the electrode 1 as the joining portion and the counterpart electrode 9 can be maintained in a large state as compared with the case where the substrate is wet and spread.

相手電極９の先端を接合面２に溶着した後は、第２の条件の下で電極１や相手電極９に対して熱処理を行い、半田Ｓを堤部３に濡れ広げる（図８（Ｄ）を参照）。半田Ｓが堤部３に濡れ広がると、上記実施形態の場合と同様、相手電極９が電極１の方へ引き寄せられて、接合部分である電極１と相手電極９との間のギャップが小さくなる。   After the tip of the mating electrode 9 is welded to the joint surface 2, the electrode 1 and the mating electrode 9 are heat-treated under the second condition to spread the solder S onto the bank 3 (FIG. 8D). See). When the solder S wets and spreads on the bank 3, the counterpart electrode 9 is drawn toward the electrode 1 as in the case of the above embodiment, and the gap between the junction electrode 1 and the counterpart electrode 9 becomes small. .

なお、相手電極９を電極１側へ加圧する際の力は、電極１或いは相手電極９が形成されている電子部品の強度や、電極１或いは相手電極９の形状、堤部３を形成している微粒子５の性状等に応じて適宜決定される。よって、相手電極９を電極１側へ加圧する際の力は一意に定まらないが、例えば、半導体チップを基板に接合する場合であれば、１チップあたり１乃至５ｋｇ程度の力で加圧すれば、半球状の形状を呈する半田Ｓが堤部３の微粒子５を押し退け、接合面２の中心部に半田Ｓが接合できると見込まれる。   In addition, the force at the time of pressurizing the other electrode 9 to the electrode 1 side is the strength of the electronic component on which the electrode 1 or the other electrode 9 is formed, the shape of the electrode 1 or the other electrode 9, and the bank 3. It is determined appropriately according to the properties of the fine particles 5. Therefore, the force for pressing the counter electrode 9 toward the electrode 1 side is not uniquely determined. For example, when a semiconductor chip is bonded to the substrate, the force is applied with a force of about 1 to 5 kg per chip. It is expected that the solder S exhibiting a hemispherical shape pushes away the fine particles 5 of the bank 3 so that the solder S can be bonded to the center of the bonding surface 2.

また、相手電極９を電極１側へ加圧しても、半田Ｓによる堤部３の微粒子５の押し退け
量が十分でない場合は、例えば、電極１と相手電極９とを相対的に横方向へ振幅させる動作を更に行えば、接合面２を覆っていた微粒子５を十分に押し退け、接合面２に対する濡れ性を向上させることができる。電極１と相手電極９とを相対的に横方向へ振幅させる際の動作量は、電極１或いは相手電極９の寸法等に応じて適宜決定される。接合面２を覆っていた微粒子５を押し退ける目的で行う振幅動作であれば、例えば、２乃至１０μｍ程度の振幅で微粒子５を十分に押し退けることができると見込まれる。 In addition, even when the counterpart electrode 9 is pressed to the electrode 1 side, if the amount of displacement of the fine particles 5 on the bank 3 by the solder S is not sufficient, for example, the electrode 1 and the counterpart electrode 9 are relatively laterally amplituded. If the operation is further performed, the fine particles 5 covering the bonding surface 2 are sufficiently pushed away, and the wettability with respect to the bonding surface 2 can be improved. The amount of movement when the electrode 1 and the counterpart electrode 9 are caused to relatively swing in the lateral direction is appropriately determined according to the dimensions of the electrode 1 or the counterpart electrode 9 and the like. If the amplitude operation is performed for the purpose of pushing away the fine particles 5 covering the bonding surface 2, it is expected that the fine particles 5 can be sufficiently pushed away with an amplitude of about 2 to 10 μm, for example.

また、本変形例に係る電極１であれば、接合面２を覆っていた堤部３が半田Ｓを包囲し、第１の条件による熱処理では半田Ｓが堤部３に濡れ広がらないため、上記実施形態の場合と同様、電極１と相手電極９との接合に用いる半田Ｓの量そのものを少なくすることができる。よって、接合部分のＩＭＣ化を短時間で実現できる。また、堤部３を形成する微粒子５の核６を、例えば、電極１を形成する銅（Ｃｕ）等の材料と同じ材料にした場合、核６が半田Ｓ中に点在しない場合に比べて、接合部分のＩＭＣ化を更に短時間で実現できる。   In the case of the electrode 1 according to this modification, the bank 3 covering the joint surface 2 surrounds the solder S, and the solder S does not wet and spread on the bank 3 in the heat treatment under the first condition. As in the case of the embodiment, the amount of solder S used for joining the electrode 1 and the counterpart electrode 9 can be reduced. Therefore, the IMC can be realized in a short time in the joint portion. Further, when the core 6 of the fine particle 5 forming the bank portion 3 is made of the same material as, for example, copper (Cu) forming the electrode 1, compared to the case where the core 6 is not scattered in the solder S. In addition, it is possible to realize the IMC at the joint portion in a shorter time.

＜電極の形成方法＞
上記電極１は、例えば、次のような方法で形成することができる。 <Method for forming electrode>
The electrode 1 can be formed by the following method, for example.

図９は、電極１を形成する基板を示した図の一例である。上記電極１を形成したい場合、例えば、図９に示すように、基板８に基部４を形成する。基部４は、様々な方法で形成してもよく、例えば、電解メッキ法によって形成できる。基部４を電解メッキ法で形成する場合、例えば、約２０〜３０μｍ程度の高さの基部４を形成することができる。   FIG. 9 is an example of a diagram illustrating a substrate on which the electrode 1 is formed. When it is desired to form the electrode 1, for example, the base 4 is formed on the substrate 8 as shown in FIG. 9. The base 4 may be formed by various methods, for example, by electrolytic plating. When the base 4 is formed by an electrolytic plating method, for example, the base 4 having a height of about 20 to 30 μm can be formed.

図１０は、パターニングされたレジストを形成した基板８を示した図の一例である。基板８の表面に基部４を形成した後は、レジストＲを基板８の全面に塗布する。そして、レジストＲを露光し、堤部３を形成したい部分が開口するようにパターニングを行う。例えば、上記実施形態のように、環状の堤部３を形成したい場合、図１０に示したように、基部４の接合面２の縁の部分だけが開口し、接合面２の中央部にはレジストＲが残るようにパターニングを行う。また、上記変形例のように、接合面２を覆う堤部３を形成したい場合、接合面２の全面が開口するようにパターニングを行う。   FIG. 10 is an example of a diagram showing the substrate 8 on which a patterned resist is formed. After the base 4 is formed on the surface of the substrate 8, a resist R is applied to the entire surface of the substrate 8. Then, the resist R is exposed and patterned so that a portion where the bank portion 3 is to be formed is opened. For example, when it is desired to form the annular bank portion 3 as in the above-described embodiment, only the edge portion of the joint surface 2 of the base portion 4 is opened as shown in FIG. Patterning is performed so that the resist R remains. Moreover, when it is desired to form the bank portion 3 that covers the joint surface 2 as in the above modification, patterning is performed so that the entire surface of the joint surface 2 is opened.

図１１は、堤部３を形成した基板８を示した図の一例である。基板８の表面にパターニングしたレジストＲを形成した後は、レジストＲの開口箇所に微粒子５を塗布する。微粒子５は、様々な方法で塗布することが可能である。すなわち、微粒子５は、例えば、溶媒などに混合してペースト状またはインク状にしておき、印刷法あるいはインクジェット法によって塗布することが可能である。溶媒を使って微粒子５を塗布した場合、加熱等を行って溶媒を揮発させ、基部４の接合面２に固着させる。基部４の接合面２に固着した微粒子５は、堤部３を形成する。なお、溶媒を揮発させる際は、基板８や基部４、微粒子５を溶損させないことが肝要であるため、例えば、１２０℃程度の温度とするのが望ましい。また、溶剤の揮発を大気中における乾燥処理によって実現する場合、微粒子５の表面には自然酸化膜が数μｍから数十μｍの厚さで形成される。   FIG. 11 is an example of a diagram illustrating the substrate 8 on which the bank portion 3 is formed. After the patterned resist R is formed on the surface of the substrate 8, the fine particles 5 are applied to the openings of the resist R. The fine particles 5 can be applied by various methods. That is, the fine particles 5 can be applied in a printing method or an ink jet method after being mixed in a solvent or the like to form a paste or ink. When the fine particles 5 are applied using a solvent, the solvent is volatilized by heating or the like and fixed to the bonding surface 2 of the base 4. The fine particles 5 fixed to the joint surface 2 of the base portion 4 form the bank portion 3. When the solvent is volatilized, it is important not to cause the substrate 8, the base portion 4, and the fine particles 5 to be melted. Therefore, for example, a temperature of about 120 ° C. is desirable. Further, when the volatilization of the solvent is realized by a drying process in the air, a natural oxide film is formed on the surface of the fine particles 5 with a thickness of several μm to several tens of μm.

図１２は、レジストＲが除去された基板８を示した図の一例である。堤部３を形成した後は、レジストＲの除去を行う。これにより、基部４の接合面２に堤部３を形成した電極１が基板８上に出現する。   FIG. 12 is an example of a diagram illustrating the substrate 8 from which the resist R has been removed. After the bank portion 3 is formed, the resist R is removed. Thereby, the electrode 1 in which the bank portion 3 is formed on the joint surface 2 of the base portion 4 appears on the substrate 8.

なお、上記変形例のように、接合面２を覆う堤部３を形成したい場合、基部４を形成した後に基部４上をエッチングすることで選択的に基部４上にのみ粘着性を持たせ、その後、基板８の全面に微粒子５を塗布する。これにより、基部４上にのみ微粒子５が残存し、レジストＲを使わなくても接合面２を覆う堤部３を形成することができる。   In addition, like the said modification, when forming the bank part 3 which covers the joint surface 2, after forming the base part 4, the base part 4 is etched and the adhesiveness is selectively given only to the base part 4, Thereafter, the fine particles 5 are applied to the entire surface of the substrate 8. Thereby, the fine particles 5 remain only on the base portion 4, and the bank portion 3 that covers the bonding surface 2 can be formed without using the resist R.

なお、上記実施形態や変形例に係る電極１の製造方法は、上述した方法に限定されるものではない。上記実施形態や変形例に係る電極１は、その他の様々な方法で製造してもよい。   In addition, the manufacturing method of the electrode 1 which concerns on the said embodiment and modification is not limited to the method mentioned above. You may manufacture the electrode 1 which concerns on the said embodiment and modification by other various methods.

また、本願は、以下のような付記的事項を含む。
（付記１）
第１の条件で熱処理されると相手電極の先端が半田を介して溶着する接合面と、
前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件で熱処理されると前記半田が濡れ広がる堤部と、を備える、
電極。
（付記２）
前記堤部は、微粒子によって形成されている、
付記１に記載の電極。
（付記３）
前記微粒子は、少なくとも表面がＮｉに覆われている、
付記２に記載の電極。
（付記４）
前記堤部は、前記第１の条件による熱処理において前記半田が前記堤部に濡れ広がるのを抑制し、前記第２の条件による熱処理において前記半田が前記堤部に濡れ広がるのを許容する被膜に覆われている、
付記１から３の何れか一項に記載の電極。
（付記５）
前記第１の条件とは、前記堤部を覆う酸化被膜を還元しないガス雰囲気であり、
前記第２の条件とは、前記堤部を覆う酸化被膜を還元するガス雰囲気である、
付記１から４の何れか一項に記載の電極。
（付記６）
前記接合面は、前記相手電極の先端面よりも小さい、
付記１から５の何れか一項に記載の電極。
（付記７）
第１の条件で熱処理されると相手電極の先端が半田を介して溶着する接合面と、前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件で熱処理されると前記半田が濡れ広がる堤部と、を備える電極と、
前記電極を、他の電子部品に配列されている前記相手電極に各々対応する位置に複数配列した部材と、を備える、
電子部品。
（付記８）
前記堤部は、微粒子によって形成されている、
付記７に記載の電子部品。
（付記９）
前記微粒子は、少なくとも表面がＮｉに覆われている、
付記８に記載の電子部品。
（付記１０）
前記堤部は、前記第１の条件による熱処理において前記半田が前記堤部に濡れ広がるのを抑制し、前記第２の条件による熱処理において前記半田が前記堤部に濡れ広がるのを許容する被膜に覆われている、
付記７から９の何れか一項に記載の電子部品。
（付記１１）
前記第１の条件とは、前記堤部を覆う酸化被膜を還元しないガス雰囲気であり、
前記第２の条件とは、前記堤部を覆う酸化被膜を還元するガス雰囲気である、
付記７から１０の何れか一項に記載の電子部品。
（付記１２）
前記接合面は、前記相手電極の先端面よりも小さい、
付記７から１１の何れか一項に記載の電子部品。
（付記１３）
少なくとも２つの電子部品と、
前記２つの電子部品のうち何れか一方の電子部品に配列される電極、及び、何れか他方の電子部品に配列される相手電極と、を備え、
前記何れか一方の電子部品に配列される各電極は、
第１の条件による熱処理によって前記相手電極の先端が半田を介して溶着している接合面と、
前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件による熱処理によって前記半田が濡れ広がっている堤部と、を各々有している、
電子装置。
（付記１４）
前記堤部は、微粒子によって形成されている、
付記１３に記載の電子装置。
（付記１５）
前記微粒子は、少なくとも表面がＮｉに覆われている、
付記１４に記載の電子装置。
（付記１６）
前記第１の条件とは、前記堤部を覆っていた酸化被膜を還元しないガス雰囲気であり、
前記第２の条件とは、前記堤部を覆っていた酸化被膜を還元するガス雰囲気である、
付記１３から１５の何れか一項に記載の電子装置。
（付記１７）
前記接合面は、前記相手電極の先端面よりも小さい、
付記１３から１６の何れか一項に記載の電子装置。
（付記１８）
電極の接合面のうち少なくとも相手電極の先端が接合される部分を取り囲む領域に、前記相手電極の先端が半田を介して前記接合面に溶着する第１の条件とは異なる第２の条件で熱処理されると、前記半田が濡れ広がる堤部を配置した前記電極に対して、前記相手電極の位置合わせを行い、
前記相手電極の位置合わせを行った前記電極に対して、前記第１の条件で熱処理を行い、
前記第１の条件で熱処理を行った前記電極に対して、前記第２の条件で熱処理を行う、
電極の接合方法。
（付記１９）
前記堤部は、微粒子によって形成されている、
付記１８に記載の電極の接合方法。
（付記２０）
前記微粒子は、少なくとも表面がＮｉに覆われている、
付記１９に記載の電極の接合方法。
（付記２１）
前記堤部は、前記第１の条件による熱処理において前記半田が前記堤部に濡れ広がるのを抑制し、前記第２の条件による熱処理において前記半田が前記堤部に濡れ広がるのを許容する被膜に覆われている、
付記１８から２０の何れか一項に記載の電極の接合方法。
（付記２２）
前記第１の条件とは、前記堤部を覆う酸化被膜を還元しないガス雰囲気であり、
前記第２の条件とは、前記堤部を覆う酸化被膜を還元するガス雰囲気である、
付記１８から２１の何れか一項に記載の電極の接合方法。
（付記２３）
前記接合面は、前記相手電極の先端面よりも小さい、
付記１８から２２の何れか一項に記載の電極の接合方法。 In addition, the present application includes the following supplementary matters.
(Appendix 1)
A joint surface on which the tip of the counterpart electrode is welded via solder when heat-treated under the first condition;
A portion of the joining surface that is disposed in a region surrounding at least a portion to which the tip of the counterpart electrode is joined, and when the heat treatment is performed under a second condition different from the first condition, Comprising
electrode.
(Appendix 2)
The bank is formed by fine particles,
The electrode according to appendix 1.
(Appendix 3)
The fine particles have at least a surface covered with Ni,
The electrode according to attachment 2.
(Appendix 4)
The bank portion is a film that suppresses the solder from spreading to the bank portion in the heat treatment under the first condition and allows the solder to spread into the bank portion in the heat treatment according to the second condition. Covered,
The electrode according to any one of appendices 1 to 3.
(Appendix 5)
The first condition is a gas atmosphere that does not reduce the oxide film covering the bank portion,
The second condition is a gas atmosphere that reduces an oxide film covering the bank portion.
The electrode according to any one of appendices 1 to 4.
(Appendix 6)
The bonding surface is smaller than the tip surface of the counterpart electrode;
The electrode according to any one of appendices 1 to 5.
(Appendix 7)
When the heat treatment is performed under the first condition, the bonding surface where the tip of the mating electrode is welded via solder, and at least a portion of the bonding surface surrounding the portion where the tip of the mating electrode is bonded, An embankment comprising a bank portion where the solder spreads when heat-treated under a second condition different from the first condition;
A plurality of the electrodes arranged at positions corresponding to the counterpart electrodes arranged in other electronic components, and
Electronic components.
(Appendix 8)
The bank is formed by fine particles,
The electronic component according to appendix 7.
(Appendix 9)
The fine particles have at least a surface covered with Ni,
The electronic component according to appendix 8.
(Appendix 10)
The bank portion is a film that suppresses the solder from spreading to the bank portion in the heat treatment under the first condition and allows the solder to spread into the bank portion in the heat treatment according to the second condition. Covered,
The electronic component according to any one of appendices 7 to 9.
(Appendix 11)
The first condition is a gas atmosphere that does not reduce the oxide film covering the bank portion,
The second condition is a gas atmosphere that reduces an oxide film covering the bank portion.
The electronic component according to any one of appendices 7 to 10.
(Appendix 12)
The bonding surface is smaller than the tip surface of the counterpart electrode;
The electronic component according to any one of appendices 7 to 11.
(Appendix 13)
At least two electronic components;
An electrode arranged on any one of the two electronic components, and a counter electrode arranged on any other electronic component,
Each electrode arranged in one of the electronic components is
A bonding surface in which the tip of the counterpart electrode is welded via solder by heat treatment according to a first condition;
A bank portion that is disposed in a region surrounding at least a portion of the bonding surface to which the tip of the counterpart electrode is bonded, and in which the solder is spread and spread by heat treatment under a second condition different from the first condition; , Each having
Electronic equipment.
(Appendix 14)
The bank is formed by fine particles,
The electronic device according to attachment 13.
(Appendix 15)
The fine particles have at least a surface covered with Ni,
The electronic device according to appendix 14.
(Appendix 16)
The first condition is a gas atmosphere that does not reduce the oxide film covering the bank portion,
The second condition is a gas atmosphere that reduces the oxide film covering the bank portion.
The electronic device according to any one of appendices 13 to 15.
(Appendix 17)
The bonding surface is smaller than the tip surface of the counterpart electrode;
The electronic device according to any one of appendices 13 to 16.
(Appendix 18)
Heat treatment under a second condition different from the first condition in which the tip of the counterpart electrode is welded to the joint surface via solder in a region surrounding at least a portion of the joint surface of the electrode where the tip of the counterpart electrode is joined Then, with respect to the electrode where the bank part where the solder spreads wet is arranged, the position of the counterpart electrode is adjusted,
The electrode subjected to the alignment of the counterpart electrode is heat-treated under the first condition,
The electrode that has been heat-treated under the first condition is heat-treated under the second condition.
Electrode bonding method.
(Appendix 19)
The bank is formed by fine particles,
The method for joining electrodes according to appendix 18.
(Appendix 20)
The fine particles have at least a surface covered with Ni,
The electrode joining method according to appendix 19.
(Appendix 21)
The bank portion is a film that suppresses the solder from spreading to the bank portion in the heat treatment under the first condition and allows the solder to spread into the bank portion in the heat treatment according to the second condition. Covered,
The method for joining electrodes according to any one of appendices 18 to 20.
(Appendix 22)
The first condition is a gas atmosphere that does not reduce the oxide film covering the bank portion,
The second condition is a gas atmosphere that reduces an oxide film covering the bank portion.
The method for joining electrodes according to any one of appendices 18 to 21.
(Appendix 23)
The bonding surface is smaller than the tip surface of the counterpart electrode;
The method for joining electrodes according to any one of appendices 18 to 22.

１・・電極；２・・接合面；３・・堤部；４・・基部；５・・微粒子；６・・核；７・・被膜；８・・基板；９・・相手電極；２０・・半導体装置；２１・・電極部；Ｓ・・半田；Ｒ・・めっきレジスト 1 .. Electrode; 2 .. Bonding surface; 3 .. Bank part; 4 .. Base part; 5 .. Fine particles;・ Semiconductor device; 21. ・ Electrode part; S ・ ・ Solder; R ・ ・ Plating resist

Claims (9)

第１の条件で熱処理されると相手電極の先端が半田を介して溶着する接合面と、
前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件で熱処理されると前記半田が濡れ広がる堤部と、を備える、
電極。 A joint surface on which the tip of the counterpart electrode is welded via solder when heat-treated under the first condition;
A portion of the joining surface that is disposed in a region surrounding at least a portion to which the tip of the counterpart electrode is joined, and when the heat treatment is performed under a second condition different from the first condition, Comprising
electrode. 前記堤部は、微粒子によって形成されている、
請求項１に記載の電極。 The bank is formed by fine particles,
The electrode according to claim 1. 前記微粒子は、少なくとも表面がＮｉに覆われている、
請求項２に記載の電極。 The fine particles have at least a surface covered with Ni,
The electrode according to claim 2. 前記堤部は、前記第１の条件による熱処理において前記半田が前記堤部に濡れ広がるのを抑制し、前記第２の条件による熱処理において前記半田が前記堤部に濡れ広がるのを許容する被膜に覆われている、
請求項１から３の何れか一項に記載の電極。 The bank portion is a film that suppresses the solder from spreading to the bank portion in the heat treatment under the first condition and allows the solder to spread into the bank portion in the heat treatment according to the second condition. Covered,
The electrode according to any one of claims 1 to 3. 前記第１の条件とは、前記堤部を覆う酸化被膜を還元しないガス雰囲気であり、
前記第２の条件とは、前記堤部を覆う酸化被膜を還元するガス雰囲気である、
請求項１から４の何れか一項に記載の電極。 The first condition is a gas atmosphere that does not reduce the oxide film covering the bank portion,
The second condition is a gas atmosphere that reduces an oxide film covering the bank portion.
The electrode according to any one of claims 1 to 4. 前記接合面は、前記相手電極の先端面よりも小さい、
請求項１から５の何れか一項に記載の電極。 The bonding surface is smaller than the tip surface of the counterpart electrode;
The electrode according to any one of claims 1 to 5. 第１の条件で熱処理されると相手電極の先端が半田を介して溶着する接合面と、前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件で熱処理されると前記半田が濡れ広がる堤部と、を備える電極と、
前記電極を、他の電子部品に配列されている前記相手電極に各々対応する位置に複数配列した部材と、を備える、
電子部品。 When the heat treatment is performed under the first condition, the bonding surface where the tip of the mating electrode is welded via solder, and at least a portion of the bonding surface surrounding the portion where the tip of the mating electrode is bonded, An embankment comprising a bank portion where the solder spreads when heat-treated under a second condition different from the first condition;
A plurality of the electrodes arranged at positions corresponding to the counterpart electrodes arranged in other electronic components, and
Electronic components. 少なくとも２つの電子部品と、
前記２つの電子部品のうち何れか一方の電子部品に配列される電極、及び、何れか他方の電子部品に配列される相手電極と、を備え、
前記何れか一方の電子部品に配列される各電極は、
第１の条件による熱処理によって前記相手電極の先端が半田を介して溶着している接合面と、
前記接合面のうち少なくとも前記相手電極の先端が接合される部分を取り囲む領域に配置されており、前記第１の条件とは異なる第２の条件による熱処理によって前記半田が濡れ広がっている堤部と、を各々有している、
電子装置。 At least two electronic components;
An electrode arranged on any one of the two electronic components, and a counter electrode arranged on any other electronic component,
Each electrode arranged in one of the electronic components is
A bonding surface in which the tip of the counterpart electrode is welded via solder by heat treatment according to a first condition;
A bank portion that is disposed in a region surrounding at least a portion of the bonding surface to which the tip of the counterpart electrode is bonded, and in which the solder is spread and spread by heat treatment under a second condition different from the first condition; , Each having
Electronic equipment. 電極の接合面のうち少なくとも相手電極の先端が接合される部分を取り囲む領域に、前記相手電極の先端が半田を介して前記接合面に溶着する第１の条件とは異なる第２の条件で熱処理されると、前記半田が濡れ広がる堤部を配置した前記電極に対して、前記相手電極の位置合わせを行い、
前記相手電極の位置合わせを行った前記電極に対して、前記第１の条件で熱処理を行い
、
前記第１の条件で熱処理を行った前記電極に対して、前記第２の条件で熱処理を行う、
電極の接合方法。 Heat treatment under a second condition different from the first condition in which the tip of the counterpart electrode is welded to the joint surface via solder in a region surrounding at least a portion of the joint surface of the electrode where the tip of the counterpart electrode is joined Then, with respect to the electrode where the bank part where the solder spreads wet is arranged, the position of the counterpart electrode is adjusted,
The electrode subjected to the alignment of the counterpart electrode is heat-treated under the first condition,
The electrode that has been heat-treated under the first condition is heat-treated under the second condition.
Electrode bonding method.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268028A (en) * 1993-03-16 1994-09-22 Fujitsu Ltd Manufacture of semiconductor device
JPH06310567A (en) * 1993-04-23 1994-11-04 Citizen Watch Co Ltd Method and structure for mounting semiconductor
JPH07169873A (en) * 1993-12-15 1995-07-04 Nec Corp Multi-layer board and manufacture thereof
JPH07273146A (en) * 1994-03-30 1995-10-20 Matsushita Electric Ind Co Ltd Mounting method for semiconductor device
JP2002151551A (en) * 2000-11-10 2002-05-24 Hitachi Ltd Flip-chip mounting structure, semiconductor device therewith and mounting method
JP2009105119A (en) * 2007-10-22 2009-05-14 Spansion Llc Semiconductor device and its manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268028A (en) * 1993-03-16 1994-09-22 Fujitsu Ltd Manufacture of semiconductor device
JPH06310567A (en) * 1993-04-23 1994-11-04 Citizen Watch Co Ltd Method and structure for mounting semiconductor
JPH07169873A (en) * 1993-12-15 1995-07-04 Nec Corp Multi-layer board and manufacture thereof
JPH07273146A (en) * 1994-03-30 1995-10-20 Matsushita Electric Ind Co Ltd Mounting method for semiconductor device
JP2002151551A (en) * 2000-11-10 2002-05-24 Hitachi Ltd Flip-chip mounting structure, semiconductor device therewith and mounting method
JP2009105119A (en) * 2007-10-22 2009-05-14 Spansion Llc Semiconductor device and its manufacturing method

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