JP2014229332A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing an influence of a leak current even when successively receiving a plurality of write commands for floating-body type memory cells.SOLUTION: A semiconductor device of the present invention is provided with a configuration in which connection between a first bit line LBL0 and a second bit line GBL is controlled by a hierarchical switch. In a first period P1 starting from the time of receiving a write command WR, a selection word line WL0 is inactivated, the hierarchical switch is disconnected, and the first bit line LBL0 is held in a pre-charged state. In a second period P2 following the first period P1, the selection word line WL0 is activated and the pre-charged state is released. In the first period P1, if another write command WR following the write command WR being responded to is not received, the first period P1 is terminated when a predetermined time has passed; and if the other write command is received, the first period P1 is extended until the predetermined time has passed further from the reception time.

Description

  The present invention relates to a semiconductor device employing a memory cell including a selection transistor having a floating body structure.

  In recent years, in a semiconductor device such as a DRAM (Dynamic Random Access Memory), for example, a floating body type transistor using an SOI (Silicon on Insulator) structure is known as a transistor structure for realizing high integration of memory cells. ing. A floating body type transistor operates in a state in which a body between a source and a drain arranged on an SOI substrate with an insulating film interposed therebetween is completely depleted and electrically floated (for example, refer to Patent Document 1). ). On the other hand, when a memory cell is configured using a floating body type transistor, a leakage current between the source and the drain is likely to be generated due to the structure, so that the accumulated charge in the capacitor of the memory cell is lost due to the influence of the leakage current. Measures to prevent it are necessary. For example, in Patent Document 1 (FIG. 11), during the read operation of a memory cell, after the bit line potential is sense-amplified, the complementary bit line is disconnected from the sense amplifier while maintaining the amplified state in the sense amplifier. A control method for precharging to a predetermined potential has been proposed. As a result, leakage current from the memory cell holding information to the bit line can be reduced.

JP 2011-146104 A

  In general, a memory cell array having a hierarchized bit line configuration tends to be employed for miniaturization and high integration of DRAM. Even when a memory cell is configured using floating body type transistors in this type of hierarchical memory cell array, as described above, there is a problem that data is lost due to leakage current from the memory cell via the local bit line. For example, assuming a write operation on a selected memory cell, a predetermined period for the above-described leakage countermeasure is provided prior to responding to a write command, and during this period, the word line is deactivated, and By detaching the local bit line from the global bit line and keeping the precharged state, it is possible to avoid data loss due to the influence of the leakage current. In this case, after the elapse of the predetermined period, the write operation to the memory cell is performed reliably by driving the word line to the selected state, releasing the precharge of the local bit line, and executing the write operation of the memory cell. be able to.

  However, the above-described leakage countermeasure control is effective when a single write command is received, but in reality, a situation where a plurality of write commands are continuously received by designating the same word line is also assumed. . In such a situation, when a write operation is executed in response to a preceding write command, even if a subsequent write command is received, there is a situation in which a predetermined period for leak countermeasures ends immediately after that. It is done. Therefore, while continuously receiving a plurality of write commands, the memory cell data is transmitted one after another via the local bit line while always holding the word line in the selected state. It is inevitable that data in the neighboring memory cell is lost due to the leak current from the cell. Therefore, in a DRAM that employs a floating body type memory cell, in a situation where a plurality of write commands are continuously received, there is a problem that the control for leakage countermeasures does not function effectively and the influence of leakage current cannot be suppressed. is there.

  In order to solve the above problems, a semiconductor device of the present invention includes a first bit line connected to a plurality of memory cells, a second bit line arranged corresponding to the first bit line, A hierarchical switch for controlling electrical connection between the first bit line and the second bit line; and a plurality of word lines for selectively connecting the plurality of memory cells to the first bit line; A precharge circuit for precharging the first bit line to a predetermined precharge voltage; and a selection of the selected word line and the plurality of memory cells among the plurality of word lines in response to a write command. A control unit that controls a write operation for the memory cell, and the control unit keeps the selected word line in an inactive state in a first period starting from reception of the write command. And the first In a second period starting from the end of the first period, the bit line is kept precharged to the predetermined precharge voltage while being separated from the second bit line by the hierarchical switch. Maintaining the selected word line in an active state, maintaining a state in which the precharge is released while the first bit line is connected to the second bit line by the hierarchical switch, and in the first period When no other write command following the write command being responded is received, the first period is terminated when a predetermined time has elapsed, and when the other write command is received, the reception time is the starting point. Further, control is performed so as to extend the first period until the predetermined time elapses.

  According to the semiconductor device of the present invention, when the write operation of the selected memory cell is performed, the first bit line is precharged while the selected word line is inactivated in the first period when the write command is received. By maintaining the state, the influence of the leakage current of the memory cell is suppressed, and thereafter, the write operation to the target memory cell is executed in the second period. At this time, if the write command is received only once, the transition to the second period is made when a predetermined time has elapsed from the start of the first period, but in the case of receiving a plurality of write commands continuously, The first period is extended until a predetermined period elapses from the timing at which the subsequent write command is received in the middle of the first period. Therefore, the write operation for the last write command becomes effective, and the problem of leakage current due to the second period becoming too long can be avoided.

  As described above, according to the present invention, in a semiconductor device having a floating body type memory cell, even in a situation where a plurality of write commands are continuously received during a write operation of the memory cell, a countermeasure against leakage is provided. It is possible to make the control function effectively and minimize problems such as data loss due to leakage current.

1 is a block diagram showing an overall configuration of a DRAM of an embodiment FIG. 2 is a diagram illustrating an example of a partial circuit configuration of the memory cell array of FIG. 1. It is a figure which shows the typical cross-section example of a floating body type memory cell. It is a figure which shows an example of a structure of a sense amplifier and its peripheral circuit part. For comparison with the present embodiment, an operation waveform when a write command is received only once after receiving an active command is shown as a comparative example. For comparison with the present embodiment, it is a diagram illustrating an operation waveform when a plurality of write commands are continuously received after reception of an active command as a comparative example. FIG. 6 is a diagram illustrating operation waveforms when a plurality of write commands are continuously received after receiving an active command in the DRAM of the present embodiment. FIG. 2 is a schematic configuration diagram of a write state generation circuit of FIG. 1. FIG. 9 is a diagram showing a specific example of a logic block of a write state generation circuit for an arbitrary bank in the configuration of FIG. 8. FIG. 10 is a timing chart illustrating an operation in a situation where a write command is received once in the write state generation circuit of FIG. 9. FIG. 10 is a timing chart showing an operation in a situation where two write commands are continuously received in the write state generation circuit of FIG. 9. It is a figure explaining the operation | movement in the case of receiving a write command with various patterns in this embodiment.

  Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. An embodiment in which the present invention is applied to a DRAM (Dynamic Random Access Memory) as an example of a semiconductor device will be described below.

  The configuration and operation of the DRAM of this embodiment to which the present invention is applied will be described below. FIG. 1 is a block diagram showing the overall configuration of the DRAM of this embodiment. The DRAM shown in FIG. 1 includes a memory cell array 10 and peripheral circuits, an X decoder / X timing generation circuit 11, a Y decoder / Y timing generation circuit 12, a data control circuit 13, a data latch circuit 14, an input / output interface 15, an internal The circuit includes a clock generation circuit 16, a control signal generation circuit 17, a DLL (Delay Locked Loop) circuit 18, and a write state generation circuit 30.

  Memory cell array 10 includes a plurality of memory cells MC provided at intersections of a plurality of word lines WL and a plurality of local bit lines LBL. As the plurality of memory cells MC, a floating body structure is assumed to be adopted, but a specific structure will be described later. Further, the bit line configuration of the memory cell array 10 is assumed to be hierarchized into a local bit line LBL in a lower hierarchy and a global bit line GBL (FIG. 2) in an upper hierarchy. The memory cell array 10 is divided into a plurality of banks (BANK) that can be controlled independently. In the example of FIG. 1, m + 1 (m is an integer) banks (BANK_0 to BANK_m) are provided. Corresponding to each bank, an X control circuit 101 and a Y control circuit 102 are provided, respectively. In addition, a sense amplifier group, which will be described later, a sub word driver group for driving the word line WL, and the like are arranged around each bank. In this embodiment, a write state generation circuit 30 for controlling various timings of a write state period and a cell write period described later in the write operation is provided in relation to the control of each bank. The operation and configuration of the circuit 30 will be described later in detail.

  The memory cell array 10 is connected to the data latch circuit 14 via a data transfer bus B3. The data latch circuit 14 is connected to the input / output interface 15 via a data transfer bus B2. The input / output interface 15 performs data input / output (DQ) with the outside via the data transfer bus B1, and inputs / outputs data strobe signals DQS and / DQS. Data transfer via the buses B1, B2, and B3 is controlled by the data control circuit 13, and the output timing at the input / output interface 15 is controlled by the DLL circuit 18 to which the external clocks CK and / CK are supplied. . The X decoder / X timing generation circuit 11 controls the X control circuit 101 of each bank, and the Y decoder / Y timing generation circuit 12 controls the Y control circuit 102 of each bank.

  The internal clock generation circuit 16 generates an internal clock based on the external clocks CK and / CK and the clock enable signal CKE and supplies it to each part of the DRAM. The control signal generation circuit 17 generates a control signal based on a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE from the outside, and supplies them to each part of the DRAM. . The X decoder / X timing generation circuit 11, the Y decoder / Y timing generation circuit 12, and the data control circuit 13 are supplied with an external address ADD and a bank address BA.

  Next, the configuration and operation of the main part of the memory cell array 10 of FIG. 1 in the DRAM of this embodiment will be described. FIG. 2 shows an example of a partial circuit configuration of the memory cell array 10 of FIG. The circuit configuration of FIG. 2 includes two local bit lines LBL0 and LBL1, two adjacent memory cells MC0 and MC1 connected to one local bit line LBL0, and the other local bit line in the memory cell array 10. This corresponds to a range including one memory cell MC2 connected to LBL1 and its peripheral circuits. The memory cell MC0 is formed at the intersection of the word line WL0 and the local bit line LBL0, and the memory cell MC1 is formed at the intersection of the word line WL1 adjacent to the word line WL0 and the local bit line LBL1. FIG. 2 shows only two memory cells MC0 and MC1 as memory cells MC connected to the local bit line LBL0, and one memory cell as another memory cell MC connected to the local bit line LBL1. Although only MC2 is shown, in reality, a predetermined number of memory cells MC are connected to each one local bit line, and the same number of word lines WL as the memory cells MC are arranged. .

  Each memory cell MC (including memory cells MC0, MC1, and MC2) in the memory cell array 10 includes a floating body type selection transistor Q0 and a capacitor Cs that stores high or low binary information as charges. Configured. Here, FIG. 3 shows a schematic cross-sectional structure example of the floating body type memory cell MC. In the structural example shown in FIG. 3, a substrate voltage VBB is applied to a P-type silicon substrate 20, and an element isolation insulating film 21 is formed thereon. An N-type impurity layer 22 serving as a source and an N-type impurity layer 23 serving as a drain are formed on the element isolation insulating film 21 as a transistor structure of the selection transistor Q0, and between the source and drain. A floating body 24 that operates in a fully depleted state is formed. One N-type impurity layer 22 is connected to the upper local bit line LBL (for example, local bit lines LBL0 and LBL1), and the other N-type impurity layer 23 is connected to the storage electrode 27 which is one electrode of the capacitor Cs. Has been. The plate electrode 28 which is the other electrode of the capacitor Cs is opposed to the storage electrode 27 with the dielectric film interposed therebetween, and is connected to the wiring of the upper layer plate voltage VPLT. A gate electrode 26 connected to the word line WL is formed above the floating body 24 sandwiched between the N-type impurity layers 22 and 23 with the gate dielectric film 25 interposed therebetween.

  The structural feature of the floating body type memory cell MC shown in FIG. 3 is that the source and drain (N-type impurity layers 22 and 23) of the selection transistor Q0 and the formation region of the floating body 24 form the element isolation insulating film 21. This is a point separated from the P-type silicon substrate 20. Thereby, the floating body 24 is in a floating state. The silicon layer on which the N-type impurity layers 22 and 23 and the floating body 24 on the element isolation insulating film 21 are formed is not particularly limited, but is formed with a thickness of, for example, 50 mm or less. In this case, the floating body 24 operates in a fully depleted state, and there is no neutral region of P-type silicon. However, since the floating body structure shown in FIG. 3 is likely to cause a leak current between the source and the drain, it is necessary to take measures against the disappearance of the accumulated charge in the capacitor Cs of the memory cell MC. It will be described later.

  Returning to FIG. 2, the transistor Q10 has a role of precharging the local bit line LBL0 to the precharge voltage VBLR in accordance with the precharge signal PCG applied to the gate. The precharge voltage VBLR is set to, for example, an intermediate potential between the power supply voltage and the ground potential (the potential corresponding to the high information and the low information corresponding to the memory cell MC). By controlling the precharge signal PCG to high, the local bit line LBL0 can be precharged to the precharge voltage VBLR. In the present embodiment, in addition to the precharge operation, control for precharging the local bit line LBL0 to the precharge voltage VBLR is also performed during a predetermined period for countermeasures against the above-described leakage current after the active operation. The other local bit line LBL1 is similarly provided with a transistor Q10 and controlled by the precharge signal PCG, but is not shown for simplicity.

  The transistor Q11 is a hierarchical switch that controls the connection state between the local bit line LBL0 and the global bit line GBL in accordance with a control signal SHR applied to the gate. When the control signal SHR is high, the local bit line LBL0 and the global bit line GBL are electrically connected. When the control signal SHR is low, the local bit line LBL0 and the global bit line GBL are electrically disconnected. A transistor Q11 is similarly provided between the other local bit line LBL1 and another global bit line (not shown), and is controlled by a control signal SHR. To do.

  The precharge signal PCG and the control signal SHR are generated by the X decoder / X timing generation circuit 11 of FIG.

  A sense amplifier SA is connected to one end of the global bit line GBL. The sense amplifier SA is connected to the global bit line GBL and the global bit line / GBL complementary to the global bit line GBL, and has a differential configuration for amplifying and holding the respective differential voltages. It is assumed that corresponding sense amplifiers SA are also provided in other global bit lines (not shown). Here, with reference to FIG. 4, an example of the configuration of the sense amplifier SA and its peripheral circuit portion will be described.

  As shown in FIG. 4, each sense amplifier SA is configured by cross-coupling the input and output of a pair of inverters composed of two PMOS transistors and two NMOS transistors. A pair of global bit lines GBL and / GBL are connected to the two input nodes of the sense amplifier SA. 4 are a common source line CSP that supplies high-potential power to the two PMOS transistors of the sense amplifier SA, and a common source line that supplies low-potential power to the two NMOS transistors of the sense amplifier SA. CSN is arranged. Each common source line CSP, CSN is connected to a sense amplifier drive circuit SAD. The sense amplifier drive circuit SAD supplies a high-potential power supply voltage to the common source line CSP and a low-potential power supply voltage to the common source line CSN according to a predetermined control signal.

  Next, an outline of the write operation of the DRAM of this embodiment will be described with reference to FIGS. First, for comparison with the present embodiment, a period (hereinafter, simply referred to as “leak countermeasure period”) for dealing with a leakage current of the memory cell MC having the floating body structure is provided, and the later-described in the present embodiment. The write operation when the timing control is not introduced will be described with reference to comparative examples shown in FIGS. The comparative example of FIG. 5 shows an operation waveform when the write command WR is received only once after receiving the active command ACT. Further, the comparative example of FIG. 6 shows an operation waveform when a plurality of write commands WR are continuously received after reception of the active command ACT.

  When the operation of FIG. 5 is started, an active command ACT is received, and the selected word line WL0 is driven high. Note that the word line WL1 (FIG. 2) remains low because it is not selected. At this time, by controlling the control signal SHR from low to high, the local bit line LBL0 and the global bit line GBL are connected via the transistor Q11 (FIG. 2), and the precharge signal PCG is controlled from high to low. As a result, the precharge of the local bit line LBL0 is released. As a result, a very small potential is read from the memory cell MC0 holding high data to the local bit line LBL0 (timing t0), and the potential is transmitted to the global bit line GBL via the transistor Q11. At this time, the precharge of the global bit line GBL is also released. Next, the sense amplifier SA (FIG. 4) is driven, and the local bit line LBL0 and the global bit line GBL are each amplified to a high potential (timing t1).

  Thereafter, the word line WL0 is returned to a non-selected low (timing t2). At this time, the local bit line LBL is disconnected from the global bit line GBL by returning the control signal SHR to low, and the local bit line LBL0 is precharged to the precharge voltage VBLR by returning the precharge signal PCG to high. The period from the timing t2 to a timing t4 described later corresponds to the above-described leakage countermeasure period. That is, in the leakage countermeasure period, the word line WL0 is maintained in a state in which the memory cell MC0 is maintained high while the local bit line LBL0 is precharged and the word line WL0 is maintained in a non-selected low level. If the word line WL0 and the local bit line LBL0 are kept in a state before the timing t2, if another memory cell MC1 connected to the local bit line LBL0 common to the memory cell MC0 holds low data, Data in the memory cell MC1 may be lost due to a leak current from the memory cell MC0 that holds high. However, by providing a leakage countermeasure period, it is possible to effectively prevent problems caused by such a leakage current.

  Next, when the write command WR is received at the timing t3, the state transits to the write state period P1. This write state period P1 secures a time required until an actual write operation to the memory cell MC0 becomes possible in response to the write command WR. During the write state period P1, the word line WL0 is The states of non-selection (low), control signal SHR being low, and precharge signal PC being high do not change. That is, the write state period P1 is included in the above-described leakage countermeasure period. When the write state period P1 ends and transitions to the cell write period P2 at timing t4, the word line WL0 is driven high again. At this time, the control signal SHR is controlled from low to high and from the precharge signal PCG high to low, respectively, and the control state is the same as when the active command ACT is received. As a result, externally input data is transmitted from the sense amplifier SA via the global bit line GBL, the transistor Q11, and the local bit line LBL0, and written to the memory cell MC0. In the example of FIG. 5, a case where low data is written to the memory cell MC0 is shown.

  Thereafter, when the cell write period P2 ends at timing t5, the precharge command PRE is received. As a result, the word line WL0 is returned to an unselected row. At this time, the control signal SHR is controlled from the high level to the low level and the precharge signal PCG is controlled from the low level to the high level, respectively, so that the control state is the same as the above-described leak countermeasure period and the write state period P1. At this time, the local bit line LBL0 is precharged to the precharge voltage VBLR.

  On the other hand, when the operation of FIG. 6 is started, from the initial time point to the reception of the active command ACT, the leakage countermeasure period, the reception of the first write command WR, and the write state period P1, the same as in FIG. It becomes an operation waveform. Next, when transitioning to the cell write period P2 at timing t4, it is understood that unlike FIG. 5, the second write command WR is received and the write command WR is repeatedly received thereafter. As apparent from FIG. 6, since the second write command WR is received when the cell write period P2 responds to the first write command WR, the state of the cell write period P2 is maintained. The same applies to the third and subsequent write commands WR, and is received before the completion of the write operation based on the write command WR preceding it, so that the cell write period P2 until the write operation based on the last write command WR is completed. This state persists. At this time, data corresponding to the last received write command WR is written and held in each memory cell (MC0, MC2,...) To be accessed on the selected word line WL0. Will be. Thus, in the comparative example of FIG. 6, since the time of the cell write period P2 is longer than that of the comparative example of FIG. 5, no countermeasure against leakage can be taken during that time, and data loss due to the leakage current may occur. There is a risk of manifestation.

  On the other hand, according to FIG. 7 of the present embodiment, the operation waveform is the same as that in FIG. 6 from the initial state to the timing t4, but the write state period P1 is maintained after the timing t4. Different from FIG. That is, the write state period P1 in FIG. 6 does not end at timing t4 after reception of the first write command WR, but is extended to timing t6 after reception of the last write command WR, and the cell write period at timing t6. Transition to P2. As a result, even if a plurality of write commands WR are continuously received, the time of the cell write period P2 does not become long, and the state of the leakage countermeasure period (the word line WL0 is not selected, the control signal SHR is low, the precharge is performed) The signal PCG can remain high). At this time, only data corresponding to the last received write command WR is written to each memory cell (MC0, MC2,...) On the selected word line WL0. As described above, when the plurality of write commands WR are continuously received by the operation of FIG. 7 according to the present embodiment, the influence of the leakage current that becomes apparent as the time of the cell write period P2 becomes longer as shown in FIG. Can be reliably avoided.

  Next, a specific configuration and control for realizing the operation of FIG. 7 according to the present embodiment will be described with reference to FIGS. The operation in FIG. 7 is controlled mainly based on the operation of the write state generation circuit 30 in FIG. FIG. 8 is a schematic configuration diagram of the write state generation circuit 30. As shown in FIG. 8, m + 1 write state generation circuits 30 (0) to 30 (m) that can be individually controlled are provided corresponding to m + 1 banks in the memory cell array 10. The write command WR is supplied in common to the write state generation circuits 30 (0) to 30 (m), and m + 1 bank addresses BA (0) to BA (m) set for each bank correspond to each other. Are individually supplied to the write state generation circuits 30 (0) to 30 (m). Each of the write state generation circuits 30 (0) to 30 (m) receives two kinds of control signals S1 (0) to S1 (m) and S2 (0) to S2 (m), which will be described later, used for timing control. Output to the corresponding bank.

  FIG. 9 shows a specific example of a logic block of the write state generation circuit 30 for an arbitrary bank in the configuration of FIG. FIG. 10 is a timing chart for explaining the operation in the situation where the write state generation circuit 30 in FIG. 9 receives one write command WR. The logic block of FIG. 9 and the operation waveform of FIG. 10 are basically common to the m write state generation circuits 30 of FIG. The write state generation circuit 30 shown in FIG. 9 includes a first delay counter 31, a second delay counter 32, a delay adjustment unit 33, an RS flip-flop 34, a cell write period delay counter 35, and many other logics. It is composed of elements (NAND gate, NOR gate, inverter, etc.).

  The above-described write command WR, bank address BA, and clock CK are input to the write state generation circuit 30 in FIG. As shown in FIG. 10, the clock CK having a fixed period is supplied to the first delay counter 31, the second delay counter 32, and the cell write period delay counter 35 of FIG. 9, and is used for each count operation. When the write command WR and the bank address BA are input, the count operation of the first delay counter 31 is started from the timing Ta (FIGS. 9 and 10) immediately after that. The first delay counter 31 counts the timing Tb (FIG. 9) delayed from the timing Ta by a time corresponding to the sum (AL + CWL) of the additive latency AL and the CAS write latency CWL. In general, (AL + CWL) corresponds to the number of cycles (write latency) from the reception of the write command WR to the actual writing of data. The second delay counter 32 counts the timing Td (FIGS. 9 and 10) delayed from the timing Tb generated by the first delay counter 31 by the number of BL / 2 cycles corresponding to half the burst length BL. To do. At this time, the control signal S1 output from the second delay counter 32 is a pulse that rises at the timing Td.

  In addition to the timing Td, the second delay counter 32 counts a timing Tc (FIGS. 9 and 10) preceding the timing Td by a predetermined number of cycles and transmits it to the delay adjusting unit 33. That is, the second delay counter 32 counts the number of cycles (BL / 2−x) shorter by x cycles than the number of cycles (BL / 2) at the timing Td. In the example of FIG. 10, it can be seen that the timing Tc precedes the timing Td by one cycle (x = 1). Then, the delay adjustment unit 33 delays the timing Tc counted by the second delay counter 32 by a predetermined delay time Δt to generate the timing Tc + Δt. As shown in FIG. 10, the delay time Δt is adjusted according to the appropriate drive timing of the word line WL0, and will be described in detail later.

  On the other hand, the cell write period delay counter 35 counts the cell write period P2 already described. The logic circuit group and the RS flip-flop 34 provided in the preceding stage of the cell write period delay counter 35 are connected to the cell write period P2 based on the output of the delay adjustment unit 33, the pulse of the timing Ta, and the output of the cell write period delay counter 35. Control the timing including Further, the control signal S2 described above is output via a logic circuit group provided in the subsequent stage of the cell write period delay counter 35. The control signal S2 rises high at timing Tc + Δt generated by the delay control unit 33, and returns low at timing Te described later. As shown in FIG. 10, it can be seen that the starting point precedes the cell write period P2 and the end point coincides with the cell write period P2 during the period in which the control signal S2 is kept high.

  FIG. 10 shows the operation waveforms of the selected word line WL0 and the selected memory cell MC0 in an overlapping manner. The word line WL0 is driven in conjunction with the rising timing of the control signal S2. On the other hand, writing to the memory cell MC0 is started in conjunction with the rising timing of the control signal S1 (timing Td of the starting point of the cell write period P2). This timing Td coincides with the activation timing of the selection signal YS that is activated when a write operation to the memory cell MC0 is performed from the outside via the global bit line GBL. In this way, when writing to the selected memory cell MC0, by starting the selected word line WL0 at a timing preceding it, it is possible to compensate for the influence due to the delay at the time of starting the word line WL0, The write recovery time tWR equivalent to the case where the start timing is controlled using the selection signal YS can be maintained.

  Next, FIG. 11 is a timing chart showing the operation in the situation where the write state generation circuit 30 of FIG. 9 receives two write commands WR continuously unlike FIG. In the following, differences from FIG. 10 in the operation waveforms of FIG. 11 will be mainly described. In FIG. 11, after the first write command WR is received, the second write command WR is received after a predetermined number of cycles of the clock CK has elapsed. At this time, it is assumed that the reception interval of the two write commands WR satisfies a condition shorter than (AL + CWL) + (BL / 2−x), which is the total number of cycles between the timings Ta to Tc described in FIG. To do.

  When the above conditions are satisfied, the control signal S1 is kept low after the first delay counter 31 and the second delay counter 32 start the counting operation in response to the first write command WR. Accordingly, in FIG. 9, in response to the second write command WR, the above-described count operation is once reset, so that the same count operation is started again from the reception time of the second write command WR. As a result, as shown in FIG. 11, the rise timings of the control signals S1 and S2 are delayed as compared with FIG. 10, and the write state period P1 is extended. As described above, the control of FIG. 7 in the present embodiment can be realized by the same control as the operation waveform of FIG.

  Next, with reference to FIG. 12, the operation when receiving the write command WR in various patterns in the present embodiment will be described. In FIG. 12, five cases 1 to 5 are compared and shown as a situation where the write command WR is received two or more times following the active command ACT. In any case, a portion corresponding to the time T1 in the write state period P1 in FIG. 5 is indicated by a broken line arrow, and a portion corresponding to the time T2 in the cell write period P2 in FIG. 5 is indicated by a solid line arrow. Further, as the operation waveforms, the word line WL0, the control signal SHR, and the inverted signal of the precharge signal PCG (denoted as / PCG in the figure) change in the same way, and are therefore shown collectively.

  Case 1 in FIG. 12 shows a situation in which, after receiving the first write command WR, following the active command ACT, the second write command WR is received after a sufficient time interval. In this case, in response to each write command WR, the write state period P1 and the subsequent cell write period P2 are controlled according to the same pattern as in FIG.

  In the case 2 of FIG. 12, when a plurality of write commands WR are repeatedly received following the active command ACT, the subsequent write command WR is received immediately after the time T2 of each cell write period P2. Indicates the situation. In this case, unlike FIG. 7, the write state period P1 is not extended, but this corresponds to the worst case in which the repetition period of the plurality of write commands WR is approximately time T1 + T2.

  In case 3 of FIG. 12, when a plurality of write commands WR are repeatedly received following the active command ACT, the subsequent write commands WR are received before the time T1 of each write state period P1 elapses. Shows the situation. That is, it corresponds to the same situation as the operation shown in FIG. 7, and since the write state period P1 is extended until the last write command WR is received, the word line WL or the like does not rise during that period.

  In the case 4 of FIG. 12, when a plurality of write commands WR are repeatedly received following the active command ACT, the time T2 of the cell write period P2 is changed after each transition from the write state period P1 to the cell write period P2. It shows a situation in which a subsequent write command WR is received before it elapses. In this case, in response to each write command WR, the word line WL and the like are raised to start the write operation, but transit to the next write state period P1 on the way. Therefore, the write operation is not guaranteed except for the last write command WR, but no problem occurs if the write operation is guaranteed only for the last write command WR.

  Case 5 in FIG. 12 shows a situation in which the first write command WR is received immediately after the active command ACT. In this case, since it is necessary to raise the word line WL and the like in response to the active command ACT, even if the time T1 has not elapsed since the reception of the first write command WR, the write operation as in cases 1 to 4 is performed. Control different from the state period P1 is performed. Note that normal control is performed for the second write command WR received thereafter.

  As described above, by adopting the configuration and control of the present embodiment, when a write command WR is received while performing control for leak countermeasures in the write operation on the selected memory cell MC. Keeps control against leakage until the time T1 elapses after the transition to the write state period P1, and also extends the write state period P1 even when a plurality of write commands WR are continuously received, thereby preventing leakage. Can be maintained appropriately. As a result, in various write operations, it is possible to effectively prevent a situation in which the leakage current of the memory cell MC causes the data of other memory cells MC to be lost via the local bit line LBL.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range. For example, the present invention is not limited to a DRAM as a semiconductor device, but is a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an ASSP (Application Specific). Standard Product) etc.

DESCRIPTION OF SYMBOLS 10 ... Memory cell array 11 ... X decoder and X timing generation circuit 12 ... Y decoder and Y timing generation circuit 13 ... Data control circuit 14 ... Data latch circuit 15 ... Input / output interface 16 ... Internal clock generation circuit 17 ... Control signal generation circuit 18 ... DLL circuit 20 ... P-type silicon substrate 21 ... Element isolation insulating films 22 and 23 ... N-type impurity layer 24 ... Floating body 25 ... Gate dielectric film 26 ... Gate electrode 27 ... Storage electrode 28 ... Plate electrode 30 ... Light state generation Circuit 31 ... First delay counter 32 ... Second delay counter 33 ... Delay adjustment unit 34 ... RS flip-flop 35 ... Cell write period delay counter MC, MC0, MC1, MC2 ... Memory cells WL, WL0, WL1 ... Word lines LBL, LBL0 , LBL1... Local bit lines GBL, / GB ... global bit lines SA ... sense amplifier SAD ... sense amplifier driving circuit Q10, Q11 ... transistors CSP, CSN ... common source line SHR ... control signal PCG ... precharge signal VBLR ... precharge voltage

Claims (9)

A first bit line connected to a plurality of memory cells;
A second bit line arranged corresponding to the first bit line;
A hierarchical switch for controlling electrical connection between the first bit line and the second bit line;
A plurality of word lines for selectively connecting the plurality of memory cells to the first bit line;
A precharge circuit for precharging the first bit line to a precharge voltage;
In response to a write command, a control unit that controls a write operation for a selected word line of the plurality of word lines and a selected memory cell of the plurality of memory cells;
With
The controller is
In a first period starting from reception of the write command, the selected word line is kept in an inactive state, and the first bit line is separated from the second bit line by the hierarchical switch Keep the precharged state at the precharge voltage,
In the second period starting from the end of the first period, the selected word line is kept active and the first bit line is connected to the second bit line by the hierarchical switch. Keep the precharge released in the state,
In the first period, when no other write command following the write command being responded is received, the first period ends when a predetermined time has elapsed, and when the other write command is received Extending the first period from the reception time until the predetermined time elapses.
A semiconductor device.   2. The semiconductor device according to claim 1, wherein each of the plurality of memory cells includes a capacitor for storing information as a charge and a selection transistor having a floating body structure. It further comprises a bit line configuration hierarchized by local bit lines and global bit lines,
2. The semiconductor device according to claim 1, wherein the first bit line is the local bit line, and the second bit line is the global bit line.   4. The semiconductor device according to claim 3, further comprising a sense amplifier that amplifies and holds the potential of the global bit line. A control signal generating circuit for generating a control signal for controlling a timing of transition from the first period to the second period;
The semiconductor device according to claim 1, wherein the control unit performs control so as to transition from the first period to the second period based on the control signal. A memory cell array divided into a plurality of banks each including the plurality of memory cells;
6. The control signal generation circuit according to claim 5, wherein the control signal generation circuit is provided for each of the plurality of banks, and the write operation for each of the plurality of banks can be controlled according to the different control signals. Semiconductor device.   The control signal generated by the control signal generation circuit includes a first control signal for generating a first timing for starting the second period, and the selection word line prior to the first timing. The semiconductor device according to claim 6, further comprising: a second control signal that generates a second timing for starting driving.   The semiconductor device according to claim 1, wherein the hierarchical switch is a transistor whose conduction is controlled according to a switch control signal applied to a gate.   2. The precharge voltage is set to an intermediate potential between a potential corresponding to high information of the plurality of memory cells and a potential corresponding to low information of the plurality of memory cells. A semiconductor device according to 1.