JP2014229209A - Multi-core system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly detect unauthorized rewriting of data.SOLUTION: A multi-core system comprises: a plurality of CPUs (Central Processing Unit); and a storage unit that stores control data related to an external peripheral device. The plurality of CPUs divide the control data for the peripheral device in initial processing, and execute check processing of unauthorized rewriting of the control data.

Description

  The present invention relates to a multi-core system.

  Patent Document 1 below discloses an electronic control device that includes a plurality of microcomputers, and that allows a control program and control data incorporated in each microcomputer to be easily and reliably rewritten. The electronic control device includes an ECU 2 on which two microcomputers 4 and 6 having a rewritable ROM 14 are mounted. The communication port P1 of the microcomputer 4 is connected to the memory rewriting device 30 via the external communication line 24, while the communication port P2 of the microcomputer 4 is connected to the communication port P1 of the microcomputer 6 via the internal communication line 25. . Each microcomputer 4, 6 stores the value obtained by adding “1” to the identification number received from the communication port P 1 as its own identification number before proceeding to the process for rewriting the contents of the ROM 14, and also “1”. Is transmitted from the communication port P2 to the microcomputer at the next stage. As a result, it is not necessary to previously store the identification number in a non-rewritable memory area in each of the microcomputers 4 and 6.

JP 09-160766 A

  By the way, in the above prior art, various data are generally stored in the ROM of each microcomputer. However, an illegal setting measure for answering a request for guarantee of reliability, that is, an unauthorized operation by a third party other than the manufacturer. No measures are taken to detect data rewrite as soon as possible. For example, in the case of a moving vehicle, data relating to the motor speed limit is stored in advance in the ROM. However, by illegally rewriting the data stored in the ROM, the motor speed is increased beyond the limit. In order to ensure safety, it is necessary to detect unauthorized rewriting of data stored in the ROM as soon as possible from the start of the moving vehicle.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to quickly detect illegal data rewriting.

  In order to achieve the above object, in the present invention, a multi-core system including a plurality of CPUs (Central Processing Units) and a storage unit that stores control data related to external peripheral devices, wherein the plurality of CPUs are: At the time of initial processing, means for dividing the control data of the peripheral device and executing a check process for illegal rewriting of the control data is adopted.

  In the present invention, as the second solving means, in the first solving means, the storage unit stores control data related to the plurality of peripheral devices, and the plurality of CPUs have high priority during initial processing. A means is employed in which the control data is illegally rewritten and checked in order from the control data of the peripheral device.

  According to the present invention, at the time of initial processing, a plurality of CPUs can quickly detect unauthorized data rewriting by dividing the control data of the peripheral device and executing the unauthorized data rewriting check process. .

It is a schematic block diagram of the multi-core system A which concerns on one Embodiment of this invention. It is a schematic diagram which shows operation | movement of the multi-core system A which concerns on one Embodiment of this invention. It is a timing chart which shows operation | movement of the multi-core system A which concerns on one Embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings.
The multi-core system A according to the present embodiment is mounted on a moving vehicle such as an electric vehicle (EV: Electric Vehicle) or a hybrid vehicle (HV: Hybrid Vehicle),
Both control peripheral devices D1 to Dn mounted on the moving vehicle. As shown in FIG. 1, the first calculation control unit E1, the second calculation control unit E2, the third calculation control unit E3, and the communication A bus B is provided.

  As shown in FIG. 1, the first arithmetic control unit E1 includes a first ROM (Read Only Memory) 11, a first RAM (Random Access Memory) 12, and a first CPU (Central Processing Unit) 13. The first ROM 11 is a storage unit in the present embodiment.

The first ROM 11 is a non-volatile memory that stores various arithmetic control programs executed by the first CPU 13 and other data.
The first RAM 12 is a volatile memory that is used as a working area that is a temporary storage destination of data when the first CPU 13 executes a calculation control program and performs various operations.

  The first CPU 13 is electrically connected to the first ROM 11 and the first RAM 1 and is also electrically connected to the peripheral devices D1 to Dn via the communication bus B, and is based on various arithmetic control programs stored in the first ROM 11. The operation of the peripheral devices D1 to Dn is controlled by performing various arithmetic processes and communicating with each unit.

  Although details will be described later, during the initial processing, the first CPU 13 together with the second CPU 23 of the second arithmetic control unit E2 and the third CPU 33 of the third arithmetic control unit E3 described later have high priority peripheral devices D1 to D1. The control data is illegally rewritten and checked in order from the control data of Dn.

  The control data of the peripheral devices D1 to Dn is setting data related to operations of the peripheral devices D1 to Dn. The control data of each peripheral device D1 to Dn is stored in each of the first ROM 11, the second ROM 21 of the second calculation control unit E2, which will be described later, and the third ROM 31 of the third calculation control unit E3.

  As shown in FIG. 1, the second arithmetic control unit E <b> 2 includes a second ROM 21, a second RAM 22, and a second CPU 23. The second ROM 21 is a storage unit in the present embodiment.

The second ROM 21 is a non-volatile memory that stores various arithmetic control programs executed by the second CPU 23 and other data.
The second RAM 22 is a volatile memory used as a working area that is a temporary storage destination of data when the second CPU 23 executes a control program and performs various operations.

  The second CPU 23 is electrically connected to the second ROM 21 and the second RAM 22 and is electrically connected to the peripheral devices D1 to Dn via the communication bus B, and is based on various arithmetic control programs stored in the second ROM 21. The operation of the peripheral devices D1 to Dn is controlled by performing various arithmetic processes and communicating with each unit. Although the details will be described later, the second CPU 23, in the initial processing, together with the first CPU 13 and the third CPU 33, checks the control data of the peripheral devices D1 to Dn having high priority in order and checks whether the control data is illegally rewritten. Execute the process.

  As shown in FIG. 1, the third arithmetic control unit E <b> 3 includes a third ROM 31, a third RAM 32, and a third CPU 33. The third ROM 31 is a storage unit in the present embodiment.

The third ROM 31 is a non-volatile memory that stores various arithmetic control programs executed by the third CPU 33 and other data.
The third RAM 32 is a volatile memory used as a working area serving as a temporary storage destination of data when the third CPU 33 executes a control program and performs various operations.

  The third CPU 33 is electrically connected to the third ROM 31 and the third RAM 32, and is also electrically connected to the peripheral devices D1 to Dn via the communication bus B, and is stored in the third ROM 31. The operation of the peripheral devices D1 to Dn is controlled by performing various arithmetic processes based on the various arithmetic control programs and communicating with each unit. Although details will be described later, during the initial processing, the third CPU 23, together with the second CPU 23 and the third CPU 33, divides the control data in order from the control data of the peripheral devices D1 to Dn having higher priorities and illegally rewrites the control data. Execute the check process.

  The communication bus B is a communication line for electrically connecting the first CPU 13, the second CPU 23 and the peripheral devices D1 to Dn. The first CPU 13, the second CPU 23, and the peripheral devices D 1 to Dn transmit and receive data via the communication bus B.

  On the other hand, the peripheral devices D1 to Dn are controllers for controlling a travel motor, a generator, a booster circuit, and the like mounted on the moving vehicle, and transmit / receive data to / from the first CPU 13 and the second CPU 23 via the communication bus B. To do.

  In each peripheral device D1 to Dn, whether or not writing and reading by the first CPU 13 and the second CPU 23 is set in advance. For example, in FIG. 1, “CPU13: R / W” and “CPU23: R / −” are described in the peripheral device D1. This is because the first CPU 13 can write and read data to the peripheral device D1, while the second CPU 23 cannot write data to the peripheral device D1 and can only read it. Is shown.

Next, the operation of the multi-core system A configured as described above will be described with reference to FIGS.
In the initialization process, the first CPU 13, the second CPU 23, and the third CPU 33 divide the control data of peripheral devices D1 to Dn having a high priority in order, and execute a check process for illegal rewriting of control data. For example, when the first CPU 13 is a master CPU, the first CPU 13 realizes the above process by transmitting instructions to the second CPU 23 and the third CPU 33 which are slave CPUs.

  Specifically, the first CPU 13 determines the priority order of the control data of the peripheral devices D1 to Dn based on the data stored in the first ROM 11. The data stored in the first ROM 11 is data relating to the priority order of the control data of the peripheral devices D1 to Dn.

  Then, the first CPU 13 outputs the priority order of the control data of the peripheral devices D1 to Dn that performs the illegal rewrite check processing to the second CPU 23 and the third CPU 33 based on the determination result. Then, the first CPU 13 executes, together with the second CPU 23 and the third CPU 33, one check process obtained by dividing the control data of the peripheral devices D1 to Dn having the highest priority.

  On the other hand, when the priority order of the control data is inputted from the first CPU 13, the second CPU 23 performs one check process of the control data of the peripheral devices D 1 to Dn having the highest priority, together with the first CPU 13 and the third CPU 33. Run. In addition, when the priority order of the control data is input from the first CPU 13, the third CPU 33 also performs a check process for one unauthorized rewrite in which the control data of the peripheral devices D 1 to Dn having the highest priority is divided into three. Or with the second CPU 23.

  When the first CPU 13, the second CPU 23, and the third CPU 33 complete the control data check process for the peripheral devices D1 to Dn with the highest priority, the control data for the peripheral devices D1 to Dn with the next highest priority are checked. Execute the process. Thereafter, the first CPU 13, the second CPU 23, and the third CPU 33 execute a check process for illegal rewrite of control data by dividing the control data of peripheral devices D1 to Dn having a high priority in order.

  For example, as shown in FIG. 2, when three control data with priority levels “high”, “medium”, and “low” are stored in the storage areas of the first ROM 11, the second ROM 21, and the third ROM 31, respectively, In addition, the first CPU 13, the second CPU 23, and the third CPU 33 execute a control data check process in which the priority stored in the first ROM 11 is “high”. Subsequently, the check process is executed from the control data having the priority “medium”, and finally the check process is executed from the control data having the priority “low”. Therefore, the timing chart of the processing of the first CPU 13, the second CPU 23, and the third CPU 33 is as shown in FIG. In the case where the peripheral devices D1 to Dn are controllers for the travel motor, the generator, and the booster circuit, the priority order is the order of the travel motor, the generator, and the booster circuit.

  According to this embodiment, the first CPU 13, the second CPU 23, and the third CPU 33 divide the control data illegally by dividing the control data in order from the control data of the peripheral devices D1 to Dn having higher priority during the initial processing. By executing this check process, it is possible to quickly detect illegal data rewriting of the peripheral devices D1 to Dn having a high priority.

As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, For example, the following modifications can be considered.
(1) Although the said embodiment is provided with two 1st CPU13 and 2nd CPU23, it is not limited to two, Two or more may be sufficient. In this case, the CPU for checking the soundness and the CPU for checking the soundness may be fixed, or the CPUs may check the soundness of each other.
(2) Although the said embodiment is mounted in the moving vehicle, you may make it mount in electronic devices, such as household appliances, besides a moving vehicle.

  A ... multi-core system, D1 to Dn ... peripheral devices, E1 ... first calculation control unit, E2 ... second calculation control unit, E3 ... third calculation control unit, B ... communication bus, 11 ... first ROM (storage unit) , 12 ... 1st RAM, 13 ... 1st CPU, 21 ... 2nd ROM (memory | storage part), 22 ... 2nd RAM, 23 ... 2nd CPU, 31 ... 3rd ROM (memory | storage part), 32 ... 3rd RAM, 33 ... 3rd CPU

Claims (2)

Multiple CPUs (Central Processing Units)
A multi-core system comprising a storage unit for storing control data related to external peripheral devices,
The plurality of CPUs divide the control data of a peripheral device and execute an illegal rewrite check process of the control data during initial processing. The storage unit stores control data related to a plurality of the peripheral devices,
The plurality of CPUs, in an initial process, divide the control data of peripheral devices having a high priority in order from the control data and execute a check process for illegal rewriting of the control data.

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