JP2014222942A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem wherein an existing semiconductor integrated circuit cannot precisely transmit/receive data.SOLUTION: A semiconductor integrated circuit includes a Soc circuit 100 and an SDRAM circuit 101 which transmit/receive data via a bidirectional signal line. The SoC circuit 100 includes: a termination circuit 204 having resistances 207, 208 disposed between power supplies and the bidirectional signal line, and switches 209, 210 for controlling on/off currents flowing through the resistances 207, 208; and a control circuit 205 for outputting a control signal 200 to the termination circuit 204 to turn on the switches 209, 210 in the case of data reception, turn off the switches 209, 210 in the case of data transmission, and keep the switches 209, 210 on for a predetermined period after the preceding data reception in the case of further data reception following the data reception.

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to power supply noise reduction.

  In a semiconductor integrated circuit, there is a problem that power supply noise is generated on each signal line used for data transfer between transmission / reception circuits, and data transfer between the transmission / reception circuits is not performed correctly. In order to reduce this power supply noise, it is required to keep the impedance on the signal line low.

  For this reason, countermeasures for reducing power supply noise such as ODT (On Die Termination) are provided on the data reception signal lines of each transmission / reception circuit (Non-patent Document 1). In particular, for bidirectional signal lines in which data is transferred bidirectionally between the transmission and reception circuits, each transmission and reception circuit turns on the ODT function when receiving data and turns off the ODT function when not receiving data. A termination circuit is provided.

JEDEC STANDARD, DDR2 SDRAM SPECIFICATION JESD79-2E (Revision of JESD79-2D), April 2008, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

  In the prior art, in the data transfer between the transmission / reception circuits via the bidirectional signal line, when the receiving circuit serving as the data receiving side turns the ODT function from on to off after receiving the data, the power supply voltage changes suddenly. Power supply noise is generated on the bidirectional signal line. If the receiving circuit turns on the ODT function from OFF to receive another data before the power noise converges, the data is affected by the power noise. Therefore, the conventional technique has a problem that data cannot be transmitted and received with high accuracy.

  A semiconductor integrated circuit according to the present invention includes first and second transmission / reception circuits that perform transmission / reception of data through a signal line, and the first transmission / reception circuit is provided between a first power source and the signal line. A first termination circuit having a first resistor provided in the first resistor and a first switch for controlling on / off of a current flowing through the first resistor, and turning on the first switch at the time of data reception, The first switch is turned off at the time of data transmission, and when another data is received after data reception, the first switch is kept on for a first predetermined period after the previous data reception. And a control circuit for outputting a first control signal to the first termination circuit.

  With the circuit configuration as described above, power supply noise can be reduced, so that data can be transmitted and received with high accuracy.

  According to the present invention, a semiconductor integrated circuit capable of transmitting and receiving data with high accuracy can be provided.

1 is a diagram showing a semiconductor integrated circuit according to a first exemplary embodiment of the present invention. 1 is a diagram showing a semiconductor integrated circuit according to a first exemplary embodiment of the present invention. 3 is a timing chart showing an operation of the semiconductor integrated circuit according to the first exemplary embodiment of the present invention. FIG. 3 is a diagram illustrating a semiconductor integrated circuit according to a second embodiment of the present invention.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. For clarity of explanation, duplicate explanation is omitted as necessary.

Embodiment 1
Embodiment 1 of the present invention will be described with reference to the drawings. In the present invention, the first transmission / reception circuit, the second transmission / reception circuit, and a signal line in which data is transferred bidirectionally between the first and second transmission / reception circuits (hereinafter simply referred to as “bidirectional signal line”) It can be applied to a circuit having an ODT function as a countermeasure against power supply noise. In this embodiment, an example will be described in which a SoC (System On Chip) circuit and an SDRAM (Synchronous Dynamic Random Access Memory) circuit are provided, and data transfer is performed between both circuits via a bidirectional signal line. .

  FIG. 1 is a semiconductor integrated circuit according to a first embodiment of the present invention. The circuit shown in FIG. 1 includes an SoC circuit (first transmission / reception circuit) 100 and an SDRAM circuit (second transmission / reception circuit) 101. Data transfer between these two circuits is performed according to the DDR (Double data rate) standard.

  First, the circuit configuration of the first embodiment will be described. The SoC circuit 100 outputs a 2-bit width clock CK and a 2-bit width clock CKB, which is a differential signal of the clock CK, to the SDRAM circuit 101. The SoC circuit 100 outputs a 16-bit width control signal CMD including a command for each address of the SDRAM circuit 101 to the SDRAM circuit 101. The SDRAM circuit 101 takes in the control signal CMD in synchronization with the clocks CK / CKB.

  Further, between the SoC circuit 100 and the SDRAM circuit 101, the 32-bit width data DQ, the 4-bit width strobe signal DQS, and the differential signal DQSB thereof are transmitted and received bidirectionally. The reception side circuit serving as the data reception side takes in the reception data DQ in synchronization with the strobe signals DQS / DQSB. For convenience, the above signal names also represent signal line names.

  FIG. 2 is a diagram illustrating one-bit bidirectional signal lines (strobe signal lines DQS [3: 0] / DQSB [3: 0] and data signal lines DQ [31: 0]) in the circuit of FIG. Only a 1-bit signal line) and corresponding peripheral circuits are shown. Here, a case where the one-bit bidirectional signal line is the data signal line DQ [0] will be described as an example. The data signal line DQ [0] is connected between the SoC circuit 100 and the SDRAM 101 as described above.

  The SoC circuit 100 includes an external terminal 201, a buffer 202, a buffer 203, a termination circuit (first termination circuit) 204 having an ODT function, and a control signal (first signal) for controlling on / off of the ODT function of the termination circuit 204. The control circuit 205 for outputting the control signal 200 and the inverter 206 are provided. The termination circuit 204 includes a resistor (first resistor) 207, a resistor 208, a switch (first switch) 209, and a switch 210. Further, the case where the switch 209 is a P-channel MOS transistor and the switch 210 is an N-channel MOS transistor will be described as an example.

  In the SoC circuit 100, the data signal line DQ [0] is connected to the input terminal of the buffer 202 and the output terminal of the buffer 203 via the external terminal 201.

  A termination circuit 204 is provided between the external terminal 201 and the buffer 202. In the termination circuit 204, a switch 209 and a resistor 207 are connected in series between the high potential side power supply terminal VDD and the node N1 on the signal line connecting the external terminal 201 and the buffer 202. A switch 210 and a resistor 208 are connected in series between the low potential side power supply terminal VSS and the node N1. More specifically, the source terminal of the switch 209 is connected to the high potential side power supply terminal VDD. The drain terminal of the switch 209 is connected to one end of the resistor 207. The other end of the resistor 207 is connected to one end of the resistor 208. The other end of the resistor 208 is connected to the drain terminal of the switch 210. The source terminal of the switch 210 is connected to the low potential side power supply terminal VSS. The other end of the resistor 207 and one end of the resistor 208 are commonly connected to the node N1. Note that the switch 209 and the resistor 207 connected in series between the high-potential-side power supply terminal VDD and the node N1 may be switched in connection. Similarly, the switch 210 and the resistor 208 connected in series between the low-potential-side power supply terminal VSS and the node N1 may be interchanged.

  The output terminal of the buffer 202 is connected to the input terminal IN of the control circuit 205. The input terminal of the buffer 203 is connected to the output terminal OUT of the control circuit 205. The output terminal C1 of the control circuit 205 is connected to the gate terminal of the switch 209 and is connected to the gate terminal of the switch 210 via the inverter 206. Such a configuration of the peripheral circuit is also adopted for other bidirectional signal lines. Note that the control circuit 205 is provided in common for each bidirectional signal line.

  Next, the operation of the first embodiment will be described. A case where the SoC circuit 100 receives (reads) data from the SDRAM circuit 101 will be described. First, the SoC circuit 100 outputs a control signal CMD to the SDRAM circuit 101. Thereafter, the SDRAM circuit 101 transmits, for example, the data DQ at the address specified by the control signal CMD and the strobe signals DQS / DQSB to the SoC circuit 100. At this time, the data DQ transmitted from the SDRAM circuit 101 has a predetermined burst length.

  The SoC circuit 100 receives each signal via the corresponding signal line, the external terminal 201, and the buffer 202. The SoC circuit 100 receives the data DQ in synchronization with the strobe signals DQS / DQSB. Data received by the SoC circuit 100 is input to the control circuit 205 and other peripheral circuits (not shown). A period from when the SoC circuit 100 transmits the control signal CMD to when reception of the data DQ is started is referred to as read latency (RL).

  Here, the SoC circuit 100 has an ODT function of the corresponding termination circuit 204 in order to suppress power supply noise generated on the data signal line DQ and the strobe signal line DQS / DQSB when data is received from the SDRAM circuit 101. Turn on. In other words, the SoC circuit 100 turns on the switches 209 and 210 included in each termination circuit 204 based on the control signal (first control signal) 200 from the control circuit 205, and sets the node on the corresponding signal line to a predetermined potential. (For example, a potential of 1/2 of the high potential side power supply VDD). As a result, the SoC circuit 100 can reduce power supply noise included in the received data, and can accurately receive the data.

  A case where the SoC circuit 100 transmits (writes) data to the SDRAM circuit 101 will be described. First, the SoC circuit 100 outputs a control signal CMD to the SDRAM circuit 101. Thereafter, the SoC circuit 100 transmits the data DQ and the strobe signals DQS / DQSB to the SDRAM circuit 101. At this time, the data DQ transmitted from the SoC circuit 100 has a predetermined burst length.

  The SDRAM circuit 101 receives the data DQ in synchronization with the strobe signal DQS / DQSB. The data DQ is written, for example, at an address specified by the control signal CMD. A period from when the SoC circuit 100 transmits the control signal CMD to when transmission of the data DQ is started is referred to as write latency (WL).

  Here, the SoC circuit 100 turns off the ODT function of the corresponding termination circuit 204 at the time of data transmission to the SDRAM circuit 101. That is, the SoC circuit 100 turns off the switches 209 and 210 included in each termination circuit 204 based on the control signal 200 from the control circuit 205, and transmits the switch 209 and 210 to the SDRAM circuit 101 via the buffer 203 and the external terminal 201. Do not attenuate the data potential. Thereby, the SoC circuit 100 can perform data transmission with high accuracy.

  Thus, the SoC circuit 100 switches between the read mode in which the SoC circuit 100 receives data from the SDRAM circuit 101 and the write mode in which the SoC circuit 100 transmits data to the SDRAM circuit 101 by the control signal CMD. The SoC circuit 100 outputs a control signal CMD having a data length corresponding to one clock CK cycle at a predetermined interval.

  For example, the SoC circuit 100 receives / transmits data in the read / write mode, and then transmits / receives another data again in the same mode at a predetermined interval. Alternatively, the SoC circuit 100 receives / transmits data in the read / write mode, and thereafter transmits / receives another data in a mode different from the mode after a predetermined interval. Such data transmission / reception is repeated.

  Here, the present embodiment is characterized in that the SoC circuit 100 receives data in the read mode and then receives another data again in the read mode after a predetermined interval. The operation at this time will be described with reference to FIG.

  First, the SoC circuit 100 outputs a control signal CMD (A in FIG. 3; hereinafter, simply referred to as “read command A”) to the SDRAM circuit 101. The SDRAM circuit 101 passes the data DQ (D in FIG. 3) having a predetermined burst length and the corresponding strobe signals DQS / DQSB to the SoC circuit 100 through the period of the read latency RL (C in FIG. 3). Send to.

  Here, when receiving data via the bidirectional signal lines (data signal line DQ and strobe signal line DQS / DQSB), the SoC circuit 100 turns on the ODT function of the termination circuit corresponding to each signal line.

  After outputting the read command A, the SoC circuit 100 outputs the read command E (E in FIG. 3) at a predetermined interval (B in FIG. 3). The SDRAM circuit 101 passes the data DQ (G in FIG. 3) having a predetermined burst length and the strobe signals DQS / DQSB corresponding thereto to the SoC circuit 100 through the period of the read latency RL (F in FIG. 3). Send to.

  At this time, the control circuit 205 provided in the SoC circuit 100 determines the interval B of the read command (A, E), the read latency RL (C, F), and the burst length (D, G) of the data DQ. Based on this, the period (H) during which the data DQ is not transferred is obtained. Thereby, the control circuit 205 determines whether or not to turn off the ODT function of the termination circuit 204 during a period (H) when the data DQ is not transferred. Then, the control circuit 205 outputs a control signal 200 to the termination circuit 204 based on the determination result. When the period (H) is less than or equal to a preset threshold value, the termination circuit 204 continues to turn on the ODT function during the period (H) (I in FIG. 3). On the other hand, if the period (H) exceeds a preset threshold value, the termination circuit 204 switches the ODT function from on to off during the period (H).

  If the termination circuit 204 continues to turn on the ODT function during a period when data transfer is not performed when the read mode is continuous, the bidirectional signal line corresponding to the termination circuit 204 is turned off from turning on the ODT function. Power supply noise due to switching to is not generated. Therefore, the SoC circuit 100 can reduce the influence of power supply noise, which has been a problem in the related art, and can accurately receive data.

  On the other hand, in the case where the read mode is continuous, if the period during which data transfer is not performed (for example, H in FIG. 3) exceeds the threshold value, the termination circuit 204 performs the ODT function during the period during which data transfer is not performed. Switch from on to off. That is, the SoC circuit 100 can switch the ODT function of the termination circuit 204 from OFF to ON again after a sufficient period of time has elapsed for the power supply noise due to switching from the ON to OFF of the ODT function to converge. Therefore, the SoC circuit 100 can reduce the influence of power supply noise and perform data reception with high accuracy. The timing for switching the ODT function from on to off may be any time as long as the power supply noise converges until the next data reception is started.

  As described above, in the semiconductor integrated circuit according to the present embodiment, when the receiving side circuit (for example, the SoC circuit 100) continuously receives data, the ODT function of the receiving side circuit depends on the data reception interval. Control on / off. That is, according to the data reception interval, it is controlled whether the ODT function of the receiving side circuit is kept on or switched from on to off. As a result, the semiconductor integrated circuit according to the present embodiment can reduce the influence of power supply noise and can accurately transmit and receive data.

Embodiment 2
In the first embodiment, the case where the SoC circuit 100 includes the termination circuit 204 has been described as an example. However, in the present embodiment, the case where the SDRAM circuit includes the termination circuit will be described.

  FIG. 4 is a circuit provided with a termination circuit (second termination circuit) 215 in addition to the SDRAM circuit 101 of FIG. FIG. 4 shows a 1-bit bidirectional signal line (strobe signal line DQS [3: 0] / DQSB [3: 0], data signal line DQ [31: 0], one bit signal line) Only the peripheral circuits corresponding thereto are shown.

  The circuit shown in FIG. 4 includes an SoC circuit 100 and an SDRAM circuit 102. The SDRAM circuit 102 includes an SDRAM unit 211, an external terminal 212, a buffer 213, a buffer 214, a termination circuit 215, and an inverter 216. The termination circuit 215 includes a resistor (second resistor) 217, a resistor 218, a switch (second switch) 219, and a switch 220. Since the circuit configuration and operation of the SoC circuit 100 are the same as those in the first embodiment, description thereof is omitted. In addition, regarding the connection relation and operation of each circuit related to the ODT function provided in the SDRAM circuit 102, only the parts different from the case of the SoC circuit 100 will be described.

  The SDRAM circuit 102 turns on the ODT function of the corresponding termination circuit 215 in order to suppress power supply noise generated on the data signal line DQ and the strobe signal line DQS / DQSB when receiving data from the SoC circuit 100. . In other words, the SDRAM circuit 102 turns on the switches 219 and 220 included in each termination circuit 215 based on the control signal (second control signal) 221 from the control circuit 205, and sets the node on the corresponding signal line to a predetermined potential. (For example, the potential is ½ of the high potential side power supply VDD). As a result, the SDRAM circuit 102 can reduce power supply noise included in the received data and perform data reception with high accuracy.

  Further, the SDRAM circuit 102 turns off the ODT function of the corresponding termination circuit 215 at the time of data transmission to the SoC circuit 100. That is, the SDRAM circuit 102 turns off the switches 219 and 220 included in each termination circuit 215 based on the control signal 221 from the control circuit 205, and transmits it to the SoC circuit 100 via the buffer 214 and the external terminal 212. Do not attenuate the data potential. Thereby, the SDRAM circuit 102 can receive data with high accuracy. In addition, since the connection relationship and operation of each circuit related to the ODT function of the SDRAM circuit 102 are the same as those in the SoC circuit 100, description thereof will be omitted.

  With such a circuit configuration, in this embodiment, in the data transfer of each transmission / reception circuit via the bidirectional signal line, even if any of the transmission / reception circuits becomes a reception side circuit, the reception side circuit By controlling the ODT function, data can be transmitted and received with high accuracy.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. Although the case where the semiconductor integrated circuit includes one SDRAM circuit has been described in the above embodiment, the present invention is not limited to this. The semiconductor integrated circuit can be appropriately changed to a circuit configuration including a plurality of SDRAM circuits.

  In the above embodiment, when the receiving circuit (for example, the SoC circuit 100) continuously receives data, the control circuit 205 performs control based on the address command interval, the read latency RL, and the burst length of the data DQ. Although the case where a signal (for example, the control signal 200) is output has been described, the present invention is not limited to this. If the ODT function can be controlled according to the data reception interval, a circuit configuration that outputs a control signal (for example, control signal 200) based on at least one of the above information (for example, address command interval) can also be used. It can be changed as appropriate.

  Further, the termination circuit is not limited to the circuit described in the above embodiment. A resistor connected in series between a power supply (first power supply) terminal having a predetermined potential (for example, a potential of 1/2 of the high potential side power supply VDD) and a node on the corresponding bidirectional signal line In addition, the circuit configuration having a switch can be appropriately changed.

DESCRIPTION OF SYMBOLS 100 SoC circuit 101 SDRAM circuit 102 SDRAM circuit 200 Control signal 201 External terminal 202 Buffer 203 Buffer 204 Termination circuit 205 Control circuit 206 Inverter 207 Resistor 208 Resistor 209 Switch 210 Switch 211 SDRAM section 212 External terminal 213 Buffer 214 Buffer 215 Inverter circuit 216 Inverter 217 Resistance 218 Resistance 219 Switch 220 Switch 221 Control signal

Claims (9)

A first external terminal;
A second external terminal;
A transmission / reception circuit that transmits / receives data to / from the outside by the first external terminal, and transmits a first control signal by the second external terminal;
With
The transmission / reception circuit is connected to a first termination circuit provided outside.
When the data is received from the first external terminal, the first control signal is set to a first potential level,
When transmitting the data from the first external terminal, the first control signal is set to a second potential level,
In the case where another data is transmitted after the data transmission, when the data transmission interval from the previous data transmission until another data is transmitted is equal to or less than a first threshold, the first control signal is set to the first control signal. A semiconductor device that maintains the potential level of 2 and changes the first control signal from the second potential level to the first potential level when the data transmission interval exceeds the first threshold value. Integrated circuit. The transmission / reception circuit is connected to an external SDRAM (Synchronous Dynamic Random Access Memory) circuit via the first external terminal and the second external terminal.
The SDRAM circuit is
The semiconductor integrated circuit according to claim 1, comprising the first termination circuit.   The semiconductor integrated circuit according to claim 2, wherein the data transmission interval is determined based on a write latency of the previous transmission data and the other transmission data. The previous transmission data and the other transmission data are each burst data, each having a predetermined burst length,
The semiconductor integrated circuit according to claim 2, wherein the data transmission interval is determined based on the burst length. The transceiver circuit is
A second termination circuit having a first resistor provided between a first power supply and the first external terminal, and a first switch for controlling on / off of a current flowing through the first resistor. When,
When the data is received from the first external terminal, the first switch is turned on. When the data is transmitted from the first external terminal, the first switch is turned off. In the case of receiving another data, if the data reception interval from the reception of the previous data until the reception of another data is equal to or smaller than the second threshold, the first switch is kept on and the data A control circuit that outputs a second control signal to the second termination circuit so as to switch the first switch from on to off when the reception interval exceeds the second threshold;
The semiconductor integrated circuit according to claim 2, further comprising:   The semiconductor integrated circuit according to claim 5, wherein the control circuit outputs the first control signal.   6. The semiconductor according to claim 5, wherein the data reception interval is determined based on a period from when the transmission / reception circuit outputs a data reception command to the SDRAM circuit until another data reception command is output. Integrated circuit.   The semiconductor according to claim 5, wherein the data reception interval is determined based on a latency from when the transmission / reception circuit outputs a data reception command to the SDRAM circuit until the SDRAM starts data reception. Integrated circuit. The data received by the transceiver circuit from the SDRAM circuit is burst data,
6. The semiconductor integrated circuit according to claim 5, wherein the data reception interval is determined based on a burst length of the received data.

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