JP2014216626A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can ensure a sufficient width of a hole after an etching process of forming the hole for forming a cylinder of a capacitor and successfully prevent block of the hole and defects in a capacitor.SOLUTION: A semiconductor device having holes of the same shape which are periodically arranged on an insulation film formed on a semiconductor substrate comprises dummy holes 51, 52 which are arranged in an outermost periphery of holes 50 and extend in an outside direction of the periodic arrangement and each of which has a larger width compared with the hole 50; pads arranged below the holes 50; and dummy pads arranged below the dummy holes 51, 52. It is preferable that the dummy pad has a width larger than that of the pad.

Description

  The present invention relates to a semiconductor device.

  In general, a DRAM (Dynamic Random Access Memory), which is a semiconductor device, is formed with a capacitor, which is a capacitor that stores information by storing electric charge. An internal circuit of the DRAM includes a memory cell configured by providing one transistor for each capacitor, and a peripheral circuit provided around a memory cell region in which a large number of memory cells are arranged. .

  When manufacturing a cylinder type capacitor which is a typical type of capacitor, the interlayer insulating film is etched to form a cylinder hole, a lower electrode is formed on the side wall, and the interlayer insulating film is etched to form the lower electrode. Then, the capacitor insulating film and the upper electrode are formed.

A process for manufacturing the above-described cylinder type capacitor will be described with reference to FIGS. As shown in FIG. 14, the holes 150 serving as cylinders are generally periodically arranged on a semiconductor substrate and have the same shape. In the etching process for forming the hole, as shown in FIG. 15, first, a capacitor contact pad 142 that contacts the capacitor contact 128 formed in connection with the source / drain region of the transistor is formed. Thereafter, as shown in FIG. 16, a stopper film 144, an insulating film 146 in which an insulating film 147 and an insulating film 148 are stacked with a predetermined thickness so as to cover the capacitor contact pad 142, an insulating film 149a, 149b are sequentially formed.

  Next, after the amorphous carbon film 160 is formed on the insulating film 149b, the amorphous carbon film 160 is patterned so that the amorphous carbon film 160 where the holes 150 are to be formed is removed. At this time, as shown in FIG. 17, the thickness dimension of the amorphous carbon film 160 on the outer peripheral portion of the semiconductor substrate 112 becomes larger than the thickness dimension of the amorphous carbon film 160 on the inner side of the semiconductor substrate 112 due to the etching dullness. Subsequently, dry etching is performed using the patterned amorphous carbon film 160 as a mask to form a hole 150 on the capacitor contact pad 142.

  However, in the dry etching process described above, the ion bombardment is as shown by the arrow in FIG. 17, and the hole 150r on the outermost peripheral portion of the hole 150 on the semiconductor substrate 112 is likely to be blocked. If the lower electrode 154 of the capacitor is formed as shown in FIG. 18 with the etching of the hole 150r being insufficiently closed, the adhesive strength of the lower electrode 154 to the insulating film 146 is lowered, and the lower electrode 154 is insulated from the insulating film 146. It becomes easy to peel off.

  Thus, in order to prevent the holes in the outer peripheral portion of the DRAM memory cell region from becoming defective due to insufficient etching, a dummy hole having the same size as the actual hole may be provided in the outermost peripheral portion of the memory cell region. However, if the dummy hole is closed like the hole 150r shown in FIG. 18, the lower electrode is peeled off during the etching process of the insulating film such as the interlayer insulating film and becomes dust, and the hole in the outer peripheral portion of the memory cell region becomes defective. Become.

  As described above, as a technique related to a method of providing a dummy hole in the outermost peripheral portion of the memory cell region, for example, Patent Document 1 discloses that a dummy well is provided in the outer periphery of the memory cell region of the semiconductor device, and a pattern on the mask. In order to make the gate electrode dimensions uniform when completed by making the dimensions different between the central area and the peripheral area, and to make the aperture ratio of each mask uniform in manufacturing a semiconductor device such as ASIC (Application Specific Integrated Circuit), etc. It is disclosed that a dummy contact which may be a slit shape is not limited to a square shape of the mask.

Further, as a technique related to a method of providing a dummy hole in the outermost peripheral part of the memory cell region, for example, Patent Document 2 discloses a dummy having the same shape at the boundary between the memory part and the logic part in order to prevent the logic part from breaking down. A semiconductor device provided with a contact plug is disclosed.
Further, for example, Patent Document 3 discloses a semiconductor device provided with a dummy pattern in which a pattern coverage gradually decreases in an outer peripheral portion of a dense pattern region of memory cells in order to prevent erosion in CMP (Chemical Mechanical Planarization) and its A manufacturing method is disclosed.

JP 2002-118235 A JP 2005-347334 A Japanese Patent Laying-Open No. 2005-074023

However, the semiconductor device and the manufacturing method thereof in Patent Document 1 do not disclose the difference in the shapes of the pattern formed in the memory cell region and the dummy pattern for forming the dummy well, and the dimensions of these patterns are set when completed. There is also no disclosure of making it different. However, there is no disclosure about the arrangement of dummy contacts.
Further, the semiconductor device disclosed in Patent Document 2 and the semiconductor device disclosed in Patent Document 3 and the manufacturing method thereof do not disclose anything about the shapes of dummy contacts and dummy patterns.

  The semiconductor device of the present invention is a semiconductor device having holes of the same shape periodically arranged in an insulating film formed on a semiconductor substrate, and is located outside the periodic arrangement of the holes at the outermost peripheral portion of the holes. A dummy hole is provided that extends in a direction and has an opening having a larger width than the hole.

  The semiconductor device of the present invention is a semiconductor device having a capacitor including a hole in a memory cell region on a semiconductor substrate, and a dummy hole having a larger area in plan view than the opening of the hole is formed on the outer periphery of the hole. It is characterized by having.

  Furthermore, the semiconductor device of the present invention is a semiconductor device having a hole in a memory cell region on a semiconductor substrate and a dummy hole around the hole, and is viewed in plan view from the hole in four directions outside the memory cell region. And the dummy hole having a wide area is provided.

 According to the semiconductor device of the present invention, the dummy hole is formed in the outermost peripheral portion of the hole so as to extend in the outer direction of the periodic arrangement of the holes and has an opening having a larger width dimension than the holes. Therefore, the width dimension of the dummy hole is sufficiently ensured after the etching process for forming the hole, and the blocking of the dummy hole and the defect of the capacitor are surely prevented. Therefore, the entire hole on the semiconductor substrate is formed satisfactorily, and the failure of the semiconductor device is avoided.

It is a top view which shows the semiconductor device of 1st embodiment to which this invention is applied. It is another top view which shows the semiconductor device of 1st embodiment to which this invention is applied. It is a figure which shows the semiconductor device of 1st embodiment to which this invention is applied, Comprising: It is sectional drawing at the time of seeing by the AA 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 1st embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the AA 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 1st embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the AA 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 1st embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the AA 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 1st embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the AA 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 1st embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the AA 'line shown in FIG. It is a top view which shows the semiconductor device of 2nd embodiment to which this invention is applied. It is a figure which shows the manufacturing process of the semiconductor device of 2nd embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the arrow at the BB 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 2nd embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the arrow at the BB 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 2nd embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the arrow at the BB 'line shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device of 2nd embodiment to which this invention is applied, Comprising: It is sectional drawing corresponding to the case where it sees by the arrow at the BB 'line shown in FIG. It is a top view which shows the conventional semiconductor device. It is a figure which shows the manufacturing process of the conventional semiconductor device, Comprising: It is sectional drawing corresponding to the case where it views on the CC 'line shown in FIG. It is a figure which shows the manufacturing process of the conventional semiconductor device, Comprising: It is sectional drawing corresponding to the case where it views on the CC 'line shown in FIG. It is a figure which shows the manufacturing process of the conventional semiconductor device, Comprising: It is sectional drawing corresponding to the case where it views on the CC 'line shown in FIG. It is a figure which shows the manufacturing process of the conventional semiconductor device, Comprising: It is sectional drawing corresponding to the case where it views on the CC 'line shown in FIG.

  A semiconductor device to which the present invention is applied will be described below with reference to FIGS. In addition, in FIGS. 1 to 13, the same components are denoted by the same reference numerals, and description thereof is omitted. Note that the drawings used in the following description are schematic, and the dimensions, ratios, and the like of length, width, and thickness are not necessarily the same as actual ones.

(First embodiment)
A DRAM 10 (semiconductor device) as an example of the semiconductor device according to the first embodiment to which the present invention is applied will be described with reference to FIGS.

 The DRAM 10 of this embodiment is provided with a plurality of memory cells. A peripheral circuit (not shown) for driving the memory cells may be provided around these memory cells. As shown in FIG. 1, in the DRAM 10, a strip-like and a plurality of active regions 14 are formed on the upper surface of a semiconductor substrate 12 at regular intervals. The active region 14 extends at a certain angle with respect to the extending direction of the buried word line 16 (gate electrode) and the bit line 18. The planar shape and alignment direction of the active region 14 are not limited to those shown in FIG.

 The buried word line 16 extends in one direction so as to cut through the active region 14 and is buried in the semiconductor substrate 12. The plurality of embedded word lines 16 are formed at predetermined intervals in a direction intersecting the extending direction of the active region 14 and the extending direction of the bit line 18. Memory cells are formed in regions where the active region 14 and the buried word line 16 intersect. Each of these memory cells includes a transistor including an active region 14, a buried word line 16, and a bit line 18, and a capacitor connected to the transistor. FIG. 1 shows only the capacitor contact pad 42 among the components of the capacitor, and the other components are not shown.

  The holes 50 for forming the capacitors of the plurality of memory cells in the DRAM 10 of this embodiment are periodically arranged in the X direction and the Y direction in the insulating film on the transistor formed on the semiconductor substrate 12. Have the same shape in plan view. However, as shown in FIG. 2, dummy holes 51 and 52 are provided in the outermost peripheral portion of the hole 50.

  The dummy holes 51 are provided in the outermost peripheral portion in the X direction of the holes 50, extend in the outer direction of the periodic arrangement of the holes 50, and have a larger width dimension in the Y direction than the holes 50. The dummy holes 52 are provided in the outermost peripheral portion of the holes 50 in the Y direction, and extend in the outward direction of the periodic arrangement of the holes 50. Specifically, the dummy hole 52 has the same size as the hole 50 in plan view, and is formed by connecting holes 50P and 50Q adjacent to each other in the X direction at the outermost peripheral portion of the hole 50 by the hole 50R. The width dimension in the X direction is larger than that of the hole 50. As described above, dummy holes 51 and 52 opened in a wider area in plan view than the hole 50 are provided in the four directions outside the memory cell region of the DRAM 10 of the present embodiment in which the hole 50 is formed. . In FIG. 2, the outer four directions indicate both sides in the X direction (upper and lower sides in the drawing) and both sides in the Y direction (left and right sides in the drawing). From the viewpoint of reliably preventing the dummy holes from being blocked in the etching process when forming the dummy holes 51 and 52, if the width dimension of the holes 50 is 60 nm, for example, the width dimension in the Y direction of the dummy holes 51 and It is preferable that the width dimension of the dummy hole 52 in the X direction is set to about 180 nm.

  A p-type silicon substrate is used as the semiconductor substrate 12 on which the transistors constituting the memory cell are formed. As shown in FIG. 3, an insulating film 13 may be formed on the semiconductor substrate 12 for appropriately dividing the memory cell formation region.

The buried word line 16 is made of a conductive film such as titanium nitride or tungsten.
A gate insulating film 20 is provided so as to cover the bottom surface and the side surface of the buried word line 16. The gate insulating film 20 includes an insulating film 20a and an insulating film 20b. Examples of the material of the insulating film 20a and the insulating film 20b include a silicon oxide film.
A protective insulating film 22 is provided so as to cover the upper surface of the buried word line 16. The protective insulating film 22 includes an insulating film 22a and an insulating film 22b. Examples of the material of the insulating film 22a and the insulating film 22b include a silicon oxide film.

  The semiconductor substrate 12 between the buried word lines 16 is an active region 14 and functions as a source / drain region of the transistor. When a voltage is applied to the buried word line 16, the semiconductor substrate 12 in contact with the gate insulating film 20 becomes a channel region of the transistor.

  The bit line 18 includes a conductive film 18a and a conductive film 18b. The bottom surface of the conductive film 18 a is in contact with the semiconductor substrate 12 between the embedded word lines 16. With such a configuration, the bit line 18 and the channel region of the transistor are electrically connected. An example of the material of the conductive film 18a is polycrystalline silicon. Examples of the material of the conductive film 18b include tungsten and a tungsten compound. A cap insulating film 24 is provided on the bit line 18. Sidewall insulating films 26 are provided on the side surfaces of the bit lines 18. Examples of the material of the cap insulating film 24 and the sidewall insulating film 26 include a silicon nitride film.

The capacitor contact 28 includes a conductive film 28a, a conductive film 28b, and a conductive film 28c. The bottom surface of the conductive film 28 a is in contact with the semiconductor substrate 12 opposite to the semiconductor substrate 12 to which the bit line 18 is connected with the embedded word line 16 interposed therebetween. With such a configuration, the capacitor contact 28 and the channel region of the transistor are electrically connected. That is, the DRAM 10 of the present embodiment includes a double gate transistor in which two adjacent embedded word lines 16 share the same bit line 18.
An example of the material of the conductive film 28a is polycrystalline silicon. Moreover, as a material of the conductive film 28b, for example, cobalt silicide can be given. Furthermore, as a material of the conductive film 28c, for example, tungsten is given. A liner film 30 is provided on the side surface of the capacitor contact 28. Examples of the material of the liner film 30 include a silicon oxide film.

  An interlayer insulating film 32 is formed between the width directions of the capacitor contacts 28 not passing through the bit line 18. The interlayer insulating film 32 may be an insulating film 36 made of a single material, or may be a laminated film of insulating films 37, 38, 39, and 40. The laminated film may be appropriately selected. Examples of the material of the insulating films 36, 37, and 40 include a spin-on dielectric material (SOD). A hard mask film 34 made of a silicon oxide film or the like is formed between the insulating film 36 and the semiconductor substrate 12.

  The capacitive contact pad 42 (pad) is provided in connection with the capacitive contact 28. As can be seen from FIG. 10, a capacitor contact pad 42 d (dummy pad) having a larger width than the capacitor contact pad 42 is formed below the dummy holes 51 and 52 according to the width of the dummy holes 51 and 52. Yes. An example of the material of the capacitor contact pads 42 and 42d is tungsten. On the capacitor contact pads 42 and 42d and on both sides in the width direction, a stopper film 44 is formed as a stopper in an etching process for forming a lower electrode 54 of the capacitor 53 described later. An example of the material of the stopper film 44 is a silicon nitride film. Hereinafter, unless otherwise specified, the capacitor contact pads 42 and 42 d are collectively referred to as the capacitor contact pad 42.

  An insulating film 46 (insulating film) is formed on the semiconductor substrate 12 via the bit line 18, the capacitor contact 28, and the interlayer insulating film 32. The insulating film 46 may be a laminated film of insulating films 47 and 48 as shown in FIG. 3, or may be an insulating film made of a single material. As described with reference to FIG. 2, the insulating film 46 is provided with holes 50 having the same shape arranged periodically in a plan view. As shown in FIGS. 2 and 3, the outermost peripheral portion of the hole 50 has the same width dimension as the hole 50 in the Y direction, and adjacent holes 50P and 50Q in the X direction are connected by the hole 50R. Thus, a dummy hole 52 having a larger width dimension than the hole 50 is formed.

  The capacitor 53 is a cylinder-type capacitor unit, and includes a lower electrode 54, a capacitor film 56, and an upper plate electrode 58. The bottom surface of the lower electrode 54 is in contact with the capacitor contact pad 42, and is provided in a cylindrical shape on the inner walls of the hole 50 and the dummy holes 51 and 52 formed in the insulating film 46. Examples of the material of the lower electrode 54 include titanium nitride. Examples of the material of the capacitive film 56 include zirconium oxide, aluminum oxide, hafnium oxide, and a laminated film thereof. Further, the material of the upper plate electrode 58 includes a laminated film of tungsten, polycrystalline silicon, and silicon nitride.

  The capacitance of the capacitor 53 is basically proportional to the surface area of the lower electrode 54, but the area of the capacitor contact pad 42 tends to be reduced by increasing the density of a semiconductor device such as a DRAM. Therefore, the height dimension of the lower electrode 54 is larger than the width dimension of the lower electrode 54, for example, about 1 μm.

Next, a method for manufacturing the DRAM 10 will be described with reference to FIGS.
First, as described above, a transistor including the active region 14, the buried word line 16, the bit line 18 and the like is formed on the semiconductor substrate 12. Since the transistor of the DRAM 10 can be formed by a method of manufacturing a transistor generally applied to a semiconductor device such as a DRAM, a detailed description thereof is omitted. Note that the upper surfaces of the cap insulating film 24, the capacitor contact 28, and the interlayer insulating film 32 are planarized using CMP or the like so as to have the same height.

  Next, a conductive film such as tungsten is formed on the cap insulating film 24, the capacitor contact 28, and the interlayer insulating film 32. After patterning the conductive film using a photolithography etching technique, dry etching is performed. Thereby, the capacitor contact pad 42 shown in FIG. 4 is formed. However, a capacitor contact pad 42 d having a width dimension larger in the X direction than the capacitor contact pad 42 is formed on the outer peripheral portion of the semiconductor substrate 12 in consideration of the width dimension in the X direction of the dummy hole 52. The thickness of the capacitor contact pad 42 can be set to 100 nm, for example.

  Next, as shown in FIG. 5, a stopper film 44 is formed with a thickness of, for example, 50 nm so as to cover the capacitor contact pad 42 by CVD or the like. Subsequently, an insulating film 46 in which an insulating film 47 and an insulating film 48 are stacked on the stopper film 44, and insulating films 49a and 49b made of a silicon nitride film or the like are formed with a predetermined thickness. The thicknesses of the insulating films 47 and 48 can be set to, for example, 1000 nm and 800 nm, respectively. The thickness of the insulating films 49a and 49b can be set to 100 nm, for example.

  Next, an amorphous carbon film 60 having a thickness of 600 nm, for example, is formed on the insulating film 49b, and then the amorphous carbon film 60 at the locations where the holes 50 and the outermost peripheral holes 50P, 50Q, 50R are to be formed is removed. As described above, the amorphous carbon film 60 is patterned using a photolithography / etching technique. At this time, as shown in FIG. 6, the thickness dimension of the amorphous carbon film 60 on the outer periphery of the semiconductor substrate 12 becomes larger than the thickness dimension of the amorphous carbon film 60 on the inner side of the outer periphery of the semiconductor substrate 12 due to the etching dullness. .

  Next, as shown in FIG. 6, by using the patterned amorphous carbon film 60 as a mask, the stopper film 44 in the cylinder forming portion on the capacitive contact pad 42, the insulating film 46, and the insulating films 49a and 49b are formed by dry etching. Is formed, and a dummy hole 52 in which the hole 50 and the holes 50P, 50Q, 50R at the outermost periphery of the hole 50 are connected is formed.

  In the above process, the impact of ions during dry etching is as shown by the arrow in FIG. 6, and as described above, the holes 50P, 50Q, 50R at the outermost peripheral portion of the hole 50 are connected to increase the opening area in plan view. Therefore, the dummy hole 52 is difficult to close. In addition, the layout of the non-resolving dummy holes exceeding the resolution of the mask layout used in the lithography / etching technology is relaxed, and the degree of freedom of the mask layout is increased. Therefore, in this step, the memory cell and its end are easily opened simultaneously. The In order to reliably prevent the dummy hole 52 from being blocked, if the width dimension of the hole 50 is 60 nm, for example, the width dimension in the X direction of the dummy hole 52 is preferably set to about 180 nm.

  Next, as shown in FIG. 7, the remaining amorphous carbon film 60 and insulating film 49b are removed. Subsequently, a titanium nitride film having a thickness small enough not to fill the hole 50 is formed on the inner walls of the hole 50 and the dummy hole 52 and the upper surface of the insulating film 49a. The thickness of this titanium nitride film can be set to 15 nm, for example. Thereafter, the titanium nitride film and the insulating film 49a are polished and removed by CMP or the like until the upper surface of the insulating film 46, that is, the upper surface of the insulating film 48 is exposed. As a result, as shown in FIG. 8, a lower electrode 54 made of cylindrical titanium nitride in contact with the capacitor contact pad 42 is formed. Subsequently, the insulating film 46 between the lower electrodes 54 adjacent to the semiconductor substrate 12 in the X direction and the Y direction is removed.

  Next, a capacitor film 56 having a predetermined thickness is formed so as to cover the lower electrode 54 and the upper surface of the remaining insulating film 46. Subsequently, a laminated film of tungsten, polycrystalline silicon, and silicon nitride is embedded in the hole 50 and the dummy holes 51 and 52 surrounded by the capacitor film 56 so as to have a certain thickness dimension above the insulating film 46. Form a film. Thereafter, the upper surface of the laminated film is removed by polishing, and an upper plate electrode 58 having a predetermined thickness dimension is formed from the upper surface of the insulating film 46. As a result, the capacitor 53 including the lower electrode 54, the capacitor film 56, and the upper plate electrode 58 is formed.

Through the above steps, the DRAM 100 shown in FIGS. 1 to 3 is completed.
In the manufacturing method of the DRAM 10 described above, the formation process of the capacitor 53 in the hole 50 and the dummy hole 52 has been described with reference to the cross-sectional view in the Y direction of the DRAM 10 shown in FIG. In the X direction shown in FIG. 2, a similar process may be performed by replacing the dummy hole 52 in the Y direction with the dummy hole 51. A process of forming the capacitor 53 in the dummy hole provided in the outermost peripheral portion in the X direction of the hole 50 and having a width dimension larger in the Y direction than the hole 50 as in the dummy hole 51 will be described later. To do.

  According to the DRAM 10 and the method of manufacturing the same of the present embodiment, the outermost peripheral portion of the hole 50 for forming the cylinder-type capacitor 53 extends in the outer direction of the periodic arrangement of the holes 50, and the holes are viewed in plan view. Dummy holes 51 and 52 having a width dimension larger than 50 are provided. The dummy hole 52 has the same size as the hole 50 in a plan view, and is a hole in which holes 50P and 50Q adjacent to each other in the X direction on the outermost peripheral portion of the hole 50 are connected by the hole 50R. Therefore, in the etching process for forming the holes 50, the opening areas of the outermost dummy holes 51 and 52 where the etching depth tends to decrease are expanded compared to the holes 50, and the width dimensions of the dummy holes 51 and 52 are increased. Sufficiently secured to prevent clogging and prevent failure. Therefore, the entire hole 50 on the semiconductor substrate 12 can be reliably opened and formed satisfactorily. As a result, the lower electrode 54 of the capacitor 53 is stably formed in the hole 50 and the dummy holes 51 and 52, and does not peel off and become dust, thereby preventing a failure of the DRAM 10.

  Further, according to the DRAM 10 and the manufacturing method thereof of the present embodiment, since the opening areas of the dummy holes 51 and 52 at the outermost peripheral portion of the hole 50 are expanded as described above, the mask layout used in the lithography / etching technique is increased. Since the layout of the non-resolution dummy holes exceeding the resolution is relaxed and the degree of freedom of the mask layout is increased, the memory cell and its end can be opened easily and simultaneously.

(Second embodiment)
Next, a DRAM 11 (semiconductor device) as an example of the semiconductor device according to the second embodiment to which the present invention is applied will be described with reference to FIG. Also, among the components of the DRAM 11 shown in FIG. 9, the same components as those of the DRAM 10 of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In the DRAM 11 of the present embodiment, a plurality of memory cells are provided as in the DRAM 10 of the first embodiment. As shown in FIG. 9, holes 50 for forming capacitors of a plurality of memory cells are periodically arranged in an X direction and a Y direction in an insulating film on a transistor formed on a semiconductor substrate 12. Have the same shape in plan view. Dummy holes 51 and 52 are provided on the outermost periphery of the hole 50. In addition, dummy holes 51 and 52 opened in a larger area in plan view than the hole 50 are provided in the four directions outside the memory cell region of the DRAM 11 of the present embodiment in which the hole 50 is formed. In FIG. 9, the outer four directions indicate both sides in the X direction (upper and lower sides in the drawing) and both sides in the Y direction (left and right sides in the drawing).

  However, although the dummy hole 51 of the DRAM 11 of the present embodiment is provided in the outermost peripheral portion of the hole 50 in the X direction, it has a width dimension larger than the hole 50 in the X direction and is substantially the same as the hole 50 in the Y direction. The width dimension is formed. The dummy holes 52 are provided in the outermost peripheral portion of the holes 50 in the Y direction and extend in the outer direction of the periodic arrangement of the holes 50, but are not holes in which the plurality of holes 50 are connected. , Having a width dimension substantially the same as that of the hole 50 in the X direction and having a width dimension larger than that of the hole 50 in the Y direction. From the viewpoint of reliably preventing the dummy holes from being blocked in the etching process when forming the dummy holes 51 and 52, when the width dimension of the holes 50 is 60 nm, for example, the width dimension in the X direction of the dummy holes 51 and It is preferable that the width dimension in the Y direction of the dummy hole 52 is set to about 120 nm. Since the configuration of the DRAM 11 other than the dummy holes 51 and 52 is the same as that of the DRAM 10 of the first embodiment, the description thereof is omitted.

Next, a method for manufacturing the DRAM 11 will be described with reference to FIGS.
First, similar to the method of manufacturing the DRAM 10 of the first embodiment, a transistor including the active region 14, the buried word line 16, the bit line 18 and the like is manufactured by a method of manufacturing a transistor generally applied to a semiconductor device such as a DRAM. It is formed on the semiconductor substrate 12. The top surfaces of the cap insulating film 24, the capacitor contact 28, and the interlayer insulating film 32 are planarized using CMP or the like so as to have the same height.

  Next, a conductive film such as tungsten is formed on the cap insulating film 24, the capacitor contact 28, and the interlayer insulating film 32. After patterning the conductive film using a photolithography etching technique, dry etching is performed. At this time, the outermost conductive film in the X direction on the semiconductor substrate 12 is patterned so that the width dimension in the X direction is increased, and the conductive film in the outermost peripheral part in the Y direction is as shown in FIG. Patterning is performed to increase the width dimension in the Y direction. Through this step, the capacitor contact pad 42 shown in FIG. 10 and the capacitor contact pad 42d having a width dimension larger in the Y direction than the capacitor contact pad 42 are formed. Form. Hereinafter, a state in which the semiconductor substrate 12 is viewed in a cross section in the Y direction will be described.

  Next, as shown in FIG. 11, a stopper film 44 is formed with a predetermined thickness so as to cover the capacitor contact pad 42 by CVD or the like. Subsequently, an insulating film 46 in which an insulating film 47 and an insulating film 48 are stacked on the stopper film 44, and insulating films 49a and 49b made of a silicon nitride film or the like are formed with a predetermined thickness.

  Next, after the amorphous carbon film 60 is formed on the insulating film 49b with a thickness dimension of 600 nm, for example, the amorphous carbon film 60 at the locations where the holes 50 and the dummy holes 52 at the outermost periphery are to be formed is removed. Then, the amorphous carbon film 60 is patterned using a photolithography / etching technique. At this time, as shown in FIG. 12, the thickness dimension of the amorphous carbon film 60 on the outer peripheral portion of the semiconductor substrate 12 becomes larger than the thickness dimension of the amorphous carbon film 60 on the inner side of the outer peripheral portion of the semiconductor substrate 12 due to the etching dullness. .

  Next, as shown in FIG. 6, by using the patterned amorphous carbon film 60 as a mask, the stopper film 44 in the cylinder forming portion on the capacitive contact pad 42, the insulating film 46, and the insulating films 49a and 49b are formed by dry etching. And the hole 50 and the dummy hole 52 at the outermost periphery of the hole 50 are formed. By this step, a dummy hole 52 having a larger width dimension in the Y direction than the hole 50 is formed in contact with the outermost capacitive contact pad 42 having a larger width dimension in the Y direction among the capacitor contact pads 42 on the semiconductor substrate 12. Is done.

  In the above process, the impact of ions during dry etching is as shown by the arrow in FIG. 12, and the opening area in plan view is increased by increasing the width dimension in the Y direction as described above. 52 becomes difficult to close. Further, as in the manufacturing of the DRAM 10 of the first embodiment, the layout of the non-resolving dummy holes exceeding the resolution of the mask layout used in the lithography / etching technique is relaxed and the degree of freedom of the mask layout is increased. The memory cell and its end are easily opened simultaneously. In order to reliably prevent the dummy hole 52 from being blocked, if the width dimension of the hole 50 is set to 60 nm, for example, the width dimension in the Y direction of the dummy hole 52 is preferably set to about 120 nm.

  Next, as shown in FIG. 13, the remaining amorphous carbon film 60 and insulating film 49b are removed. Thereafter, the same processes as those described with reference to FIG. 8 are performed in the method of manufacturing the DRAM 10 of the first embodiment.

Through the above steps, the DRAM 11 shown in FIG. 9 is completed.
In the manufacturing method of the DRAM 11 described above, the formation process of the capacitor 53 in the hole 50 and the dummy hole 52 has been described by the cross-sectional view in the Y direction shown in FIG. 9 with reference to FIGS. In the X direction, the dummy hole 52 in the Y direction is replaced with the dummy hole 51 and the same process may be performed.

  According to the DRAM 11 and the manufacturing method thereof of the present embodiment, the outermost peripheral portion of the hole 50 for forming the cylinder-type capacitor 53 extends in the outer direction of the periodic arrangement of the holes 50, and the holes are viewed in plan view. Dummy holes 51 and 52 having a width dimension larger than 50 are provided. The dummy hole 51 is a hole having a width dimension larger than the hole 50 in the X direction on the semiconductor substrate 12 and having substantially the same width dimension as the hole 50 in the Y direction. The dummy hole 52 is a hole having substantially the same width dimension as the hole 50 in the X direction and having a width dimension larger than the hole 50 in the Y direction. Therefore, in the etching process for forming the holes 50, the opening areas of the outermost dummy holes 51 and 52 where the etching depth tends to decrease are expanded compared to the holes 50, and the width dimensions of the dummy holes 51 and 52 are increased. Sufficiently secured to prevent clogging and prevent failure. Therefore, the entire hole 50 on the semiconductor substrate 12 can be reliably opened and formed satisfactorily. As a result, the lower electrode 54 of the capacitor 53 is stably formed in the hole 50 and the dummy holes 51 and 52, and does not come off and become dust, thereby preventing a failure of the DRAM 11.

  Further, according to the DRAM 11 and the manufacturing method thereof of the present embodiment, since the opening areas of the dummy holes 51 and 52 at the outermost peripheral portion of the hole 50 are expanded as described above, the mask layout used in the lithography / etching technique is increased. Since the layout of the non-resolution dummy holes exceeding the resolution is relaxed and the degree of freedom of the mask layout is increased, the memory cell and its end can be opened easily and simultaneously.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications are possible within the scope of the gist of the present invention described in the claims. Deformation / change is possible.

  That is, the dummy holes 51 and 52 at the outermost periphery of the hole 50 for forming the capacitors of the plurality of memory cells in the semiconductor device of the present invention are formed on the insulating film on the transistor formed on the semiconductor substrate 12 as X As long as the area in the plan view is expanded from the holes 50, the expansion direction of the area is not limited. For example, the dummy holes 51 and 52 may be holes having a larger width dimension than the hole 50 in both the X direction and the Y direction. Further, the dummy holes 51 and 52 may be holes in which a plurality of outermost peripheral portions of the hole 50 are connected in the circumferential direction.

  10, 11, 100 ... DRAM (semiconductor device), 12, 112 ... semiconductor substrate, 42 ... capacitive contact pad (pad), 46, 146 ... insulating film, 50, 50P, 50Q, 50R, 150, 150r ... hole, 51 52 ... dummy holes, 53 ... capacitors

Claims (8)

A semiconductor device having holes of the same shape periodically arranged in an insulating film formed on a semiconductor substrate,
A semiconductor device comprising: a dummy hole that extends in an outer direction of the periodic arrangement of the holes at an outermost peripheral portion of the hole and has an opening having a larger width dimension than the hole.   2. The semiconductor device according to claim 1, wherein a pad is disposed under the hole, a dummy pad is disposed under the dummy hole, and the dummy pad has a width dimension larger than that of the pad. A semiconductor device having a capacitor including a hole in a memory cell region on a semiconductor substrate,
A semiconductor device comprising a dummy hole having a larger area in plan view than the opening of the hole on the outer periphery of the hole.   4. The semiconductor device according to claim 3, wherein the dummy hole extends in an outer direction of the memory cell region and has a large area in plan view.   The hole includes a first row arranged at a constant cycle and a second row arranged at the constant cycle, and the dummy hole is an area located at the outermost peripheral portion of the first row at the constant cycle. 4. The semiconductor device according to claim 3, wherein the semiconductor device is formed so as to include the outermost peripheral portion of the second row and the region located at the constant period.   4. The semiconductor device according to claim 3, wherein a pad is disposed under the hole, a dummy pad is disposed under the dummy hole, and the dummy pad has a width dimension larger than that of the pad. A semiconductor device having a hole in a memory cell region on a semiconductor substrate and a dummy hole around the hole,
A semiconductor device comprising: the dummy holes opened in a wider area in plan view than the holes in four directions outside the memory cell region.   The semiconductor device according to claim 7, wherein a pad is disposed under the hole, a dummy pad is disposed under the dummy hole, and the dummy pad is larger than the pad.

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