JP2014216521A - Field effect semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect a contact plug and a metal source-drain electrode reliably, while suppressing junction leakage or increase in resistance.SOLUTION: A field effect semiconductor device having a metal S/D structure includes a semiconductor substrate 10, a gate electrode 13 formed on the substrate 10 via a gate insulating film 12, a source-drain electrode 20 formed on the surface of the substrate 10 across a channel region under the gate electrode 13 and composed of an alloy of a semiconductor composing the substrate 10 and a meal, and a contact plug 30 coming into contact with the source-drain electrode 20. The interface of the source-drain electrode 20 in a region 22 directly under the contact plug and the substrate 10 exists at a position deeper to the substrate side than the interface of the source-drain electrode 20 in other region 21 and the substrate 10.

Description

  Embodiments described herein relate generally to a field effect semiconductor device having a metal S / D structure and a method for manufacturing the same.

  Currently, the miniaturization of Si-MOSFETs is being faced, and low power consumption of LSIs that do not depend on miniaturization has become a major issue, and the III-V group has higher mobility than conventional Si in the MOSFET channel. Research using semiconductors and Ge has been conducted energetically.

  On the other hand, a so-called metal S / D structure in which a source / drain (S / D) metal electrode and a channel are adjacent to each other has been proposed as a structure that can be expected to have advantages such as reduction in parasitic resistance and simplification of an element manufacturing process. For example, a process for forming Ni-InGaAs, which is an alloy of Ni and InGaAs, on a source / drain (S / D) electrode in a self-aligned manner has been developed, and a prototype of a metal S / D InGaAs-nMOSFET using the process has been developed. It has been reported (Non-Patent Document 1).

  Further, in order to miniaturize a metal S / D MOSFET, it is necessary to reduce the thickness of the S / D electrode layer to about 1/3 of the gate length from the viewpoint of suppressing the short channel effect. It has also been reported that an ultra-thin Ni—InGaAs alloy layer having a film thickness of 10 nm or less can be formed by controlling the heat treatment temperature (Patent Document 1, Non-Patent Document 2).

  Therefore, by combining these techniques, a metal S / D InGaAs-nMOSFET having an ultrathin Ni-InGaAs S / D electrode can be produced.

JP2013-008832A

S. H. Kim et al., IEDM Tech. Dig., Pp. 596 (2010). T. Irisawa et al., Ext. Abst. SSDM, pp.947 (2011).

  In a normal Si-CMOS-LSI contact formation process, a process of forming a contact hole in an interlayer insulating film using reactive ion etching (RIE) and embedding a contact metal plug is performed. However, when an equivalent process is performed on a metal S / D InGaAs-nMOSFET having an ultrathin S / D electrode, the InGaAs alloy layer may be over-etched and the InGaAs alloy layer under the plug may disappear.

  In principle, if the RIE of the contact hole is completed at the same time as reaching the InGaAs alloy layer, overetching will not occur, but overetching is unavoidable in order to secure a process margin on the entire wafer surface. The disappearance of the InGaAs alloy layer under the plug is thought to cause problems such as an increase in junction leakage and an increase in resistance due to contact area reduction, and the alloy layer under the plug remains even after a sufficient process margin. It is desirable.

  The problem to be solved by the present invention is that the contact plug and the metal source / drain electrode can be reliably connected while securing the RIE process margin for forming the contact hole, and the junction leakage and the resistance increase. It is providing the field effect type semiconductor device which can suppress, and its manufacturing method.

  The field effect semiconductor device of the present invention is formed on the surface portion of the substrate with a semiconductor substrate, a gate electrode formed on the substrate through a gate insulating film, and a channel region under the gate electrode, A source / drain electrode made of an alloy of a semiconductor and a metal constituting the substrate; and a contact plug contacting the source / drain electrode. The interface between the source / drain electrode in the region immediately below the contact plug and the substrate exists at a deeper position on the substrate side than the interface between the source / drain electrode in the other region and the substrate. Features.

  The method for manufacturing a field effect semiconductor device of the present invention includes a step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and a surface portion of the substrate with a channel region under the gate electrode interposed therebetween. Forming a first source / drain electrode made of an alloy of a semiconductor and a metal on the substrate; forming an interlayer insulating film so as to cover the gate electrode and the first source / drain electrode; A step of forming contact holes in the interlayer insulating film for connection to the source / drain electrodes; and a second source / drain electrode made of an alloy of a semiconductor and a metal constituting the substrate at the bottom of the contact holes. And forming a contact plug in contact with the second source / drain electrode in the contact hole. To.

  According to the present invention, the metal S / D electrode / semiconductor substrate interface immediately below the contact plug is present at a deeper position on the semiconductor substrate side than the S / D electrode / semiconductor substrate interface in other regions. Even if overetching for forming a contact hole occurs, the contact plug and the metal S / D electrode are reliably connected. Thereby, a sufficient process margin can be ensured in the RIE for forming the contact hole without causing problems such as junction leakage and an increase in resistance.

Sectional drawing which shows schematic structure of InGaAs-MOSFET concerning 1st Embodiment. Sectional drawing which shows the manufacturing process of InGaAs-MOSFET of 1st Embodiment. Sectional drawing which shows the manufacturing process of InGaAs-MOSFET of 1st Embodiment. Sectional drawing which shows the manufacturing process of InGaAs-MOSFET of 1st Embodiment. Sectional drawing which shows schematic structure of InGaAs-MOSFET concerning 2nd Embodiment. Sectional drawing which shows the manufacturing process of InGaAs-MOSFET of 2nd Embodiment. Sectional drawing which shows the manufacturing process of InGaAs-MOSFET of 2nd Embodiment. Sectional drawing which shows schematic structure of InGaAs-MOSFET concerning 3rd Embodiment. Sectional drawing which shows the manufacturing process of InGaAs-MOSFET of 3rd Embodiment. Sectional drawing which shows the manufacturing process of InGaAs-MOSFET of 3rd Embodiment.

  Hereinafter, a field effect semiconductor device according to an embodiment will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing a schematic structure of an InGaAs-MOSFET according to the first embodiment.

A gate electrode 13 is formed on an In _x Ga _1-x As substrate (semiconductor substrate) 10 via a gate insulating film 12, and a source / drain made of a metal electrode is formed on the surface of the substrate 10 with the gate electrode 13 interposed therebetween. An (S / D) electrode 20 is formed. That is, the S / D electrode 20 has a so-called metal S / D structure in which a metal electrode such as Ni-InGaAs is adjacent to the channel.

As the gate insulating film 12, Al ₂ O _3, HfO ₂ , La ₂ O _{3 or} a mixture thereof can be used, and as the material of the gate electrode 13, Ta, TaN, Ti, TiN, Ni, Au, Various metals such as Pt, alloys such as NiSix and NiGex, and poly Si _1-x Ge _x subjected to high concentration doping can be used. Furthermore, there are no restrictions on the gate stack structure and materials. Further, as the material of the S / D electrode 20, it is possible to use an alloy containing Co, Pt, etc. in addition to Ni.

  An interlayer insulating film 17 is provided on the substrate 10 on which the gate insulating film 12 and the gate electrode 13 are formed. A contact hole is formed in the interlayer insulating film 17 and the contact plug 30 is connected to the S / D electrode 20 by embedding the contact plug 30 in the contact hole. The portion (second S / D electrode) 22 immediately below the plug of the S / D electrode 20 is formed deeper than the peripheral portion (first S / D electrode) 21. That is, the interface between the second S / D electrode 22 immediately below the plug and the semiconductor exists deeper on the semiconductor substrate side than that of the first S / D electrode 21 in the peripheral portion. The plug 30 includes a barrier metal 31 such as Ti or TiN and a conductive film 32 made of W, Pd, Al, Cu, Au, or an alloy thereof. There are no restrictions on the structure and material of the plug, and the use of the barrier metal 31 is not essential.

  Next, the manufacturing method of this embodiment is demonstrated with reference to FIG. 2 thru | or FIG.

First, as shown in FIG. 2A, an element isolation embedded insulating film 11 is formed so as to surround an element formation region in an In _x Ga _1-x As substrate 10, and then a gate electrode is interposed via a gate insulating film 12. 13 is formed. There is no limitation on the method of forming the In _x Ga _1-x As substrate 10, and it is formed by epitaxial growth on a compound semiconductor substrate such as InP or GaAs, or a Si or Ge substrate, or by bonding to various base substrates. Can do.

Next, as shown in FIG. 2B, a metal film 14 containing Ni is deposited to form an S / D electrode. Prior to metal deposition, the gate sidewall may be formed of SiO ₂ , SiN, or the like. However, when TaN is used for the gate electrode, for example, TaN oxide is naturally formed on the side surface of the gate electrode, so the sidewall formation is essential is not. The thickness of the deposited metal film 14 is preferably 30 nm or less, but more preferably 10 nm or less. This is because alloying with InGaAs is performed in the subsequent heat treatment, but the film thickness of the alloy is preferably about 10 nm or less from the viewpoint of short channel effect resistance, and for this purpose, the amount of deposited metal is limited to 10 nm or less. It is necessary to do.

  Next, as shown in FIG. 2C, a first S / D electrode 21 made of an alloy of the above metal and InGaAs and having a thickness of 10 nm or less is formed by performing heat treatment and alloying treatment. . The temperature of the heat treatment for alloying is desirably 200 to 350 ° C. This is because the alloying reaction hardly occurs at a temperature lower than this temperature range, and the alloy layer becomes thick at a high temperature.

  After the alloying heat treatment, the metal film 14 connecting the gate electrode 13 and the S / D electrode 21 is etched. In the case where Ni is deposited, it is possible to perform etching while maintaining a selectivity with the S / D electrode 21 made of Ni-InGaAs with HCl. Thereby, electrical separation between the gate electrode 13 and the S / D electrode 21 is performed.

  Subsequently, a post process according to the Si-LSI process is performed. First, as shown in FIG. 2D, an insulating film 16 serving as an etching stopper for contact hole etching such as SiN is deposited.

Next, as shown in FIG. 3E, an interlayer insulating film 17 such as SiO ₂ is deposited. The film thickness of these films is arbitrary and may be set according to the application. After the interlayer insulating film 17 is deposited, the surface is flattened by chemical mechanical polishing (CMP).

  Next, as shown in FIG. 3F, contact holes 18 are formed in the interlayer insulating film 17 and the stopper insulating film 16 using RIE. In the RIE of each film, in order to ensure a process margin, it is necessary to perform etching for a time longer than the etching time calculated backward from the etching rate.

  At this time, it is assumed that the underlying S / D electrode 21 is over-etched, and in some cases, as shown in FIG. 3G, the alloy layer becomes extremely thin or all of the alloy layer is etched. If a contact plug is formed in a state where the alloy layer has disappeared, problems such as an increase in leakage current and an increase in resistance due to contact area reduction are caused. Therefore, in this embodiment, the alloy layer is re-formed after the contact hole is formed.

  In re-forming the alloy layer, a metal film 19 such as Ni is deposited as shown in FIG. Although it is desirable to deposit the same metal as the metal used for forming the S / D electrode previously, the metal species may be changed. The deposited film thickness is desirably 30 nm or less.

  Next, as shown in FIG. 4 (i), the alloy layer, that is, the second S / D electrode 22 is formed by performing a heat treatment at 200 to 350 ° C. as in the case of forming the S / D electrode. At this time, the S / D electrode 22 is formed in the contact hole portion to a position deeper than the surroundings. That is, as the metal S / D electrode 20, S / D electrodes 21, 22 having different film thicknesses are formed immediately below the contact plug and other than that.

  Next, as shown in FIG. 4J, the unreacted metal film 19 is selectively etched with HCl or the like. Thereafter, deposition of barrier metal 31 and plug metal 32 is performed to form contact plug 30, thereby obtaining the structure shown in FIG. Thereafter, a wiring process according to the Si-LSI process can be performed.

  As described above, according to the present embodiment, for the metal S / D-InGaAs-MOSFET having the ultrathin Ni-InGaAs layer 21, the contact hole 18 is formed in the interlayer insulating film 17, and then Ni is deposited and heat-treated again. As a result, a Ni-InGaAs alloy layer 22 is newly formed immediately below the contact hole. As a result, the contact plug 30 and the Ni—InGaAs layer (S / D electrode) 20 are securely connected, and a sufficient process margin is achieved in the RIE for forming the contact hole without causing problems such as junction leakage and increased resistance. Can be secured.

  That is, it is possible to establish a reliable connection between the contact plug and the metal source / drain electrodes while securing a RIE process margin for forming the contact hole. Accordingly, it is possible to suppress junction leakage and increase in resistance. This is effective for realizing a CMOS-LSI with high performance and low power consumption.

(Second Embodiment)
FIG. 5 is a cross-sectional view showing a schematic structure of an InGaAs-MOSFET according to the second embodiment. In addition, the same code | symbol is attached | subjected to the same part as FIG. 1, and the detailed description is abbreviate | omitted.

  The difference between the present embodiment and the first embodiment described above is that the metal S / D electrode is not formed after the contact hole is formed, but the metal S / D electrode is formed thick in advance in a region other than the vicinity of the gate. There is.

  In the present embodiment, gate sidewall insulating films 41 are formed on both sides of the gate electrode 13 in addition to the same configuration as in FIG. The thickness of the S / D electrode 50 is thin at the portion (first S / D electrode) 51 below the gate sidewall insulating film 41 and thick at the portion outside it (second S / D electrode) 52. ing. That is, the S / D electrode 50 is thick at the contact portion and thin near the gate. Since the S / D electrode 50 is thick at the contact portion, it does not penetrate through the formation of the contact hole. Further, the S / D electrode 20 can be made sufficiently thin in the vicinity of the gate.

  Next, the manufacturing method of this embodiment is demonstrated with reference to FIG.6 and FIG.7.

First, as shown in FIG. 6A, an element isolation buried insulating film 11 is formed so as to surround an element formation region in an In _x Ga _1-x As substrate 10, and then a gate insulating film 12 and a gate electrode 13 are formed. Form. Subsequently, a thin first S / D electrode 51 is formed in a region excluding the gate portion. For the formation of the S / D electrode 51, a Ni film deposition process, a heat treatment process, and an unreacted Ni film removal process may be performed as in the first embodiment.

  Next, as shown in FIG. 6B, a gate sidewall insulating film 41 is formed. The gate sidewall insulating film 41 may be formed by, for example, depositing a silicon oxide film on the entire surface and then etching back to leave the oxide film on the gate sidewall.

  Next, as shown in FIG. 6C, a metal film 42 containing Ni is deposited to form an S / D electrode. The thickness of the deposited metal film 42 is desirably 30 nm or less, for example, 20 nm. The reason why it is thicker than in the first embodiment is that it is not necessary to limit the film thickness of the alloy to about 10 nm or less because it is a region excluding the vicinity of the gate.

  Next, as shown in FIG. 6D, a second S / D electrode 52 made of an alloy of the above metal and InGaAs is formed by performing a heat treatment and an alloying process. As a result, the S / D electrodes 51 and 52 having different film thicknesses are formed as the metal S / D electrode 50 immediately below the gate sidewall insulating film and other than that. Note that the temperature of the heat treatment for alloying is desirably 200 to 350 ° C. This is because the alloying reaction hardly occurs at a temperature lower than this temperature range, and the alloy layer becomes thick at a high temperature.

  After the alloying heat treatment, the metal film 42 connecting the gate electrode 13 and the S / D electrode 50 is etched. In the case where Ni is deposited, it is possible to perform etching with HCl while maintaining a selectivity with the S / D electrode 50 of Ni-InGaAs. Thereby, electrical separation between the gate electrode 13 and the S / D electrode 50 is performed.

  Subsequently, a post process according to the Si-LSI process is performed. First, as shown in FIG. 7E, an insulating film 16 serving as an etching stopper for contact hole etching such as SiN is deposited.

Next, as shown in FIG. 7F, an interlayer insulating film 17 such as SiO ₂ is deposited. The film thickness of these films is arbitrary and may be set according to the application. After the interlayer insulating film 17 is deposited, the surface is flattened by chemical mechanical polishing (CMP).

  Next, as shown in FIG. 7G, contact holes are formed in the interlayer insulating film 17 and the stopper insulating film 16 using RIE. In the RIE of each film, in order to ensure a process margin, it is necessary to perform etching for a time longer than the etching time calculated backward from the etching rate. At this time, even if overetching occurs, the S / D electrode 50 does not penetrate because of the thick film.

  Thereafter, by depositing the barrier metal 31 and the plug metal 32 to form the contact plug 30, the structure shown in FIG. 5 is obtained.

  As described above, according to the present embodiment, the S / D electrode 50 is thinly formed under the gate sidewall insulating film near the gate, and the S / D electrode 50 is thickly formed directly under the contact plug. For this reason, even if some over-etching for forming the contact hole occurs, the S / D electrode 50 does not disappear. Therefore, the same effect as in the first embodiment can be obtained.

(Third embodiment)
FIG. 8 is a sectional view showing a schematic structure of an InGaAs-MOSFET according to the third embodiment. 1 and 5 are denoted by the same reference numerals, and detailed description thereof is omitted.

  This embodiment is different from the second embodiment described above in that the thickness of the S / D electrode 20 is changed using the gate sidewall insulating film 41 and the sidewall insulating film 41 is finally removed. is there.

  In the present embodiment, as in FIG. 5, the thickness of the S / D electrode 60 is thin in the vicinity of the gate portion (second S / D electrode) 62 and the portion outside the first portion (first S / D electrode). (S / D electrode) 61 is thicker. The difference from FIG. 5 is that there is no gate sidewall insulating film 41.

  Next, the manufacturing method of this embodiment is demonstrated with reference to FIG.9 and FIG.10.

First, as shown in FIG. 9A, after an element isolation embedded insulating film 11 is formed so as to surround an element formation region in an In _x Ga _1-x As substrate 10, a gate insulating film 12 and a gate electrode 13 are formed. Form. Subsequently, gate sidewall insulating films 41 such as silicon oxide films are formed on both side surfaces of the gate portion.

  Next, as shown in FIG. 8B, a first metal film made of an alloy of the above metal and InGaAs is formed by depositing a metal film 42 containing Ni and then performing heat treatment to form an S / D electrode. The S / D electrode 61 is formed. At this time, the thickness of the deposited metal film 42 is desirably 30 nm or less, for example, 20 nm.

  Next, as shown in FIG. 8C, after the alloying heat treatment, the metal film 42 that has not been alloyed is etched, and the sidewall insulating film 41 is further etched.

  Next, as shown in FIG. 8D, a second metal film made of an alloy of the above metal and InGaAs is formed by depositing a metal film 43 containing Ni and then performing heat treatment to form an S / D electrode. The S / D electrode 62 is formed. At this time, the thickness of the deposited metal film 43 is set to 10 nm or less. This is to make the film thickness of the alloy near the gate 10 nm or less.

  Next, as shown in FIG. 10E, the unreacted metal film 43 is etched.

Subsequently, a post process according to the Si-LSI process is performed. First, as shown in FIG. 10F, an insulating film 16 serving as an etching stopper for contact hole etching such as SiN is deposited. Subsequently, an interlayer insulating film 17 such as SiO ₂ is deposited. The film thickness of these films is arbitrary and may be set according to the application. After the interlayer insulating film 17 is deposited, the surface is flattened by chemical mechanical polishing (CMP).

  Next, as shown in FIG. 10G, contact holes are formed in the interlayer insulating film 17 and the stopper insulating film 16 using RIE. In the RIE of each film, in order to ensure a process margin, it is necessary to perform etching for a time longer than the etching time calculated backward from the etching rate. At this time, even if overetching occurs, the underlying S / D electrode 60 is thick, so that no penetration occurs.

  Next, by depositing a barrier metal 24 and a plug metal 25 to form a contact plug, the structure shown in FIG. 8 is obtained.

  As described above, according to the present embodiment, the S / D electrode 60 is formed thin near the gate, and the S / D electrode 60 is formed directly below the contact plug. For this reason, the S / D electrode 60 does not disappear even if some over-etching for forming the contact hole occurs. Therefore, the same effect as the second embodiment can be obtained.

(Modification)
The present invention is not limited to the above-described embodiments.

  The semiconductor substrate is not necessarily a bulk substrate, and may be a substrate in which a semiconductor layer is formed.

In the embodiment, it is assumed that the channel material is In _x Ga _1-x As (0 <x <1), but the channel material is not limited to In _x Ga _1-x As, and InP, In _x Ga It is also possible to apply to _1-x Sb, Si _1-x Ge _x , and Ge _1-x Sn _x . Of course, the present invention can also be applied to a laminated structure thereof. Furthermore, it is not necessarily limited to a compound semiconductor, but may be a single layer of Ge or Si, and can be applied to a semiconductor having an effective metal S / D structure.

  Further, the metal for alloying with the semiconductor substrate is not limited to Ni, and a metal such as Co or Pt can also be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

10 ... In _x Ga _1-x As substrate (semiconductor substrate)
DESCRIPTION OF SYMBOLS 11 ... Element isolation embedding insulating film 12 ... Gate insulating film 13 ... Gate electrode 14, 19, 42, 43 ... Metal film 16 ... Stopper insulating film 17 ... Interlayer insulating film 20, 50, 60 ... Metal S / D electrode 21, 51 , 61 ... First S / D electrode 22, 52, 62 ... Second S / D electrode 31 ... Barrier metal 32 ... Plug electrode 41 ... Gate sidewall insulating film

Claims (8)

A semiconductor substrate;
A gate electrode formed on the substrate via a gate insulating film;
A source / drain electrode formed on the surface portion of the substrate across the channel region under the gate electrode and made of an alloy of a semiconductor and a metal constituting the substrate;
A contact plug in contact with the source / drain electrode;
Comprising
The interface between the source / drain electrode and the substrate in a region immediately below the contact plug is present at a deeper position on the substrate side than the interface between the source / drain electrode and the substrate in another region. Field effect semiconductor device. A semiconductor substrate;
A gate electrode formed on the substrate via a gate insulating film;
A gate sidewall insulating film provided on the substrate across the gate electrode;
A source / drain electrode formed on the surface portion of the substrate across the channel region under the gate electrode and made of an alloy of a semiconductor and a metal constituting the substrate;
A contact plug in contact with the source / drain electrode;
Comprising
The source / drain electrodes are formed to have a greater film thickness in a lower region opposite to the channel of the gate sidewall insulating film than in a region under the gate sidewall insulating film. Effect type semiconductor device. A semiconductor substrate;
A gate electrode formed on the substrate via a gate insulating film;
A source / drain electrode formed on the surface of the substrate across the channel region under the gate electrode, and made of an alloy of a semiconductor and a metal constituting the substrate;
A contact plug in contact with the source / drain electrode;
Comprising
2. The field effect semiconductor device according to claim 1, wherein the source / drain electrode is formed thicker in a region outside the region than the region near the gate electrode. The channel region includes In _x Ga _1-x As (0 <x <1), InP, In _x Ga _1-x Sb (0 <x <1), and Si _x Ge _1-x (0 <x <1). The field effect semiconductor device according to claim 1, wherein the field effect semiconductor device is formed of any one of the above.   5. The field effect semiconductor device according to claim 4, wherein the source / drain electrode is an alloy of any one of Ni, Co, and Pt and a semiconductor constituting the substrate. Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a first source / drain electrode made of an alloy of a semiconductor and a metal of the substrate on a surface portion of the substrate across a channel region under the gate electrode;
Forming an interlayer insulating film so as to cover the gate electrode and the first source / drain electrode;
Forming a contact hole for connecting to the source / drain electrode in the interlayer insulating film;
Forming a second source / drain electrode made of an alloy of a semiconductor and a metal constituting the substrate at the bottom of the contact hole;
Forming a contact plug in contact with the second source / drain electrode in the contact hole;
A method of manufacturing a field effect semiconductor device, comprising: Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a first source / drain electrode made of an alloy of a semiconductor and a metal of the substrate on a surface portion of the substrate across a channel region under the gate electrode;
Forming a gate sidewall insulating film on a side portion of the gate electrode so as to partially overlap the first source / drain electrode;
Below the region opposite to the channel of the gate sidewall insulating film, is made of an alloy of a semiconductor and a metal of the substrate, and the second source / drain is formed deeper in the substrate than the first source / drain electrode. Forming a drain electrode;
Forming an interlayer insulating film so as to cover the gate electrode and the first and second source / drain electrodes;
Forming a contact hole for connecting to the second source / drain electrode in the interlayer insulating film;
Forming a contact plug in contact with the second source / drain electrode in the contact hole;
A method of manufacturing a field effect semiconductor device, comprising: Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a gate sidewall insulating film on a side of the gate electrode;
Forming a first source / drain electrode made of an alloy of a semiconductor and a metal of the substrate on a surface portion of the substrate across the gate electrode and the gate sidewall insulating film;
Removing the gate sidewall insulating film after forming the first source / drain electrodes;
The surface of the substrate exposed by the removal of the gate sidewall insulating film is made of an alloy of a semiconductor and a metal of the substrate, and the second source reaches a shallower position in the substrate than the first source / drain electrode. A step of forming a drain electrode;
Forming an interlayer insulating film so as to cover the gate electrode and the first and second source / drain electrodes;
Forming a contact hole for connecting to the first source / drain electrode in the interlayer insulating film;
Forming a contact plug in contact with the first source / drain electrode in the contact hole;
A method of manufacturing a field effect semiconductor device, comprising:

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