JP2014204276A - Pipelined AD converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pipelined AD converter that implements a low power consumption while maintaining a high SN ratio.SOLUTION: The pipelined AD converter includes: a plurality of residual operation stages 31 connected in a cascade; a final stage sub AD converter 12; a digital synthesis circuit 13 for synthesizing AD conversion signals Dsub output from sub AD conversion circuit sections 14 disposed individually in the plurality of residual operation stages and the sub AD converter, respectively; and first operational amplifiers 32 for supplying a high level reference voltage to and second operational amplifiers 33 for supplying a low level reference voltage to residual operation circuit sections comprising switched capacitor circuits disposed individually in the plurality of residual operation stages. The first operational amplifiers 32 are configured to vary the capability of driving an output current on the basis of a total capacitance value of input capacitive elements Cs supplied with the high level reference voltage, and the second operational amplifiers 33 are configured to vary the capability of driving an output current on the basis of a total capacitance value of input capacitive elements Cs supplied with the low level reference voltage.

Description

  The present invention relates to a touch panel controller mounted on, for example, a smartphone, a tablet terminal, an electronic blackboard, a car navigation device, and the like, and an AD converter used in other signal processing systems, and in particular, a pipeline type AD converter. About.

  Currently, touch panel systems are rapidly being installed in various electronic devices such as portable information devices such as smartphones and vending machines such as vending machines. For mobile terminals such as smartphones and tablet terminals, it is essential to reduce the power consumption of components because of the necessity of battery driving.

  The touch panel system uses an AD converter that recognizes touch information on the panel and converts it into a digital signal. Since the AD converter is required to convert it to a digital signal without damaging the information of the original analog signal as much as possible, an AD converter having a high S / N ratio is required.

  In order to achieve a higher signal-to-noise ratio, it is necessary to satisfy the two requirements of higher resolution (number of bits) and lower circuit noise. Further, a high conversion speed is required for the AD converter. This is because the amount of information handled per unit time is increasing with the advancement of the system.

  There is a pipeline type AD converter as a method of the AD converter suitable for such a condition. As shown in the block diagram of FIG. 1, the general pipelined AD converter 10 includes a plurality of cascaded residual calculation stages 11, a final stage sub AD converter 12, and a digital synthesis circuit 13. It is prepared for.

  The residual calculation operation in each residual calculation stage 11 is generally realized using a switched capacitor circuit. FIG. 2 shows a basic circuit configuration of the residual calculation stage 11, and FIG. 3 shows an example of a circuit configuration using a switched capacitor circuit.

  As shown in FIG. 2, the residual calculation stage 11 includes a sub AD conversion circuit unit 14, a sub DA conversion circuit unit 15, a subtracter 16, and a residual amplifier 17. Further, the sub DA conversion circuit unit 15, the subtractor 16, and the residual amplifier 17, specifically, as shown in FIG. 3, the sub DA conversion circuit unit 15 and the subtracter 16, are a multiplexer 18, a capacitive element. Cf, a plurality of input capacitance elements Cs, a plurality of switches S0, a plurality of switches S1, a switch S2, and a switch S3 are used, and the residual amplifier 17 is formed using an operational amplifier 19. Further, the multiplexer 18 is supplied with a high level reference voltage VHref and a low level reference voltage VLref as reference voltages from the outside, and according to the AD conversion value Dsub of the sub AD conversion circuit unit 14 for each input capacitance element Cs. The high level reference voltage VHref and the low level reference voltage VLref are selected and supplied.

  As shown in FIG. 3, the high level reference voltage VHref and the low level reference voltage VLref are normally supplied using voltage follower type operational amplifiers 20 and 21 for voltage stabilization.

In FIG. 3, for ease of explanation, the case where the digital output Dsub of the sub A / D conversion circuit unit 14 is 2 bits is illustrated, and the number of the input capacitance element Cs and the switch S1 is three. . When the digital output is M bits, the number of input capacitance elements Cs and switches S1 is (2 ^M −1) when the capacitances of the input capacitance elements Cs are the same.

  Each of the switches S0 to S3 is controlled to be turned on / off in synchronization with a clock signal (not shown). The residual calculation stage 11 repeats sampling and holding by switching on and off each of the switches S0 to S3 according to the synchronization signal. An example of the residual calculation of the residual calculation stage 11 will be described with reference to FIG.

  First, in the sampling period, the switches S0 and S2 are turned on (short-circuited), the switches S1 and S3 are turned off (opened), and the analog input voltage VIN is charged to the capacitive element Cf and the plurality of input capacitive elements Cs. . In parallel with the charging, the sub AD conversion circuit unit 14 converts the analog input voltage VIN into a digital value. The circuit state during the sampling period is simply shown in FIG.

  The conversion from the analog input voltage VIN to the digital value by the sub A / D conversion circuit unit 14 is mainly realized by comparing the divided values of the high level reference voltage VHref and the low level reference voltage VLref by the three comparators 22. Is done.

  Since the non-inverting input terminal of the operational amplifier 19 is grounded, the inverting input terminal becomes an imaginary short in the sampling period, and is considered to be substantially in the ground state. Accordingly, the amount of charge Qs charged in the capacitive element Cf and the plurality of input capacitive elements Cs is given by the following equation (1). The capacitances of the capacitive elements Cf and Cs are Cf and Cs, respectively.

(Equation 1)
Qs = VIN × (3 × Cs + Cf)

  Next, in the hold period, when the switches S0 and S2 are turned off and the switches S1 and S3 are turned on, the charge amount of the capacitive element Cf is given by the following formula 2, and the output voltage VOUT of the operational amplifier 19 is The residual amount is calculated by Equation 3 and output as an analog input voltage of the next stage residual calculation stage 11 or the final stage sub-AD converter 12. However, Vref1 to Vref3 in Equation 2 are the high-level reference voltage VHref and the low-level reference voltage VLref that are selected according to the decoded value (0 to 3) of the output digital value (2 bits) of the sub AD conversion circuit unit 14. Any one of these is expressed, and in Formula 3, it is assumed that Cf = Cs. The circuit state during the hold period is simply shown in FIG.

(Equation 2)
Cf * VOUT = Cf * VIN- {Cs * (Vref1-VIN)
+ Cs × (Vref2−VIN) + Cs × (Vref3−VIN)}

(Equation 3)
VOUT = 4VIN− (Vref1 + Vref2 + Vref3)

  As an example, as shown in FIG. 6, when the high level reference voltage VHref is 1V, the low level reference voltage VLref is −1V, and the analog input voltage VIN is 0.6V, the output digital value (2 Bit) is “11” (decode value is 3), and the residual value VOUT calculated based on Equation 3 is 0.4V. In this case, the decode value is 3, and Vref1 to Vref3 are all VHref (1 V).

  The high level reference voltage VHref and the low level reference voltage VLref for charging the three input capacitance elements Cs during the hold period are supplied using the operational amplifiers 20 and 21.

  A pipelined AD converter is a cascade connection of the above-described residual calculation stages, and a sub-AD converter at the final stage is connected to the subsequent stage so that a digital signal having a desired number of bits can be output to an analog input. Generate.

  In a pipelined AD converter having a general configuration, there is a trade-off between power and S / N ratio. The same relationship applies to general AD converters other than pipeline AD converters.

  In order to solve such a problem, in Patent Document 1 below, in accordance with a required signal-to-noise ratio, a resolution variable with a variable resolution for analog-to-digital conversion of an analog input signal to a digital signal is applied to the residual calculation stage. An AD converter, a resolution variable DA converter that converts an output digital signal of the variable resolution AD converter into an analog signal, and a difference calculation result of the analog input signal and the analog signal output from the resolution variable DA converter is predetermined. Providing an operational amplifier with a variable gain that can be amplified with a large gain allows the power to be set to an optimum value according to the required S / N ratio, and it is proposed to reduce the power when viewed on a time average basis. ing.

JP 2010-166447 A

  As described above, the pipelined AD converter converts the analog input signal into a high-resolution digital signal while the cascaded residual calculation stages repeat sampling and holding in synchronization with the synchronization signal input to the AD converter. In the conversion system, when each residual calculation stage is held, the input capacitance element is charged using the high level reference voltage VHref and the low level reference voltage VLref. As shown in FIG. 5, the reference voltages VHref and VLref are generally supplied using voltage follower type operational amplifiers for voltage stabilization.

  Either the high-level reference voltage VHref or the low-level reference voltage VLref is used for charging the input capacitance element at the time of holding. The operational amplifier of each reference voltage is designed on the assumption that all of the input capacitance elements can be charged at each hold, so that the bias current becomes excessive on average and wasteful power consumption occurs.

  For example, in the case of the residual calculation stage shown in FIG. 3, the bias current is set so that a maximum of three input capacitance elements Cs can be charged.

  Since the AD converter used in the above-described mobile terminal is required to reduce power consumption, it is necessary to reduce power consumption by optimizing the bias current of the operational amplifier.

  However, in Patent Document 1, it is not considered that the capacitive load charged by the operational amplifier changes during operation. Regarding the surplus of the bias current of the operational amplifier for charging the input capacitive element Cs as described above, It is not considered at all.

  The present invention has been made in view of the above problems, and an object thereof is to provide a pipeline AD converter capable of reducing power consumption while maintaining a high SN ratio.

In order to achieve the above object, the present invention provides a plurality of cascaded residual calculation stages, a sub A / D converter connected to a subsequent stage of the plurality of residual calculation stages, and a plurality of residual calculation stages. Digital synthesizing circuit for synthesizing AD conversion signals output from each of the provided sub A / D conversion circuit unit and the sub A / D converter, and a switched capacitor circuit provided separately in each of the plurality of residual calculation stages A first operational amplifier that supplies a high-level reference voltage and a second operational amplifier that supplies a low-level reference voltage to a residual calculation circuit unit configured using
In each of the plurality of residual calculation stages, the residual calculation circuit unit inputs an analog input voltage input to the residual calculation stage, the AD conversion signal output from the sub AD conversion circuit unit, and the first Based on the high level reference voltage and the low level reference voltage supplied from the first and second operational amplifiers, respectively, a plurality of input capacitance elements of the switched capacitor circuit are charged and discharged, thereby obtaining a residual after AD conversion. A value is derived and configured to be output to an analog input terminal of the next stage of the residual calculation stage or the sub AD converter;
The first operational amplifier is configured to vary output current drive capability based on the total capacitance value of the input capacitive element that supplies the high-level reference voltage, and the second operational amplifier supplies the low-level reference voltage. A pipeline type AD converter is provided, wherein the output current drive capability is variable based on the total capacitance value of the input capacitance elements.

  Furthermore, it is preferable that the pipeline type AD converter having the above-described characteristics is configured such that the first and second operational amplifiers can change the driving capability by adjusting a bias current.

  Furthermore, in the pipeline type AD converter having the above characteristics, it is preferable that the first and second operational amplifiers are configured such that the bias current can be adjusted by switching the parallelism of the bias circuits.

  Further, in the pipeline type AD converter having the above characteristics, it is preferable that the adjustment of the bias current is executed at a timing of a half cycle of the synchronization signal used for the residual calculation process and a multiple thereof.

  Further, in the pipeline type AD converter having the above characteristics, the first and second operational amplifiers are paired with respect to all of the plurality of residual calculation stages, or each of the plurality of residual calculation stages or a group. It is preferable that one pair is provided for each.

  According to the pipeline type AD converter having the above characteristics, a high-level reference voltage or a low-level reference voltage is applied to each of the plurality of input capacitance elements of the switched capacitor circuit constituting the residual arithmetic circuit unit of each residual arithmetic stage. The first and second operational amplifiers for supplying the output current are configured so that the drive capability of the output current is variable based on the total capacitance value of the input capacitive element to which the corresponding reference voltage is supplied. Since the bias current for determining the first and second operational amplifiers is not set to an excessively fixed value, the power consumption of the first and second operational amplifiers can be reduced. Can be achieved.

Block diagram showing a circuit configuration example of a general pipeline AD converter Circuit diagram showing basic circuit configuration of residual calculation stage of pipelined AD converter Circuit diagram showing an example of a circuit configuration using a switched capacitor circuit of a residual calculation stage of a pipelined AD converter The figure which shows simply the circuit state during the sampling period of the residual calculation stage shown in FIG. The figure which shows simply the circuit state during the holding period of the residual calculation stage shown in FIG. Explanatory drawing explaining an example of the residual calculation of the residual calculation stage shown in FIG. The block diagram which shows the circuit structural example in 1st Embodiment of the pipeline type AD converter which concerns on this invention. FIG. 7 is a circuit diagram showing a circuit configuration example of a residual calculation stage used in the pipeline type AD converter shown in FIG. FIG. 8 is a circuit diagram showing a circuit configuration example of the first and second operational amplifiers used in the residual calculation stage shown in FIG. FIG. 8 is a diagram showing a list of reference voltages supplied to each input capacitive element and total loads of the first and second operational amplifiers according to decode values in the residual calculation process of the residual calculation stage shown in FIG. The block diagram which shows the circuit structural example in 2nd Embodiment of the pipeline type AD converter which concerns on this invention. FIG. 11 is a circuit diagram showing a circuit configuration example of first and second operational amplifiers used in the pipeline type AD converter shown in FIG.

  Hereinafter, embodiments of a pipelined AD converter according to the present invention (hereinafter, appropriately referred to as “the device of the present invention”) will be described with reference to the drawings. In order to facilitate understanding of the description, the same components as those in the general pipeline AD converter shown in FIGS. 1 to 3 will be described with the same reference numerals.

<First Embodiment>
FIG. 7 shows a block configuration in the first embodiment of the apparatus of the present invention. The basic circuit configuration is similar to the circuit configuration of the general pipelined AD converter shown in FIG. 1, and the device 30 of the present invention includes a residual calculation stage 31 and a final stage sub-AD connected in cascade. A converter 12 and a digital synthesis circuit 13 are provided. The AD conversion signal Dsub AD-converted by each residual calculation stage 31 and the sub AD converter 12 is combined by the digital combining circuit 13 and corresponds to the analog input voltage VIN input to the first residual calculation stage 31. The AD conversion signal Dout of the device 30 is output. The residual value calculated by the residual calculation stage 31 of each stage becomes the analog input voltage VIN of the next stage.

  FIG. 8 shows a circuit configuration example of the residual calculation stage 31 using the switched capacitor circuit used in the present embodiment. Similar to the conventional residual calculation stage 11 shown in FIG. 3, the residual calculation stage 31 includes a sub A / D conversion circuit unit 14, a multiplexer 18, an operational amplifier 19, a capacitive element Cf, three input capacitive elements Cs, and four switches. S0, three switches S1, switch S2, and switch S3, and further includes a first operational amplifier 32 for supplying a high-level reference voltage VHref to each input capacitance element Cs and a plurality of low-level reference voltages VLref. A second operational amplifier 33 for supplying to the element Cs is provided. The multiplexer 18, the operational amplifier 19, the capacitive element Cf, the three input capacitive elements Cs, the four switches S0, the three switches S1, the switch S2, and the switch S3 constitute a residual calculation circuit unit.

  Similar to the residual calculation stage 11 shown in FIG. 3, the residual calculation stage 31 switches on / off of the switches S0 to S3 in synchronization with the clock signal, and repeats sampling and holding, thereby performing the residual calculation stage. 31, an analog input voltage VIN input to the sub AD converter circuit section 14, an AD conversion signal Dsub output from the sub AD converter circuit 14, and a high level reference voltage VHref 1 and a low level reference voltage supplied from the first and second operational amplifiers 32 and 33, respectively. Based on VLref1 (the same voltage as the high-level reference voltage VHref and the low-level reference voltage VLref, respectively), the residual element calculation process is executed by charging and discharging the capacitive element Cf and the plurality of input capacitive elements Cs.

  Since the residual calculation stage 31 is the same in circuit configuration and residual calculation processing method except for the residual calculation stage 11 shown in FIG. 3 and the first and second operational amplifiers 32 and 33, overlapping description will be omitted. Omitted.

  FIG. 9 shows a circuit configuration example of the first and second operational amplifiers 32 and 33. The circuit configurations of the first and second operational amplifiers 32 and 33 are basically the same circuit configuration. Hereinafter, the first operational amplifier 32 will be described as an example. The first operational amplifier 32 includes a bias current variable unit 34, a bias current control unit 35, a differential amplification unit 36, and an output buffer unit 37. Although not shown, the high level reference voltage VHref is input to the non-inverting input of the differential amplifier 36, and the high level reference voltage VHref1 output from the output buffer unit 37 is input to the inverting input of the differential amplifier 36. input. The differential amplifying unit 36 and the output buffer unit 37 can be realized by using a well-known circuit configuration, and are not limited to the circuit configuration shown in FIG. 9, and other circuit configurations may be adopted. Note that the gate voltages Vg1 to Vg5 of the MOS transistors constituting the differential amplifier 36 are respectively supplied from a bias generation circuit (not shown).

  The bias current varying unit 34 includes four P-type MOS transistors QB0 to QB3, switches SB0 to SB3 having different gate widths, and an N-type MOS transistor Q0. The sources of the P-type MOS transistors QB0 to QB3 are connected to the high-potential power supply voltage, the drains are connected to one ends of the corresponding switches SB0 to SB3, and the gates are connected to the common bias voltage Vbias. The other ends of the switches SB0 to SB0 are commonly connected to the drain and gate of the N-type MOS transistor Q0, and the source of the N-type MOS transistor Q0 is connected to a low-potential power supply voltage.

  The gate of the N-type MOS transistor Q0 is connected to the gate of the N-type MOS transistor Q3, which is the current source of the two N-type MOS transistors Q1 and Q2 constituting the differential input pair of the differential amplifier 36, and the N-type MOS transistor Q0 is connected. The MOS transistor Q0 and the N-type MOS transistor Q3 form a current mirror circuit, and the bias current adjusted by the bias current variable unit 34 flows through the N-type MOS transistor Q3 of the differential amplifier 36. In the circuit configuration shown in FIG. 9, as the bias current increases, the gate voltages of the P-type MOS transistor Qp and the N-type MOS transistor Qn of the output buffer unit 37 are adjusted to increase the drive capability of the output current with respect to the load. To do.

  The gate widths of the P-type MOS transistors QB0 to QB3 are set to increase in the order of QB0 to QB3, and the current flowing through the P-type MOS transistor is set to increase in the order of QB0 to QB3. On / off of the switches SB0 to SB3 is controlled by the bias current control unit 35.

  The bias current control unit 35 receives the 2-bit AD conversion signal Dsub output from the sub A / D conversion circuit unit 14, and one of the switches SB0 to SB3 according to the decoded value (0 to 3). Is turned on, and the remaining three are controlled to be turned off. Specifically, when the decode value is i (i = 0 to 3), the switch SBi is turned on.

  Similar to the residual calculation of the conventional residual calculation stage 11 described above, the first and second input capacitance elements Cs are held in the first and second input capacitance elements Cs at the time of holding according to the decode value (0 to 3) of the AD conversion signal Dsub. Either the high level reference voltage VHref1 or the low level reference voltage VLref1 output from the second operational amplifiers 32 and 33 is supplied. When the decode value is i (i = 0 to 3), the high level reference voltage VHref1 is supplied to the i input capacitance elements Cs, and the low level reference voltage VLref1 is supplied to the (3-i) input capacitance elements Cs. The three input capacitance elements Cs are charged.

  Here, as the decode value i increases, the number of input capacitive elements Cs that supply the high-level reference voltage VHref1 increases and the load of the first operational amplifier 32 increases, and the input capacitive element Cs that supplies the low-level reference voltage VLref1 increases. As the number decreases, the load on the second operational amplifier 33 decreases. With the above configuration, the first operational amplifier 32 increases the bias current according to the size of the load as the decode value i increases, and the drive capability of the load in supplying the high-level reference voltage VHref1 increases. On the other hand, the second operational amplifier 33 has the on / off control of the switch SBi in the bias current variable unit 34 opposite to that of the first operational amplifier 32, and when the decode value is i (i = 0 to 3), the switch SBj (j = 3-i) is turned on. That is, in the second operational amplifier 33, as the decode value i is smaller, the bias current increases according to the magnitude of the load, and the drive capability of the load in supplying the low level reference voltage VLref1 increases.

  The gate widths of the P-type MOS transistors QB0 to QB3 of the operational amplifiers 32 and 33 are set so that the drive capability of the output buffer unit 37 changes in proportion to the size of each load by a bias current determined by the gate width. Are preset.

  Assuming that the high level reference voltage VHref is 1V, the low level reference voltage VLref is -1V, and the analog input voltage VIN is changed in the range of -1V to 1V, -1V ≦ VIN <−0.5V, AD conversion signal The decode value i of Dsub is 0, −0.5V ≦ VIN <0V, the decode value i is 1, 0V ≦ VIN <0.5V, the decode value i is 2, and 0.5V ≦ VIN ≦ 1V. The decode value i is 3. FIG. 10 shows reference voltages (referred to as Cs1 to Cs3 for convenience) supplied to the three input capacitance elements Cs by the operation of the multiplexer 18 at the time of holding at each decode value i under the assumption. The high level reference voltage VHref1 or the low level reference voltage VLref1) and the total load of each of the first and second operational amplifiers 32 and 33 are displayed as a list.

  Note that the circuit configuration of the second operational amplifier 33 is different from the first operational amplifier 32 only in the on / off control of the switch SBi (i = 0 to 3) and the voltage of the reference voltage output from the output buffer unit 37. Since the basic circuit configuration is the same, redundant description is omitted. In addition, the bias current control unit 35 of the first operational amplifier 32 and the bias current control unit 35 of the second operational amplifier 33 may share one bias current control unit 35. In this case, the signal for controlling on / off of the switch SBi (i = 0 to 3) of the first operational amplifier 32 simultaneously controls on / off of the switch SBj (j = 3-i) of the second operational amplifier 33.

  By using the residual calculation stage 31 including the first and second operational amplifiers 32 and 33, the high level reference voltage VHref1 and the low level reference voltage VLref1 are supplied to the input capacitance element Cs at the time of holding. The bias current of each operational amplifier 32, 33 is optimized. In addition, since the drive capability of the operational amplifiers 32 and 33 is adjusted according to the size of the load, charging of each reference voltage to the input capacitance element Cs is not performed by adjusting the bias current and the residual calculation stage 11. The operational amplifiers 32 and 33 can be reduced in power consumption without affecting the residual calculation process.

Second Embodiment
In the first embodiment, the circuit configuration including the first and second operational amplifiers 32 and 33 for each residual calculation stage 31 has been described. However, in the second embodiment, a plurality of first and second operational amplifiers 32 and 33 are provided. Used in common in the residual calculation stage 31.

  FIG. 11 shows an example of a block configuration in the second embodiment of the device of the present invention. In the device 40 of the present invention shown in FIG. 11, it is assumed that a pair of first and second operational amplifiers 42 and 43 are used in common in all residual calculation stages 41, but all residual calculation stages 41 are used. May be divided into two or more groups, and one pair of first and second operational amplifiers 42 and 43 may be provided in each group.

  The residual calculation stage 41 used in the second embodiment is different from the residual calculation stage 31 used in the first embodiment in that the first and second operational amplifiers 32 and 33 are not individually provided. Other than that, the circuit configuration is the same as in the circuit configuration shown in FIG. 8, and the sub AD conversion circuit unit 14, the multiplexer 18, the operational amplifier 19, the capacitive element Cf, the three input capacitive elements Cs, the four switches S0, A switch S1, a switch S2, and a switch S3 are provided. The circuit elements and the circuit operation of the residual calculation stage 41 are the same as those of the residual calculation stage 31, and a duplicate description is omitted.

  As shown in FIG. 11, in the second embodiment, the high-level reference voltage VHref1 and the low-level reference voltage VLref1 output from the first and second operational amplifiers 42 and 43 are respectively connected to the odd-numbered stages via the switch SW1. It is input to the residual calculation stage 41 and input to each of the even number of residual calculation stages 41 via the switch SW2.

  During the sampling period of each odd-numbered residual calculation stage 41, the even-numbered residual calculation stage 41 becomes a hold period, and conversely, during the sampling period of each of the even-numbered residual calculation stages 41, Each residual calculation stage 41 is a hold period. Accordingly, the switch SW1 is controlled so as to be in the on state during the hold period of each of the odd-numbered residual calculation stages 41 and to be in the off state during the sampling period. On the other hand, the switch SW2 is controlled so as to be turned on during the hold period of each of the even-numbered residual calculation stages 41 and to be turned off during the sampling period. The on / off control of the switches SW1 and SW2 is controlled so that the on / off state is switched every half cycle of the clock cycle input to the device of the present invention or every multiple thereof.

  The first and second operational amplifiers 42 and 43 used in the second embodiment are driven by the total sum of the capacitances of the input capacitance elements Cs of the odd-numbered or even-numbered residual calculation stages 41 to be charged at the time of holding, respectively. This is the maximum capacity load to be performed. When the number of odd-numbered stages and even-numbered stages excluding the final stage (final stage sub-AD converter 12) is different, the total of the capacitances of the input capacitive element Cs having the larger number of stages is the capacity to be driven. The maximum load value.

  In the second embodiment, the first and second operational amplifiers 42 and 43 have a larger load maximum value driven by one operational amplifier 42 and 43 than the first embodiment. Therefore, at least the size of each transistor of the output buffer unit 47 is made larger than the circuit configuration of the first and second operational amplifiers 32 and 33 used in the first embodiment shown in FIG. It needs to be bigger. For this reason, as shown in FIG. 12, the parallel number m of the P-type MOS transistors QB0 to QBm-1 and the switches SB0 to SBm-1 constituting the bias current variable unit 44 is an odd number from 4 in the first embodiment. And it is increased according to the number of stages of even stages. For example, when the number of stages is 3, the maximum number of input capacitive elements Cs that are charged at one hold is 9, so that the parallel number is 10 and the bias current can be adjusted in 1 to 10 stages. Is preferred. Therefore, in the first embodiment, in the case of the same number of stages, the odd number of residual calculation stages 31 are used, and the parallel number of the three pairs of the first and second operational amplifiers 32 and 33 is 3 to 12 stages. Compared with the adjustment, the power consumption can be further reduced on average.

  In the first and second operational amplifiers 42 and 43 of the second embodiment, the bias current control unit 45 is similar to the bias current control unit 35 of the first embodiment, and the residual of the odd-numbered stage or even-numbered stage to be held. The AD conversion signal Dsub output from each sub AD conversion circuit unit 14 of the operation stage 41 may be input separately via a switch controlled in the same manner as the switches SW1 and SW2, as shown in FIG. As described above, the AD conversion signals DOsub and DEsub obtained by synthesizing the AD conversion signals Dsub output from the sub AD conversion circuit units 14 of the odd-numbered or even-numbered residual calculation stages 41 to be held through the digital combining circuit 13. It is good also as a structure which inputs.

<Another embodiment>
Hereinafter, another embodiment of the circuit of the present invention will be described.

  In each of the above embodiments, an example of a preferred embodiment of the circuit of the present invention has been described in detail. The circuit configuration of the circuit of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the present invention.

  For example, the circuit configuration of the switched capacitor circuit constituting the residual calculation stages 31 and 41 is not limited to the circuit configuration illustrated in FIG. Further, the number of bits of the AD conversion signal Dsub output from the sub AD conversion circuit unit 14 is not limited to two. As another circuit configuration of the switched capacitor circuit, for example, the circuit configuration disclosed in Patent Document 1 and a modified configuration thereof can be used. Furthermore, the number of the capacitive element Cf, the input capacitive element Cs, and the switches S0 to S3 used in the switched capacitor circuit can be appropriately changed according to the circuit configuration to be employed. Further, the capacitances of the plurality of input capacitance elements Cs are not the same as each other, and the input capacitance elements Cs weighted by a power of 2 may be used to suppress the number of use.

  Furthermore, the circuit configurations of the first operational amplifiers 32 and 42 and the second operational amplifiers 33 and 43 are not limited to the circuit configuration shown in FIG. However, the configurations of the differential amplifiers 36 and 46 and the output buffer units 37 and 47 need to be circuit configurations capable of adjusting the drive capability of the load by changing the bias current.

  In the first and second embodiments, the P-type MOS transistors QB0 to QB3 and QB0 to QBm-1 of the bias current variable units 34 and 44 of the first operational amplifiers 32 and 42 and the second operational amplifiers 33 and 43 are gates. The width is different, and one of a plurality of parallel P-type MOS transistors is selected so as to have a driving capability according to the size of the load that supplies the reference voltage. The same bias current may be adjusted by changing the combination of the number of parallel P-type MOS transistors selected in parallel (the degree of parallelism) and the selected gate width.

  Further, the bias currents of the first operational amplifiers 32 and 42 and the second operational amplifiers 33 and 43 are not adjusted by selection of the P-type MOS transistors QB0 to QB3 and QB0 to QBm-1 of the bias current variable units 34 and 44, The bias current flowing through the N-type MOS transistor Q3 can be adjusted by configuring the P-type MOS transistor as one and changing the current mirror ratio of the current mirror circuit formed by the N-type MOS transistors Q0 and Q3. You may make it do. In this case, the N-type MOS transistor Q3 is turned on / off by connecting a series circuit of the switches SB0-SB3, SB0-SBm-1 in parallel like the P-type MOS transistors QB0-QB3, QB0-QBm-1. Thus, the current mirror ratio may be adjusted.

  The pipeline type AD converter according to the present invention is used for a touch panel controller mounted on a smart phone, a tablet terminal, an electronic blackboard, a car navigation device, etc., and an AD converter used for other signal processing systems. Can do.

10: Conventional pipelined AD converter 11, 31, 41: Residual calculation stage 12: Sub AD converter in the final stage 13: Digital synthesis circuit 14: Sub AD conversion circuit unit 15: Sub DA conversion circuit unit 16: Subtractor 17: Residual amplifier 18: Multiplexer 19-21: Operational amplifier 22: Comparator 30, 40: Pipeline type AD converter 32, 42 according to the present invention: First operational amplifier 33, 43: Second operational amplifier 34, 44 : Bias current variable section 35, 45: Bias current control section 36, 46: Differential amplification section 37, 47: Output buffer section Cf: Capacitance element Cs: Input capacitance element DEsub: AD conversion signal of even-numbered residual calculation stage (After synthesis)
DOsub: AD conversion signal of odd-numbered residual calculation stage (after synthesis)
Dout: AD conversion signal (after synthesis)
Dsub: AD conversion signal QB0-QB3, QBm-1: P-type MOS transistor for bias current adjustment Qp: P-type MOS transistor Q0-Q3, Qn: N-type MOS transistor S0-S3: Switch SB0-SB3, SBm-1 : Bias current adjustment switch SW1, SW2: Switch Vbias: Bias voltage Vg1-Vg5: Gate voltage VHref: High level reference voltage VHref1: High level reference voltage (after buffering)
VIN: Analog input voltage VLref: Low level reference voltage VLref1: Low level reference voltage (after buffering)
VOUT: Output voltage (residual amount)

Claims (5)

Cascaded multiple residual computation stages,
A sub A / D converter connected to a subsequent stage of the plurality of residual calculation stages;
A digital synthesizing circuit that synthesizes AD conversion signals output from each of the sub AD conversion circuit unit and the sub AD converter provided separately in each of the plurality of residual calculation stages; and
A first operational amplifier that supplies a high-level reference voltage and a first operational amplifier that supplies a low-level reference voltage to a residual calculation circuit unit that is configured using a switched capacitor circuit provided separately in each of the plurality of residual calculation stages. 2 operational amplifiers,
In each of the plurality of residual calculation stages, the residual calculation circuit unit inputs an analog input voltage input to the residual calculation stage, the AD conversion signal output from the sub AD conversion circuit unit, and the first Based on the high level reference voltage and the low level reference voltage supplied from the first and second operational amplifiers, respectively, a plurality of input capacitance elements of the switched capacitor circuit are charged and discharged, thereby obtaining a residual after AD conversion. A value is derived and configured to be output to an analog input terminal of the next stage of the residual calculation stage or the sub AD converter;
The first operational amplifier is configured to be variable in output current drive capability based on a total capacitance value of the input capacitive element that supplies the high-level reference voltage.
The pipeline type AD converter, wherein the second operational amplifier is configured so that a drive capability of an output current is variable based on a total capacitance value of the input capacitance element that supplies the low-level reference voltage.   2. The pipelined AD converter according to claim 1, wherein each of the first operational amplifier and the second operational amplifier is configured to be able to change the driving capability by adjusting a bias current. 3.   3. The pipelined AD converter according to claim 2, wherein each of the first and second operational amplifiers is configured to be capable of adjusting the bias current by switching a parallel degree of a bias circuit. 4.   4. The pipeline type AD converter according to claim 2, wherein the adjustment of the bias current is executed at a timing of a half cycle of a synchronization signal used for residual calculation processing and a multiple thereof. The first and second operational amplifiers are provided in one pair for all of the plurality of residual calculation stages, or one pair for each of the plurality of residual calculation stages or for each group. The pipeline type AD converter according to any one of claims 1 to 4, wherein

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