JP2014200028A - Communication device, communication method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a possibility that a buffer to store data received from an asynchronous communication network and transmitted to a synchronous communication network over-flows or under-flows.SOLUTION: A communication device includes: a storage unit that stores data received from a second communication network by communication asynchronous with communication in a first communication network; a transmission unit that reads out the data stored by the storage unit according to a clock signal and transmits it to the first communication network; a first changing unit that changes the frequency of the clock signal within a prescribed range depending on the amount of data stored in the storage unit; a measuring unit that measures the degree of fluctuation of reception intervals of data from the second communication network; and a second changing unit that changes the amount of data allowed to be stored in the storage unit on the basis of the measurement result of the degree of fluctuation.

Description

  The present invention relates to a communication device, a communication method, and a program.

  A device (hereinafter referred to as an “IP converter”) that enables an asynchronous communication network such as an IP network that cannot transmit the clock signal between synchronous communication networks that synchronize communication by transmitting a clock signal. ) Exists.

  For example, one IP converter is installed between one synchronous communication network and an asynchronous communication network, and one IP converter is installed between the other synchronous communication network and the asynchronous communication network. For example, IP packets are transmitted between IP converters via an asynchronous communication network.

  When IP packets are transmitted, even if the transmission side transmits IP packets at regular intervals, the reception side may not always receive IP packets at regular intervals, and there may be fluctuations in the arrival intervals of IP packets. Yes. The IP converter is provided with a reception buffer so that synchronous communication to the synchronous communication network is not interrupted even if such fluctuations occur. The IP converter on the receiving side uses the frequency of the clock signal for reading data from the reception buffer (hereinafter referred to as “buffer data amount”) so that the amount of data in the reception buffer (hereinafter referred to as “buffer data amount”) is stabilized at a predetermined value. “Clock frequency”). Specifically, the IP converter increases the clock frequency when the buffer data amount increases from a predetermined value, and decreases the clock frequency when the buffer data amount decreases from the predetermined value. As a result, one synchronous communication network and the other synchronous communication network can be artificially synchronized. The predetermined value is, for example, a value half the size of the reception buffer (hereinafter referred to as “center value”).

JP 2008-199159 A JP 2002-9821 A International Publication No. 2002/032083

  However, the clock frequency needs to be within an allowable range of a device that performs synchronous communication with the IP converter. That is, there is a limit to the fluctuation range of the clock frequency. Therefore, depending on the degree of fluctuation of the packet arrival interval, it may be difficult to avoid overflow or underflow of the reception buffer only by adjusting the clock frequency.

  Therefore, an object of one aspect is to reduce the possibility that a buffer for storing data received from an asynchronous communication network and transmitted to the synchronous communication network will overflow or underflow.

  In one plan, the communication device stores a data received from the second communication network by communication asynchronous to the communication in the first communication network, and the data stored by the storage unit, A transmitter that reads out according to a clock signal and transmits it to the first communication network, and a first unit that changes a frequency of the clock signal within a predetermined range according to a data amount of data stored in the storage unit. A change unit, a measurement unit that measures the degree of fluctuation in the reception interval of data from the second communication network, and the amount of data that is allowed to be stored in the storage unit based on the measurement result of the degree of fluctuation A second changing unit to be changed.

  According to one aspect, it is possible to reduce the possibility that a buffer for storing data received from an asynchronous communication network and transmitted to the synchronous communication network will overflow or underflow.

It is a figure which shows the structural example of the communication system in embodiment of this invention. It is a figure which shows the structural example of the hardware of the IP converter in embodiment of this invention. It is a figure which shows the function structural example of the IP converter in 1st embodiment. It is a flowchart for demonstrating an example of the process sequence of the adjustment process of the clock frequency which the IP converter of the receiving side performs. It is a flowchart for demonstrating an example of the process sequence of the change process of the buffer size in 1st embodiment. It is a figure which shows the function structural example of the IP converter in 2nd Embodiment. It is a flowchart for demonstrating an example of the process sequence of the change process of the buffer size in 2nd embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a configuration example of a communication system according to an embodiment of the present invention. In FIG. 1, legacy devices 10-1 and 10-2 (hereinafter referred to as “legacy device 10” when they are not distinguished from each other) are connected via a synchronous communication network 11-1 or 11-2 constructed with, for example, an optical fiber. Synchronously communicate data. In the present embodiment, synchronous communication refers to communication in which data transmission or reception is synchronized between a data transmission side and a reception side, for example, by a clock signal. However, synchronization may be achieved by means other than the clock signal. As an example of the legacy device 10, voice, 2 Mbps MUX, ITU-T recommendation V. 24, X21, and other devices that perform data communication.

  In FIG. 1, an asynchronous communication network 15 including an IP (Internet Protocol) network 18 is interposed between the synchronous communication networks 11-1 and 11-2. In the present embodiment, asynchronous communication refers to communication asynchronous to the synchronous communication network 11-1 or 11-2. As an example of asynchronous communication, communication such as IP that cannot transmit a clock signal for synchronization used in the synchronous communication network 11-1 or 11-2 or that is not synchronized based on the clock signal can be given. . Note that a communication protocol other than IP may be used in the asynchronous communication network 15.

  An IP conversion device 12-1 is installed between the synchronous communication network 11-1 and the asynchronous communication network 15, and an IP conversion device 12 is provided between the synchronous communication network 11-2 and the asynchronous communication network 15. -2 is installed. The IP conversion apparatuses 12-1 and 12-2 (hereinafter referred to as “IP conversion apparatus 12” when they are not distinguished from each other) execute processing for mediating communication between the legacy devices 10 via the IP network 18. Device.

  Specifically, each IP conversion device 12 sends a legacy network 14-1 or 14-2 to each legacy device 10 of the synchronous communication network 11-1 or 11-2 (hereinafter referred to as “legacy network 14 "). Further, each IP conversion device 12 is connected via the IP network 18 so as to be communicable with the corresponding IP conversion device 12. Each IP conversion device 12 is set with a unique IP address.

  In the present embodiment, it is assumed that the legacy device 10-1 is a data transmission side and the legacy device 10-2 is a data reception side. Therefore, the IP conversion apparatus 12-1 receives the data transmitted from the legacy device 10-1 via the legacy network 14-1. The IP conversion device 12-1 converts the received data into an IP packet format and transmits the data to the IP conversion device 12-2 via the IP network 18. On the other hand, the IP conversion device 12-2 receives an IP packet from the IP network 18. The IP conversion device 12-2 transmits the data included in the received IP packet to the legacy device 10-2 via the legacy network 14-2.

  FIG. 2 is a diagram illustrating a hardware configuration example of the IP conversion apparatus according to the embodiment of the present invention. In FIG. 2, the IP conversion apparatus 12 includes a CPU 36, a RAM 50, a ROM 52, a legacy interface unit 20, an IP interface unit 22, a packet processing unit 24, a variable clock unit 26, and the like that are mutually connected by a bus 48. .

  The ROM 52 stores, for example, a program that causes the IP conversion device 12 to function as each unit shown in FIG. When the IP conversion device 12 is activated, the program stored in the ROM 52 is read into the RAM 50. The program read into the RAM 50 causes the CPU 36 to execute the processing implemented in the program.

  The legacy interface unit 20 is a circuit that receives data from the legacy network 14 or transmits data to the legacy network 14. The IP interface unit 22 is a circuit that receives an IP packet from the IP network 18 or transmits an IP packet to the IP network 18. The packet processing unit 24 is a circuit that performs processing related to transmitted or received IP packets. The variable clock unit 26 is a circuit that generates a clock signal that defines a read cycle of data from the reception buffer 502. The frequency (hereinafter referred to as “clock frequency”) of the clock signal generated by the variable clock unit 26 of the IP converter 12-1 on the data transmission side is fixed to a preset value. The clock frequency of the variable clock unit 26 of the IP converter 12-2 on the data receiving side is the amount of data stored in the reception buffer 502 (hereinafter referred to as “buffer data amount”), for example, the reception buffer 502. Is adjusted to be stable to the median value of the upper limit value Cmax and the lower limit value Cmin (hereinafter referred to as “center value Co”). Specifically, when the buffer data amount exceeds the center value Co, the clock frequency increases, and when the buffer data amount falls below the center value Co, the clock frequency decreases. The upper limit value Cmax is, for example, the capacity of the reception buffer 502. The lower limit value Cmin is 0, for example. Therefore, the center value Co is, for example, a half value of the capacity of the reception buffer 502.

  FIG. 3 is a diagram illustrating a functional configuration example of the IP conversion device according to the first embodiment. In FIG. 3, the same parts as those of FIG. In FIG. 3, the IP conversion apparatus 12 includes a transmission buffer 501 and a reception buffer 502. Each of these buffers can be realized using the RAM 50, for example. The IP converter 12 further includes a packet assembling unit 241, a packet disassembling unit 242, a receiving buffer monitoring unit 461, an excess / deficiency count measuring unit 462, a buffer capacity changing unit 463, and the like. The packet assembling unit 241 and the packet disassembling unit 242 are hardware constituting the packet processing unit 24. The reception buffer monitoring unit 461, the excess / deficiency count measuring unit 462, and the buffer capacity changing unit 463 are realized by processing that the program causes the CPU 46 to execute.

  The transmission buffer 501 stores data transmitted from the legacy device 10 via the legacy network 14 and received by the legacy interface unit 20 (hereinafter, data communicated in the legacy network 14 is referred to as “synchronous communication data”). It is a buffer.

  The packet assembling unit 241 generates an IP packet that stores the data stored in the transmission buffer 501. The IP packet generated by the packet assembly unit 241 is transmitted to the IP network 18 by the IP interface unit 22.

  The packet decomposing unit 242 decomposes the IP packet received by the IP interface unit 22 and extracts data transmitted from the legacy device 10 from the IP packet. The reception buffer 502 stores the data extracted by the packet decomposition unit 242. The data stored in the reception buffer 502 is read by the legacy interface unit 20 and transmitted to the legacy device 10 via the legacy network 14. Data read processing from the reception buffer 502 by the legacy interface unit 20 is synchronized with the frequency of the clock signal generated by the variable clock unit 26.

  The reception buffer monitoring unit 461 monitors whether or not the buffer data amount has reached the upper limit value Cmax, the center value Co, or the lower limit value Cmin of the reception buffer 502, so that the buffer data amount is stabilized at the center value Co. Further, the clock frequency of the variable clock unit 26 is adjusted to the maximum frequency fmax, the minimum frequency fmin, or the reference frequency fo. The maximum frequency fmax is, for example, the upper limit value of the allowable range of the clock frequency of the legacy device 10-2. The minimum frequency fmin is, for example, the lower limit value of the allowable range of the clock frequency of the legacy device 10-2. The maximum frequency fmax and the minimum frequency fmin may be actual measured values or estimated values. The reference frequency fo is a reference clock frequency and is, for example, the median value of the maximum frequency fmax and the minimum frequency fmin. Note that the clock frequency of the transmission-side IP conversion device 12-1 is fixed to a preset fixed value.

  The excess / deficiency count measuring unit 462 measures (counts) the number of occurrences of overflow or underflow of the reception buffer 502 per predetermined time.

  The buffer capacity changing unit 463 changes the capacity of the reception buffer 502 (hereinafter referred to as “buffer size”) according to the measurement result by the excess / deficiency number measuring unit 462. The capacity of the reception buffer 502 refers to the amount of data that is allowed to be stored in the RAM 50.

  Hereinafter, in the first embodiment, a processing procedure executed by the IP conversion apparatus 12-2 on the receiving side will be described. FIG. 4 is a flowchart for explaining an example of a processing procedure of clock frequency adjustment processing executed by the IP conversion device on the receiving side.

  For example, when the IP conversion device 12-2 is activated and reception of an IP packet is started, the legacy interface unit 20 waits until the buffer data amount reaches the center value Co, and then starts reading the reception buffer 502 (S101). Thereafter, the reading of the reception buffer 502 is performed in synchronization with the clock frequency of the variable clock unit 26 (in a cycle based on the clock frequency). At the start of reading of the reception buffer 502, the clock frequency is the reference frequency fo. The reason for waiting until the buffer data amount reaches the center value Co is to reduce the possibility of occurrence of underflow in the reception buffer 502.

  Thereafter, when the reception buffer monitoring unit 461 detects that the buffer data amount has reached the upper limit value Cmax or the lower limit value Cmin (Yes in S102), the clock frequency of the variable clock unit 26 is set to the maximum frequency fmax or the minimum frequency fmin. Set (S103). That is, when the buffer data amount reaches the upper limit value Cmax, the clock frequency of the variable clock unit 26 is set to the maximum frequency fmax. When the buffer data amount reaches the lower limit value Cmin, the clock frequency of the variable clock unit 26 is set to the minimum frequency fmin. The reason why the maximum frequency fmax or the minimum frequency fmin is set is to quickly eliminate the state where the buffer data amount deviates from the center value Co. In step S103 and subsequent steps, reading from the reception buffer 502 is performed based on the new clock frequency.

  Subsequently, the reception buffer monitoring unit 461 waits until the buffer data amount decreases or increases due to the change of the clock frequency and reaches the center value Co (S104). During this time, data reception from the IP network 18 and data reading from the reception buffer 502 are performed.

  When the buffer data amount reaches the center value Co, the reception buffer monitoring unit 461 sets the clock frequency of the variable clock unit 26 to the reference frequency fo (S105). Thereafter, step S102 and subsequent steps are repeated and executed.

  In the state where the clock frequency of the variable clock unit 26 is the reference frequency fo, when the tendency to increase the buffer data amount continues, a frequency (for example, the reference frequency fo + β) larger than the reference frequency fo is variable in step S105. The clock frequency of the clock unit 26 may be used. If the buffer data amount still increases and reaches the upper limit value Cmax, the clock frequency of the variable clock unit 26 may be set to a larger value (for example, the reference frequency fo + 2β). As a result of repeating such control, when the buffer data amount is stabilized near the center value Co, the clock frequency at that time may be set to the reference frequency fo thereafter.

  If the tendency of the buffer data amount to decrease continues in a state where the clock frequency of the variable clock unit 26 is the reference frequency fo, in step S105, a frequency smaller than the reference frequency fo (for example, reference frequency fo-β). May be the clock frequency of the variable clock unit 26. If the buffer data amount still decreases and reaches the lower limit Cmin, a smaller value (for example, the reference frequency fo-2β) may be set as the clock frequency of the variable clock unit 26. As a result of repeating such control, when the buffer data amount is stabilized near the center value Co, the clock frequency at that time may be set to the reference frequency fo thereafter.

  With the control as described above, the period during which the buffer data amount is near the center value Co can be extended.

  On the other hand, even if the clock frequency of the variable clock unit 26 is set to the maximum frequency fmax, the buffer data amount does not decrease and the reception buffer 502 overflows due to the congestion of IP packet arrival intervals in the IP network 18. There is a possibility. Similarly, even if the clock frequency of the variable clock unit 26 is set to the minimum frequency fmin, the buffer data amount does not increase and the reception buffer 502 underflows due to depopulation of the arrival interval of IP packets in the IP network 18. There is a possibility that.

  When the reception buffer 502 overflows or underflows (Yes in S106), the legacy interface unit 20 stops reading data from the reception buffer 502 (S107). Subsequently, the reception buffer monitoring unit 461 clears the reception buffer 502 (S108). As a result, the reception buffer 502 becomes empty. The reception buffer 502 is cleared when an overflow occurs. This is because in the case of underflow, the reception buffer 502 is already empty. In the case of an overflow, the reception buffer 502 is cleared because the communication is in an abnormal state due to the occurrence of data that could not be buffered due to the overflow, and the abnormal state is once resolved. Clearing the reception buffer 502 causes data to be lost. For example, in the case of communication that requires real-time performance, it is better to maintain the real-time performance than to request retransmission of an IP packet. It can be said that this is an appropriate control from the viewpoint.

  Subsequent to step S108, step S101 and subsequent steps are repeatedly executed.

  Through the above processing procedure, synchronous communication data is transmitted to the legacy device 10-2 in synchronization with the clock frequency within the allowable range of the legacy device 10-2. Therefore, the legacy device 10-2 can be synchronized with the synchronous communication data transmitted from the legacy device 10-1 and stored in the IP packet via the IP network 18.

  In parallel with the processing described with reference to FIG. 4, the IP conversion apparatus 12-2 executes buffer size change processing.

  FIG. 5 is a flowchart for explaining an example of the processing procedure of the buffer size changing process in the first embodiment.

  After the start of communication, the excess / deficiency count measurement unit 462 counts, for example, the number of underflows or overflows in one minute (S201). Here, the count is performed without distinction between underflow and overflow. The consecutively received IP packets that cause underflow are sparse and the packets are continuously received that cause overflow. This is because the IP packet congestion state is considered to be equivalent in view of the fact that they occur in pairs. In other words, if IP packets are transmitted from the transmission side at a constant interval, there is a high possibility that a state in which the IP packet interval is too dense will occur after the IP packet interval is in a sparse state. In addition, in both cases of underflow and overflow, both are considered to be equivalent in view of the fact that synchronous communication is interrupted.

  When the count number is 0 (Yes in S202), the buffer capacity changing unit 463 decreases the buffer size (S203). That is, the value of the upper limit value Cmax is reduced, and the center value Co is also reduced due to the influence. The method of reducing the capacity is not limited to a predetermined method. For example, it may be decreased by a certain amount or may be decreased by a certain rate. The reason why the buffer size is decreased when the count number is 0 is that the buffer size may be excessive. Note that a lower limit value greater than 0 may be provided for the buffer size. For example, when the buffer size is the lower limit in step S203, the buffer size may not be reduced.

  On the other hand, when the count number is 1 or more (No in S202), the buffer capacity changing unit 463 determines whether the count number is 2 or less (S204). When the count number is 2 or less (Yes in S204), the buffer capacity changing unit 463 keeps the buffer size as it is (S205).

  When the count number is 3 or more (No in S204), the buffer capacity changing unit 463 increases the buffer size (S206). This is because with the current buffer size, there is a high possibility that underflow or overflow occurs frequently only by adjusting the clock frequency. That is, by increasing the buffer size, it is possible to increase resistance to fluctuations in the arrival interval of IP packets, and as a result, it is possible to reduce the risk of occurrence of underflow or overflow. The method of increasing the capacity is not limited to a predetermined method. For example, it may be increased by a certain amount or may be increased by a certain rate.

  Note that the threshold for the number of counts in FIG. 4 is merely an example. For example, the threshold shown in FIG. 4 is effective when a state where the number of underflows and overflows per minute is 2 or less is allowed. For example, if underflow and overflow are not allowed, the buffer size may be increased even if the count is 1 or 2 (Yes in S204). Further, the degree of increase in the buffer size may be determined based on the count number. For example, the amount of increase in the buffer size may be increased as the count number is increased.

  If the count number is 0 (Yes in S202), the buffer size may be left as it is if the buffer size has been increased in the past. When the buffer size is repeatedly reduced, when the buffer size is increased due to the occurrence of overflow or underflow, the count number is 0, which means that the current buffer size is different from the current communication. This is because it is considered to be an appropriate size.

  As described above, according to the first embodiment, the buffer size can be adjusted according to the occurrence of underflow or overflow. Here, underflow or overflow is a phenomenon that occurs as a result of fluctuations in the arrival interval (reception interval) of IP packets. Therefore, it can be said that grasping the occurrence state of underflow or overflow is grasping the degree of fluctuation of the arrival interval (reception interval) of IP packets. Therefore, according to the first embodiment, the buffer size can be adjusted according to the degree of fluctuation of the arrival interval of IP packets. As a result, even if the underflow or overflow cannot be avoided only by adjusting the clock frequency, the underflow or overflow can be avoided. Further, when the fluctuation of the arrival interval of the IP packet is small, an increase in delay time in the synchronous communication on the receiving side can be suppressed by reducing the buffer size. That is, if the buffer size is small, the center value also becomes small, and the waiting time until the buffer data amount reaches the center value can be shortened. As a result, the delay time of synchronous communication can be shortened.

  In other words, if it is attempted to avoid the occurrence of underflow or overflow by simply increasing the capacity of the reception buffer, there is a high possibility that the delay time of synchronous communication will be prolonged. On the other hand, according to the first embodiment, the buffer size can be set to an appropriate value while balancing the avoidance of the risk of occurrence of underflow or overflow and the avoidance of a prolonged delay time.

  Next, a second embodiment will be described. In the second embodiment, differences from the first embodiment will be described. Accordingly, points not particularly mentioned may be the same as those in the first embodiment.

  FIG. 6 is a diagram illustrating a functional configuration example of the IP conversion device according to the second embodiment. In FIG. 6, the same parts as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 6, the IP conversion device 12 includes an arrival interval measurement unit 464. The arrival interval measurement unit 464 measures the arrival interval (reception interval) of the IP packet received by the IP interface unit 22 and calculates the degree of variation in the arrival interval. The degree of variation is the degree of variation with respect to the transmission interval of IP packets that is constant on the transmission side. The arrival interval measurement unit 464 may be realized by a process that the program causes the CPU 46 to execute, or may be implemented as hardware (circuit).

  In the second embodiment, the IP conversion device 12 may not have the excess / deficiency count measuring unit 462. Therefore, in FIG. 6, the excess / deficiency count measuring unit 462 is not shown.

  FIG. 7 is a flowchart for explaining an example of a processing procedure of a buffer size changing process in the second embodiment.

  After the start of communication, for example, the arrival interval measurement unit 464 measures an interval (arrival interval) with the previous IP packet every time an IP packet is received in a predetermined period (for example, several minutes). The arrival interval measurement unit 464 calculates the standard deviation σ of the set of arrival intervals in the predetermined period using the following equation (1).

In Expression (1), n is the number of arrival intervals in a predetermined period, that is, the number of IP packets received in the predetermined period minus one. T is an IP packet transmission interval by the IP converter 12-1. T _i is the i-th arrival interval in a predetermined period. i is 1 or more and n or less.

  According to Expression (1), the standard deviation (variation) of arrival intervals in a predetermined period with respect to the transmission interval T, which is a constant interval, is derived. Therefore, the standard deviation σ increases with respect to the transmission interval T in a state where IP packets continuously received are sparse or in a state where IP packets continuously received are sparse. Note that the value of the transmission interval T is known to the arrival interval measurement unit 464.

  Subsequently, the buffer capacity changing unit 463 determines whether or not the standard deviation σ ÷ transmission interval T (hereinafter referred to as “σ / T”) is less than the threshold A (S302). The reason why the standard deviation σ is divided by the transmission interval T is to evaluate the arrival status of the IP packet in a predetermined period by the ratio of the standard deviation σ to the transmission interval T. However, the value in consideration of the transmission interval T may be the threshold A. Specifically, threshold A × transmission interval T may be set as threshold A. In this case, the standard deviation σ and the threshold value A may be compared.

  When σ / T is less than the threshold value A (Yes in S302), the buffer capacity changing unit 463 decreases the buffer size (S303). In this case, the variation (fluctuation) in the arrival interval of the IP packet is small, and it is considered that the possibility of occurrence of overflow or underflow is low. As for the buffer size, a lower limit value greater than 0 may be provided, as in the first embodiment. Also, the degree of buffer size reduction may be determined based on σ / T. For example, the amount of decrease in buffer size may be reduced as σ / T increases.

  On the other hand, when σ / T is equal to or greater than the threshold A (No in S302), the buffer capacity changing unit 463 determines whether σ / T is less than the threshold B (S304). The threshold value B is a value larger than the threshold value A, and it is highly likely that the occurrence frequency of overflow or underflow can be suppressed within an allowable range depending on the current buffer size. Note that the threshold A and the threshold B may change according to the buffer size.

  When σ / T is less than the threshold value B (Yes in S304), the buffer capacity changing unit 463 keeps the buffer size as it is (S305).

  When σ / T is equal to or greater than the threshold value B (No in S304), the buffer capacity changing unit 463 increases the buffer size (S306). The degree of increase in buffer size may be determined based on σ / T. For example, the amount of increase in the buffer size may be increased as σ / T increases.

  In FIG. 5, when σ / T is equal to or greater than the threshold A, the buffer size may be increased without performing the determination based on the threshold B.

  As described above, according to the second embodiment, the buffer size can be adjusted according to fluctuation (variation) in the arrival interval of IP packets. The fluctuation in the arrival interval of IP packets is a major cause of underflow or overflow. Therefore, by adjusting the buffer size according to the fluctuation (variation) of the arrival interval of the IP packet, the buffer size can be made as small as possible while reducing the risk of underflow or overflow. That is, the possibility of obtaining the same effect as that of the first embodiment can be increased.

  Note that the first embodiment and the second embodiment may be combined. That is, the buffer size may be changed based on the standard deviation σ of the IP packet arrival interval while being changed according to the number of underflows and overflows.

  In each of the above embodiments, the IP conversion device 12 is an example of a communication device. The synchronous communication network 11-1 or 11-2 is an example of a first communication network. The asynchronous communication network 15 is an example of a second communication network. The reception buffer 502 is an example of a storage unit. The legacy interface unit 20 is an example of a transmission unit. The reception buffer monitoring unit 461 is an example of a changing unit. The excess / deficiency count measurement unit 462 or the arrival interval measurement unit 464 is an example of a measurement unit.

  As mentioned above, although the Example of this invention was explained in full detail, this invention is not limited to such specific embodiment, In the range of the summary of this invention described in the claim, various deformation | transformation・ Change is possible.

10-1, 10-2 Legacy devices 11-1, 11-2 Synchronous communication networks 12-1, 12-2 IP converters 14-1, 14-2 Legacy network 15 Asynchronous communication network 18 IP network 20 Legacy interface unit 22 IP interface unit 24 packet processing unit 26 variable clock unit 36 CPU
50 RAM
52 ROM
201 alarm monitoring unit 241 packet assembling unit 242 packet disassembling unit 461 reception buffer monitoring unit 462 excess / deficiency count measuring unit 463 buffer capacity changing unit 464 arrival interval measuring unit 501 transmission buffer 502 reception buffer

Claims (5)

A storage unit for storing data received from the second communication network by communication asynchronous to communication in the first communication network;
The data stored by the storage unit is read according to a clock signal, and transmitted to the first communication network,
A first changing unit that changes a frequency of the clock signal within a predetermined range in accordance with a data amount of data stored in the storage unit;
A measurement unit that measures the degree of fluctuation in the reception interval of data from the second communication network;
A communication apparatus comprising: a second changing unit that changes a data amount that is allowed to be stored in the storage unit based on a measurement result of the degree of fluctuation.   The communication device according to claim 1, wherein the measurement unit measures the degree of fluctuation based on an occurrence state of underflow or overflow of the storage unit.   The communication apparatus according to claim 1, wherein the measurement unit measures the degree of fluctuation based on a standard deviation of the reception interval. The communication device
Storing data received from the second communication network by communication asynchronous to communication in the first communication network in the storage unit;
Read the data stored by the storage unit according to the clock signal, send to the first communication network,
In accordance with the amount of data stored in the storage unit, the frequency of the clock signal is changed within a predetermined range,
Measure the degree of fluctuation of the data reception interval from the second communication network,
Based on the measurement result of the degree of fluctuation, change the amount of data allowed to be stored in the storage unit,
A communication method that executes processing. A storage unit for storing data received from the second communication network by communication asynchronous to communication in the first communication network;
A communication device having a transmission unit that reads out data stored in the storage unit according to a clock signal and transmits the data to the first communication network.
In accordance with the amount of data stored in the storage unit, the frequency of the clock signal is changed within a predetermined range,
Measure the degree of fluctuation of the data reception interval from the second communication network,
Changing the capacity of the storage unit according to the amount of data stored in the storage unit;
A program that executes processing.

Images