JP2014192919A - Motor drive and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a motor drive the fail-safe function of which can be managed centrally, and to provide an electronic apparatus, and the like.SOLUTION: A motor drive 200 includes a motor drive circuit (210) for driving a motor 280, a control circuit 240 for controlling the motor drive circuit (210), by controlling transition between a plurality of states including a charge state, a decay state and an abnormal state, and a watch dog timer 250 for counting a period based on the transition between the plurality of states. The control circuit 240 controls the watch dog timer 250 to start counting of a first period, when making a transition to the charge state. The control circuit 240 makes a transition to the abnormal state when end of the first period is notified from the watch dog timer 250 without satisfying the transition conditions from the charge state to the decay state.

Description

  The present invention relates to a motor drive device, an electronic device, and the like.

  As a motor driving device for driving a direct current motor, a method of controlling the number of rotations of a motor by controlling a chopping current is known. In this method, the current flowing through the bridge circuit is subjected to current / voltage conversion by a sense resistor, and the chopping current is detected by comparing the voltage with a reference voltage. Then, the detection result is fed back to the control circuit, and the motor is rotated at a constant speed by PWM control of the drive signal of the bridge circuit (for example, Patent Document 1).

  In such a motor drive device, there is a possibility that the motor or the motor drive device may be damaged due to an abnormality or failure. For example, Patent Documents 2 and 3 describe that under certain conditions (for example, wiring short circuit), the chopping operation may not be performed normally, leading to abnormal heat generation or damage to the motor, or damage to the motor drive device. Has been.

JP-A-11-206189 Japanese Patent Laid-Open No. 05-111144 Japanese Patent Laid-Open No. 05-111145

  Some motor drive devices have a fail-safe function in order to prevent such abnormalities and failures as described above, and perform operations to protect the device when abnormalities or failures are detected. However, since there are many factors for abnormalities and failures, there is a problem that the management of the fail-safe function becomes complicated if each factor is dealt with.

  According to some aspects of the present invention, it is possible to provide a motor drive device, an electronic device, and the like that can centrally manage the fail-safe function.

  One embodiment of the present invention includes a motor drive circuit that drives a motor, a control circuit that controls transition between a plurality of states including a charge state, a decay state, and an abnormal state, and controls the motor drive circuit, A watchdog timer that counts a period based on transitions between the states, wherein the control circuit causes the watchdog timer to start counting a first period when transitioning to the charge state, When the watchdog timer notifies the end of the first period while the transition condition from the decay state to the decay state is not satisfied, the motor drive device transitions to the abnormal state.

  According to one aspect of the present invention, when the transition to the charge state is made, the watchdog timer starts counting the first period, and when the first period elapses without satisfying the transition condition from the charge state to the decay state. The transition to the abnormal state is performed. As a result, the fail-safe function can be centrally managed.

  In one aspect of the present invention, the control circuit causes the watchdog timer to start counting the second period when transitioning to the decay state, and the transition condition from the decay state to the charge state is not satisfied. If the end of the second period is notified from the watchdog timer, the transition to the abnormal state may be made.

  In this way, when the second period elapses without satisfying the transition condition from the decay state to the charge state, the transition to the abnormal state is performed. As a result, the fail safe function including the fail safe in the decay state can be centrally managed.

  In one aspect of the present invention, the control circuit includes a period setting register in which a length of a decay period that is a period of the decay state is set, and the control circuit has not yet elapsed the decay period set in the period setting register. If the end of the second period is notified from the watchdog timer, the transition to the abnormal state may be made.

  In one aspect of the present invention, the decay mode in the decay state includes a mode setting register in which a plurality of decay modes having different rates of decrease in the drive current of the motor are set, and the control circuit includes the plurality of decay modes. Even in any of the modes, the transition to the abnormal state may be made when the end of the second period is notified from the watchdog timer.

  In one aspect of the present invention, the control circuit further includes a threshold setting register that sets a threshold value of a driving current that drives the motor, and the control circuit does not reach the threshold value that is set in the threshold setting register. When the end of the first period is notified from the watchdog timer, a transition to the abnormal state may be made.

  According to these aspects of the present invention, the drive current can be controlled by changing the set value of the register, and the motor can be controlled to a desired rotational speed. However, when such register writing is performed, malfunction or damage of the motor or the motor driving device may occur due to, for example, writing failure or an unintended setting value. In this respect, according to one aspect of the present invention, the state transition condition is not satisfied and the transition to the abnormal state occurs when the first period or the second period elapses, so that it is possible to prevent malfunction or damage of the motor or the motor driving device. It becomes.

  In one embodiment of the present invention, a reference voltage generation circuit that generates a reference voltage corresponding to the threshold value set in the register, the reference voltage, and a voltage obtained by converting the drive current into a current voltage by a sense resistor are compared. The control circuit may determine whether the drive current has reached the threshold based on an output signal of the voltage detection circuit.

  In this way, based on the output signal of the voltage detection circuit, it can be determined whether or not the drive current has reached the threshold value set in the register, and based on the determination result whether or not to transit to the abnormal state. Can be determined.

  In one aspect of the present invention, the motor drive circuit includes a bridge circuit that repeats a charge operation that increases a drive current for driving the motor and a decay operation that decreases the drive current by turning on and off the switch element. The control circuit may turn off the switch element of the bridge circuit in the abnormal state.

  By doing so, the current path flowing through the motor can be interrupted by turning off the switch element of the bridge circuit in the abnormal state. As a result, it is possible to prevent the motor from generating heat, overcurrent, and accompanying damage, thereby realizing a fail-safe function.

  Moreover, the other aspect of this invention is related with the electronic device containing the motor drive unit described in either of the above.

1 is a configuration example of a motor drive device of the present embodiment. Explanatory drawing of charge operation. Explanatory drawing of the first decay operation | movement in synchronous rectification. Explanatory drawing of motor drive control. FIG. 5A is a state transition diagram of the present embodiment. FIG. 5B is an explanatory diagram of the decay mode. The timing chart of the state transition control in normal operation. The timing chart of the state transition when abnormality occurs in the charge state. The timing chart of the state transition when abnormality occurs in the decay state. Explanatory drawing of the slow decay operation | movement in synchronous rectification. FIG. 10A is an explanatory diagram of a first decay operation in asynchronous rectification. FIG. 10B is an explanatory diagram of a slow decay operation in asynchronous rectification. An example of drive current characteristics in fast decay mode. The example of a drive current characteristic in slow decay mode. The example of a drive current characteristic in mixed decay mode. Explanatory drawing of the motor control method using decay mode. Explanatory drawing of the motor control method using decay mode. Configuration example of an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Motor Drive Device FIG. 1 shows a configuration example of the motor drive device of this embodiment. The motor driving device 200 includes a bridge circuit 210, a comparator 220 (voltage detection circuit), a reference voltage generation circuit 230, a register unit 235, a control circuit 240, a watch dog timer 250, a pre-driver 260, and a clock generation circuit 270. The register unit 235 includes a period setting register 236, a mode setting register 237, and a threshold setting register 238.

  The bridge circuit 210 drives an external motor 280 (DC motor) based on the PWM signal from the control circuit 240. Specifically, the bridge circuit 210 includes transistors Q1 to Q4 (switch elements) configured as an H bridge and diodes D1 to D4. For example, the transistors Q1 and Q2 are P-type, and the transistors Q3 and Q4 are N-type. Alternatively, the transistors Q1 to Q4 may all be N-type.

  The transistor Q1 and the diode D1 are provided between the node of the power supply voltage VCC and the terminal OUT1 to which one end of the motor 280 is connected. The transistor Q2 and the diode D2 are provided between the node of the power supply voltage VCC and the terminal OUT2 to which the other end of the motor 280 is connected. The transistor Q3 and the diode D3 are provided between the terminal OUT1 and a terminal RNF connected to the other end of the sense resistor 290 to which a ground voltage is supplied at one end. The transistor Q4 and the diode D4 are connected between the terminal OUT2 and the terminal RNF.

  The reference voltage generation circuit 230 generates a reference voltage VR for detecting a chopping current. Specifically, the reference voltage generation circuit 230 is configured by a D / A conversion circuit. The D / A conversion circuit generates a plurality of voltages based on the reference voltage Vref, and a voltage corresponding to the register value (chopping current Ich in FIG. 4) set in the threshold setting register 238 from the plurality of voltages. And the selected voltage is output as the reference voltage VR.

  The comparator 220 detects whether or not the current for driving the motor 280 has reached a chopping current (threshold value). Specifically, the comparator 220 compares the voltage VS at one end of the sense resistor 290 input via the terminal RNF with the reference voltage VR. Then, when it is detected that the voltage VS has reached the reference voltage VR, the detection signal is output to the control circuit 240 as an output signal cmp_out.

  The control circuit 240 is a circuit that controls the chopping operation of the bridge circuit 210, and operates based on the clock signal clk from the clock generation circuit 270. The chopping operation is an operation of controlling the charge / decay of the current that drives the motor 280 by the on / off control of the transistors Q1 to Q4. Specifically, the control circuit 240 controls the pulse width of the PWM signal based on the detection signal from the comparator 220 so that the chopping current is constant. Then, an on / off control signal for the transistors Q 1 to Q 4 is generated from the PWM signal, and the generated on / off control signal is output to the pre-driver 260.

  The pre-driver 260 includes buffers 261 to 264. The buffers 261 to 264 buffer the on / off control signal from the control circuit 240 and output it as drive signals G1 to G4 to the gates of the transistors Q1 to Q4.

  The watchdog timer 250 monitors the state transition of the control circuit 240. When the watchdog timer 250 times out for a predetermined period while remaining in a specific state, the watchdog timer 250 notifies the control circuit 240 accordingly. Specifically, the control circuit 240 transitions between a charge state that performs a charge operation in motor driving, a decay state that performs a decay operation in motor driving, and an abnormal state that performs an operation when an abnormality occurs in motor driving. It operates as a state machine. The control circuit 240 resets the count of the watchdog timer 250 when transitioning to the charge state and the decay state. When the watchdog timer 250 reaches a predetermined count value without being reset, the control circuit 240 shifts to an abnormal state and turns off the transistors Q1 to Q4 of the bridge circuit 210. Further detailed operations of the watchdog timer 250 and the control circuit 240 will be described later.

2. Basic Operation of Motor Drive The basic operation of the motor drive device 200 will be described using FIGS. 2 to 4 as an example of the first decay mode of synchronous rectification. 2 and 3, illustration of the diodes D1 to D4 is omitted.

  As shown in FIG. 4, it is assumed that driving of the motor 280 is started at time t0. When driving is started, the control circuit 240 shifts to the charge state, and the bridge circuit 210 performs the charge operation. That is, as shown in FIG. 2, the transistors Q1 and Q4 are turned on, and the transistors Q2 and Q3 are turned off. At this time, a drive current flows from the power supply voltage VCC to the ground voltage via the transistor Q1, the motor 280, the transistor Q4, and the sense resistor 290, as indicated by a solid line arrow in FIG.

  The drive current increases with time, and the voltage VS converted by the sense resistor 290 also increases. When the voltage VS becomes higher than the reference voltage VR, the output signal of the comparator 220 changes from the low level to the high level. As shown in FIG. 4, the driving current at this time (time t1) is the chopping current Ich, and the chopping current Ich is detected by detecting the voltage VS.

  In response to the output signal of the comparator 220 becoming high level, the control circuit 240 makes a transition to the decay state, and the bridge circuit 210 performs a decay operation. That is, as shown in FIG. 3, the transistors Q2 and Q3 are turned on, and the transistors Q1 and Q4 are turned off. At this time, as indicated by a dotted arrow in FIG. 3, a drive current (regenerative current) flows from the ground voltage to the power supply voltage VCC via the sense resistor 290, the transistor Q3, the motor 280, and the transistor Q2. As shown in FIG. 4, in the decay period TD1, the drive current decreases with time.

  The control circuit 240 detects, for example, that a predetermined time has elapsed since the transition to the decay state by using a counter circuit or the like, and transitions to the charge state. This shifts to the charge period TC1, so that the drive current rises again and shifts to the decay period TD2 when the chopping current Ich is reached. Thereafter, by repeating this, the chopping current Ich is controlled to be constant, and the rotation speed of the motor 280 is kept constant.

3. State Transition Control in Normal Operation Next, state transition control in the present embodiment will be described. FIG. 5A shows a state transition diagram. FIG. 5B shows an explanatory diagram of the decay mode. FIG. 6 shows a timing chart of state transition control in normal operation. In the following, the flag “1” indicates that the flag is active, and “0” indicates that the flag is inactive.

  As shown in FIG. 5 (A), when the motor is normally driven, it reciprocates between the charge state CS and the decay state (FastDS, SlowDS). When an abnormality occurs, the watchdog timer 250 monitors that no transition occurs between the charge state CS and the decay state. That is, when the watchdog timer 250 times out without any transition, the state is shifted to the abnormal state IS and the motor drive is stopped. In the abnormal state IS, the transistors Q1 to Q4 of the bridge circuit 210 are turned off to interrupt the current path flowing through the motor 280. Thereby, overheating of the motor 280 and failure of the motor drive device 200 can be prevented in advance.

  First, state transition in normal operation will be described using the slow decay mode as an example. Although the decay mode will be described later, the slow decay mode is a mode in which the motor drive current is gradually reduced in the decay operation.

  When the motor drive device 200 is set to the reset state, the idle state IDEL is set. In the idle state IDEL, the motor 280 is not driven. For example, the motor driving device 200 is set in a power-down state. Next, when the motor driving device 200 is set to the enable state, the state transitions from the idle state IDEL to the charge state CS. In the charge state CS, the charge operation as described in FIG. 2 is performed.

  As shown in A1 of FIG. 6, when the output signal cmp_out of the comparator 220 continues to be high level twice at the rising edge of the clock signal clk, it is determined that the drive current of the motor 280 has exceeded the chopping current Ich, As shown in A2, the flag cmp_det = 1 (active) is set. Further, as shown at A3, a flag nextDS = 1 is set indicating that the next transition state is the decay state. Then, as indicated by A4, the flag nextDS = 1 is received, and a transition is made to the slow decay state SlowDS at the rising edge of the next cycle of the clock signal clk.

  At this time, as indicated by A5, in response to the flag cmp_det = 1, the count value Decay_cnt for counting the period of the entire decay state is restarted (counting starts from the count value “0”). Also, as shown at A6, the flag nextDS = 1 is received and the flag WT_clear = 1 for starting the watchdog process is set. As indicated by A7, the watchdog timer 250 receives the flag WT_clear = 1 and restarts the count value WT_cnt of the watchdog process (starts counting from the count value “0”).

  As shown in A8, when the count value Decay_cnt reaches a desired value (the register value Reg_Decay_time = Td in FIG. 5B, for example, the hexadecimal number “FF”), the next transition state is charged as shown in A9. A flag nextCS = 1 indicating the state is set. Then, as indicated by A10, the flag nextCS = 1 is received and the state transits to the charge state CS at the rising edge of the next cycle of the clock signal clk. At this time, as shown in A11, the flag nextCS = 1 is received and the flag WT_clear = 1 is set. As indicated by A12, the watchdog timer 250 receives the flag WT_clear = 1 and restarts the count value WT_cnt.

  Thereafter, the transition is repeated between the charge state CS and the slow decay state SlowDS in the same process, and the motor 280 is driven.

  As shown in FIG. 5B, the decay operation includes a fast decay mode in which the motor drive current is rapidly reduced, a slow decay mode in which the motor drive current is gently reduced, and a mixed decay in which these are combined. There are modes. Which mode to operate depends on the register value Reg_Decay_mode set in the mode setting register 237 and the register values Reg_Fast_decay_time and Reg_Decay_time set in the period setting register 236. The register value Reg_Decay_time is set to the length Tfs of the period operating in the decay mode, and the register value Reg_Fast_decay_time is set to the length Td of the period operating in the fast decay mode.

  When Reg_Decay_mode = 0 and Tfs <Td, the operation is performed in the mixed decay mode. That is, as shown in FIG. 5A, when the flag cmp_det = 1, the flag nextDS = 1, and first the state transitions from the charge state CS to the first decay state FastDS. At this time, in addition to the count value Decay_cnt, the count value Fast_Decay_cnt for counting the period of the first decay state FastDS is restarted (counting starts from the count value “0”). When the count value Fast_Decay_cnt reaches the desired value Tfs, the state transitions to the slow decay state SlowDS. When the count value Decay_cnt reaches the desired value Td, the flag nextCS = 1, and the state transits to the charge state CS.

  When Reg_Decay_mode = 0 and Tfs> Td, the operation is performed in the fast decay mode. That is, when the flag cmp_det = 1, the flag nextDS = 1, and the state transitions from the charge state CS to the first decay state FastDS. When the count value Fast_Decay_cnt reaches Tfs, the flag nextCS = 1 and the state transitions to the charge state CS.

  When Reg_Decay_mode = 1, the operation is performed in the slow decay mode. The state transition in the slow decay mode is as described in FIG.

4). State transition control when abnormality occurs Next, state transition when abnormality occurs in the charge state CS will be described.

  In the charge state CS, the following abnormalities are assumed. For example, when a node at one end or the other end of the motor 280 is short-circuited to the ground voltage, the drive current does not flow through the sense resistor 290, and thus the comparator 220 cannot detect the voltage. Alternatively, when the wiring from one end of the sense resistor 290 to the input terminal of the comparator 220 is disconnected, the comparator 220 cannot detect the voltage. In such a case, since the transition condition to the decay state (cmp_det = 1) is not satisfied, the charging operation continues, an overcurrent flows through the motor 280, which may lead to overheating or destruction of the motor 280 or the motor driving device 200. is there. In this regard, in this embodiment, since the transition to the abnormal state IS occurs due to the timeout of the watchdog timer 250, the current flowing through the motor 280 can be interrupted.

  FIG. 7 shows a timing chart of state transition when an abnormality occurs in the charge state CS.

  As shown in B1 of FIG. 7, when the flag cmp_det = 0 (inactive) remains, the watchdog timer 250 is not restarted and continues counting. Then, as shown in B2, when the count value WT_cnt of the watchdog timer 250 reaches a predetermined value (for example, hexadecimal “FFF”), as shown in B3, a flag nextIS = Set 1 As shown in B4, in response to the flag nextIS = 1, the state transits to the abnormal state IS at the rising edge of the next cycle of the clock signal clk. In the abnormal state IS, all the transistors Q1 to Q4 of the bridge circuit 210 are turned off. The abnormal state IS is not canceled until the motor driving device 200 is reset, for example, and returns to the idle state IDEL again when the motor driving device 200 is reset.

  Note that the count value at which the watchdog timer 250 times out may be a value built into the circuit, for example, or may be variably set as a register value in the register unit 235.

  Next, state transition when an abnormality occurs in the decay state (FastDS, SlowDS) will be described.

  In the decay state, the following abnormalities are assumed. That is, as will be described later with reference to FIGS. 14 and 15, there is a case where the decay mode is switched in order to improve the current followability when the rotational speed of the motor is changed. At this time, since the user sets the decay mode (Reg_Decay_mode) and its period (Reg_Fast_Decay_time, Reg_Decay_time) in the register unit 235, there is a possibility that an erroneous setting value or a setting value that cannot operate normally may be written. In such a case, the motor 280 may operate unexpectedly. Alternatively, if the first decay state FastDS (FIG. 3) is set to continue for a long time, the current flowing through the motor 280 is gradually reversed to reversely rotate the motor 280, and the current continues to increase. There is a possibility that an overcurrent flows to 280. In this respect, in the present embodiment, the state transitions to the abnormal state IS due to the time-out of the watchdog timer 250, so that the current flowing through the motor 280 can be cut off and the motor 280 and the motor driving device 200 can be protected.

  FIG. 8 is a timing chart of state transition when an abnormality occurs in the decay state (FastDS, SlowDS).

  For example, when an incorrect value is set for the register value Reg_Decay_time = Td, or when the counter that counts the count value Decay_cnt fails, the count value Decay_cnt reaches the desired value as shown by E1 in FIG. Before, the count value WT_cnt of the watchdog timer 250 reaches a set value (for example, hexadecimal “FFF”). In response to this, the flag nextIS = 1 is set. As indicated by E3, the flag nextIS = 1 is received, and the state transits to the abnormal state IS at the rising edge of the next cycle of the clock signal clk. In the abnormal state IS, all the transistors Q1 to Q4 of the bridge circuit 210 are turned off.

  In the first decay state FastDS, when the count value WT_cnt of the watchdog timer 250 reaches the set value before the count value Fast_Decay_cnt reaches the desired value, the flag nextIS = 1 is set and the state transits to the abnormal state IS.

  Now, according to the present embodiment described above, the fail-safe function can be centrally managed by making a transition to the abnormal state IS when the watchdog timer 250 times out without making a state transition. This point will be described with reference to a comparative example.

  As a comparative example, for example, a method of monitoring the output signal cmp_out of the comparator 220 and determining that the chopping current Ich is abnormally detected when the output signal cmp_out does not become high level within a predetermined period can be considered. However, since this method performs fail-safe according to the output signal cmp_out, it cannot cope with other abnormalities. Therefore, it is necessary to perform fail-safe corresponding to various abnormalities, and there is a problem that the control becomes complicated.

  In this regard, the motor driving device 200 of the present embodiment includes a motor driving circuit (bridge circuit 210) that drives the motor 280, a plurality of states including a charge state CS, a decay state (FastDS, SlowDS), and an abnormal state IS. A control circuit 240 that controls the transition of the motor and the motor drive circuit, and a watch dog timer 250 that counts a period (count value WT_cnt) based on the transition between the plurality of states. Then, the control circuit 240 causes the watchdog timer 250 to start counting for the first period (for example, “FFF” in FIG. 7) when the state transitions to the charge state CS (sets the flag WT_clear = 1). The control circuit 240 transitions to the abnormal state IS when the watchdog timer 250 notifies the end of the first period while the transition condition to the decay state (flag nextDS = 1) is not satisfied.

  In this way, if the transition from the charge state CS to the decay state does not occur within the first period, the transition is made to the abnormal state IS. Therefore, regardless of the content of the abnormality, fail safe is performed if no state transition occurs. be able to. For example, in addition to the abnormal detection of the chopping current Ich, it is also possible to provide a detection unit for overheating or overcurrent of the motor 280, and when the detection unit detects overheating or overcurrent, it is possible to transition to the abnormal state IS. is there. That is, if the state transition is not caused when those abnormalities are detected, the fail-safe function can be centrally managed by the transition to the abnormal state IS.

  In the present embodiment, the control circuit 240 causes the watchdog timer 250 to start counting the second period (for example, “FFF” in FIG. 8) when transitioning to the decay state (FastDS, SlowDS) (flag WT_clear = 1). Stand up). The control circuit 240 transitions to the abnormal state IS when the watchdog timer 250 notifies the end of the second period while the transition condition to the charge state CS (flag nextCS = 1) is not satisfied.

  In this way, if the transition from the decay state to the charge state CS does not occur within the second period, the transition is made to the abnormal state IS. Therefore, even when an abnormality occurs in the decay state, fail safe can be performed. That is, not only the abnormality in the charge state CS but also the abnormality in the decay state can be centrally managed. 7 and 8 show an example in which the first period and the second period counted by the watchdog timer 250 are the same. In the present embodiment, the first period and the second period have different lengths. It may be.

  The motor driving device 200 of this embodiment includes a period setting register 236, a mode setting register 237, and a threshold setting register 238. In the period setting register 236, the length of the decay period (register value Reg_Decay_time, Reg_Fast_decay_time), which is the period of the decay state, is set. In the mode setting register 237, a plurality of decay modes (register values Reg_Decay_mode) having different drive current reduction rates of the motor 280 are set as decay modes in the decay state. In the threshold setting register 238, a driving current threshold (chopping current Ich) for driving the motor 280 is set.

  As will be described later, in the present embodiment, the driving current of the motor 280 is changed by rewriting these register values to control the rotational speed of the motor 280. For this reason, for example, a problem such as a write mistake when writing from the host to the register unit 235 or an incorrect register value is assumed. If such a problem occurs, the motor drive may not be performed normally, but according to the present embodiment, the fail-safe function works because the watchdog timer 250 times out without causing a state transition. Such problems can be dealt with.

5. Decay Mode Next, details of the decay mode will be described with reference to FIGS. FIG. 9 to FIG. 10B are explanatory diagrams of the decay operation of the bridge circuit 210. 11 to 13 are examples of drive current characteristics in the decay modes. 14 and 15 are explanatory diagrams of a motor control method using the decay mode. The first decay period TFD corresponds to the register value Reg_Fast_decay_time = Tfs of FIG. 5B, and the slow decay period TSD corresponds to the difference Td−Tfs of the register values Reg_Decay_time and Reg_Fast_decay_time.

  First, the first decay mode will be described. In the first decay mode, as shown in FIG. 11, the charge period TC for performing the charge operation (FIG. 2) and the first decay period TFD for performing the first decay operation are repeated. In the fast decay operation when performing synchronous rectification, as shown in FIG. 3, the transistors Q2 and Q3 are turned on, the transistors Q1 and Q4 are turned off, and power regeneration is performed via the transistors Q2 and Q3. In the first decay operation in the case of performing asynchronous rectification, as shown in FIG. 10A, the transistors Q1 to Q4 are turned off, and power regeneration is performed via the diodes D2 and D3. In any case, since a voltage is applied to both ends of the motor 280 to cause the current to flow in the direction opposite to the drive current, the decrease rate (slope) of the drive current in the first decay period TFD increases.

  Next, in the slow decay mode, as shown in FIG. 12, the charge period TC and the slow decay period TSD in which the slow decay operation is performed are repeated. In the slow decay operation in the case of performing synchronous rectification, as shown in FIG. 9, the transistors Q3 and Q4 are turned on, the transistors Q1 and Q2 are turned off, and a current flows to the ground voltage via the transistors Q3 and Q4. In the slow decay operation when performing asynchronous rectification, the transistor Q4 is turned on, the transistors Q1 to Q3 are turned off, and a current flows to the ground voltage via the diode D3 and the transistor Q4. In any case, since the motor 280 continues to rotate due to inertia, the decrease rate (slope) of the drive current in the slow decay period TSD is smaller than that in the fast decay period TFD.

  Next, in the mixed decay mode, as shown in FIG. 13, the charge period TC, the first decay period TFD, and the slow decay period TSD are repeated. That is, first, the charge period TC shifts to the first decay period TFD, and the drive current rapidly decreases. Then, the slow decay period TSD is entered, and the drive current decreases gradually.

  Next, a control method using the decay mode when changing the motor rotation speed will be described. FIG. 14 schematically shows changes in drive current when only the slow decay mode is used.

  As shown in FIG. 14, when the motor rotation speed is increased, the set value of the chopping current Ich is increased stepwise. Immediately after the set value of the chopping current Ich is increased, the charging period continues until the drive current reaches a new chopping current Ich, and thereafter, the charging period and the slow decay period are regularly repeated. On the other hand, when the motor speed is decreased, the set value of the chopping current Ich is decreased stepwise. In the slow decay mode, the rotational speed of the drive current is small, so that the motor rotation speed can be made more stable. The motor speed cannot be changed.

  Therefore, in the present embodiment, the fast decay mode or the mixed decay mode is used when the motor rotational speed is decreased. FIG. 15 schematically shows changes in the drive current in that case.

  As shown in FIG. 15, when the set value of the chopping current Ich is reduced, first, the fast decay mode is set. Since the output signal cmp_out of the comparator 220 remains at the high level until the chopping current Ich becomes smaller, the charge period becomes almost zero and the decay operation continues. When the chopping current Ich falls below, the mixed decay mode is set, and the charge operation, the first decay operation, and the slow decay operation are regularly repeated. This operation is performed according to the register values Reg_decay_time and Reg_Fast_decay_time. As described above, by using the first decay mode or the mixed decay mode, the decrease rate of the drive current is increased, and it is possible to follow the decrease of the chopping current Ich.

  As described above, in this embodiment, since the motor 280 is controlled by switching the three decay modes, the register value is frequently rewritten. For this reason, there is a high possibility that a write failure or a set value error will occur. For example, if the user intends to set the slow decay mode but unintentionally enters another decay mode, the register value Reg_Fast_decay_time, which should be invalid, becomes valid as shown in FIG. 5B. At this time, if the register value Reg_Fast_decay_time is set to a large value that is not intended, as described above, the drive current may decrease and reverse in the decay operation, and the motor 280 may reversely rotate. In this regard, according to the present embodiment, when the watchdog timer 250 times out without satisfying the transition condition, the motor 280 can be prevented from malfunctioning or being damaged because the transition is made to the abnormal state IS.

6). Electronic Device FIG. 16 shows a configuration example of an electronic device to which the motor driving device 200 (motor driver) of this embodiment is applied. The electronic device includes a processing unit 300, a storage unit 310, an operation unit 320, an input / output unit 330, a motor driving device 200, a bus 340 connecting these units, and a motor 280. In the following description, a printer that controls the head and paper feeding by motor drive will be described as an example. However, the present embodiment is not limited to this and can be applied to various electronic devices.

  The input / output unit 330 is configured by an interface such as a USB connector or a wireless LAN, and receives image data and document data. The input data is stored in the storage unit 310 which is an internal storage device such as a DRAM. When the printing instruction is received by the operation unit 320, the processing unit 300 starts a printing operation of data stored in the storage unit 310. The processing unit 300 sends an instruction to the motor drive device 200 in accordance with the print layout of the data, and the motor drive device 200 rotates the motor 280 based on the instruction to move the head and feed the paper.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Also, the configuration and operation of the control circuit, watchdog timer, bridge circuit, motor drive device, electronic device, motor drive method, state transition control method, etc. are not limited to those described in this embodiment, and various modifications are possible. Implementation is possible.

200 motor drive device, 210 bridge circuit (motor drive circuit),
220 comparator (voltage detection circuit), 230 reference voltage generation circuit,
235 register, 236 period setting register,
237 mode setting register, 238 threshold setting register,
240 control circuit, 250 watchdog timer,
260 pre-drivers, 261-264 buffers,
270 clock generation circuit, 280 motor, 290 sense resistor,
300 processing unit, 310 storage unit, 320 operation unit, 330 input / output unit,
340 bus,
clk clock signal, cmp_out comparator output signal,
CS charge state, D1-D4 diode,
FastDS first decay state, G1-G4 drive signal,
Ich chopping current, IDEL idle state,
IS abnormal state, OUT1 and OUT2 terminals,
Q1-Q4 transistor, RNF terminal,
SlowDS slow decay state,
TC, TC1, TC2 charge period, TD1, TD2 decay period,
TFD first decay period, TSD slow decay period,
VCC power supply voltage, VR reference voltage, Vref reference voltage

Claims (8)

A motor drive circuit for driving the motor;
A control circuit that controls transition between a plurality of states including a charge state, a decay state, and an abnormal state, and controls the motor driving circuit;
A watchdog timer that counts periods based on transitions between the plurality of states;
Including
The control circuit includes:
Causing the watchdog timer to start counting the first period when transitioning to the charge state;
The motor drive device according to claim 1, wherein when the watchdog timer notifies the end of the first period while the transition condition from the charge state to the decay state is not satisfied, the motor drive device transitions to the abnormal state. In claim 1,
The control circuit includes:
Causing the watchdog timer to start counting the second period when transitioning to the decay state;
The motor drive device according to claim 1, wherein when the watchdog timer notifies the end of the second period while the transition condition from the decay state to the charge state is not satisfied, the motor drive device transitions to the abnormal state. In claim 2,
A period setting register in which the length of the decay period that is the period of the decay state is set;
The control circuit includes:
The motor drive device according to claim 1, wherein when the end of the second period is notified from the watchdog timer while the decay period set in the period setting register has not yet elapsed, the motor drive device is shifted to the abnormal state. In claim 2 or 3,
As a decay mode in the decay state, including a mode setting register in which a plurality of decay modes with different speeds of reduction of the drive current of the motor are set,
The control circuit includes:
Even when the mode is set to any one of the plurality of decay modes, when the end of the second period is notified from the watchdog timer, the state transits to the abnormal state. Motor drive device. In any one of Claims 1 thru | or 4,
A threshold value setting register for setting a threshold value of a driving current for driving the motor;
The control circuit includes:
The motor drive characterized by transitioning to the abnormal state when the watchdog timer notifies the end of the first period while the drive current does not reach the threshold set in the threshold setting register apparatus. In claim 5,
A reference voltage generation circuit for generating a reference voltage corresponding to the threshold set in the register;
A voltage detection circuit for comparing the reference voltage and a voltage obtained by converting the drive current into a current voltage by a sense resistor;
Including
The control circuit includes:
A motor drive device that determines whether or not the drive current has reached the threshold value based on an output signal of the voltage detection circuit. In any one of Claims 1 thru | or 6.
The motor drive circuit is
A bridge circuit that repeats a charge operation for increasing the drive current for driving the motor and a decay operation for decreasing the drive current by turning on and off the switch element;
The control circuit includes:
The motor drive device characterized in that the switch element of the bridge circuit is turned off in the abnormal state.   An electronic apparatus comprising the motor drive device according to claim 1.

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