JP2014192855A - A/d conversion circuit and sensor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D conversion circuit that facilitates an appropriate offset correction.SOLUTION: In an A/D conversion circuit 1 which has a reference signal generation section 11 for generating a reference signal, a conversion process section for performing an A/D conversion process on an input to output an output value, and a control section 17 for performing the process of inputting the reference signal to produce a first output value, the process of inputting an input signal to produce a second output value and the process of applying an offset correction to the second output value on the basis of the first output value, and which A/D-converts the input signal, the reference signal generation section generates the reference signal such that a trend of fluctuation in a signal value by an external factor matches with the input signal.

Description

  The present invention relates to an A / D conversion circuit and a sensor device including the same.

  Conventionally, an A / D conversion circuit has been used as a circuit for converting an input signal input from various sensors into a digital signal. As the A / D conversion circuit, for example, a quadruple integration type A / D conversion circuit as disclosed in Patent Document 1 can be cited.

  The quadruple integration type A / D conversion circuit is a development of the double integration type A / D conversion circuit, and measures the input signal based on a measurement result using a reference signal (for example, a reference voltage). It is configured to perform offset correction at the time. According to the quadruple integration type A / D conversion circuit, it is possible to perform A / D conversion processing with higher accuracy than the double integration type A / D conversion circuit.

JP 2009-38433 A

  As described above, the quadruple integration type A / D conversion circuit performs offset correction when measuring the input signal based on the measurement result using the reference signal. By the way, the value of the input signal input to the A / D conversion circuit may fluctuate due to various external factors. For example, when a resistor is used for the sensor, the characteristic of the resistor changes due to a change in environmental temperature or the like, and the value of the input signal also changes.

  If the variation tendency of the signal value due to external factors is different between the input signal and the reference signal, the above-described offset correction may not be performed properly. As a result, the accuracy of A / D conversion processing in the A / D conversion circuit may be degraded. In view of the above-described problems, an object of the present invention is to provide an A / D conversion circuit that facilitates appropriate offset correction and a sensor device using the A / D conversion circuit.

  An A / D conversion circuit according to the present invention includes a reference signal generation unit that generates a reference signal, a conversion processing unit that performs an A / D conversion process on an input and outputs an output value, and a first input using the reference signal as the input. A control unit that performs a process of obtaining an output value, a process of obtaining a second output value using the input signal as the input, and a process of correcting an offset of the second output value based on the first output value. An A / D conversion circuit that performs A / D conversion, wherein the reference signal generation unit generates the reference signal so that a variation tendency of a signal value due to an external factor matches the input signal. According to this configuration, it is easy to appropriately perform offset correction.

  More specifically, as the above configuration, the input signal may be input from a sensor, and the reference signal generation unit may be formed using an element having the same characteristics as an element configuring the sensor.

  According to this configuration, it is easy to generate the reference signal so that the fluctuation tendency of the signal value due to an external factor matches the input signal. The “same characteristics” here is not limited to the case where the characteristics are completely the same, but is a meaning that allows a difference within a range where such an effect is exhibited.

  More specifically, as the above configuration, the input signal is input from the sensor having a predetermined circuit, and the reference signal generation unit is formed using a circuit having the same configuration as the predetermined circuit. Also good.

  According to this configuration, it is easy to generate the reference signal so that the fluctuation tendency of the signal value due to an external factor matches the input signal. The “same configuration” here is not limited to the case where the configurations are completely the same, but means that a difference within a range where such an effect is exhibited is allowed.

  More specifically, as the above configuration, the conversion processing unit includes an integration circuit, and the A / D conversion process includes a charging process in which charging according to the input is performed for a known set time; and It is good also as a structure including the discharge process which performs the discharge for the part charged by the charge process, and the count process which counts the time concerning the said discharge.

  More specifically, the reference signal generation unit generates a first reference signal and a second reference signal having different values as the reference signal, and the control unit includes the first reference signal and the first reference signal. The first output value may be obtained for each of the two reference signals. According to this configuration, it becomes easy to accurately detect the offset.

  More specifically, in the above configuration, the control unit performs a range adjustment process before performing the process of obtaining the first output value, and the range adjustment process includes the charging when the reference signal is the input. It is good also as a structure which is the process which makes the charge amount in a process approach a predetermined target value. According to this configuration, the charging process can be performed more appropriately.

  More specifically, in the above-described configuration, the range adjustment process measures the time until the amount charged by the charging process reaches the target value when the reference signal is the input, and the measurement is performed. It is good also as a process which is the process which makes the set time the said setting time.

  More specifically, as the above configuration, a clock generation unit that generates a clock signal used for the counting is provided, and the clock generation unit includes a ring oscillator in which a plurality of delay elements that generate a delay are coupled in a ring shape. A clock signal generation circuit that receives each pulse signal out of phase from each coupling point of the delay elements and generates a high-frequency pulse signal having a higher frequency than the pulse signal as the clock signal using the received signal It is good also as a structure provided with these.

  More specifically, the clock signal generation circuit may be configured to generate, as the high-frequency pulse signal, a signal whose level changes in response to rising and falling of each pulse signal.

  More specifically, the clock generation unit includes a plurality of signal transmission lines for transmitting the pulse signals from the ring oscillator to the clock signal generation circuit, and the plurality of signal transmissions. Each of the lines may be formed to have the same length. According to this configuration, it is possible to generate a high-frequency pulse signal with higher accuracy. The “same length” here is not limited to the case where the lengths are completely the same, but means that a difference within a range where such an effect is exhibited is allowed.

  More specifically, as the above configuration, at least one of the plurality of signal transmission lines may be configured to meander. According to this configuration, it is easy to make the lengths of the signal transmission lines uniform.

  The sensor device according to the present invention includes an A / D conversion circuit according to the above configuration and a sensor that outputs the input signal to the A / D conversion circuit. Furthermore, an electronic device according to the present invention includes a sensor device according to the above configuration. According to this configuration, it is possible to enjoy the advantages of the A / D conversion circuit according to the above configuration.

  According to the A / D conversion circuit of the present invention, it is easy to appropriately perform offset correction. Further, according to the sensor device or the electronic apparatus according to the present invention, it is possible to enjoy the advantages of the A / D conversion circuit according to the present invention.

It is a block diagram of the sensor apparatus which concerns on this embodiment. It is explanatory drawing regarding D range adjustment processing. It is explanatory drawing regarding D range adjustment processing. It is explanatory drawing regarding an offset detection process. It is explanatory drawing regarding an offset detection process. It is a timing chart regarding a series of processes which an A / D conversion circuit performs. It is a block diagram of a clock signal generation circuit and its periphery. It is a timing chart regarding each pulse signal and a high frequency pulse signal. It is explanatory drawing regarding the form of a signal transmission line. It is explanatory drawing regarding the adjustment process of D range. It is an external view of a mobile phone (smart phone). It is an external view of a portable information terminal (tablet PC). It is an external view of a digital still camera. It is an external view of a digital video camera.

  Embodiments of the present invention will be described below with reference to the drawings.

[Configuration of sensor device]
FIG. 1 is a configuration diagram of a sensor device according to the present embodiment. As shown in the figure, the sensor device includes an A / D conversion circuit 1 and a sensor 2.

  The sensor 2 is, for example, a resistance type sensor or a capacitance type sensor, and outputs a detection result signal. A signal output from the sensor 2 is input to the A / D conversion circuit 1 as an input voltage signal Sin (a voltage analog signal that is a target of A / D conversion). Various forms may be adopted for the specific configuration of the sensor 2, the detection target, and the like.

  The A / D conversion circuit 1 includes a reference voltage signal generation circuit 11, a signal selection circuit 12, an amplifier 13, an integrator 14, a first comparator 15, a second comparator 16, a control circuit 17, and an OSC circuit 18. And plays the role of A / D converting the input voltage signal Sin.

  The reference voltage signal generation circuit 11 generates a signal having a predetermined voltage as the first reference voltage signal Sr1 (voltage analog signal), and a voltage half the predetermined voltage as the second reference voltage signal Sr2 (voltage analog signal). Generate a signal. These reference voltage signals (Sr1, Sr2) are input to the signal selection circuit 12.

  The circuit characteristics of the reference voltage signal generation circuit 11 are set to be as close as possible to the circuit characteristics of the sensor 2. For example, the reference voltage signal generation circuit 11 is formed using a circuit having the same configuration as a predetermined circuit included in the sensor 2. Further, the reference voltage signal generation circuit 11 is formed using an element having the same characteristics as the element constituting the sensor 2. For example, when the sensor 2 includes a resistance element, the reference voltage signal generation circuit 11 is formed using a resistance element having the same characteristics (the same characteristics such as a resistance value and a resistance temperature coefficient).

  Since the circuit characteristics of the reference voltage signal generation circuit 11 are set in accordance with the sensor 2, the reference voltage signal generation circuit 11 has a tendency that the signal value fluctuates due to external factors (temperature, power supply voltage, etc.). Each reference voltage signal (Sr1, Sr2) is generated so as to match. For example, when the value of the input voltage signal Sin fluctuates due to a change in environmental temperature, the reference voltage signal generation circuit 11 generates each reference voltage signal (Sr1, Sr2) that fluctuates in the same tendency.

  The signal selection circuit 12 receives the input voltage signal Sin from the sensor 2 and the reference voltage signals (Sr1, Sr2) from the reference voltage signal generation circuit 11. Then, the signal selection circuit 12 selects any one of these signals in accordance with an instruction from the control circuit 17 and sends the selected signal to the amplifier 13. The amplifier 13 amplifies the signal received from the signal selection circuit 12 and outputs the amplified signal to the integration circuit 14.

  The integrating circuit 14 includes resistors (14a, 14b), open / close switches (14c to 14e), an operational amplifier 14f, and a capacitor 14g. The resistor 14a has one end connected to the output side of the amplifier 13 and the other end connected to the inverting input terminal of the operational amplifier 14f via the open / close switch 14c. The resistor 14b has one end grounded and the other end connected to the inverting input terminal of the operational amplifier 14f via the open / close switch 14d.

  The output terminal of the operational amplifier 14f is connected to the inverting input terminal of the operational amplifier 14f through the open / close switch 14e and the capacitor 14g in parallel. Further, the non-inverting input terminals of the first comparator 15 and the second comparator 16 are connected. It is connected to the. The voltage at the non-inverting input terminal of the operational amplifier 14f and the voltage at the inverting input terminal of the first comparator 15 are fixed to a predetermined reference voltage Vref1. The voltage at the inverting input terminal of the second comparator 16 is fixed to a predetermined reference voltage Vref2.

  The first comparator 15 outputs a signal Sc1 representing the comparison result of the signals input to the input terminals to the control circuit 17. The second comparator 16 outputs a signal Sc2 representing the comparison result of the signals input to the input terminals to the control circuit 17.

  The control circuit 17 is formed as a logic circuit, and controls each unit so that the A / D conversion circuit 1 operates appropriately. The control circuit 17 includes a clock signal generation circuit 17a and a counter 17b.

  The clock signal generation circuit 17a cooperates with the OSC circuit 18 to generate a counter clock signal mainly used by the counter 17b in addition to the general clock signal used for predetermined processing. The specific configurations of the clock signal generation circuit 17a and the OSC circuit 18 and the clock signal generation method will be described in detail again. The counter 17b counts time using the counter clock signal.

  The A / D conversion circuit 1 having the above-described configuration has a function of performing an A / D conversion process (A / D conversion process) on the input voltage signal Sin and each reference voltage signal (Sr1, Sr2).

  In this A / D conversion process, (1) a charging process in which charging with a current corresponding to a signal input to the integration circuit 14 is performed for a known set time dreng, and (2) an amount charged by the charging process. A discharge process for performing discharge, and (3) a count process for counting the time taken for the discharge are included. The count result (digital output value) is an A / D converted signal for the signal input to the integration circuit 14.

[Operation of A / D conversion circuit]
Next, the operation of the A / D conversion circuit 1 will be described. When performing A / D conversion of the input voltage signal Sin, the A / D conversion circuit 1 sequentially executes D [Dynamic] range adjustment processing, offset detection processing, and actual conversion processing. Each process executed prior to the actual conversion process corresponds to a process for performing the actual conversion process (A / D conversion of the input voltage signal Sin) more appropriately. Hereinafter, each of these processes will be described in more detail.

(1) D range adjustment process As described above, the A / D conversion process includes a charging process (a process in which charging with a current corresponding to a signal input to the integration circuit 14 is performed for a known set time). The appropriate value of the charge amount (corresponding to the D range) in this charging process is determined by the specification of the integrating circuit 14 (for example, the capacity of the capacitor 14g).

  If the amount of charge is too small, the performance of the integrating circuit 14 cannot be fully utilized. On the other hand, if the amount of charge is too large, the latter half of charging is not performed properly, causing an error. Therefore, it is desirable that the amount of charge be as close to an appropriate value as possible. By doing in this way, it can be made hard to be influenced by a leak, noise, etc., and an improvement in operation accuracy is realized. Therefore, the A / D conversion circuit 1 executes D range adjustment processing having the contents described below.

  First, the control circuit 17 closes the open / close switch 14c, opens the open / close switches (14d, 14e), and controls the signal selection circuit 12 to selectively output the first reference voltage signal Sr1. As a result, charging of the integrating circuit 14 is started with a current corresponding to the first reference voltage signal Sr1.

  When the charging is started, the control circuit 17 starts counting time using the counter 17b and monitors the output signal Sc2 of the comparator 16. The voltage Vref2 at the inverting input terminal of the comparator 16 is set so as to correspond to a predetermined target value (specifically, the above-described aptitude value). Therefore, the level of the output signal Sc2 changes when the amount charged in the integrating circuit 14 reaches the target value.

  The control circuit 17 counts the time until the level of the output signal Sc2 changes (until the amount charged in the integration circuit 14 reaches the target value). The control circuit 17 sets the time represented by the count result Nt as the set time Tdreng. As a result, the newly set time Tdreng is valid in the subsequent offset detection process and the charging process in the actual conversion process.

  The control circuit 17 opens the open / close switch 14c and closes the open / close switch 14d after the level of the output signal Sc2 changes. Thereby, the discharge for the charged part is started. At this time, the control circuit 17 monitors the output signal Sc1 of the comparator 15, and discharges until the level of the output signal Sc1 changes. When discharging is performed until the level of the output signal Sc1 changes, the next offset detection process is started.

  As described above, according to the D range adjustment process, in the charging process when the first reference voltage signal Sr1 is input to the integrating circuit 14 for the set time Tdreng, the charge amount becomes substantially equal to the target value. Therefore, according to the A / D conversion circuit 1, compared with the case where the set time is fixed, the charge amount in the charging process can be brought close to the target value, and the charging process can be performed appropriately.

  This point will be described more specifically with reference to FIG. 2 and FIG. 2 and 3 illustrate timing charts of the output voltage Vo of the integration circuit 14 when the A / D conversion process is performed on the first reference voltage signal Sr1. The voltage Vo corresponds to the amount of charge in the integrating circuit 14.

  FIG. 2 is a graph of a case where the set time is assumed to be fixed. In the A / D conversion circuit 1, the RC value in the integration circuit 14 may vary due to quality variations during manufacturing. As shown in FIG. 2, when the RC value is normal (in the case of “RC normal” shown in FIG. 2), the charge amount in the A / D conversion process is set to the target value (the amount corresponding to the voltage Vref2). Almost matches. However, when the RC value is relatively large (in the case of “RC large” shown in FIG. 2), the amount of charge is too small. Conversely, when the RC value is relatively small (“RC small” shown in FIG. 2). In this case, the amount of charge is too large.

  On the other hand, FIG. 3 is a graph of the case where the D range adjustment processing is performed as in the present embodiment. In this case, as shown in FIG. 3, even if the RC value varies, the set time is determined so that the charge amount in the A / D conversion process matches the target value. Therefore, in any case, the charge amount substantially matches the target value, and the charging process can be performed appropriately.

(2) Offset detection process In the A / D conversion process, an offset of the output value may occur due to various factors. In order to perform A / D conversion with high accuracy, it is important to cancel this offset. For this purpose, it is necessary to detect the offset with high accuracy. Therefore, the A / D conversion circuit 1 executes an offset detection process having the contents described below.

  First, the control circuit 17 performs an A / D conversion process (corresponding to offset measurement in a half range) for the second reference voltage signal Sr2, and acquires an output value Na.

  That is, the control circuit 17 closes the open / close switch 14c, opens the open / close switches (14d, 14e), and controls the signal selection circuit 12 so that the second reference voltage signal Sr2 is selectively output. As a result, the second reference voltage signal Sr2 is input to the integrating circuit 14, and charging with a current corresponding to the second reference voltage signal Sr2 is started.

  When this charging is performed for the set time Tdreng, the control circuit 17 opens the open / close switch 14c and closes the open / close switch 14d to start discharging the charged amount. The control circuit 17 uses the counter 17b to count the time from the start of the discharge until the level of the signal Sc1 changes, and obtains the count result as the output value Na.

  Next, the control circuit 17 performs an A / D conversion process (corresponding to the offset measurement in the full range) for the first reference voltage signal Sr1, and acquires the output value Nb.

  That is, the control circuit 17 closes the open / close switch 14c, opens the open / close switches (14d, 14e), and controls the signal selection circuit 12 so that the first reference voltage signal Sr1 is selectively output. As a result, the first reference voltage signal Sr1 is input to the integration circuit 14, and charging with a current corresponding to the first reference voltage signal Sr1 is started.

  When this charging is performed for the set time Tdreng, the control circuit 17 opens the open / close switch 14c and closes the open / close switch 14d to start discharging the charged amount. Further, the control circuit 17 uses the counter 17b to count the time from the start of the discharge until the level of the signal Sc1 changes, and obtains the count result as the output value Nb.

  When acquiring the output value Na and the output value Nb, the control circuit 17 detects an offset based on these two values. As described above, the control circuit 17 detects the offset based on each output value obtained using the reference voltage signals (Sr1, Sr2) having different values. For this reason, the control circuit 17 detects the offset with higher accuracy than a method (a method for detecting an offset based on one output value) according to a general quadruple integration type A / D converter. Is possible.

  This point will be described more specifically with reference to FIGS. 4 and 5. 4 and 5 illustrate graphs of the input / output relationship of the AD conversion process (the horizontal axis represents input and the vertical axis represents output code). In any of the figures, the solid line represents the actual input / output relationship and the broken line represents the input / output relationship recognized.

  FIG. 4 is a graph of a case where an offset is detected by a general quadruple integration type A / D converter. If the output value Nout is obtained for the input Vin, the A / D converter recognizes, for example, a straight line passing through the origin (0, 0) and coordinates (Vin, Nout) as the input / output relationship of the AD conversion process. To do.

  However, as shown in FIG. 4, if the actual input / output relationship is far from the origin, a relatively large error occurs between the recognized input / output relationship and the actual input / output relationship. Therefore, the A / D converter cannot detect the offset with high accuracy.

  On the other hand, FIG. 5 is a graph of a case where an offset is detected by the A / D conversion circuit 1 of the present embodiment. In this case, an output value Na is obtained for the input of the second reference voltage signal Sr2 (referred to as voltage Vr2), and an output value Nb is provided for the input of the first reference voltage signal Sr1 (referred to as voltage Vr1). can get. Then, the control circuit 17 recognizes a straight line passing through the coordinates (Vr2, Na) and the coordinates (Vr1, Nb) as an input / output relationship of AD conversion processing.

  In this case, even if the actual input / output relationship is far from the origin, no significant error occurs between the recognized input / output relationship and the actual input / output relationship. Therefore, the control circuit 17 can detect the offset with high accuracy.

(3) Actual conversion process After completion of the offset detection process described above, the control circuit 17 immediately executes the actual conversion process. That is, the control circuit 17 closes the open / close switch 14c, opens the open / close switches (14d, 14e), and controls the signal selection circuit 12 so that the input voltage signal Sin is selectively output. As a result, the input voltage signal Sin is input to the integrating circuit 14, and charging with a current corresponding to the input voltage signal Sin is started.

  When this charging is performed for the set time Tdreng, the control circuit 17 opens the open / close switch 14c and closes the open / close switch 14d to start discharging the charged amount. Further, the control circuit 17 uses the counter 17b to count the time from the start of the discharge until the level of the signal Sc1 changes.

  The control circuit 17 acquires the count result as an output value Nm. Then, the control circuit 17 performs an offset correction for canceling an offset (an offset detected in advance by the offset detection process) on the output value Nm (digital signal). The control circuit 17 acquires the output value Nm subjected to the offset correction as the input voltage signal Sin after A / D conversion. The A / D converted input voltage signal Sin is output to, for example, an external circuit and used as detection information of the sensor 2.

  As described above, the A / D conversion circuit 1 executes a series of processes when performing A / D conversion of the input voltage signal Sin. Here, in order to make the operation of the A / D conversion circuit 1 easier to understand, the output voltage Vo of the integration circuit 14 when each series of processing is performed, the count by the counter 17b, the output signal Sc1 of the first comparator 15, FIG. 6 illustrates a timing chart regarding the output signal Sc2 of the second comparator 16. Hereinafter, the flow of each process will be described with reference to FIG.

  After the open / close switch 14e is closed and the voltage Vo is adjusted to the voltage Vref1, the control circuit 17 sequentially executes the D range adjustment process, the offset detection process, and the actual conversion process. In the D range adjustment process, charging is performed using the first reference voltage signal Sr1 until the voltage Vo becomes the voltage Vref2, and then discharging is performed until the voltage Vo returns to the voltage Vref1. The time required for this charging is set to the set time Tdreng.

  In the offset detection process, charging is performed for a set time Tdreng using the second reference voltage signal Sr2, and then discharging is performed until the voltage Vo returns to the voltage Vref1. Next, after charging for a set time Tdreng using the first reference voltage signal Sr1, discharging is performed until the voltage Vo returns to the voltage Vref1. An offset is detected based on the count results (output values Na and Nb) of the time taken for these discharges.

  In the actual conversion process, charging is performed for the set time Tdreng using the input voltage signal Sin, and then discharging is performed until the voltage Vo returns to the voltage Vref1. Then, the result of offset correction performed on the count result (output value Nm) of the time taken for the discharge is obtained as the A / D converted input voltage signal Sin.

  As described above, the A / D conversion circuit 1 performs the offset detection process and the offset correction every time the input voltage signal Sin is A / D converted. Therefore, the A / D conversion circuit 1 can detect an offset that can vary depending on the conditions at that time, and can cancel the offset.

[Generate clock signal]
As described above, the clock signal generation circuit 17a cooperates with the OSC circuit 18 to generate a clock signal having a predetermined frequency. Hereinafter, a circuit configuration and a generation method related to generation of a clock signal will be described with reference to the drawings.

  FIG. 7 is a configuration diagram relating to the clock signal generation circuit 17a and its periphery. As shown in the figure, the OSC circuit 18 is a ring oscillator formed by five NOT gates (18a to 18e). Each NOT gate (18a to 18e) is a delay element (an element that causes a delay), and is coupled in a ring shape.

  The ring oscillator operates so as to circulate a pulse signal having a predetermined frequency f while being delayed in each NOT gate (18a to 18e). Note that the number of delay elements is not limited to five, and can be handled in the same manner as long as they are plural and odd.

  In addition, signal transmission lines (19a to 19e) are connected to the connection points between these NOT gates (18a to 18e). The signal transmission line 19a is connected to a connection point between the NOT gate 18a and the NOT gate 18b. The signal transmission line 19b is connected to a connection point between the NOT gate 18b and the NOT gate 18c. The signal transmission line 19c is connected to a connection point between the NOT gate 18c and the NOT gate 18d. The signal transmission line 19d is connected to a connection point between the NOT gate 18d and the NOT gate 18e. The signal transmission line 19e is connected to a connection point between the NOT gate 18e and the NOT gate 18a.

  These signal transmission lines (19a to 19e) play a role of transmitting a pulse signal from the ring oscillator to the clock signal generation circuit 17a. The pulse signal Pa transmitted by the signal transmission line 19a, the pulse signal Pb transmitted by the signal transmission line 19b, the pulse signal Pc transmitted by the signal transmission line 19c, the pulse signal Pd transmitted by the signal transmission line 19d, and the signal transmission line 19e. The pulse signals Pe transmitted by are out of phase with each other due to a delay in the NOT gate. The amount of phase shift is set so that generation of a high-frequency clock signal Ph described later (see FIG. 8) is appropriately performed.

  The clock signal generation circuit 17a includes an FF (flip flop) circuit and the like, and is connected to each signal transmission line (19a to 19e). The clock signal generation circuit 17a generates, for example, a general clock signal (a signal having a frequency f) used for predetermined processing using the pulse signal Pa.

  Further, the clock signal generation circuit 17a uses the pulse signals (Pa to Pe) received via the signal transmission lines (19a to 19e) to generate a high frequency pulse signal Ph having a frequency higher than the frequency f as a counter clock. Generate as a signal.

  More specifically, the clock signal generation circuit 17a uses the FF circuit to generate, as the high frequency pulse signal Ph, a signal whose level changes in response to the rise and fall of each pulse signal (Pa to Pe). .

  FIG. 8 shows a timing chart of each pulse signal (Pa to Pe) and the high frequency pulse signal Ph. As shown in the figure, the high-frequency pulse signal Ph is generated so that the H level and the L level are switched corresponding to all the rising and falling timings of the pulse signals (Pa to Pe). As a result, a pulse signal having a frequency (frequency 5f) five times that of each pulse signal (Pa to Pe) is generated as the high frequency pulse signal Ph.

  As described above, the A / D conversion circuit 1 can obtain a high-frequency counter clock signal by using a ring oscillator. The counter 17b can perform high-accuracy counting using the counter clock signal, thereby improving the accuracy of AD conversion processing.

  According to the configuration of the present embodiment, it is possible to obtain a high-frequency counter clock signal while keeping the frequency of the pulse signal used in the OSC circuit 18 low. When the frequency of the pulse signal used in the OSC circuit 18 is low, the design of the OSC circuit 18 is easier than when it is high, the OSC circuit 18 is less likely to be a noise source, and the power consumption of the OSC circuit 18 is suppressed. This is advantageous in terms of

  In order to generate the high frequency pulse signal Ph as accurately as possible, it is important to make the transmission time of each pulse signal (Pa to Pe) from the OSC circuit 18 to the clock signal generation circuit 17a as uniform as possible. is there. Therefore, it is desirable that the signal transmission lines (19a to 19e) are formed to have the same length.

  FIG. 9 shows an example in which the signal transmission lines (19a to 19e) are formed to have the same length. In the example of this figure, in order to make the length of each signal transmission line (19a-19e), four signal transmission lines (19b-19e) are formed to meander. By adopting a configuration in which all or part of the signal transmission lines are meandered in this way, it becomes easy to make the lengths of the respective signal transmission lines uniform by adjusting the number of meandering times and the width of the meandering portion. .

[Other D range adjustment methods]
As described above, the A / D conversion circuit 1 can adjust the D range (amount of charge in the charging process) by performing the D range adjustment process. Here, as a method of adjusting the D range, there is a method of changing the RC value in the integration circuit 14 in addition to a method of changing the set time as in the D range adjustment processing.

  Specifically, there is a method in which means for changing the resistance value of the resistor 14a or means for changing the capacitance value of the capacitor 14g is provided, and the RC value is adjusted so that the D range is appropriate. . For example, if a trimming circuit for changing the resistance value of the resistor 14a or a trimming circuit for changing the capacitance value of the capacitor 14g is provided, the RC value can be adjusted by the trimming process.

  When using this method, as shown in FIG. 10, if the RC value is too large, the RC value is decreased until it becomes appropriate, and if the RC value is too small, the RC value is increased until it becomes appropriate. Just do it. Thereby, the D range is improved, and the charging process can be performed more appropriately.

[Application to various electronic devices]
The sensor device having the A / D conversion circuit 1 according to the present embodiment can be applied to various electronic devices. Specific examples of the electronic device include a mobile phone (smart phone) A, a portable information terminal (tablet PC) B, a digital still camera C, and a digital video camera D, as shown in FIGS. It is done.

  FIG. 11 is an external view of the mobile phone A. FIG. In terms of appearance, the mobile phone A includes an imaging unit A1 mounted on the front and back of the main body, an operation unit A2 (such as various buttons) that accepts user operations, and a display unit A3 that displays characters and images. Have. The display unit A3 is equipped with a touch panel function for accepting a user's touch operation.

  FIG. 12 is an external view of the portable information terminal B. In terms of appearance, the portable information terminal B has an imaging unit B1 mounted on the front and back of the main body, an operation unit B2 (such as various buttons) that accepts user operations, a display unit B3 that displays characters and video, Have The display unit B3 is equipped with a touch panel function for accepting a user's touch operation. Examples of portable information terminals include notebook PCs and portable game machines in addition to tablet PCs.

  FIG. 13 is an external view of the digital still camera C. FIG. In terms of appearance, the digital still camera C includes an imaging unit C1 that captures a still image, an operation unit C2 that accepts user operations (such as a release button and a zoom lever), and a display unit C3 that displays captured images and a menu screen. Have.

  FIG. 14 is an external view of a digital video camera. The external appearance of the digital video camera D is an imaging unit D1 that captures a moving image, an operation unit D2 that accepts a user operation (such as a shooting start / stop button and a zoom lever), and a display unit that displays a captured image and a menu screen. D3.

  Any of the electronic devices A to D can receive the advantages by mounting the sensor device having the A / D conversion circuit 1 described above.

[Others]
As described above, the A / D conversion circuit 1 includes the reference voltage signal generation circuit 11 that generates each of the reference voltage signals (Sr1, Sr2), and a function unit that performs A / D conversion processing on the input and outputs an output value ( Conversion processing unit). Further, the A / D conversion circuit 1 uses the reference voltage signals (Sr1, Sr2) as the inputs to perform the offset detection process for obtaining the first output values (the output value Na and the output value Nb), and the input voltage signal Sin as the second input A function unit (control unit) that performs an actual conversion process for obtaining an output value (output value Nm) and a process for offset-correcting the second output value based on the first output value; D-convert.

  Further, the reference voltage signal generation circuit 11 generates each reference voltage signal (Sr1, Sr2) so that the fluctuation tendency of the signal value due to an external factor matches the input voltage signal Sin. Therefore, according to the A / D conversion circuit 1, it is easy to perform offset correction appropriately.

  That is, according to the A / D conversion circuit 1, even if the input voltage signal Sin fluctuates due to external factors, the reference voltage signals (Sr1, Sr2) changed in the same tendency are generated. Therefore, for example, the fluctuation can be canceled in the offset correction, and it is easy to appropriately perform the offset correction accordingly.

  The sensor device having the A / D conversion circuit and the sensor of the present invention can be applied to various electronic devices as described above. The A / D conversion circuit of the present invention is not limited to the output signals of various sensors, and can be configured to perform A / D conversion on various analog signals.

  The configuration of the present invention can be variously modified in addition to the above embodiment without departing from the spirit of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be used for A / D conversion circuits for various purposes.

DESCRIPTION OF SYMBOLS 1 A / D conversion circuit 11 Reference voltage signal generation circuit 12 Signal selection circuit 13 Amplifier 14 Integrator 14a, 14b Resistance 14c-14e Open / close switch 14f Operational amplifier 14g Capacitor 15 1st comparator 16 2nd comparator 17 Control circuit 17a Clock signal Generation circuit 17b Counter 18 OSC circuit 18a-18e NOT gate 19a-19e Signal transmission line 2 Sensor A Cellular phone (smart phone)
B Personal digital assistant (tablet PC)
C Digital still camera D Digital video camera A1, B1, C1, D1 Imaging unit A2, B2, C2, D2 Operation unit A3, B3, C3, D3 Display unit

Claims (13)

A reference signal generator for generating a reference signal;
A conversion processing unit that performs A / D conversion processing on the input and outputs an output value;
A control unit that performs a process of obtaining a first output value using the reference signal as the input, a process of obtaining a second output value using the input signal as the input, and a process of offset correcting the second output value based on the first output value And comprising
An A / D conversion circuit for A / D converting the input signal,
The reference signal generator is
The A / D conversion circuit characterized in that the reference signal is generated so that a fluctuation tendency of a signal value due to an external factor matches the input signal. The input signal is input from the sensor,
The reference signal generator is
The A / D conversion circuit according to claim 1, wherein the A / D conversion circuit is formed using an element having the same characteristics as an element constituting the sensor. The input signal is input from the sensor having a predetermined circuit,
The reference signal generator is
The A / D conversion circuit according to claim 2, wherein the A / D conversion circuit is formed using a circuit having the same configuration as the predetermined circuit. The conversion processing unit has an integration circuit,
The A / D conversion process includes
A charging process for performing charging according to the input for a known set time; and
A discharge process for discharging the amount charged by the charge process;
A counting process for counting the time taken for the discharge;
The A / D conversion circuit according to claim 1, wherein the A / D conversion circuit is included. The reference signal generator is
Generating a first reference signal and a second reference signal having different values as the reference signal;
The controller is
The A / D conversion circuit according to claim 4, wherein a first output value is obtained for each of the first reference signal and the second reference signal. The controller is
Perform the range adjustment process before performing the process to obtain the first output value,
The range adjustment process is:
6. The A / D conversion circuit according to claim 4, wherein the charge amount in the charging process when the reference signal is used as the input is a process of approaching a predetermined target value. The range adjustment process is:
It is a process of measuring the time until the amount charged by the charging process reaches the target value when the reference signal is the input, and setting the measured time as the set time. The A / D conversion circuit according to claim 6. A clock generator for generating a clock signal used for the counting;
The clock generator is
A ring oscillator in which a plurality of delay elements that cause a delay are coupled in a ring shape;
A clock signal generation circuit that receives each pulse signal out of phase from each coupling point of the delay elements and generates a high-frequency pulse signal having a higher frequency than the pulse signal as the clock signal using the received signal; ,
8. The A / D conversion circuit according to claim 4, further comprising: The clock signal generation circuit includes:
9. The A / D conversion circuit according to claim 8, wherein a signal whose level changes in response to rising and falling of each pulse signal is generated as the high-frequency pulse signal. The clock generator is
A plurality of signal transmission lines for transmitting each pulse signal from the ring oscillator to the clock signal generation circuit;
10. The A / D conversion circuit according to claim 8, wherein each of the plurality of signal transmission lines is formed to have the same length. 11.   The A / D conversion circuit according to claim 10, wherein at least one of the plurality of signal transmission lines is formed to meander. An A / D conversion circuit according to any one of claims 1 to 11,
A sensor that outputs the input signal to the A / D conversion circuit;
A sensor device comprising:   An electronic apparatus comprising the sensor device according to claim 12.

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