JP2014187635A - Logical operation processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical operation processing unit whose circuit size is small, capable of performing high-speed processing of multistage logical operation processing that is processed with a plurality of clocks.SOLUTION: Multiple cycle logical operation processing is executed with a logic circuit constituted of an input terminal I(0), an output terminal OUT, two sets of dynamic reconfigurable circuits C(0) 110, C(1) 120 to which a clock t is applied, two sets of storage element (register) groups R(0) 130, R(1) 140, and two sets of controllers 150, 160 for allocating reconfiguration circuits.

Description

  The present invention relates to a logical operation processing device that performs complex logical operation processing using a plurality of logical operation processing devices.

  For example, a multi-cycle logical operation processing system consisting of 4 cycles as shown in FIG. 1 is considered using a plurality of logical operation processing devices, and the input / output value I for each cycle unit is set to I (0) to I (3). When the logical operation F is a variable of F (0) to F (3), generally, a logical operation processing system as shown below can be considered.

  For example, as shown in FIG. 5, there are five register groups R (0) to R (4), four logic circuits C (0) to C (3), and five register groups and four logic circuits are provided. In the time chart of clocks t (0), t (1),... Shown in FIG. 6 alternately connected in cascade, R (0) input / output, C (0) input / output, R (1) input / output, General logic for processing in the order of C (1) input / output, R (2) input / output, C (2) input / output, R (3) input / output, C (3) input / output, R (4) input / output It is a processing system (first prior art).

  Further, as shown in FIG. 7, two register groups R (0), R (1), one reconfigurable logic circuit C (0), and one reconfigurable circuit allocation controller are included. One reconfigurable logic circuit C (0) is cascade-connected between two register groups, and a clock t (shown in FIG. 8) has a circuit configuration in which the reconfigurable circuit assignment controller reconfigures the logic circuit. 0), t (1), ..., R (0) input / output, C (0) input / output, R (1) input / output, I (1) values are temporarily saved (saved value storage) ), F (1) allocation (circuit reconfiguration) to C (0), save value setting to R (0) input, and a logical processing system (second prior art) by a reconfigurable circuit that sequentially processes. is there.

  Further, as background art of the present technology, for example, hardware capable of reconfiguring data processing as described in JP 2000-90237 A (Patent Document 1) (field programmable gate array: hereinafter referred to as FPGA) There is a method of using.

  In this publication, as a problem, “the circuit scale of the drawing processing apparatus as a whole is made compact and sufficient high-speed processing is realized” is cited. As a means for solving this problem, “hardware capable of reconfiguring input image data processing” is cited. Hardware (FPGA), using reconfigurable hardware common to both the non-real-time path and the real-time path, and combining the processing logic required for a series of image processing with the non-real-time path and the real-time path The rewrite control means executes rewriting of the FPGA based on the table, and rewrites the FPGA by appropriately combining the modules based on the number of gate conversions of the FPGA. (See abstract).

JP 2000-90237 A

http://en.wikipedia.org/wiki/%E5%8B%95%E7%9A%84%E5%86%8D%E6%A7%8B%E6%88%90

  As in the first prior art, a logic processing system in which a plurality of logic circuits C (0) and register groups R (0) and R (1) are cascade-connected and logically calculated in a tandem manner performs processing in a small number of cycles. It has features that can be done, but on the other hand, the logic scale becomes large. For example, there is a problem that a logic circuit and a register group corresponding to the number of objective logic functions are required, and the scale increases accordingly.

  Further, as in the second prior art, one reconfigurable circuit C (0) is reconfigured with a reconfigurable circuit assignment controller, and a plurality of logics are calculated with one reconfigurable circuit. According to the logic processing system, the logic scale can be reduced and the problems of the general logic processing system can be corrected, but there is a problem that the execution cycle becomes long.

  Also, in Patent Document 1, the processing result of the previous logic circuit is temporarily stored in a storage or the like, and after the logic circuit is reconfigured for the processing of the next logic circuit, the processing result is read from the register and re-executed. Since the process of transferring to the input side of the logic circuit after the configuration is required, there is a problem that the execution cycle becomes long and the processing speed decreases like the logic processing system by the reconfigurable circuit.

  Therefore, the present invention provides a logic operation processing device that has a small circuit scale of the logic operation processing device and has a short execution cycle of multi-cycle logic operation processing that is processed with a plurality of clocks, that is, capable of high-speed processing.

  In order to achieve the above object, the present invention has two sets of dynamically reconfigurable logic circuits and two sets of storage element groups (hereinafter referred to as register groups). Execute the process.

For example, the logical operation processing device of the present invention is:
In a logic circuit that executes multi-cycle logical operation processing processed in a plurality of cycles, two sets of reconfigurable logic circuits and two sets of registers that hold the processing results of the two sets of reconfigurable logic circuits And a control means for alternately changing and controlling the processing functions of the two reconfigurable logic circuits.

  The two reconfigurable logic circuits of the present invention are characterized in that an FPGA (Field Programmable Gate Array) is a component.

  The two reconfigurable logic circuits of the present invention are characterized by being configured by a combination of a dynamically reconfigurable logic circuit and a register group, which is smaller than the number of stages of multi-cycle logical operation processing to be processed.

For example, the logical operation processing device of the present invention is:
In a logic circuit that executes multi-cycle logic operation processing processed in a plurality of cycles,
Reconfigurable first and second logic circuits, first and second register groups holding the processing results of the first and second logic circuits, and the first and second reconfigurable circuits Reconfigurable circuit allocation control means for reconfiguring the logic circuit;
The first and second reconfigurable logic circuits and the first and second register groups are alternately connected in a ring shape,
The reconfigurable circuit allocating control means reconfigures the first and second reconfigurable logic circuits, rewrites and controls the processing functions of the logic circuits alternately, and the first, A multi-cycle logic operation process is performed by the second reconfigurable logic circuit and the first and second register groups.

Further, the logical operation processing device of the present invention is
In a logic operation processing device including a logic circuit that is processed in a plurality of cycles and executes multi-cycle logic operation processing,
First and second reconfigurable circuits, first and second register groups for holding logical processing results of the first and second reconfigurable circuits, and the first and second reconfigurable circuits A first and second reconfigurable circuit allocation controller for changing and reconfiguring the logic processing function of the circuit,
The first and second reconfigurable circuits and the first and second register groups are alternately connected in a ring shape,
The first and second reconfigurable circuit allocation controllers are:
The first reconfigurable circuit C (0) executes a first logical process F (0), the first register group stores and holds the first logical process result, and the second reproduction is performed. Allocation control to reconfigure the possible circuit C (1) into a circuit that executes the second logic process F (1);
The second reconfigurable circuit C (1) executes the second logic processing F (1), the second register group stores and holds the second logic processing result, and the first logic processing F (1). Assign control to reconfigure the reproducible circuit C (0) to a circuit that executes the third logic process F (2);
The first reconfigurable circuit C (0) executes the third logic process F (2), the first register group stores and holds the logic process result, and the second logic circuit C. (1) performs allocation control so as to reconfigure the circuit that executes the fourth logical process F (3);
The second reconfigurable circuit C (1) executes the fourth logic process F (3), the second register group stores and holds the calculation process result,
Control means for controlling the logic processing to repeat a predetermined number of times is provided.

  According to the present invention, it is possible to provide a logical operation processing device that executes multi-cycle logical operation processing with two sets of dynamically reconfigurable circuits (FPGA and the like) and two sets of storage elements (registers and the like). it can. Therefore, the circuit scale of the logical operation processing device can be reduced. For example, the circuit scale can be further reduced by mounting these logic circuits and memory element groups on both surfaces (front and back surfaces) of the substrate.

  In addition, by configuring the two reconfigurable circuits and the memory element (register) group in a circular manner, a series of processing can be performed without interruption, and high-speed processing is possible.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

A model example of multi-cycle logic operation processing is a diagram schematically showing a processing system that receives input I (0), performs multi-cycle logic operation processing F (0) to F (3) consisting of four cycles, and outputs OUT. is there. It is a block diagram which shows the connection relationship of the reconfigurable circuit of the logical operation processing apparatus of this invention, a memory element group, and the controller for reconfiguration circuit allocation. FIG. 3 is a time chart illustrating a process of processing in each unit of the logical operation processing device in FIG. 2. It is a figure which shows the example of mounting to the board of the reconfigurable circuit and memory element group of the logical operation processing apparatus of this invention. It is a block diagram which shows an example of the conventional logical operation processing apparatus. FIG. 6 is a time chart illustrating a process of processing in each unit of the logical operation processing device in FIG. 5. It is a block diagram which shows the other example of the conventional logical operation processing apparatus. It is a time chart explaining the process of the process in each part of the logical operation processing apparatus of FIG.

  Hereinafter, examples will be described with reference to the drawings. In this embodiment, a well-known FPGA is used as the two dynamically reconfigurable circuits, and a register group is assumed as the two storage element groups.

FIG. 1 shows an example of a model of multi-cycle logic operation processing, schematically showing a processing system that receives input I (0), performs multi-cycle logic operation processing F (0) to F (3) consisting of four cycles, and outputs OUT. FIG.
The method described above has been proposed as a method for executing such multi-cycle logic operation processing, but there has been the problem described above.

  In view of the problems, the present invention provides a logical operation processing device having a small logical scale and a short execution cycle. Specific examples thereof will be described below.

  FIG. 2 is a block diagram showing the connection relationship of two dynamic reconfigurable circuits, two register groups, and a reconfigurable circuit allocation controller of the logical operation processing device of the present invention.

  In the figure, a logical operation processing device 100 includes two sets of dynamically reconfigurable circuits 110 and 120 (hereinafter referred to as C (0) and C (1)), two sets of register groups 130 and 140 (hereinafter referred to as R (0), R (1)), and reconfigurable circuit allocation controllers 150 and 160.

The register groups R (0) and R (1) receive clocks t (0) to t (4), respectively, and execute an operation to be described later based on the clocks.
In addition, the register groups R (0) and R (1) respectively reconfigure the input value IN that receives the processing result output from the reconfigurable circuits C (1) and C (0), and the output value of the register group. It has an output terminal OUT that outputs to a possible circuit.

  The output terminal OUT of the register group 130 is connected to the input side of the dynamic reconfigurable circuit 110 (C (0)), and the input terminal IN of the register group 130 is connected to the dynamic reconfigurable circuit 120 (C (1)). ) Connect to the output side. The input terminal IN of the register group 140 is connected to the output side of the dynamically reconfigurable circuit 110 (C (0)), and the output terminal OUT of the register group 140 is the dynamically reconfigurable circuit 120 (C (1)). ) Connect to the input side.

  That is, the register group 140 (R (1)) is arranged between the output side of the dynamically reconfigurable circuit 110 (C (0)) and the input side of the dynamic reconfigurable circuit 120 (C (1)). The register group 130 (R (0)) is arranged between the output side of the dynamic reconfigurable circuit 120 (C (1)) and the input side of the dynamic reconfigurable circuit 110 (C (0)). And it connects so that each may become a cyclic | annular structure.

  For example, when the reconfigurable circuit C (0) executes the arithmetic processing F (0) and stores the processing result in the register group R (1), the reconfigurable circuit allocation controller 160 The circuit of C (1) is reconfigured so as to assign logic for performing the next arithmetic processing F (1). Further, the reconfigurable circuit allocation controller 150 performs reconfiguration when, for example, the reconfigurable circuit C (1) executes the arithmetic processing F (1) and stores the processing result in the register group R (0). The circuit of the possible circuit C (0) is reconfigured so that the logic for performing the next arithmetic processing F (2) is assigned. In the same manner, it has a reconfiguration function for sequentially assigning logic.

  The clock t is given to the register groups 130 and 140 at the next clock t (1),. The clock t is performed by a clock synchronization circuit (not shown) including a clock generator. Details will be described later.

  In this embodiment, the reconfiguration for allocating logic is realized with two reconfigurable circuit allocation controllers, but the above-described reconfiguration may be realized with one reconfigurable circuit allocation controller.

  So-called reconfigurable circuits C (0), C (1), register groups R (0), R (1) so that the logic processing results of the reconfigurable circuits C (0), C (1) circulate. As shown in the figure, they are alternately arranged in an annular shape.

  Then, the logical operation processing by the two reconfigurable circuits C (0) and C (1) is decomposed into processing for each clock, and the target logical functions F (0), F mounted on the logical circuit are divided. (1)... F (m) multi-cycle logic operation processing is executed.

  Next, processing operations such as logical processing, processing result holding, and logical reassignment (reconfiguration) of the logical operation processing device will be described. As a premise, the multi-cycle logic operation processing is decomposed into processing for each clock, and these are set as objective logic functions F (0), F (1)... F (m). Here, m indicates the number of stages of logical operation processing. This clock is performed at the timing shown in FIG.

  FIG. 3 is a diagram illustrating a time chart, in which the horizontal axis indicates time T, the vertical axis indicates a clock of the logical operation processing device, reconfigurable circuits C (0), C (1), and register group R (0 ), R (1), and the processing timing of each of these parts.

  In FIG. 3, first, in the initial state, the reconfigurable circuit allocation controller 150 allocates the reconfigurable circuit C (0) with the logic for performing the processing of F (0). This reconfigurable circuit allocation controller uses a known technique, for example, “dynamic reconfiguration” described in Non-Patent Document 1 described above, and a detailed description thereof is omitted.

  Next, the first clock t (0) is given to the reconfigurable circuits C (0) and C (1) and the register groups R (0) and R (1) (see FIG. 3a). Then, the reconfigurable circuit C (0) receives I (0) output from the register R (0), executes the processing of F (0), and outputs I (1) (FIGS. 3b to 3d). reference). The processing result I (1) at this time is held (stored / stored) in the register group R (1) (see FIGS. 3e to 3f). At the same time, the reconfigurable circuit assignment controller 160 assigns the logic F (1) to the reconfigurable circuit C (1) and reconfigures the reconfigurable circuit (see FIG. 3g).

  When the reconfiguration of the logic circuit C (1) is completed, the next clock t (1) is applied. Then, the reconfigurable circuit C (1) receives I (1) output from the register group R (1), executes the process of F (1), and outputs I (2) (FIG. 3h to FIG. 3). i). The processing result I (2) at this time is held (stored / stored) in the register group R (0) (see FIGS. 3j to k). At the same time, the reconfigurable circuit assignment controller 150 assigns the logic F (2) to the reconfigurable circuit C (0) and reconfigures the reconfigurable circuit (see FIG. 3l).

  When the reconfiguration of the reconfigurable circuit C (0) is completed, the next clock t (2) is given. Then, the reconfigurable circuit C (0) receives I (2) output from the register group R (0), executes the process of F (2), and outputs I (3) (FIG. n). The processing result I (3) at this time is held (stored / stored) in the register group R (1) (see FIGS. 3o to p). At the same time, the reconfigurable circuit assignment controller 160 assigns the logic F (3) to the reconfigurable circuit C (1) and reconfigures the reconfigurable circuit (see FIG. 3q).

  When the reconfiguration of the reconfigurable circuit C (1) is completed, the next clock t (3) is given. Then, the reconfigurable circuit C (1) executes the process of F (3) and outputs OUT (see FIGS. 3r to 3s). The output (OUT) at this time is held (stored / stored) in the register group R (0) (see FIGS. 3 (t) to (u)).

The above-described processing is repeated until the number of stages F (m) of the logical operation processing is completed.
As a result, multi-cycle logic operation processing can be executed with the two reconfigurable circuits C (0) and C (1) and the two register groups R (1) and R (2).

  If the above-described operation is described by a general formula, it can be described as follows. The following n is an integer greater than or equal to 0, and in the initial state, logic for processing F (0) is assigned to the logic circuit C (0). Further, an input I (0) for logical operation processing is given to the input of the register group R (0).

(1) The clock of t (2n) is given to the logic circuits C (0) and C (1) and the register groups R (0) and R (1). As a result, the value on the input side of the register group R (0) is taken into the output side and becomes the input of the logic circuit C (0).
(2) The following processing is performed during the clock from t (2n) to t (2n + 1).
1) The process of F (2n) is performed in the reconfigurable circuit C (0), and the processing result is set on the input side of the register group R (0).
2) The reconfigurable circuit C (1) is reconfigured, and logic for performing the processing of F (2n + 1) is assigned.
(3) The clock of t (2n + 1) is given to the logic circuits C (0) and C (1) and the register groups R (0) and R (1). As a result, the value on the input side of the register group R (1) is taken into the output side and becomes the input of the reconfigurable circuit C (1).
(4) The following processing is performed during the clock from t (2n + 1) to t (2 (n + 1)).
1) The logic circuit C (1) performs logic processing of F (2n + 1), and the processing result is set on the input side of the register group R (1).
2) The reconfigurable circuit C (0) is reconfigured, and logic for performing the processing of F (2 (n + 1)) is assigned.

The processes (1) to (4) are repeated until the process F (m) is completed.
Here, when the processing of F (m) is completed, if m is an odd number, the value input to the register group R (0) is used. If m is an even number, the register group R (1) is used. If the value that is input is taken out, the result of the multi-cycle logic operation processing is taken out.

  FIG. 4 shows a case in which reconfigurable circuits C (0) and C (1) are mounted on both sides (front and back sides) of a single board (circuit board). 2 is a diagram illustrating an example in which register groups R (0) and R (1) that are storage element groups accessible from 110 and 120 are installed. FIG.

  That is, consider a case in which a series of processes including the following processes (A), (B), (C), and (D) are processed by the reconfigurable circuits C (0) and C (2) having the configuration shown in the figure. .

(1) The following is configured as an initial state.
Reconfigurable circuit C (0): Configuration for process (A) Reconfigurable circuit C (1): Configuration for process (B) Output of storage element group (register group) R (0): Process (A) Input

(2) The following processing is performed in units of the first clock.
Reconfigurable circuit C (0): Processing (A)
As a result, the result of the processing (A) is held in the register group R (1).

(3) The following processing is performed in units of the next clock.
Reconfigurable circuit C (1): Inputs the contents of register group R (1) Reconfigurable circuit C (1): Processing (B)
Reconfigurable circuit C (0): Reconfigured to process (C) Thereby, the result of process (B) is held in the register group R (0).

(4) The following processing is performed in units of the next clock.
Reconfigurable circuit C (0): Inputs the contents of register group R (0) Reconfigurable circuit C (0): Processing (C)
Reconfigurable circuit C (1): Reconfiguration for processing (D) Thereby, the result of processing (C) is held in the register group R (1).

(5) The following processing is performed in units of the next clock.
Reconfigurable circuit C (1): Inputs the contents of register group R (1) Reconfigurable circuit C (1): Processing (D)

  Through the above series of processing, the result of the processing (D) is held in the register group R (0).

The relationship between the reconfigurable circuits C (0) and C (1) and the register groups R (0) and R (1) in the above configuration is as follows.
・ Reconfigurable circuit C0
Input: Register group R (1),
Output: Register group R (0)
・ Reconfigurable circuit C (1)
Input: Register group R (0),
Output: Register group R (1)

  According to the embodiment described above, it is possible to reduce the circuit scale of a processing device that performs multi-stage logical operation processing that is processed with a plurality of clocks, and to realize sufficiently high-speed processing.

  In addition, multistage (multi) logic operation processing that is processed with a plurality of clocks can be realized with two sets of dynamically reconfigurable logic circuits (for example, FPGA) and two sets of registers.

  Further, by arranging the reconfigurable circuit and the memory element group on both sides of the board, the mounting density can be increased and the scale of the logic circuit can be reduced.

  In addition, this invention is not limited to the Example mentioned above, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  The present invention can also be applied to a logic verification board vendor using reconfigurable logic such as FPGA.

110, 120 (C (0), C (1)) Reconfigurable circuit 130, 140 (R (1), R (2)) Storage element group (register group)
150, 160 Reconfigurable circuit allocation controller (control means)
t clock 400 board

Claims (6)

  In a logic circuit that executes multi-cycle logical operation processing processed in a plurality of cycles, two sets of reconfigurable logic circuits and two sets of registers that hold the processing results of the two sets of reconfigurable logic circuits A logic operation processing device comprising: logic circuits alternately connected in a ring shape; and control means for alternately changing and controlling the processing functions of the two reconfigurable logic circuits.   2. The logical operation processing apparatus according to claim 1, wherein the two reconfigurable logic circuits include an FPGA (field programmable gate array) as a constituent element.   2. The two reconfigurable logic circuits are configured by a combination of a dynamically reconfigurable logic circuit and a register group, which is less than the number of stages of multi-cycle logical operation processing to be processed. Logic processing unit. In a logic circuit that executes multi-cycle logic operation processing processed in a plurality of cycles,
Reconfigurable first and second logic circuits, first and second register groups holding the processing results of the first and second logic circuits, and the first and second reconfigurable circuits Reconfigurable circuit allocation control means for reconfiguring the logic circuit;
The first and second reconfigurable logic circuits and the first and second register groups are alternately connected in a ring shape,
The reconfigurable circuit allocating control means reconfigures the first and second reconfigurable logic circuits, rewrites and controls the processing functions of the logic circuits alternately, and the first, A logic operation processing apparatus, wherein a multi-cycle logic operation process is performed by a second reconfigurable logic circuit and the first and second register groups. In a logical operation processing device including a logic circuit that is processed with a plurality of clocks and executes multi-cycle logical operation processing,
The first and second reconfigurable circuits, the first and second storage element groups holding the logical processing results of the first and second reconfigurable circuits, and the first and second logic circuits. Reconfigurable circuit allocating means for changing and reconfiguring the logic processing function,
The first and second reconfigurable circuits and the first and second memory element groups are alternately connected in a ring shape,
The reconfigurable circuit allocating means includes:
The first reconfigurable circuit performs a first logical process, the first storage element group stores and holds the first logical process result, and the second reconfigurable circuit includes the first logical process. Reconfigured to assign the logic to process
The second reconfigurable circuit executes the first logical processing, the second storage element group stores and holds the second logical processing result, and the first reconfigurable circuit includes the first logical processing. Reconfigured to perform 2 logic processing,
The first reconfigurable circuit performs a second logical process, the first storage element group stores and holds the logical process result, and the second reconfigurable circuit performs a third logical process. Reconfigure to assign logic,
The second reconfigurable circuit executes the third logic process, and the second storage element group stores and holds the calculation processing result;
A logical operation processing apparatus comprising control means for controlling the logical processing to repeat a predetermined logical number of times.   6. The first and second reconfigurable circuits include an FPGA (Field Programmable Gate Array) as a component, and the first and second storage element groups are register groups. Logical operation processing device.

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