JP2014183228A - Semiconductor device and manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device designed such that the surface area of a floating gate can be increased and the coupling ratio of a nonvolatile memory cell can be improved without relying on the width of an active area, and to provide a manufacturing method therefor.SOLUTION: In a semiconductor device 1 selectively having nonvolatile memory cells 20 on a semiconductor substrate 2, a trench 10 formed on the semiconductor substrate 2 has a projection part 13 projecting upward beyond the surface of the semiconductor substrate 2. A memory cell area 3 of the semiconductor substrate 2 has: an element separation part 5 sectioning an active area 6; and a floating gate 26 arranged in the active area 6 and selectively having portions 26a overlapping the element separation part 5. The floating gate 26 is formed in a dented shape with respect to the overlapping portions 26a.

Description

  The present invention relates to a semiconductor device including a nonvolatile memory cell and a manufacturing method thereof.

  Patent Document 1 discloses a nonvolatile memory type semiconductor device having a control gate and a floating gate in which a logic circuit is embedded. In the semiconductor device, a plurality of field oxide film isolation regions are formed by a LOCOS method or the like. A memory cell and a select transistor for the memory cell are formed in one element formation region between the isolation regions.

JP-A-9-283634

  As a method of improving the writing speed and erasing speed of the floating gate type nonvolatile memory, there are a method of reducing the width of the active region and a method of improving the coupling ratio by increasing the surface area of the floating gate. However, since the size of the width of the active region is restricted by the design rule at the time of design, it is desired to improve the coupling ratio.

  An object of the present invention is to provide a semiconductor device that can increase the surface area of a floating gate and improve the coupling ratio of a nonvolatile memory cell regardless of the width of an active region, and a method for manufacturing the same.

  In order to achieve the above object, the invention according to claim 1 is a semiconductor device that selectively includes a nonvolatile memory cell on a semiconductor substrate, and is formed in a trench formed in the semiconductor substrate rather than a surface of the semiconductor substrate. An element isolation portion that is embedded so as to protrude upward and divides an active region in the region for the nonvolatile memory cell of the semiconductor substrate, and a portion that is disposed in the active region and overlaps the element isolation portion is selected. The floating gate is a semiconductor device having a shape recessed with respect to the overlap portion.

  According to this configuration, the element isolation portion is embedded so as to protrude above the surface of the semiconductor substrate, and the floating gate is formed so as to overlap the element isolation portion. As a result, the floating gate is formed in a recessed shape with respect to the overlapped portion, and thus has a larger surface area than a floating gate that does not have a recess. As a result, the coupling ratio of the floating gate is improved, and the writing speed and erasing speed characteristics of the semiconductor device can be improved.

According to a second aspect of the present invention, a plurality of the active regions are formed so as to be adjacent to each other with the element isolation portion interposed therebetween, and the floating gates on the active regions adjacent to each other share a common end portion. The semiconductor device according to claim 1, wherein the semiconductor device overlaps the element isolation portion.
With this configuration, the same effects as those described in relation to the invention of claim 1 can be obtained in a plurality of floating gates. Further, since the element isolation portion is shared by a plurality of floating gates, the memory cell can be miniaturized.

According to a third aspect of the present invention, in the floating gate, the end portion overlaps both of the element isolation portions arranged on both sides thereof, and a concave surface is formed in a central portion sandwiched between the both end portions. The semiconductor device according to claim 2, wherein the semiconductor device is formed.
According to a fourth aspect of the present invention, the portion of the element isolation portion that protrudes above the surface of the semiconductor substrate may have a side surface that is perpendicular to the surface of the semiconductor substrate. Alternatively, as in the fifth aspect of the invention, the element isolation portion may include an STI (Shallow Trench Isolation) structure in which the trench is backfilled with an insulating material.

By forming various element isolation portions as in these configurations, the same effects as those described in relation to the invention of claim 1 can be obtained.
The invention according to claim 6 is the semiconductor device according to any one of claims 1 to 5, wherein the width of the active region is 0.13 μm or more.
In this configuration, it is possible to reduce the width of the active region while ensuring the surface area of the floating gate. As a result, it is possible to improve the write / erase characteristics of the semiconductor device while miniaturizing the semiconductor device.

  According to a seventh aspect of the present invention, the semiconductor device further includes another semiconductor element formed outside the region for the nonvolatile memory cell of the semiconductor substrate, and the element isolation portion includes the other element. An active region may be further partitioned in the region for the semiconductor element. Further, as in the invention according to claim 8, even if the protruding amount of the element isolation portion in the region for the other semiconductor element is smaller than the protruding amount of the element isolation portion for the nonvolatile memory cell. Good. According to a ninth aspect of the present invention, the other semiconductor element may include a CMOS transistor.

  The invention according to claim 10 is a method of manufacturing a semiconductor device which selectively includes a nonvolatile memory cell on a semiconductor substrate, and divides an active region into the region for the nonvolatile memory cell of the semiconductor substrate. As described above, a step of forming a trench in the semiconductor substrate, a step of embedding an element isolation part in the trench so as to protrude above the surface of the semiconductor substrate, and a selective overlap with the element isolation part As described above, a method for manufacturing a semiconductor device includes a step of forming a floating gate in the active region.

With this configuration, it is possible to manufacture a semiconductor device having the same effects as those described in relation to the invention of claim 1.
According to an eleventh aspect of the present invention, the step of embedding the element isolation portion includes a step of forming a sacrificial film having an opening for selectively exposing the trench on the surface of the semiconductor substrate, A step of embedding a material from the trench to the opening of the sacrificial film; and after embedding the element isolation portion, removing the sacrificial film, thereby removing a part of the element isolation portion embedded in the opening The method of manufacturing a semiconductor device according to claim 10, further comprising a step of remaining as a protruding portion with respect to the surface of the semiconductor substrate.

In this configuration, an element isolation portion having a portion protruding from the surface of the semiconductor substrate can be easily formed.
The sacrificial film may be formed prior to the formation of the trench, and the step of forming the trench may include the step of forming the trench by etching from the opening of the sacrificial film. It is a manufacturing method of the semiconductor device of Claim 11 containing.

In this configuration, since a common sacrificial film can be used in the trench formation process and the element embedding material embedding process, the manufacturing process can be simplified and the cost can be reduced.
Further, as in the invention described in claim 13, the sacrificial film may be made of a material having an etching selectivity with respect to the element isolation portion, and in the invention described in claim 14, the The element isolation part may be made of silicon oxide, and the sacrificial film may be made of silicon nitride.

  In these configurations, when the sacrificial film is removed by etching, the protruding portion of the element isolation portion can be prevented from being etched together with the sacrificial film. Thus, the protruding portion can be reliably left after the sacrificial film is removed.

FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view as seen from each cutting plane line in FIG. FIG. 3 is a cross-sectional view as seen from each cutting plane line in FIG. FIG. 4 is a cross-sectional view of the semiconductor device for explaining the coupling ratio. FIG. 5 is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device. FIG. 6 is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device. FIG. 7 is a diagram showing the next manufacturing process after FIG. FIG. 8 is a diagram showing a manufacturing process subsequent to FIG. FIG. 9 is a diagram showing a manufacturing process subsequent to FIG. FIG. 10 is a diagram showing a manufacturing process subsequent to FIG. FIG. 11 is a diagram showing a manufacturing process subsequent to FIG. FIG. 12 is a diagram showing a manufacturing process subsequent to FIG. FIG. 13 is a diagram showing a manufacturing process subsequent to FIG. FIG. 14 is a diagram showing a manufacturing process subsequent to FIG. FIG. 15 is a diagram showing the next manufacturing step after FIG. 13. FIG. 16 is a view showing the next manufacturing step after FIG. FIG. 17 is a view showing the next manufacturing step after FIG. FIG. 18 is a view showing the next manufacturing step after FIG. FIG. 19 is a diagram showing a manufacturing process subsequent to FIG. FIG. 20 is a view showing the next manufacturing step after FIG. FIG. 21 is a view showing the next manufacturing step after FIG. FIG. 22 is a view showing the next manufacturing step after FIG. FIG. 23 is a view showing the next manufacturing step after FIG. 21. FIG. 24 is a view showing the next manufacturing step after FIG. FIG. 25 is a view showing the next manufacturing step after FIG. FIG. 26 is a view showing the next manufacturing step after FIG. FIG. 27 is a view showing the next manufacturing step after FIG. FIG. 28 is a view showing the next manufacturing step after FIG. FIG. 29 is a view showing the next manufacturing step after FIG. 27. FIG. 30 is a view showing the next manufacturing step after FIG. 28. FIG. 31 is a view showing the next manufacturing step after FIG. 29. FIG. 32 is a diagram showing the next manufacturing step after FIG. 30. FIG. 33 is a diagram showing the next manufacturing step after FIG. 31. FIG. 34 is a diagram showing the next manufacturing step after FIG. 32. FIG. 35 is a view showing the next manufacturing step after FIG. 33. FIG. 36 is a diagram showing the next manufacturing step after FIG. 34. FIG. 37 is a view showing the next manufacturing step after FIG. FIG. 38 is a view showing the next manufacturing step after FIG. 36. FIG. 39 is a view showing the next manufacturing step after FIG. FIG. 40 is a view showing the next manufacturing step after FIG. 38.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a plan view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 1A is a plan view showing the memory cell region 3 of the semiconductor device 1, and FIG. 1B is a plan view showing the CMOS region 4 of the semiconductor device 1. 2 is a cross-sectional view as seen from each cutting plane line in FIG. 1 (a). FIG. 2 (a) corresponds to the cutting plane line IIa-IIa, and FIG. 2 (b) shows the cutting plane line. It corresponds to IIb-IIb. 3 is a cross-sectional view as seen from each cutting plane line in FIG. 1 (b). FIG. 3 (a) corresponds to the cutting plane line IIIa-IIIa, and FIG. 3 (b) shows the cutting plane line. It corresponds to IIIb-IIIb.

In the following, first, the memory cell region 3 of the semiconductor device 1 will be described with reference to FIGS. 1A, 2A, and 2B, and then FIGS. 1B and 3A. , (B), the CMOS region 4 of the semiconductor device 1 will be described.
<Memory cell area>
The semiconductor device 1 includes a semiconductor substrate 2 and a memory cell region 3 set on the semiconductor substrate 2. The semiconductor substrate 2 is, for example, a silicon substrate having p-type conductivity.

The memory cell region 3 is partitioned into a plurality of active regions 6 by the element isolation unit 5. The element isolation portion 5 includes a trench 10 formed on the surface of the semiconductor substrate 2 and a buried insulating film 11 buried in the trench 10.
In this embodiment, the trenches 10 are arranged in stripes so that linear line trenches are parallel to each other. The distance between adjacent trenches 10 is, for example, 0.13 μm or more, and preferably 0.17 μm to 0.19 μm. This distance corresponds to the width of each active region 6. Each trench 10 is formed in a taper shape whose width narrows in the depth direction from the opening end to the bottom in a cross-sectional view when cut in the width direction orthogonal to the longitudinal direction (hereinafter simply referred to as “cross-sectional view”). Has been. Moreover, although the trench 10 is a shallow trench having a depth of 0.23 μm to 0.25 μm in this embodiment, the depth can be changed as appropriate.

The buried insulating film 11 is made of silicon oxide (SiO ₂ ), and includes a buried portion 12 accommodated in the trench 10 and a protruding portion 13 formed outside the trench 10 and protruding above the surface of the semiconductor substrate 2. Including one.
The embedded portion 12 is formed in a tapered shape whose width is narrowed following the shape of the trench 10 in a cross-sectional view, and has a side surface inclined with respect to the surface of the semiconductor substrate 2. On the other hand, the projecting portion 13 is formed in a quadrangular shape projecting perpendicularly to the surface of the semiconductor substrate 2 in a cross-sectional view, and has a top surface (flat surface) parallel to the surface of the semiconductor substrate 2 and a vertical surface. It has a side. Further, the protruding amount of the protruding portion 13 is, for example, 0.063 μm to 0.077 μm based on the surface of the semiconductor substrate 2.

Each of the plurality of active regions 6 partitioned by the element isolation unit 5 is provided with one nonvolatile memory cell 20 (EEPROM).
The non-volatile memory cell 20 is arranged so as to face an n-type source region 23 and an n-type drain region 24 formed on the surface portion of the semiconductor substrate 2 at a distance from each other, and a channel region 25 therebetween. A floating gate 26 and a control gate 27 stacked on the floating gate 26 are provided. Silicides 21, 22, and 31 are formed on the surfaces of the n-type source region 23, the n-type drain region 24, and the control gate 27, respectively.

One floating gate 26 is provided in each active region 6. Each floating gate 26 is formed so that both end portions (overlap portion 26 a) in the width direction orthogonal to the longitudinal direction of the active region 6 overlap the protruding portion 13 of the buried insulating film 11.
Thereby, in the floating gate 26, the overlap part 26a on the protrusion 13 is disposed at a relatively high position with respect to the central part 26b on the surface of the semiconductor substrate 2, and the central part 26b is selectively selected. It is depressed. The height difference between the overlap portion 26 a and the central portion 26 b forms a concave surface in which the central portion 26 b is selectively recessed on the top surface (upper surface) of the floating gate 26. In this embodiment, the concave surface is a curved surface having a smooth downward gradient from the overlap portion 26a toward the central portion 26b. For example, the deepest portion is disposed at the center in the width direction of the active region 6. . The concave surface may be, for example, a step surface that is one step lower than the surface of the overlap portion 26a.

  One floating gate 26 having such a shape is provided in each active region 6 as described above. Accordingly, the floating gates 26 are arranged on one side in the width direction and on the opposite side with respect to one element isolation part 5, and these floating gates 26 are embedded in the embedded insulating film 11 (protrusion) of the common element isolation part 5. Part 13).

  The control gate 27 is formed in a straight line extending in the width direction orthogonal to the longitudinal direction of the active region 6. The control gate 27 extends over the plurality of active regions 6 and covers all the floating gates 26 so that the upper surface thereof is flat. That is, the control gate 27 serves as a common electrode for the plurality of nonvolatile memory cells 20.

  Specifically, the control gate 27 is formed so that one surface (lower surface) follows the surfaces of the floating gate 26 and the active region 6. Therefore, the lower surface of the control gate 27 is a convex surface (for example, a curved convex surface) corresponding to the concave surface of the floating gate 26 on the floating gate 26. On the other hand, the other surface (upper surface) of the control gate 27 is formed as a flat surface parallel to the surface of the semiconductor substrate 2 on the floating gate 26.

  Further, both side surfaces of the floating gate 26 and the control gate 27 in the longitudinal direction of the active region 6 are formed flush with each other. Thereby, the laminated structure of the floating gate 26 and the control gate 27 has a planar side surface without a step. That is, these two gates 26 and 27 are accommodated in a region on the same space of the semiconductor substrate 2. By these two gates 26 and 27, variation in threshold voltage of the floating gate 26 is suppressed, and the non-volatile memory cell 20 is miniaturized. Both side surfaces of the floating gate 26 and the control gate 27 are covered with sidewalls 28 made of an insulating material such as silicon nitride.

An n-type source low-concentration layer 29 and an n-type drain low-concentration layer 30 are formed between the n-type source region 23 and the n-type drain region 24 and the floating gate 26, that is, in the region immediately below the sidewall 28, respectively. Has been. Thereby, an LDD (Lightly Doped Drain) structure is formed.
The n-type source low concentration layer 29 and the n-type drain low concentration layer 30 are formed at a lower concentration than the n-type source / drain regions 23 and 24 and are formed by implanting impurity ions shallower than these. It is. The n-type source / drain low concentration layers 29 and 30 are formed in a self-aligned manner with respect to the floating gate 26 and the control gate 27. On the other hand, the n-type source / drain regions 23 and 24 are formed in a self-aligned manner with respect to the sidewall 28.

  A tunnel oxide film 37 is formed on the surface of the semiconductor substrate 2 in the channel region 25 so as to face the floating gate 26. The thickness of the tunnel oxide film 37 is, for example, about 90 mm. The tunnel oxide film 37 allows electrons to pass between the channel region 25 and the floating gate 26 by FN (Fowler-Nordheim) tunneling.

The floating gate 26 and the control gate 27 are insulated by an insulating film. This insulating film is made of, for example, an ONO (oxide film-nitride film-oxide film) structure film (hereinafter referred to as ONO film 36) in which a silicon nitride film is sandwiched between a pair of silicon oxide films. The ONO film 36 is formed so that one surface and the other surface thereof follow the surface of the floating gate 26. Therefore, the ONO film 36 also has a concave surface like the floating gate 26.
<CMOS area>
The semiconductor device 1 includes an HV-CMOS (High Voltage-Complementary Metal Oxide Semiconductor) region 40, an MV-CMOS (Middle Voltage-Complementary Metal Oxide Semiconductor) region 70, and an LV-CMOS (Low Voltage-Complementary Metal Oxide Semiconductor) region 90. Are provided on a common semiconductor substrate 2.

The HV-CMOS region 40, the MV-CMOS region 70, and the LV-CMOS region 90 are separated from each other by the element isolation unit 5. Hereinafter, (1) the HV-CMOS region 40, (2) the MV-CMOS 70 region, and (3) the LV-CMOS region 90 will be described in this order.
(1) HV-CMOS region The HV-CMOS region 40 includes an n-type HV-nMOS 41 and a p-type HV-pMOS 42. The n-type HV-nMOS 41 and the p-type HV-pMOS 42 are separated from each other by an element isolation portion 5 that surrounds them in a rectangular shape. The HV-nMOS 41 and the HV-pMOS 42 are, for example, high breakdown voltage elements whose rated voltage exceeds 5V and is 40V or less.

In the region for the HV-nMOS 41, a deep n-type well 32 is formed along the side of the element isolation portion 5 surrounding the region in a rectangular shape, and in the inner region of the deep n-type well 32, a p-type is formed. A base region 43 is formed. The p-type base region 43 is formed so that the bottom thereof is deeper than the trench 10.
An HV-nMOS gate insulating film 51 is formed on the surface of the semiconductor substrate 2 in the p-type base region 43. The HV-nMOS gate insulating film 51 is formed with a thickness of, for example, 380 to 440 mm. An HV-nMOS gate electrode 52 is formed so as to face the semiconductor substrate 2 with the HV-nMOS gate insulating film 51 interposed therebetween. A silicide 49 is formed on the surface of the HV-nMOS gate electrode 52. Further, both side surfaces of the HV-nMOS gate electrode 52 are covered with sidewalls 53 made of an insulating material such as silicon nitride.

Then, an HV-n type drift region 50, an HV-n type source region 44 and an HV-n type source contact region 47 are formed on one side with respect to the HV-nMOS gate electrode 52, and on the opposite side, an HV− An n-type drift region 50, an HV-n-type drain region 45, and an HV-n-type drain contact region 48 are formed.
The HV-n type drift region 50 is formed in a self-aligned manner with respect to the HV-nMOS gate electrode 52, and the HV-n type source / drain regions 44 and 45 are formed in a self-aligned manner with respect to the sidewall 53. Has been. The HV-n type source / drain contact regions 47 and 48 are formed in the inner regions of the HV-n type source / drain regions 44 and 45, respectively. Silicides are formed on the surfaces of the HV-n type source / drain contact regions 47 and 48, respectively.

In the region for the HV-pMOS 42, similarly to the region for the HV-nMOS 41, a deep n-type well 32 is formed along the side of the element isolation portion 5 surrounding the region in a rectangular shape. An n-type base region 54 is formed in the inner region 32. The n-type base region 54 is formed so that the bottom thereof is deeper than the trench 10.
An HV-pMOS gate insulating film 62 is formed on the surface of the semiconductor substrate 2 in the n-type base region 54. The HV-pMOS gate insulating film 62 is formed with the same thickness as the HV-nMOS gate insulating film 51, for example, a thickness of 380 to 440 mm. An HV-pMOS gate electrode 63 is formed so as to face the semiconductor substrate 2 with the HV-pMOS gate insulating film 62 interposed therebetween. A silicide 60 is formed on the surface of the HV-pMOS gate electrode 63. Further, both side surfaces of the HV-pMOS gate electrode 63 are covered with sidewalls 64 made of an insulating material such as silicon nitride.

Then, an HV-p type drift region 61, an HV-p type source region 55 and an HV-p type source contact region 58 are formed on one side with respect to the HV-pMOS gate electrode 63, and HV− A p-type drift region 61, an HV-p type drain region 56, and an HV-p type drain contact region 59 are formed.
The HV-p type drift region 61 is formed deeper than the HV-n type drift region 50 and is formed in a self-aligned manner with respect to the HV-pMOS gate electrode 63. The HV-p type source / drain regions 55 and 56 are formed at the same depth as the HV-n type source / drain regions 44 and 45, and are formed in a self-aligned manner with respect to the sidewall 64. The HV-p type source / drain contact regions 58 and 59 are formed at the same depth as the HV-n type source / drain contact regions 47 and 48. It is formed in one side area. Silicides are formed on the surfaces of the HV-p type source / drain contact regions 58 and 59, respectively.
(2) MV-CMOS region The MV-CMOS region 70 includes an n-type MV-nMOS 71 and a p-type MV-pMOS 72. The n-type MV-nMOS 71 and the p-type MV-pMOS 72 are separated from each other by an element isolation portion 5 that surrounds them in a rectangular shape. The MV-nMOS 71 and the MV-pMOS 72 are, for example, medium withstand voltage elements having a rated voltage of 2V or more and 5V or less.

  Similar to the region for the HV-nMOS 41, a deep n-type well 32 is formed in the region for the MV-nMOS 71 along the side of the element isolation portion 5 surrounding the region in a rectangular shape. An MV-p type well 73 is formed in the inner region of 32. The MV-p type well 73 has a higher impurity concentration than the p type base region 43 and is shallower than the p type base region 43. For example, the MV-p type well 73 is formed so that the bottom thereof is at the same depth as the bottom of the trench 10. The MV-p type well 73 is formed with the same impurity concentration and the same depth as the HV-p type drift region 61 and the LV-p type well 93 described later.

In the inner region of the MV-p type well 73, an MV-n type source region 74 and an MV-n type drain region 75 are formed along the surface of the semiconductor substrate 2 so as to be spaced from each other. A region between the MV-n type source region 74 and the MV-n type drain region 75 is a channel region of the MV-p type well 73.
An MV-nMOS gate insulating film 77 is formed on the surface of the semiconductor substrate 2 in the region for the MV-nMOS 71. The MV-nMOS gate insulating film 77 is formed thinner than the HV-nMOS gate insulating film 51 described above. The thickness is, for example, 130 to 145 mm. Then, an MV-nMOS gate electrode 78 is formed so as to face the channel region of the MV-nMOS 71 with the MV-nMOS gate insulating film 77 interposed therebetween. Silicide 76 is formed on the surface of the MV-nMOS gate electrode 78. The MV-n type source region 74 and the MV-n type drain region 75 are formed in a self-aligned manner with respect to the MV-nMOS gate electrode 78.

Both side surfaces of the MV-nMOS gate electrode 78 are covered with sidewalls 79 made of an insulating material such as silicon nitride.
In the inner regions of the MV-n type source / drain regions 74 and 75, the MV-n type source contact region 80 and the MV-n type drain contact region 33 are self-aligned with the sidewall 79, respectively. Is formed. Silicides are formed on the surfaces of the MV-n type source / drain contact regions 80 and 33, respectively.

  Similar to the region for the HV-nMOS 41, a deep n-type well 32 is formed in the region for the MV-pMOS 72 along the side of the element isolation portion 5 surrounding the region in a rectangular shape. An MV-n type well 81 is formed in the inner region of 32. The MV-n type well 81 has a higher impurity concentration than the n-type base region 54 and is shallower than the n-type base region 54. For example, the MV-n type well 81 is formed so that the bottom thereof is at the same depth as the bottom of the trench 10. Further, the MV-n type well 81 is formed with the same impurity concentration and the same depth as those of the LV-n type well 101 described later.

In the inner region of the MV-n type well 81, an MV-p type source region 82 and an MV-p type drain region 83 are formed along the surface of the semiconductor substrate 2 so as to be spaced from each other. A region between the MV-p type source region 82 and the MV-p type drain region 83 is a channel region of the MV-n type well 81.
An MV-pMOS gate insulating film 85 is formed on the surface of the semiconductor substrate 2 in the region for the MV-pMOS 72. The MV-pMOS gate insulating film 85 is formed of the same thickness and the same material as the MV-nMOS gate insulating film 77. An MV-pMOS gate electrode 86 is formed so as to face the channel region of the MV-pMOS 72 with the MV-pMOS gate insulating film 85 interposed therebetween. Silicide 84 is formed on the surface of the MV-pMOS gate electrode 86. The MV-p type source region 82 and the MV-p type drain region 83 are formed in a self-aligned manner with respect to the MV-pMOS gate electrode 86.

Both side surfaces of the MV-pMOS gate electrode 86 are covered with sidewalls 87 made of an insulating material such as silicon nitride.
In the inner regions of the MV-p type source / drain regions 82 and 83, the MV-p type source contact region 88 and the MV-p type drain contact region 89 are self-aligned with the sidewall 87. Is formed. Silicides are formed on the surfaces of the MV-p type source / drain contact regions 88 and 89, respectively.
(3) LV-CMOS region The LV-CMOS region 90 includes an n-type LV-nMOS 91 and a p-type LV-pMOS 92. The n-type LV-nMOS 91 and the p-type LV-pMOS 92 are separated from each other by an element isolation portion 5 that surrounds them in a rectangular shape. The LV-nMOS 91 and the LV-pMOS 92 are, for example, low breakdown voltage elements having a rated voltage of less than 2V.

In the region for the LV-nMOS 91 and the region for the LV-pMOS 92, a deep n-type well 140 is formed along the side of the element isolation portion 5 so as to cover these regions collectively. The deep n-type well 140 is formed with the same impurity concentration and the same depth as the n-type base region 54.
In the inner region of the deep n-type well 140 in the region for the LV-nMOS 91, an LV-p-type well 93 is formed along the side of the element isolation portion 5 surrounding the region in a rectangular shape. The LV-p type well 93 is formed with a higher impurity concentration than the p type base region 43 and shallower than the p type base region 43. For example, the LV-p type well 93 is formed so that the bottom thereof is at the same depth as the bottom of the trench 10.

In the inner region of the LV-p type well 93, an LV-n type source region 94 and an LV-n type drain region 95 are formed along the surface of the semiconductor substrate 2 so as to be spaced from each other. A region between the LV-n type source region 94 and the LV-n type drain region 95 is a channel region of the LV-p type well 93.
An LV-nMOS gate insulating film 97 is formed on the surface of the semiconductor substrate 2 in the region for the LV-nMOS 91. The LV-nMOS gate insulating film 97 is formed thinner than the MV-nMOS gate insulating film 77 described above. The thickness is, for example, 23 to 25 mm. An LV-nMOS gate electrode 98 is formed so as to face the channel region of the LV-nMOS 91 with the LV-nMOS gate insulating film 97 interposed therebetween. A silicide 96 is formed on the surface of the LV-nMOS gate electrode 98. The LV-n type source region 94 and the LV-n type drain region 95 are formed in a self-aligned manner with respect to the LV-nMOS gate electrode 98. Further, both side surfaces of the LV-nMOS gate electrode 98 are covered with sidewalls 99 made of an insulating material such as silicon nitride.

In the inner regions of the LV-n type source / drain regions 94 and 95, the LV-n type source contact region 100 and the LV-n type drain contact region 34 are self-aligned with the sidewall 99, respectively. Is formed. Silicides are formed on the surfaces of the LV-n type source / drain contact regions 100 and 34, respectively.
In the inner region of the deep n-type well 140 in the region for the LV-pMOS 92, the LV-n well 101 is formed along the side of the element isolation portion 5 surrounding the region in a rectangular shape. The LV-n type well 101 has a higher impurity concentration than the n-type base region 54 and is shallower than the n-type base region 54. For example, the LV-n type well 101 is formed so that the bottom thereof is at the same depth as the bottom of the trench 10.

In the inner region of the LV-n type well 101, an LV-p type source region 102 and an LV-p type drain region 103 are formed at a distance from each other along the surface of the semiconductor substrate 2. A region between the LV-p type source region 102 and the LV-p type drain region 103 is a channel region of the LV-n type well 101.
An LV-pMOS gate insulating film 105 is formed on the surface of the semiconductor substrate 2 in the region for the LV-pMOS 92. The LV-pMOS gate insulating film 105 is formed with the same thickness and the same material as the LV-nMOS gate insulating film 97. An LV-pMOS gate electrode 106 is formed so as to face the channel region of the LV-pMOS 92 with the LV-pMOS gate insulating film 105 interposed therebetween. Silicide 104 is formed on the surface of the LV-pMOS gate electrode 106. The LV-p type source region 102 and the LV-p type drain region 103 are formed in a self-aligned manner with respect to the LV-pMOS gate electrode 106. Further, both side surfaces of the LV-pMOS gate electrode 106 are covered with sidewalls 107 made of an insulating material such as silicon nitride.

  The LV-p type source contact region 108 and the LV-p type drain contact region 109 are self-aligned with the sidewall 107 in the inner regions of the LV-p type source / drain regions 102 and 103, respectively. Is formed. Silicides are formed on the surfaces of the LV-p type source / drain contact regions 108 and 109, respectively.

An interlayer insulating film 110 is stacked on the semiconductor substrate 2 so as to cover the memory cell region 3 and the CMOS region 4 described above. Interlayer insulating film 110 is made of an insulating material such as silicon oxide, for example.
A plurality of wirings 111 made of a conductive material such as aluminum are formed on the interlayer insulating film 110. The plurality of wirings 111 are connected to the n-type source region 23, the n-type drain region 24, the HV-n-type source contact region 47, the HV-n-type drain contact region 48, via a contact plug 113 that penetrates the interlayer insulating film 110. HV-p type source contact region 58, HV-p type drain contact region 59, MV-n type source contact region 80, MV-n type drain contact region 33, MV-p type source contact region 88, MV-p type drain The contact region 89, the LV-n type source contact region 100, the LV-n type drain contact region 34, the LV-p type source contact region 108, and the LV-p type drain contact region 109 are connected to each other.

A surface protective film 118 made of an insulating material such as silicon nitride is formed on the interlayer insulating film 110 so as to cover each wiring 111.
Each operation of writing, erasing and reading information on the nonvolatile memory cell 20 can be performed as follows.
For example, electrons are injected into the floating gate 26 when a positive voltage is applied to the control gate 27 and the n-type drain region 24 in a state where the n-type source region 23 is at the ground potential, the tunnel oxide film 37 from the n-type source region 23. Electrons are injected into the floating gate 26 by FN tunneling via.

For example, when the n-type drain region 24 is open, a negative voltage is applied to the control gate 27 and a positive voltage is applied to the n-type source region 23. Electrons are extracted to the n-type source region 23 by FN tunneling through the tunnel oxide film 37.
When electrons are injected into the floating gate 26, the threshold voltage to be applied to the control gate 27 in order to make the nonvolatile memory cell 20 conductive when the floating gate 26 is charged increases. Therefore, the read voltage to be applied to the control gate 27 is maintained between the n-type source region 23 and the n-type drain region 24 when the floating gate 26 is in an uncharged state (a state where electrons are extracted), and The value is set so that the n-type source region 23 and the n-type drain region 24 can be electrically connected when the floating gate 26 is in a charged state (electron-injected state). At this time, whether or not electrons are injected into the floating gate 26 can be discriminated by examining whether or not current flows on the source side. In this manner, information writing, erasing and reading operations can be performed on the nonvolatile memory cell 20.

Next, writing, erasing and reading characteristics of information with respect to the nonvolatile memory cell 20 will be described based on a coupling ratio which can be derived from the configuration of the floating gate 26 and the element isolation portion 5.
FIG. 4 is a cross-sectional view of the semiconductor device 1 for explaining the coupling ratio.
As shown in FIG. 2B, in the nonvolatile memory cell 20 of this embodiment, both ends (overlap portion 26a) of the floating gate 26 are overlapped with the protruding portion 13 of the buried insulating film 11, thereby floating. The gate 26 is recessed to form a concave surface. With this configuration, the coupling ratio of the nonvolatile memory cell 20 is improved.

  For example, according to the conventional configuration, since the buried insulating film 11 is almost completely buried in the trench 10 formed in the semiconductor substrate 2, the protruding portion 13 is not formed in the buried insulating film 11. That is, the protruding amount D of the buried insulating film 11 with respect to the semiconductor substrate 2 is close to zero (that is, D≈0 in FIG. 4). At this time, if the dimension of the floating gate 26 (surface distance between both ends in the width direction) is A, the thickness of the floating gate 26 is B, and the width of the active region 6 is C, the conventional coupling ratio Z is x Can be expressed as the following equation (1).

Z = x (A + 2B) / C (1)
On the other hand, according to the configuration of this embodiment, the buried insulating film 11 protruding by the protruding amount D is formed to such an extent that a concave surface can be formed in the floating gate 26. As a result, the top surface of the floating gate 26 becomes concave, and the dimension can be made longer than the dimension A of the conventional floating gate 26. That is, if the dimension of the floating gate 26 of this embodiment is A ′, the coupling ratio Z ′ can be expressed as the following equation (2).

Z ′ = x (A ′ + 2B) / C (2)
Comparing the above equations (1) and (2), the dimension A ′ of the floating gate 26 of this embodiment is larger than the dimension A of the conventional floating gate 26 (ie, A ′> A). The coupling ratio Z ′ of this embodiment has a larger value than the conventional coupling ratio Z (that is, Z ′> Z).

  Accordingly, in this nonvolatile memory cell 20, by forming the floating gate 26 having a concave surface, the surface area of the floating gate 26 can be increased and the coupling ratio can be improved without being restricted by the design rules at the time of design. it can. That is, the coupling ratio of the floating gate 26 can be improved regardless of the width of the active region 6. As a result, the writing speed and erasing speed characteristics of the semiconductor device 1 can be improved.

In addition, since the element isolation portion 5 is shared by the plurality of floating gates 26, the nonvolatile memory cell 20 can be miniaturized.
Next, the manufacturing process of the semiconductor device 1 will be described with reference to FIGS.
5 to 40 are cross-sectional views for explaining an example of the manufacturing process of the semiconductor device 1 of the present invention in the order of processes. 5 to 40, the odd-numbered drawings as shown in FIGS. 5, 7, and 9 show the process of the memory cell region 3, and the even-numbered drawings as shown in FIGS. 6, 8, and 10 are the CMOS region. 4 steps are shown.

  To manufacture the semiconductor device 1, as shown in FIGS. 5 and 6, a pad oxide film 114 is formed on the surface of the semiconductor substrate 2 by, for example, a thermal oxidation method, and then the pad oxide film 114 by, for example, a CVD method. A hard mask 120 as an example of the sacrificial film of the present invention is formed thereon. The thickness of the pad oxide film 114 is, for example, about 125 mm. The hard mask 120 is formed of a silicon nitride film having a thickness of about 800 mm, for example.

  Next, as shown in FIGS. 7 and 8, the hard mask 120 and the pad oxide film 114 are selectively etched in order to selectively form an opening in a region where the trench 10 is to be formed. Then, an etching gas is supplied to the semiconductor substrate 2 through this opening. Etching gas advances from the opening toward the depth direction of the semiconductor substrate 2, and a trench 10 having a tapered cross-sectional view is formed simultaneously in the memory cell region 3 and the CMOS region 4.

  Next, as shown in FIGS. 9 and 10, the trench 10 is backfilled by deposition of silicon oxide. The silicon oxide is deposited by, for example, a P-CVD (Plasma-Enhanced Chemical Vapor Deposition) method or an HDP-CVD (High-Density Plasma Chemical Vapor Deposition) method. The HDP-CVD method is preferable. The openings of the trench 10 and the hard mask 120 are backfilled with silicon oxide, and the hard mask 120 is completely covered with silicon oxide.

  Thereafter, unnecessary portions of the silicon oxide (portions outside the openings of the trench 10 and the hard mask 120) are removed by a CMP (Chemical Mechanical Polishing) method. CMP is continued until the surface of the hard mask 120 and the surface of the buried oxide film (polishing surface) are flush with each other. Thereby, the buried insulating film 11 is buried so as to fill the openings of the trench 10 and the hard mask 120, and the element isolation portion 5 is formed. In this step, in order to uniformly and uniformly bury silicon oxide in the trench 10, for example, thinning by RIE (Reactive Ion Etching) method and deposition by P-CVD method or HDP-CVD method are used. The silicon oxide may be deposited while alternately repeating the above.

  After the formation of the element isolation portion 5, as shown in FIGS. 11 and 12, in the memory cell region 3, the hard mask 120 is completely removed from the pad oxide film 114 by etching or the like. As a result, a part of the buried insulating film 11 buried in the opening of the hard mask 120 remains as the protruding portion 13 protruding from the surface of the pad oxide film 114 (semiconductor substrate 2). The remaining protrusion 13 is formed to have a side surface perpendicular to the surface of the semiconductor substrate 2.

  At this time, since the silicon nitride constituting the hard mask 120 has an etching selectivity with respect to the silicon oxide constituting the buried insulating film 11, the etching rate of the buried insulating film 11 is slower than that of the hard mask 120. can do. Therefore, when the hard mask 120 is etched, the etching amount (scraping amount) of the buried insulating film 11 can be suppressed, so that the shape of the buried insulating film 11 can be maintained substantially the same as before the etching. Thereby, it is possible to suppress a decrease in the protruding amount D (see FIG. 4) of the protruding portion 13 of the buried insulating film 11. In addition, since the common hard mask 120 can be used in the process of forming the trench 10 and the process of embedding the buried insulating film 11 in the trench 10, the manufacturing process can be simplified and the cost can be reduced.

  On the other hand, in the CMOS region 4, the buried insulating film 11 remaining in the opening of the hard mask 120 is also removed together with the hard mask 120. At this time, the buried insulating film 11 is formed so that the surface thereof is flush with the surface of the semiconductor substrate 2. Similar to the buried insulating film 11 in the memory cell region 3, the protruding portion 13 may be formed in the buried insulating film 11 in the CMOS region 4.

Next, in the HV-CMOS region 40 and the MV-CMOS region 70, an n-type impurity ion is used in a region where the deep n-type well 32 is to be formed using a resist film, a silicon oxide film or the like as a mask (not shown). Are selectively injected. For example, arsenic (As ⁺ ) ions or phosphorus (P ⁺ ) ions are used as n-type impurity ions. Thereby, the deep n-type well 32 is formed.

Next, in the HV-CMOS region 40 and the LV-CMOS region 90, a resist film, a silicon oxide film, or the like is used as a mask (not shown) in each region where the n-type base region 54 and the deep n-type well 140 are to be formed. N-type impurity ions are selectively implanted. For example, arsenic (As ⁺ ) ions or phosphorus (P ⁺ ) ions are used as n-type impurity ions. Thereby, the n-type base region 54 and the deep n-type well 140 are simultaneously formed.

Next, in the HV-CMOS region 40, p-type impurity ions are selectively implanted into a region where the p-type base region 43 is to be formed using a resist film, a silicon oxide film, or the like as a mask (not shown). The For example, boron (B ⁺ ) ions are used as p-type impurities. Thereby, the p-type base region 43 is formed.
Next, as shown in FIGS. 13 and 14, a hard mask 122 is formed over the entire surface of the semiconductor substrate 2 by, for example, a CVD method. The hard mask 122 is formed of a silicon nitride film having a thickness of about 300 mm, for example. After the hard mask 122 is formed, an oxide film 123 is formed on the surface of the hard mask 122. The oxide film 123 can be formed by oxidizing the surface of the hard mask 122 made of silicon nitride, for example, by a thermal oxidation method. Note that the oxide film 123 may be formed by a CVD method.

Next, as shown in FIGS. 15 and 16, the oxide film 123, the hard mask 122, and the pad oxide film 114 on the memory cell region 3 and the HV-CMOS region 40 are selectively removed by etching, for example. . Thereby, the surface of the semiconductor substrate 2 is exposed in the memory cell region 3 and the HV-CMOS region 40.
Next, as shown in FIGS. 17 and 18, the semiconductor substrate 2 is thermally oxidized with the MV-CMOS region 70 and the LV-CMOS region 90 covered with the hard mask 122. Thereby, a tunnel oxide film 37 is formed on the surface of the semiconductor substrate 2 in the memory cell region 3 and the HV-CMOS region 40 that are not covered with the hard mask 122. Next, a polysilicon film 115 to which impurity ions (for example, phosphorus (P ⁺ ) ions) are added is deposited on the semiconductor substrate 2. The thickness of the polysilicon film 115 is, for example, about 700 mm.

Next, as shown in FIGS. 19 and 20, in the memory cell region 3, the polysilicon film 115 on the element isolation portion 5 is selectively removed. As a result, a floating gate 26 having an overlap portion 26 a that overlaps the protruding portion 13 of the buried insulating film 11 and a central portion 26 b that is selectively recessed is formed.
Next, as shown in FIGS. 21 and 22, a three-layer ONO film 36 is formed by sequentially stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film on the semiconductor substrate 2. Next, a protective film 126 is formed on the ONO film 36. The protective film 126 is made of, for example, silicon nitride and is formed thinner than the hard mask 122 that covers the MV-CMOS region 70 and the LV-CMOS region 90. For example, the protective film 126 is about 100 mm, and the hard mask 122 is 300 mm.

Next, a thermal oxidation process for the CMOS region 4 is performed. Specifically, thermal oxidation of the HV-CMOS region 40, the MV-CMOS region 70, and the LV-CMOS region 90 is performed in this order.
First, gate oxidation for the HV-CMOS region 40 is performed. As shown in FIGS. 23 and 24, the protective film 126, the ONO film 36, and the polysilicon film 115 covering the HV-CMOS region 40 are selectively removed. At this time, also in the MV-CMOS region 70 and the LV-CMOS region 90, the protective film 126, the ONO film 36, and the polysilicon film 115 on the hard mask 122 are removed. Next, the surface of the semiconductor substrate 2 is exposed in the HV-CMOS region 40 by removing the tunnel oxide film 37 in the HV-CMOS region 40. When the tunnel oxide film 37 is removed, the oxide film 123 on the hard mask 122 is removed.

  Next, as shown in FIGS. 25 and 26, the semiconductor substrate 2 is thermally oxidized with the hard mask 122 left in the MV-CMOS region 70 and the LV-CMOS region 90. This thermal oxidation is performed at 900 ° C. to 1000 ° C. for 10 minutes to 30 minutes, for example. Thereby, the HV-nMOS gate insulating film 51 and the HV-pMOS gate insulating film 62 are simultaneously formed in the HV-CMOS region 40 not covered with the hard mask 122, the polysilicon film 115, the ONO film 36, and the like. At this time, the hard mask 122 and the protective film 126 are also oxidized from the surface side, and silicon oxide portions are formed on the respective surface portions. In this embodiment, the thickness of the protective film 126 is about 100 mm. However, if the silicon nitride portion remains below the protective film 126 after the thermal oxidation of the HV-CMOS region 40 (that is, the protective film). If 126 is fully oxidized and not dominated by the silicon oxide portion of the surface), it may be thinner.

Next, hydrofluoric acid (HF) is supplied onto the semiconductor substrate 2 to selectively remove the silicon oxide portions on the surfaces of the hard mask 122 and the protective film 126 and then supply phosphoric acid (H ₃ PO ₄ ). Thus, the hard mask 122 and the protective film 126 covering the MV-CMOS region 70 and the LV-CMOS region 90 are simultaneously removed. At this time, since the protective film 126 is formed thinner than the hard mask 122, the etching time required for removing the protective film 126 can be shorter than the etching time of the hard mask 122. Therefore, the removal of the protective film 126 can be reliably completed when the removal of the hard mask 122 is completed. Thereby, it is possible to prevent the protective film 126 from remaining on the ONO film 36.

  Next, gate oxidation for the MV-CMOS region 70 is performed. Specifically, as shown in FIGS. 27 and 28, the pad oxide film 114 is selectively removed from the MV-CMOS region 70 and the LV-CMOS region 90 exposed by removing the hard mask 122. Then, the exposed surface of the semiconductor substrate 2 in the MV-CMOS region 70 and the LV-CMOS region 90 is thermally oxidized. This thermal oxidation is performed at a lower temperature than the gate oxidation for the HV-CMOS region 40, for example, at 850 ° C. to 950 ° C. for 5 minutes to 10 minutes. Thereby, the MV-nMOS gate insulating film 77 and the MV-pMOS gate insulating film 85 are simultaneously formed in the MV-CMOS region 70. Thereafter, the insulating film 116 formed in the LV-CMOS region 90 is selectively removed by this thermal oxidation.

  Next, gate oxidation for the LV-CMOS region 90 is performed. As shown in FIGS. 29 and 30, the surface of the semiconductor substrate 2 exposed in the remaining LV-CMOS region 90 is thermally oxidized, so that the LV-nMOS gate insulating film 97 and the LV- A pMOS gate insulating film 105 is formed at the same time. This thermal oxidation is performed at a lower temperature than the gate oxidation for the MV-CMOS region 70, and is performed, for example, at 700 ° C. to 800 ° C. for 5 minutes to 10 minutes.

Next, as shown in FIGS. 31 and 32, n-type impurity ions are selectively implanted into regions where MV-n well 81 and LV-n well 101 are to be formed. Thereby, the MV-n type well 81 and the LV-n type well 101 are formed simultaneously.
Next, p-type impurity ions are selectively implanted into regions where the MV-p well 73 and the LV-p well 93 are to be formed. Thereby, the MV-p type well 73 and the LV-p type well 93 are formed simultaneously.

Next, a polysilicon film 117 to which impurity ions (for example, phosphorus (P ⁺ ) ions) are added is deposited on the semiconductor substrate 2. The thickness of the polysilicon film 117 is, for example, about 210 nm.
Next, as shown in FIGS. 33 and 34, this polysilicon film 117 is selectively etched. Thereby, the control gate 27, the HV-nMOS gate electrode 52, the HV-pMOS gate electrode 63, the MV-nMOS gate electrode 78, the MV-pMOS gate electrode 86, the LV-nMOS gate electrode 98 and the LV-pMOS gate electrode 106 are simultaneously formed. It is formed. That is, the gate electrodes 52, 63, 78, 86, 98 and 106 in the CMOS region 4 are formed using the material of the control gate 27.

  Thereafter, tunnel oxide film 37, HV-nMOS gate insulating film 51, HV-pMOS gate insulating film 62, MV-nMOS gate insulating film 77, MV-pMOS gate insulating film 85, LV-nMOS gate insulating film 97 and LV-pMOS Portions of the gate insulating film 105 other than the portions immediately below the gate electrodes 27 (26), 52, 63, 78, 86, 98, and 106 are selectively removed.

  Next, as shown in FIGS. 35 and 36, by selective ion implantation into the semiconductor substrate 2, the n-type source low concentration layer 29, the n-type drain low concentration layer 30, the HV-n type drift region 50, HV -P-type drift region 61, MV-n type source region 74, MV-n type drain region 75, MV-p type source region 82, MV-p type drain region 83, LV-n type source region 94, LV-n A type drain region 95, an LV-p type source region 102, and an LV-p type drain region 103 are formed.

  Next, as shown in FIGS. 37 and 38, the side walls 28, 63, 78, 86, 98, 106 on the side surfaces of the floating gate 26 and the control gate 27 and the side surfaces of the gate electrodes 52, 63, 78, 86, 98, 106 in the CMOS region 4, respectively. 53, 64, 79, 87, 99, 107 are formed simultaneously. The sidewalls 28, 53, 64, 79, 87, 99, and 107 are etched by dry etching after an insulating film such as a silicon nitride film is formed on the entire surface of the semiconductor substrate 2 by, for example, the CVD method. Formed by backing.

  Next, as shown in FIG. 39 and FIG. 40, the n-type source region 23, the n-type drain region 24, the HV-n-type source region 44, and the HV-n-type drain by selective ion implantation into the semiconductor substrate 2. Region 45, HV-n type source contact region 47, HV-n type drain contact region 48, HV-p type source region 55, HV-p type drain region 56, HV-p type source contact region 58, HV-p type Drain contact region 59, MV-n type source contact region 80, MV-n type drain contact region 33, MV-p type source contact region 88, MV-p type drain contact region 89, LV-n type source contact region 100, LV-n type drain contact region 34, LV-p type source contact region 108 and LV-p type drain contact region Tact region 109 is formed.

  Next, the control gate 27, HV-nMOS gate electrode 52, HV-pMOS gate electrode 63, MV-nMOS gate electrode 78, MV-pMOS gate electrode 86, LV-nMOS gate electrode 98, LV-pMOS gate electrode 106, n Type source region 23, n type drain region 24, HV-n type source contact region 47, HV-n type drain contact region 48, HV-p type source contact region 58, HV-p type drain contact region 59, MV-n Type source contact region 80, MV-n type drain contact region 33, MV-p type source contact region 88, MV-p type drain contact region 89, LV-n type source contact region 100, LV-n type drain contact region 34 LV-p type source contact region 108 and Silicide is formed on each surface of the LV-p type drain contact region 109.

  Thereafter, as shown in FIGS. 2 and 3, after the interlayer insulating film 110 is formed, various contact plugs 113 and wirings 111 are formed. Next, a surface protective film 118 made of an insulating material such as silicon nitride is formed so as to cover the interlayer insulating film 110 and each wiring 111 in the memory cell region 3 and the CMOS region 4, and each electrode is formed on the surface protective film 118. Openings (not shown) that are exposed as pads for wire bonding are formed.

Through the above steps, the semiconductor device 1 including the memory cell region 3 and the CMOS region 4 shown in FIGS. 1 to 3 is obtained. Note that a plurality of interlayer insulating films 110 may be stacked.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above-described embodiment, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 is reversed may be employed. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.

A peripheral circuit region in which various elements such as a charge pump, a Zener diode, and a MIS transistor are formed may be set around the memory cell region 3 and the CMOS region 4.
In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Memory cell area | region 4 CMOS area | region 5 Element isolation | separation part 6 Active area | region 10 Trench 11 Embedded insulating film 12 Embedded part 13 Protrusion part 20 Non-volatile memory cell 26 Floating gate 26a Overlapping part 26b Central part 40HV- CMOS region 41 HV-nMOS
42 HV-pMOS
70 MV-CMOS region 71 MV-nMOS
72 MV-pMOS
90 LV-CMOS region 91 LV-nMOS
92 LV-pMOS
120 hard mask

Claims (14)

A semiconductor device that selectively includes a nonvolatile memory cell on a semiconductor substrate,
An element isolation part embedded in a trench formed in the semiconductor substrate so as to protrude above the surface of the semiconductor substrate and partitioning an active region in the region for the nonvolatile memory cell of the semiconductor substrate;
A floating gate that is disposed in the active region and selectively has a portion overlapping the element isolation portion,
The semiconductor device, wherein the floating gate has a recessed shape with respect to the overlap portion. A plurality of the active regions are formed so as to be adjacent to each other with the element isolation portion interposed therebetween,
2. The semiconductor device according to claim 1, wherein the end portions of the floating gates on the active regions adjacent to each other overlap the common element isolation portion.   3. The floating gate according to claim 2, wherein the end portion overlaps both of the element isolation portions arranged on both sides of the floating gate, and a concave surface is formed at a central portion sandwiched between the both end portions. Semiconductor device.   The part which protruded upwards rather than the said surface of the said semiconductor substrate of the said element isolation part has a side surface perpendicular | vertical with respect to the said surface of the said semiconductor substrate. Semiconductor device.   5. The conductor device according to claim 1, wherein the element isolation portion includes an STI (Shallow Trench Isolation) structure in which the trench is backfilled with an insulating material.   The semiconductor device according to claim 1, wherein a width of the active region is 0.13 μm or more. The semiconductor device further includes another semiconductor element formed outside the region for the nonvolatile memory cell of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the element isolation unit further divides an active region into the region for the other semiconductor element.   The semiconductor device according to claim 7, wherein a protrusion amount of the element isolation portion in the other semiconductor element region is smaller than a protrusion amount of the element isolation portion for the nonvolatile memory cell.   The semiconductor device according to claim 7, wherein the other semiconductor element includes a CMOS transistor. A method of manufacturing a semiconductor device that selectively includes a nonvolatile memory cell on a semiconductor substrate,
Forming a trench in the semiconductor substrate so as to partition an active region in the non-volatile memory cell region of the semiconductor substrate;
Embedding an element isolation portion in the trench so as to protrude above the surface of the semiconductor substrate;
Forming a floating gate in the active region so as to selectively overlap the element isolation portion. The step of embedding the element isolation part includes:
Forming a sacrificial film having an opening for selectively exposing the trench on the surface of the semiconductor substrate;
Burying the material of the element isolation part from the trench to the opening of the sacrificial film;
Removing the sacrificial film after embedding the element isolation portion, thereby leaving a part of the element isolation portion embedded in the opening as a protruding portion with respect to the surface of the semiconductor substrate. Item 11. A method for manufacturing a semiconductor device according to Item 10. The sacrificial film is formed prior to the formation of the trench,
The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the trench includes a step of forming the trench by etching from the opening of the sacrificial film.   The method of manufacturing a semiconductor device according to claim 11, wherein the sacrificial film is made of a material having an etching selectivity with respect to the element isolation portion.   The method of manufacturing a semiconductor device according to claim 11, wherein the element isolation portion is made of silicon oxide, and the sacrificial film is made of silicon nitride.

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