JP2014183065A - Latch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To add a sufficient capacitance to a storage node without increasing a chip area.SOLUTION: A slit contact scont1 is provided on a region constituting a first storage node NOD1 connecting an input of a first inverter and an output of a second inverter and has a shape extended in at least a first direction, wherein the first inverter and the second inverter constitute a latch circuit. A slit contact scont2 is provided on a region constituting a second storage node NOD2 connecting an output of the first inverter and an input of the second inverter and has a shape extended in at least the first direction. The slit contact scont1 and the slit contact scont2 face each other along the first direction.

Description

  The present invention relates to a latch circuit.

  Along with miniaturization of semiconductor devices, malfunction due to soft errors has become a problem. A soft error is a phenomenon in which data held in a storage node in an SRAM (Static Random Access Memory) or the like is inverted due to an external factor such as electrons generated by alpha rays emitted from a package or neutron rays from space. It is.

  To solve this soft error problem, a method has been proposed in which the inversion of data due to external factors is reduced by increasing the capacity of the storage node. That is, a method for reducing the occurrence of a soft error by connecting a capacitive element to a storage node has been proposed. However, this method has disadvantages such as an increase in chip area due to the addition of the capacitive element and an increase in manufacturing process costs associated with the addition of the capacitive element.

  On the other hand, Patent Document 1 discloses a semiconductor device in which a gate electrode and a diffusion layer are electrically connected with a metal covering a common contact hole. By forming the transistor Tr below the common contact hole, a capacitive element for improving soft error resistance is realized.

  In Patent Document 2, a static type is provided in an interlayer insulating film, and the interval S1 between a pair of contact holes reaching the source and drain located on both sides of the gate electrode is made smaller than the interval between contact holes on the surface of the interlayer insulating film. A semiconductor memory device is disclosed. Further, Patent Document 2 suggests that when a metal wiring is embedded in an interlayer insulating film, a damascene wiring is employed and a trench for the damascene wiring is expanded laterally.

JP 2002-270701 A JP 2004-128239 A

  However, when a transistor is formed below the common contact hole as in Patent Document 1, a leak current is generated between the gate and well, between the source and well, and between the drain and well of the transistor. When the transistor has a thick film structure in order to avoid a leakage current, a sufficient capacity cannot be obtained.

  Further, as described in Patent Document 2, even when a damascene wiring trench is expanded in the lateral direction, the position of the metal wiring that contributes to the majority of the parasitic capacitance is not changed. A sufficient capacity increase cannot be obtained over the previous capacity.

  In other words, the above-described method has a problem that a sufficient capacity cannot be added to the storage node without increasing the chip area.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the latch circuit includes a first contact having an extended shape on a region constituting the first storage node on the latch circuit, and on the region constituting the second storage node on the latch circuit. A second contact having an elongated shape is provided on the first contact, and the first contact and the second contact face each other.

  According to the embodiment, a sufficient capacity can be added to the storage node without increasing the chip area.

3 is an equivalent circuit diagram of a memory cell having a latch circuit according to the first embodiment; FIG. 2 is a plan view of a memory cell having a latch circuit according to the first embodiment; FIG. 3 is a cross-sectional view of a memory cell having a latch circuit according to the first embodiment; FIG. 3 is a cross-sectional view of a memory cell having a latch circuit according to the first embodiment; FIG. 3 is a cross-sectional view of a memory cell having a latch circuit according to the first embodiment; FIG. 4 is a plan view of a memory cell having a latch circuit according to a second embodiment; FIG. FIG. 4 is a cross-sectional view of a memory cell having a latch circuit according to a second embodiment. FIG. 4 is a cross-sectional view of a memory cell having a latch circuit according to a second embodiment. 7 is a plan view of a memory cell having a latch circuit according to a third embodiment; FIG. FIG. 4 is a cross-sectional view of a memory cell having a latch circuit according to a third embodiment. FIG. 4 is a cross-sectional view of a memory cell having a latch circuit according to a third embodiment. FIG. 4 is a cross-sectional view of a memory cell having a latch circuit according to a third embodiment. 7 is a plan view of a memory cell having a latch circuit according to a fourth embodiment; FIG. FIG. 7 is a cross-sectional view of a memory cell having a latch circuit according to a fourth embodiment. FIG. 7 is a cross-sectional view of a memory cell having a latch circuit according to a fourth embodiment. FIG. 7 is a cross-sectional view of a memory cell having a latch circuit according to a fifth embodiment. FIG. 7 is a cross-sectional view of a memory cell having a latch circuit according to a fifth embodiment. FIG. 7 is a cross-sectional view of a memory cell having a latch circuit according to a fifth embodiment. FIG. 6 is a flip-flop circuit including a latch circuit according to first to fifth embodiments. FIG.

<Embodiment 1>
The configuration of the semiconductor device according to the present embodiment will be described below with reference to the drawings as appropriate. For clarity of explanation, the following description and the drawings are omitted and simplified as appropriate.

  FIG. 1 is an equivalent circuit diagram of an SRAM (Static Random Access Memory) cell having a latch circuit according to the present embodiment. Note that the SRAM includes a memory cell array region in which memory cells are formed, and a peripheral circuit region in which peripheral circuits that control the operation of the memory cells are formed.

The RAMic Random Access Memoryy memory cell has a first inverter and a second inverter that constitute a latch circuit, and two access MOS transistors (MN3 and MN4 which are NMOS). The first inverter includes a driver transistor MN1 and a load transistor MP1. The second inverter includes a driver transistor MN2 and a load transistor MP2.

  The first inverter and the second inverter connect each other's input and output. The first storage node NOD1 is connected to the first terminal of MN3. The second storage node NOD2 is connected to the first terminal of MN4. The gate of MN3 is connected to the word line WL. The gate of MN4 is connected to the word line WL. The second terminal of MN3 is connected to the bit line BL. The second terminal of MN4 is connected to the bit line BL.

  The source of MP1 is connected to the power supply (VDD), and the drain of MP1 is connected to the first storage node NOD1. The source of MP2 is connected to the power supply (VDD), and the drain of MP2 is connected to the second storage node NOD2. The source of MN1 is connected to GND, and the drain of MN1 is connected to the first storage node NOD1. The source of MN2 is connected to GND, and the drain of MN2 is connected to the second storage node NOD2.

  Here, as shown by the dotted line in FIG. 1, the memory cell according to the present embodiment has a configuration substantially equivalent to the formation of the capacitive element C1 between the first storage node NOD1 and the second storage node NOD2. This configuration will be described below.

  A plurality of memory cells are arranged in the memory cell array region of the semiconductor device according to the present embodiment. In each memory cell, the storage node, the diffusion layer, and the gate electrode are connected by a slit contact (described later). Since the configuration of each memory cell is the same, the configuration of each memory cell will be described with reference to FIG.

  FIG. 2 is a plan view of the memory cell according to the present embodiment. In FIG. 2, the arrangement positions of the transistors (MN1 to MN4, MP1, MP2) and the storage nodes (NOD1, NOD2) are also displayed.

  N + diffusion layer n1 is formed on P well region pw1. Similarly, P + diffusion layer p1 is formed on N well region nw1. A gate electrode g1 is provided to connect the P well region pw1 and the N well region nw1. Similarly, an N + diffusion layer n2 is formed on the P well region pw2. A gate electrode g2 is provided so as to connect the P well region pw2 and the N well region nw1. Although not shown, element isolation films (STI) for separating semiconductor elements are also formed on the P well regions pw1, pw2 and the N well region nw1. In addition, the lamination | stacking relationship of each layer is later mentioned with reference to sectional drawing of FIGS.

  Here, in addition to the storage node and the diffusion layer, two contacts (scont1, scont2) that are connected so as to connect the gate electrodes are arranged with an interval therebetween. That is, the memory cell is not provided with a hole shape (substantially square shape) in a plan view, but is provided with two contacts (cont1, const2) that form grooves extending in a plurality of axial directions as shown in the figure. Yes. In the following description, a contact having an extending direction that is not substantially a hole shape, such as sct1 and scont2, is referred to as a slit contact. In addition, metal wiring layers (m1 to m8) are provided above the contacts (cont1 to cont8) other than the slit contacts. For convenience of explanation, a y-axis direction (first direction) and an x-axis direction (second direction) are defined in FIG. According to this, the slit contacts sct1 and scont2 extend in the x-axis direction and extend in the y-axis direction.

  Hereinafter, the configurations of the planar A / -A cross section, B / -B cross section, and C / -C cross section in FIG. 2 will be described. FIG. 3 is a diagram showing an A / -A cross section of the memory cell (FIG. 2).

  As illustrated, an N-type well region nw1 is formed on the semiconductor substrate sub. On the N-type well region nw1, a P + diffusion layer p1 is formed by implanting an impurity of a conductivity type opposite to that of the N-type well region nw1 (ie, P-type). Furthermore, an element isolation film STI for element isolation is provided in the N-type well region nw1. The element isolation film STI is configured, for example, by generating a buried oxide film by a shallow trench isolation method.

  Gate electrodes g1 and g2 are formed on the N-type well region nw1 through gate insulating films gd1 and gd2. With the gate insulating films (gd1, gd2), the lower surfaces of the gate electrodes g1 and g2 are electrically insulated from the N-type well region nw1. The gate electrodes g1 and g2 are made of, for example, a polysilicon film doped with impurities.

  An interlayer insulating film IDF is provided so as to cover the upper portions of the gate electrodes g1 and g2, the P + diffusion layer p1, and the element isolation film STI. The interlayer insulating film IDF is provided to insulate the metal wirings provided in the contacts (cont1 to cont8) and the slit contacts (scont1, sconc2).

  In the interlayer insulating film IDF, contact holes are provided, and the contacts (cont1 to cont8) and slit contacts (scont1, scont2) are formed by covering the contact holes with aluminum, tungsten, or the like. As described above, the contacts (cont1 to cont8) have a substantially hole shape when seen in a plan view, and the slit contacts (scont1, scont2) extend in a specific direction (FIG. 2). In the A / -A cross section shown in FIG. 4, the contact cont2 shown at the right end in the drawing has a substantially hole shape, and the slit contacts scont1 and snt2 shown in the other (leftmost, center) have an extended structure. A metal wiring layer m2 is provided on the contact cont2.

  Next, the B / -B cross section of the memory cell (FIG. 2) will be described with reference to FIG. As illustrated, N-type well regions nw1, nw2 and a P-type well region pw1 are provided on a semiconductor substrate sub. A gate electrode g4 is formed on the P-type well region pw1 with the gate insulating film gd3 interposed therebetween. A gate electrode g2 is formed on the N-type well region nw1 and the P-type well region p2 with the gate insulating film gd4 interposed therebetween. In the well region (pw1, nw1, pw2), an element isolation film STI for element isolation is provided. As in FIG. 3, an interlayer insulating film IDF is provided so as to cover the upper portion of the gate electrode and the element isolation film STI.

  In the interlayer insulating film IDF, a substantially hole-shaped contact cont5 is formed on the gate electrode g4, and a slit contact cont1 extending in a specific direction (FIG. 2) is formed on the gate electrode g2. A metal wiring layer m5 is provided on the contact cont5.

  Next, the C / -C cross section of the memory cell (FIG. 2) will be described with reference to FIG. As illustrated, N-type well regions nw1, nw2 and a P-type well region pw1 are provided on a semiconductor substrate sub. An N + diffusion layer n1 is formed on the P-type well region pw1, P + diffusion layers p1 and p2 are formed on the N-type well region nw1, and an N + diffusion layer n2 is formed on the P-type well region nw2. . An element isolation film STI is provided between the respective diffusion layers. An interlayer insulating film IDF is formed so as to cover the element isolation film STI and each diffusion layer (n1, p1, p2, n2), and a contact hole is provided on the interlayer insulating film IDF and covered with metal to thereby form a slit contact scont1 and scont2 is formed as shown. As shown in the figure, the contacts sct1 and scont2 are formed to extend in the extending direction of the C / -C cross section. The above is the description of the configuration of the memory cell according to this embodiment.

  Prior to describing the effect of the memory cell having the latch circuit according to the present embodiment, the technical problems of Patent Document 1 and Patent Document 2 will be described again. As described above, the techniques of Patent Document 1 and Patent Document 2 have a problem that a sufficient capacity cannot be added to the storage node without increasing the chip area. Further, in the technique of Patent Document 2, in the process of expanding the damascene wiring trench in the lateral direction, the interval between metal portions that do not need to be reduced (the same metal layer portion of the entire chip) is also reduced, which is unnecessary. Parasitic capacitance may be added. In this case, the capacity (response speed) of the inverter or the like may be deteriorated. In addition, when a process step that extends in the lateral direction is applied only to a portion where the interval is desired to be reduced, this process step becomes a dedicated process step, resulting in an increase in manufacturing cost. Here, the dedicated process step is to divide the trench creation process of the part that you want to reduce the interval and the part that you do not want to reduce (mask the part you want to reduce the interval and create the trench that you do not want to reduce the interval, Then the reverse process is performed.) That is, the technique described in Patent Document 2 also has a problem of causing an increase in manufacturing process (cost).

  Next, the effect of the memory cell having the latch circuit according to this embodiment will be described. As shown in FIG. 2 and the like, the slit contact scont1 (first contact) on the first storage node NOD1 and the slit contact scont2 (second contact) on the second storage node NOD2 are in the y-axis direction (first direction). Are facing along. Here, the first storage node NOD1 and the second storage node NOD2 have different potentials, and the slit contacts (scont1, scont2) having the extended structure face each other, so that a large parasitic capacitance is generated between the slit contacts.

  In addition, since the slit contacts scont1 and scont2 have a stretched shape, a large parasitic capacitance is generated between the slit contact and the gate on one storage node. These parasitic capacitances increase the capacity of the storage nodes (NOD1, NOD2).

  In addition, the slit contacts sct1 and scont2 have an extending structure in the x-axis direction (second direction (positive x-axis direction) and third direction (negative x-axis direction, substantially opposite to the second direction)). As a result, the metal region formed by the slit contact scont1 and the slit contact sot2 is provided in parallel, and a large parasitic capacitance is generated between the storage nodes.

  Since parasitic capacitance is generated between the storage nodes as described above, the same effect as that of providing the capacitor (dotted line portion in the drawing) in the equivalent circuit diagram of FIG. 1 can be obtained. According to the measurement by the inventors, the capacity of the storage node in the SRAM memory cell is increased by about 30% by adopting the SRAM memory cell having the above-described configuration (FIGS. 2 to 5). The soft error tolerance is improved by increasing the capacity of the storage node.

  In the above-described configuration, since there is no metal wiring layer covering the slit contacts (scont1, sconc2), the parasitic capacitance of the bit line BL is reduced. Thereby, the read speed can be improved. According to the estimation by the inventor, the lead speed was improved by about 7%.

  Further, since there is no metal wiring layer covering the slit contacts (scont1, sconc2), the dimension in the y direction between the gate electrode g1 and the gate electrode g2 / g4 can be shortened. Thereby, the cell area can be reduced. This is because the metal wiring layer is usually arranged so as to cover the contact, and the wiring width of the metal wiring layer is larger than the contact width, so even if it is desired to reduce the contact interval, the layout is determined by the wiring reference. is there.

  In FIG. 2, the slit contacts contact1 and contact2 have been described as having a biaxial shape extending in the orthogonal direction (x-axis and y-axis), but the present invention is not limited to this, and the angle formed by the multiaxial is 90. It may be other than 60 degrees (for example, 60 degrees).

  Since the above configuration can increase the capacity of the storage node without adding a capacitor, the circuit scale can be reduced as compared with a configuration having a general soft error countermeasure (a configuration having a capacitor). Can do.

  Furthermore, the layout configuration described above can be formed without adding a new manufacturing process. That is, the above-described layout configuration can be formed by using a general contact hole generation method and a metal wiring method for the contact hole. Since the addition of a new process step is unnecessary, an increase in the cost of the manufacturing process can be avoided.

  As described above, the occurrence of parasitic capacitance between the slit contacts (sct1, sct2) improves the soft error resistance. If the two slit contacts are present at a certain distance or more, parasitic capacitance is generated, so that there are no major restrictions on the shapes of the slit contacts scont1 and scont2. Since the restrictions on the shapes of the slit contacts scont1 and scont2 are small, an increase in the cost of the manufacturing process can be avoided.

  The wiring width of the slit contact on the gate electrode may be smaller than the wiring width of the slit contact on the STI. As a result, the gate electrode and the source (or drain) generated when the slit contact on the upper part of the transistors (MN1 and MP1, MN2 and MP2) constituting the latch circuit is shifted from the gate electrode to the source (or drain) side in the manufacturing process. ) And a short circuit between the gate electrode and the source (or drain). Note that only one of the slit contacts scont1 and scont2 can have such a structure.

  In addition, the slit contacts (sct1, sconc2) do not need to be in contact with the other parts as long as the parts to be connected in the latch circuit are connected to each other. For example, the slit contact connects only a portion where the slit contact scont1 and the N + diffusion layer n1 in FIG. 2 overlap, a portion where the slit contact scont1 and the P + diffusion layer p1 overlap, a portion where the slit contact scont1 and the gate electrode g2 overlap, and the like. I just need it. When these portions are connected, the latch circuit operates normally. In the case where the slit contacts (sct1, sconc2) are connected to the minimum necessary parts, the process development is facilitated by reducing the number of parts to be trenched.

  Further, the slit contacts (scont1, sconc2) may have a further extended structure. For example, the slit contact sct1 may further extend in the negative y-axis direction (fourth direction) from the end point on the N + diffusion layer n1. That is, the slit contacts (scont1 and scont2) may have a structure that sequentially extends in different directions. By having such a stretched structure, application to a later-described flip-flop circuit (FIG. 19, a configuration having a transfer) is facilitated.

<Embodiment 2>
The latch circuit according to the present embodiment is characterized in that the shapes of the slit contacts sct1 and scont2 having the extending structure are different from those of the first embodiment. The memory cell having the latch circuit according to the present embodiment will be described below with respect to differences from the first embodiment.

  FIG. 6 is a plan view of a memory cell having a latch circuit according to the present embodiment. In the memory cell according to the present embodiment, the slit contact score1 is provided along the P + diffusion layer p1 and is formed in the direction connecting the N + diffusion layer n1 and the P + diffusion layer p1 (negative x-axis direction). It is not formed on the gate electrode g2. The slit contact scont2 is provided along the P + diffusion layer p2, and is provided so as to connect the P + diffusion layer p2 and the N + diffusion layer n2, but is formed in the extending direction (positive x-axis direction) of the gate electrode g1. Not. Other configurations are the same as those in FIG.

  Hereinafter, configurations of the planar A / -A cross section and the B / -B cross section in FIG. 6 will be described. Note that the C / -C cross section is the same as the configuration of the first embodiment (FIG. 5), and a description thereof will be omitted. FIG. 7 is a diagram showing an A / -A cross section of the memory cell (FIG. 6). In the A / -A cross section of the memory cell according to the present embodiment, unlike the configuration of the first embodiment (FIG. 3), the slit contact scont2 is not formed on the gate electrode g1. The other configuration is the same as the configuration of the first embodiment (FIG. 3), and a description thereof will be omitted.

  FIG. 8 is a diagram showing a B / -B cross section of the memory cell (FIG. 6). Unlike the configuration of the first embodiment (FIG. 4), the slit contact scont1 is provided on the gate electrode g2, but is not extended in the B / -B cross-sectional direction (provided to extend in the x-axis direction). Not) The other configuration is the same as the configuration of the first embodiment (FIG. 4), and a description thereof will be omitted.

  Next, the effect of the latch circuit according to the present embodiment will be described. Also in the present embodiment, as shown in FIG. 6 and the like, the slit contact scont1 on the first storage node NOD1 and the slit contact scont2 on the second storage node NOD2 face each other along the y-axis direction (first direction). ing. Here, the first storage node NOD1 and the second storage node NOD2 have different potentials, and the slit contacts (scont1, scont2) having the extended structure face each other, so that a large parasitic capacitance is generated between the slit contacts. A large parasitic capacitance is also generated between the slit contact and the gate on one storage node. This creates a large parasitic capacitance between the storage nodes. Due to the large parasitic capacitance between the storage nodes, the soft error resistance is improved.

  Further, in the configuration of FIG. 6, compared with the first embodiment (FIG. 2), since the facing area of the slit contacts (sct1, sconc2) is reduced, the increased capacitance is reduced, but the parasitic capacitance to the bit line is reduced. Compared with the configuration of the first embodiment, the read speed is improved.

<Embodiment 3>
The latch circuit according to the present embodiment is characterized in that a metal wiring layer is provided so as to cover the slit contacts scont1 and scont2. Regarding the latch circuit according to the present embodiment, differences from the first embodiment will be described below.

  FIG. 9 is a plan view of a memory cell having a latch circuit according to the present embodiment. In addition to the configuration of the second embodiment (FIG. 6), the memory cell according to the present embodiment is provided with a metal wiring layer m9 so as to cover the slit contact sgt1, and a metal wiring layer m10 so as to cover the slit contact scont2. Is provided.

  Hereinafter, the configurations of the planar A / -A cross section, B / -B cross section, and C / -C cross section in FIG. 9 will be described. FIG. 10 is a diagram showing an A / -A cross section of the memory cell (FIG. 9). As shown in the drawing, a metal wiring layer m9 is provided so as to cover the upper part of the slit contact scont1. Other configurations are the same as those in the second embodiment (FIG. 7).

  FIG. 11 is a diagram showing a B / -B cross section of the memory cell (FIG. 9). As shown in the drawing, a metal wiring layer m9 is provided so as to cover the upper part of the slit contact scont1. Other configurations are the same as those of the second embodiment (FIG. 8).

  FIG. 12 is a diagram showing a C / -C cross section of the memory cell (FIG. 9). As shown in the drawing, a metal wiring layer m9 is provided so as to cover the upper part of the slit contact scont1. Similarly, a metal wiring layer m10 is provided so as to cover the upper part of the slit contact scont2. Other configurations are the same as those in the first embodiment (FIG. 5) and the second embodiment.

  Also in the present embodiment, since the slit contacts scont1 and scont2 have an extending structure in the y-axis (first direction), parasitic capacitance is generated between the storage nodes, and soft error resistance is improved as compared with a general memory cell. Further, as shown in FIG. 9 and the like, the metal wiring layers (m9, m10) can be arranged without being affected by the formation of the slit contact. In the above description, the metal wiring layers m9 and m10 are configured to cover all the upper portions of the slit contacts scont1 and scon2. However, the metal wiring layers m9 and m10 cover only a part of the upper part of the slit contacts scont1 and scont2. May be configured. Further, only one of the metal wiring layers m9 and m10 may be provided on the memory cell.

  In the present embodiment, by providing the metal wiring layers m9 and m10, the opposing areas also increase in the z direction (vertical direction in the cross-sectional view). This further improves resistance to soft errors. In this embodiment, since the parasitic capacitance for the bit line also increases, the read speed decreases. Therefore, the configuration according to the present embodiment is effective when a high read speed is not required.

<Embodiment 4>
The latch circuit according to the present embodiment is characterized in that the diffusion layers are connected by a metal wiring layer. The difference between the latch circuit according to the present embodiment and the first embodiment will be described below.

  FIG. 13 is a plan view showing the configuration of the memory cell having the latch circuit according to the present embodiment. Differences from the first embodiment will be described below. The slit contact scont1 extends on the P + diffusion layer p1 (that is, extends in the y-axis direction on p1) and extends on the gate electrode g2 (that is, extends on the g2 in the x-axis direction). Formed in shape). A columnar contact cont9 (third contact) is formed on the N + diffusion layer n1. The metal wiring layer m11 is provided so as to connect the contact cont9 and the slit contact sgt1.

  Similarly, the slit contact scont2 extends on the P + diffusion layer p2 (that is, extends in the y-axis direction on p2) and extends on the gate electrode g1 (that is, on the g1 in the x-axis direction). Formed in an elongated form). A columnar contact cont10 is formed on the N + diffusion layer n2. The metal wiring layer m12 is provided so as to connect the contact cont10 and the slit contact scont2. Other configurations are the same as those in the first embodiment.

  Hereinafter, the configuration of the planar A / -A cross section and the C / -C cross section in FIG. 13 will be described. Since the B / -B cross section in FIG. 13 is the same as the B / -B cross section of Embodiment 1 (FIG. 4), description thereof is omitted.

  FIG. 14 is a diagram showing an A / -A cross section of the memory cell (FIG. 13). As shown in the drawing, a metal wiring layer m11 is provided on part of the upper portion of the slit contact scont1. Other configurations are the same as those of the first embodiment (FIG. 3).

  FIG. 15 is a diagram showing a C / -C cross section of the memory cell (FIG. 13). As shown in the drawing, a metal wiring layer m11 is provided on the upper surfaces of the contact cont9 and the slit contact cont1. That is, the metal wiring layer m11 connects the contact cont9 and the slit contact scont1. A metal wiring layer m12 is provided on the upper surfaces of the slit contact scont2 and the contact cont10. That is, the metal wiring layer m12 connects the contact cont10 and the slit contact scont2. Other configurations are the same as those of the first embodiment (FIG. 5).

  Also in the present embodiment, since the slit contacts scont1 and scont2 have an extending structure in the y-axis (first direction), parasitic capacitance is generated between the storage nodes, and soft error resistance is improved as compared with a general memory cell. Note that only one of the slit contacts sct1 and scont2 can be configured as shown in FIG. 13, and the other can be configured in the same manner as in the other embodiments.

<Embodiment 5>
The latch circuit according to the present embodiment is characterized in that a plurality of metal wiring layers are provided as compared with the first embodiment. Differences from the first embodiment regarding the configuration of the latch circuit according to the present embodiment will be described below.

  Since the plan view of the memory cell having the latch circuit according to this embodiment is the same as that of the first embodiment (FIG. 1), description thereof is omitted. With reference to FIGS. 16 to 18, the A / -A cross section, B / -B cross section, and C / -C cross section of the memory cell according to the present embodiment will be described.

  FIG. 16 is a diagram showing an A / -A cross section of the memory cell according to the present embodiment. As shown in the drawing, each slit contact (cont1, scont2) and each contact (cont2) have a multi-stage shape. That is, the slit contacts scont1, scont2 and contact cont2 are configured by a three-layer structure. The three-layer slit contact and contact are generated by repeating the generation of the contact hole and the formation of the wiring metal film three times.

  17 is a diagram showing a B / -B cross section of the memory cell according to the present embodiment, and FIG. 18 is a diagram showing a C / -C cross section of the memory cell according to the present embodiment. As shown in the figure, each contact has a three-layer structure. The number of layers of each contact is not limited to three and may be any number. That is, the contacts and slit contacts in the memory cell can have a multilayer structure.

  Also in the present embodiment, as in the first embodiment, a parasitic capacitance is generated between the storage nodes, so that soft error resistance is improved as compared with a general memory cell.

<Utilization method of latch circuit>
Examples of utilization of the latch circuits according to the first to fifth embodiments as described above will be described below. FIG. 19 shows a flip-flop circuit configured by the latch circuit according to any one of the first to fifth embodiments.

  As shown in the figure, the flip-flop circuit has two latch portions (a circuit surrounded by a dotted line). The two latch portions are connected via a transfer. Each latch section (circuit surrounded by a dotted line) has substantially the same configuration as the equivalent circuit shown in FIG. Therefore, each latch portion can have the layout described in the first to fifth embodiments.

  Even when the layouts of the first to fifth embodiments described above are applied to the flip-flop circuit, a capacity can be given to the storage nodes (NOD1, NOD2). Thereby, the tolerance with respect to a soft error improves.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

MN1-MN4 NMOS
MP1 to MP4 PMOS
NOD1 First storage node NOD2 Second storage node WL Word line BL Bit line VDD Power supply nw1 N well region pw1, pw2 P well region STI Element isolation film n1, n2 N + diffusion layer p1, p2 P + diffusion layer cont1, scont2 slit contact cont1 Cont10 contacts m1 to m10 metal wiring layer sub semiconductor substrate gd1 to gd4 gate insulating film IDF interlayer insulating films g1 to g4 gate electrode

Claims (12)

A first contact having a shape extending at least in a first direction, provided on a region constituting a first storage node that connects an input of a first inverter and an output of a second inverter constituting the latch circuit;
A second contact provided on a region constituting a second storage node connecting the output of the first inverter and the input of the second inverter, and having a shape extending at least in the first direction;
The latch circuit, wherein the first contact and the second contact face each other along the first direction. The first contact has a shape extended in the first direction and a shape extended in a second direction which is a direction different from the first direction,
2. The latch circuit according to claim 1, wherein the second contact has a shape extended in the first direction and a shape extended in a third direction substantially opposite to the second direction.   The first contact and the second contact have a shape extended in one direction different from the first direction from one end of the shape extended in the first direction, and The latch circuit according to claim 1, wherein the latch circuit has a shape extending from a second end of the shape extending in the first direction in a third direction substantially opposite to the second direction.   The latch circuit according to claim 1, wherein the first contact and the second contact have a multilayer structure.   The latch circuit according to claim 1, wherein a metal wiring layer is provided so as to cover the upper part of the first contact.   The latch circuit according to claim 1, wherein a metal wiring layer is provided so as to cover an upper portion of the second contact.   The latch circuit according to claim 1, wherein a third contact is provided on a diffusion layer different from the diffusion layer provided with the first contact, and the first contact and the third contact are connected by a metal wiring layer.   2. The latch circuit according to claim 1, wherein a third contact is provided on a diffusion layer different from the diffusion layer provided with the second contact, and the second contact and the third contact are connected by a metal wiring layer.   2. The latch circuit according to claim 1, wherein at least one of the first contact and the second contact is configured such that a wiring width on the gate electrode is smaller than a wiring width on the element isolation film.   4. The latch circuit according to claim 3, wherein the first contact and the second contact further have a shape extended in a fourth direction from the other end of the shape extended in the second direction. 5.   An SRAM comprising the latch circuit according to claim 1.   A flip-flop circuit comprising the latch circuit according to claim 1.

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